WO2022014623A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2022014623A1
WO2022014623A1 PCT/JP2021/026375 JP2021026375W WO2022014623A1 WO 2022014623 A1 WO2022014623 A1 WO 2022014623A1 JP 2021026375 W JP2021026375 W JP 2021026375W WO 2022014623 A1 WO2022014623 A1 WO 2022014623A1
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Prior art keywords
region
concentration
peak
semiconductor device
collector
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PCT/JP2021/026375
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English (en)
French (fr)
Japanese (ja)
Inventor
泰典 阿形
徹 白川
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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Priority to JP2022536411A priority Critical patent/JP7405261B2/ja
Priority to CN202180007761.8A priority patent/CN114902426A/zh
Priority to DE112021000205.8T priority patent/DE112021000205T5/de
Publication of WO2022014623A1 publication Critical patent/WO2022014623A1/ja
Priority to US17/844,052 priority patent/US12414342B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/137—Collector regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/422—PN diodes having the PN junctions in mesas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/50—Physical imperfections
    • H10D62/53—Physical imperfections the imperfections being within the semiconductor body 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors

Definitions

  • the present invention relates to a semiconductor device.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2015-135954
  • a first conductive type drift region provided on the semiconductor substrate, a first conductive type field stop region provided below the drift region and having one or more peaks, and the like.
  • a second conductive type collector region provided below the field stop region is provided, and the integrated concentration of the collector region is x [cm -2 ], and the shallowest of one or a plurality of peaks from the back surface of the semiconductor substrate. The depth of one peak is y1 [ ⁇ m].
  • Line A1: y1 (-7.4699E-01) ln (x) + (2.7810E + 01)
  • Line B1: y1 (-4.7772E-01) ln (x) + (1.7960E + 01)
  • the integrated concentration in the collector region may be 8.00E15 cm-2 or less.
  • the integrated concentration in the collector region may be 3.00E14 cm -2 or less.
  • the integrated concentration in the collector region may be 2.00E 14 cm -2 or less.
  • the integrated concentration in the collector region may be 1.00E14 cm -2 or less.
  • the integrated concentration in the collector region may be 5.00E 13 cm -2 or less.
  • the integrated concentration in the collector region may be 3.00E13 cm -2 or less.
  • the integrated concentration in the collector region may be 1.00E 13 cm -2 or less.
  • the depth of the first peak may be 0.5 ⁇ m or more and 7.2 ⁇ m or less.
  • the depth of the first peak may be 2.0 ⁇ m or more and 7.2 ⁇ m or less.
  • the depth of the second peak which is the second shallowest from the back surface of one or more peaks, is y2 [ ⁇ m].
  • Line A2: y2 (-3.1095E + 00) ln (x) + (1.1416E + 02)
  • Line B2: y2 (-1.9239E + 00) ln (x) + (7.1030E + 01)
  • the depth of the second peak and the integrated concentration may be in the range between the line A2 and the line B2.
  • the depth of the second peak may be 3.5 ⁇ m or more and 28 ⁇ m or less.
  • the stray inductance Ls of the circuit connected to the semiconductor device is Xc [nH], and the collector current reduction rate dIce / dt is Yc [A / ⁇ s].
  • Line C1: Yc 10000Xc -1 ,
  • the stray inductance Ls and the collector current reduction rate dIce / dt may be in a range larger than that of the line C1.
  • the dopant for one or more peaks may be hydrogen.
  • An active region provided on the semiconductor substrate and an outer peripheral region provided on the outer periphery of the active region in the top view of the semiconductor substrate may be provided.
  • a second conductive type contact region having a higher doping concentration than the base region and a plurality of gate trench portions provided on the semiconductor substrate may be provided.
  • the doping concentration at the boundary between the field stop region and the collector region may be 1E 16 cm -3 or less.
  • the doping concentration at the boundary between the field stop region and the collector region may be 5E15 cm -3 or less.
  • the doping concentration at the boundary between the field stop region and the collector region may be 2E15 cm -3 or less.
  • the hydrogen chemical concentration at the boundary between the field stop region and the collector region may be 1E18 cm -3 or less.
  • the hydrogen chemical concentration at the boundary between the field stop region and the collector region may be 1E17 cm -3 or less.
  • the hydrogen chemical concentration at the boundary between the field stop region and the collector region may be 1E15 cm -3 or higher.
  • the hydrogen chemical concentration at the boundary between the field stop region and the collector region may be 1E16 cm -3 or higher.
  • FIG. 1A It is a figure which shows an example of the aa'cross section in FIG. 1A. This is an example of a circuit at the time of a clamp withstand voltage test of the semiconductor device 100. It is a figure for demonstrating the clamp energy of the semiconductor device 100. The relationship between the doping concentration of the collector region 22 and the clamping energy is shown. The relationship between the doping concentration of the collector region 22 and the withstand voltage of the device is shown. An example of the current-voltage characteristics of the semiconductor device 100 according to the embodiment is shown. An example of the current-voltage characteristics of the semiconductor device 500 according to the comparative example is shown. An example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown.
  • Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown. Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown. Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown. Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown. Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown. Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown. Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown. Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown.
  • Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1 is shown.
  • the relationship between the integrated concentration of the collector region 22 and the depth of the second peak P2 is shown.
  • Another example of the relationship between the integrated concentration of the collector region 22 and the depth of the second peak P2 is shown.
  • the relationship between the integrated concentration of the collector region 22 and the depth of the second peak P2 is shown. It is a figure for demonstrating the relationship between a stray inductance Ls and a collector current reduction rate dIce / dt. It is a figure for demonstrating the relationship between the specific stray inductance Ls ⁇ A and the current density dJce / dt. It is a figure for demonstrating the relationship between the specific stray inductance Ls ⁇ A and the specific gate resistance Rg ⁇ A.
  • one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper”, and the other side is referred to as “lower”.
  • the upper surface is referred to as the upper surface and the other surface is referred to as the lower surface.
  • the directions of "top”, “bottom”, “front”, and “back” are not limited to the direction of gravity or the direction of mounting on a substrate or the like when mounting a semiconductor device.
  • orthogonal coordinate axes of X-axis, Y-axis, and Z-axis Orthogonal axes only specify the relative positions of the components and do not limit a particular direction.
  • the Z axis does not limit the height direction with respect to the ground.
  • the + Z-axis direction and the ⁇ Z-axis direction are opposite to each other. When positive or negative is not described and is described as the Z-axis direction, it means the direction parallel to the + Z-axis and the -Z-axis.
  • the plane parallel to the upper surface of the semiconductor substrate is referred to as the XY plane, and the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X axis and the Y axis.
  • the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is defined as the Z axis.
  • the depth direction of the semiconductor substrate may be referred to as the Z axis.
  • the case where the semiconductor substrate is viewed in the Z-axis direction is referred to as a plan view.
  • the direction parallel to the upper surface and the lower surface of the semiconductor substrate including the X-axis and the Y-axis may be referred to as a horizontal direction.
  • the first conductive type is N type and the second conductive type is P type, but the first conductive type may be P type and the second conductive type may be N type.
  • the conductive types such as the substrate, the layer, and the region in each embodiment have opposite polarities.
  • error When referred to as “same” or “equal” in the present specification, it may include a case where there is an error due to manufacturing variation or the like.
  • the error is, for example, within 10%.
  • the conductive type of the doping region doped with impurities is described as P type or N type.
  • an impurity may mean, in particular, either an N-type donor or a P-type acceptor, and may be referred to as a dopant.
  • doping means that a donor or acceptor is introduced into a semiconductor substrate to obtain a semiconductor showing an N-type conductive type or a semiconductor showing a P-type conductive type.
  • the doping concentration means the concentration of a donor or the concentration of an acceptor in a thermal equilibrium state.
  • the net doping concentration means the net concentration of the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, including the polarity of the charge.
  • the donor concentration N D, the acceptor concentration and N A, the net doping concentration of the net at any position is N D -N A.
  • the donor has the function of supplying electrons to the semiconductor.
  • the acceptor has a function of receiving electrons from a semiconductor.
  • Donors and acceptors are not limited to the impurities themselves.
  • the VOH defect to which the pores (V), oxygen (O) and hydrogen (H) present in the semiconductor are bonded functions as a donor for supplying electrons.
  • VOH defects may be referred to simply as hydrogen donors.
  • P + type or N + type means that the doping concentration is higher than P type or N type
  • P-type or N-type means that the doping concentration is higher than P-type or N-type. It means that the concentration is low.
  • P ++ type or N ++ type in the present specification it means that the doping concentration is higher than that of P + type or N + type.
  • the chemical concentration refers to the atomic density of impurities measured regardless of the state of electrical activation.
  • the chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS).
  • the net doping concentration described above can be measured by a voltage-capacity measurement method (CV method).
  • the carrier concentration measured by the spread resistance measurement method (SR method) may be used as the net doping concentration.
  • the carrier concentration measured by the CV method or the SR method may be a value in a thermal equilibrium state.
  • the donor concentration is sufficiently higher than the acceptor concentration, so the carrier concentration in the region may be used as the donor concentration.
  • the carrier concentration in the region may be used as the acceptor concentration.
  • Each concentration in the present invention may be a value at room temperature. As the value at room temperature, the value at 300 K (Kelvin) (about 26.9 ° C.) may be used as an example.
  • the peak value may be used as the concentration of the donor, acceptor or net doping in the region.
  • the concentration of the donor, the acceptor or the net doping is substantially uniform, the average value of the concentration of the donor, the acceptor or the net doping in the region may be used as the concentration of the donor, the acceptor or the net doping.
  • the carrier concentration measured by the SR method may be lower than the concentration of the donor or acceptor.
  • the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder of the crystal structure due to lattice defects or the like.
  • the concentration of the donor or acceptor calculated from the carrier concentration measured by the CV method or the SR method may be lower than the chemical concentration of the element indicating the donor or acceptor.
  • the donor concentration of phosphorus or arsenic as a donor in a silicon semiconductor, or the acceptor concentration of boron (boron) as an acceptor is about 99% of these chemical concentrations.
  • the donor concentration of hydrogen as a donor in a silicon semiconductor is, for example, about 0.1% to 10% of the chemical concentration of hydrogen.
  • the unit system of this specification is an SI unit system unless otherwise specified.
  • the unit of length may be displayed in cm or the like, but various calculations may be performed after converting to meters (m).
  • the doping concentration refers to the concentration of a donor or accepted dopant.
  • the unit is / cm 3.
  • the concentration difference between the donor and the acceptor (that is, the net doping concentration) may be referred to as the doping concentration.
  • the doping concentration can be measured by the SR method.
  • the chemical concentration of the donor and the acceptor may be used as the doping concentration.
  • the doping concentration can be measured by the SIMS method. Unless otherwise limited, any of the above may be used as the doping concentration. Unless otherwise limited, the peak value of the doping concentration distribution in the doping region may be used as the doping concentration in the doping region.
  • the dose amount means the number of ions per unit area injected into the wafer when ion implantation is performed. Therefore, the unit is / cm 2 .
  • the dose amount in the semiconductor region can be an integrated concentration obtained by integrating the doping concentration over the depth direction of the semiconductor region.
  • the unit of the integrated concentration is / cm 2 . Therefore, the dose amount and the integrated concentration may be treated as the same.
  • the integrated concentration may be an integrated value up to the full width at half maximum, and when it overlaps with the spectrum of another semiconductor region, it may be derived excluding the influence of the other semiconductor region.
  • the high and low doping concentrations can be read as the high and low dose amounts. That is, when the doping concentration in one region is higher than the doping concentration in the other region, it can be understood that the dose amount in the one region is higher than the dose amount in the other region.
  • FIG. 1A is an example of a top view of the semiconductor device 100.
  • the semiconductor device 100 includes an active region 110, an outer peripheral region 120, and a pad region 130.
  • the semiconductor device 100 is a semiconductor chip including a transistor unit 70 and a diode unit 80.
  • the semiconductor device 100 includes a temperature sense unit 76 and may be mounted on a module such as an IPM (Intelligent Power Module).
  • IPM Intelligent Power Module
  • the transistor unit 70 includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor).
  • the diode section 80 includes a diode such as a freewheeling diode (FWD: Free Wheel Diode).
  • the semiconductor device 100 of this example is a reverse conduction IGBT (RC-IGBT: Reverse Control IGBT) having a transistor portion 70 and a diode portion 80 on the same chip.
  • the transistor of the transistor unit 70 is an IGBT.
  • the semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, or the like.
  • the semiconductor substrate 10 of this example is a silicon substrate.
  • the semiconductor substrate 10 has an active region 110 and an outer peripheral region 120.
  • the transistor portion 70 and the diode portion 80 may be alternately and periodically arranged periodically in the XY plane.
  • the semiconductor device 100 of this example includes a plurality of transistor units 70 and a plurality of diode units 80, respectively.
  • the transistor portion 70 and the diode portion 80 of this example have a trench portion extending in the Y-axis direction.
  • the transistor portion 70 and the diode portion 80 may have a trench portion extending in the X-axis direction.
  • the temperature sense unit 76 is provided above the active region 110.
  • the temperature sense unit 76 may be formed of single crystal or polycrystalline silicon.
  • the forward voltage of the current flowing through the temperature sense unit 76 changes.
  • the temperature of the semiconductor device 100 can be detected based on the change in the forward voltage.
  • the active region 110 has a transistor unit 70 and a diode unit 80.
  • the active region 110 is a region in which a main current flows between the front surface and the back surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in the ON state. That is, it is a region in which a current flows in the depth direction inside the semiconductor substrate 10 from the front surface to the back surface of the semiconductor substrate 10 or from the back surface to the front surface.
  • the transistor unit 70 and the diode unit 80 are referred to as element units or element regions, respectively.
  • the region sandwiched between the two element portions is also referred to as the active region 110.
  • the active region 110 also includes a region sandwiched between the element portions and provided with the gate runner 51.
  • the gate runner 51 may supply the gate potential supplied from the gate pad 131 of the pad region 130 to the gate conductive portion of the transistor portion 70.
  • the gate runner 51 is provided along the outer circumference of the active region 110 in top view.
  • the gate runner 51 may also be provided in the region between the transistor portion 70 and the diode portion 80 in a top view.
  • the outer peripheral region 120 is provided around the end portion of the semiconductor substrate 10 so as to surround the active region 110 and the pad region 130 in the top view. It is a region between the outer peripheral edge of the semiconductor substrate 10.
  • the outer peripheral region 120 is provided so as to surround the active region 110 in top view.
  • the outer peripheral region 120 may have an edge termination structure.
  • the edge terminal structure portion relaxes the electric field concentration on the front surface side of the semiconductor substrate 10.
  • the edge termination structure has a guard ring, a field plate, a resurf, and a combination thereof.
  • the pad area 130 includes a gate pad 131, a sense IGBT 132, a sense emitter pad 133, an anode pad 134, and a cathode pad 135.
  • the cathode pad 135, the anode pad 134, the gate pad 131, the sense IGBT 132, and the sense emitter pad 133 are provided side by side in this order in the X-axis direction.
  • Each pad may be an electrode pad containing gold (Au), silver (Ag), copper (Cu), aluminum (Al), or the like.
  • the gate pad 131 is electrically connected to the gate conductive portion of the transistor portion 70 via the gate runner 51.
  • the gate pad 131 is set to the gate potential.
  • the sense IGBT 132 is an IGBT for detecting the main current flowing through the transistor unit 70.
  • the main current of the transistor unit 70 can be detected by incorporating the sense current flowing through the sense IGBT 132 into a control circuit provided outside the semiconductor device 100.
  • the sense emitter pad 133 of this example has the same potential as the emitter of the sense IGBT 132.
  • the sense current may be taken into the above-mentioned control circuit from the sense emitter pad 133 via the sense IGBT 132.
  • the control circuit may detect the main current based on the sense current and cut off the current flowing through the transistor section 70 when the overcurrent is flowing through the transistor section 70.
  • the anode pad 134 is electrically connected to the temperature sense unit 76 and is set to the anode potential of the temperature sense unit 76.
  • the cathode pad 135 is electrically connected to the temperature sense unit 76 and is set to the cathode potential of the temperature sense unit 76.
  • the anode pad 134 and the cathode pad 135 can be used to detect the potential difference between the anode and the cathode of the temperature sensing unit 76.
  • FIG. 1B is an example of a top view of the semiconductor device 100 corresponding to the region A of FIG. 1A. That is, an enlarged view of the end portion of the active region 110 is shown.
  • the transistor portion 70 is a region in which a collector region 22 provided on the back surface side of the semiconductor substrate 10 is projected onto the front surface of the semiconductor substrate 10.
  • the collector region 22 has a second conductive type.
  • the collector area 22 of this example is a P + type as an example.
  • the transistor portion 70 includes a boundary portion 90 located at the boundary between the transistor portion 70 and the diode portion 80.
  • the diode portion 80 is a region in which the cathode region 82 provided on the back surface side of the semiconductor substrate 10 is projected onto the front surface of the semiconductor substrate 10.
  • the cathode region 82 has a first conductive type.
  • the cathode region 82 of this example is N + type as an example.
  • the semiconductor device 100 of this example has a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface of the semiconductor substrate 10. Be prepared. Further, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10.
  • the emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Further, the gate metal layer 50 is provided above the well region 17 and the gate runner 51. The emitter electrode 52 of this example is set to the emitter potential of the transistor portion 70.
  • the gate metal layer 50 is electrically connected to the gate conductive portion of the transistor portion 70, and supplies a gate voltage to the transistor portion 70.
  • the gate metal layer 50 is electrically connected to the gate pad 131.
  • the gate metal layer 50 is provided along the outer periphery of the active region 110 in top view.
  • the gate metal layer 50 may also be provided between the transistor portion 70 and the diode portion 80 when viewed from above.
  • the gate runner 51 connects the gate metal layer 50 and the gate conductive portion in the gate trench portion 40.
  • the gate runner 51 is not connected to the dummy conductive portion in the dummy trench portion 30.
  • the gate runner 51 is formed of polyether that is doped with impurities or the like.
  • the emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal.
  • the emitter electrode 52 may be formed of aluminum, aluminum-silicon alloy, or aluminum-silicon-copper alloy.
  • the emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like in the lower layer of a region formed of aluminum or the like.
  • the emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
  • the emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film 38 interposed therebetween.
  • the interlayer insulating film 38 is omitted in FIG. 1B.
  • the interlayer insulating film 38 is provided with a contact hole 54, a contact hole 55, and a contact hole 56 penetrating.
  • the contact hole 55 connects the gate metal layer 50 and the gate runner 51.
  • a plug made of tungsten or the like may be formed inside the contact hole 55.
  • the contact hole 55 may be provided along the gate runner 51.
  • the contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30.
  • a plug made of tungsten or the like may be formed inside the contact hole 56.
  • connection portion 25 electrically connects the emitter electrode 52 and the plug inside the contact hole 56.
  • the connection portion 25 has a conductive material such as polysilicon doped with impurities.
  • the connection portion 25 of this example is polysilicon doped with N-type impurities.
  • the connecting portion 25 covers a larger area than the contact hole 56 in the top view.
  • the connecting portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film.
  • the gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example).
  • the gate trench portion 40 of this example has two stretched portions 41 and 2 that are parallel to the front surface of the semiconductor substrate 10 and stretched along a stretch direction (Y-axis direction in this example) perpendicular to the arrangement direction. It may have a connecting portion 43 connecting the two stretched portions 41.
  • the connecting portion 43 is formed in a curved shape.
  • the dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Similar to the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example). Like the gate trench portion 40, the dummy trench portion 30 of this example may have a U-shape on the front surface of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two stretching portions 31 that stretch along the stretching direction and a connecting portion 33 that connects the two stretching portions 31.
  • the well region 17 is a second conductive type region provided on the front surface side of the semiconductor substrate 10 with respect to the drift region 18 described later.
  • the well region 17 is an example of a well region provided on the edge side of the semiconductor device 100.
  • the well region 17 is P + type as an example.
  • the well region 17 is formed in a predetermined range from the end of the active region 110 on the side where the gate metal layer 50 is provided.
  • the diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30.
  • a part of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17.
  • the bottom of the extending end of the gate trench 40 and the dummy trench 30 may be covered by the well region 17.
  • the contact hole 54 is formed in the transistor portion 70 above each region of the emitter region 12 and the contact region 15. Further, the contact hole 54 is provided above the base region 14 in the diode portion 80. The contact hole 54 is provided above the contact area 15 at the boundary portion 90. Neither contact hole 54 is provided above the well regions 17 provided at both ends in the stretching direction. As described above, one or a plurality of contact holes 54 are formed in the interlayer insulating film 38. The one or more contact holes 54 may be provided by being stretched in the stretching direction.
  • the boundary portion 90 is provided in the transistor portion 70 and is a region adjacent to the diode portion 80.
  • the boundary portion 90 has a contact region 15.
  • the boundary portion 90 of this example does not have an emitter region 12.
  • the boundary portion 90 of this example is arranged so that both ends in the arrangement direction are dummy trench portions 30.
  • the mesa portion 71, the mesa portion 91, and the mesa portion 81 are the mesa portions provided adjacent to the trench portion in the plane parallel to the front surface of the semiconductor substrate 10.
  • the mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the front surface of the semiconductor substrate 10 to the depth of the deepest bottom of each trench portion. ..
  • the extended portion of each trench portion may be used as one trench portion. That is, the region sandwiched between the two stretched portions may be the mesa portion.
  • the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70.
  • the mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface of the semiconductor substrate 10.
  • the emitter region 12 and the contact region 15 are alternately provided in the stretching direction.
  • the mesa portion 91 is provided at the boundary portion 90.
  • the mesa portion 91 has a base region 14, a contact region 15, and a well region 17 on the front surface of the semiconductor substrate 10.
  • both ends in the arrangement direction are in contact with the dummy trench portion 30, but at least one of them may be in contact with the gate trench portion 40.
  • one mesa portion 91 is provided, but a plurality of mesa portions 91 may be provided.
  • the mesa portion 81 is provided in the diode portion 80 in a region sandwiched between adjacent dummy trench portions 30.
  • the mesa portion 81 has a base region 14 and a well region 17 on the front surface of the semiconductor substrate 10.
  • the base region 14 is a second conductive type region provided on the front surface side of the semiconductor substrate 10 in the transistor portion 70 and the diode portion 80.
  • the base region 14 is P-type as an example.
  • the base region 14 may be provided at both ends of the mesa portion 71 and the mesa portion 91 in the stretching direction on the front surface of the semiconductor substrate 10. Note that FIG. 1B shows only one end of the base region 14 in the stretching direction.
  • the emitter region 12 is a first conductive type region having a higher doping concentration than the drift region 18.
  • the emitter region 12 of this example is N + type as an example.
  • An example of a dopant in the emitter region 12 is arsenic (As).
  • the emitter region 12 is provided in contact with the gate trench portion 40 on the front surface of the mesa portion 71.
  • the emitter region 12 may be provided extending from one of the two trench portions sandwiching the mesa portion 71 to the other in the arrangement direction.
  • the emitter region 12 is also provided below the contact hole 54.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 of this example is in contact with the dummy trench portion 30.
  • the emitter region 12 does not have to be provided in the mesa portion 91 of the boundary portion 90.
  • the contact region 15 is a second conductive type region having a higher doping concentration than the base region 14.
  • the contact region 15 of this example is a P + type as an example.
  • the contact region 15 of this example is provided on the front surface of the mesa portion 71 and the mesa portion 91.
  • the contact region 15 may be provided in the arrangement direction from one of the two trench portions sandwiching the mesa portion 71 or the mesa portion 91 to the other.
  • the contact region 15 may or may not be in contact with the gate trench portion 40. Further, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40.
  • the contact area 15 is also provided below the contact hole 54.
  • the contact region 15 may also be provided in the mesa portion 81.
  • FIG. 1C is a diagram showing an example of a bb'cross section in FIG. 1B.
  • the bb'cross section is an XZ plane that passes through the emitter region 12 in the transistor portion 70.
  • the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in a bb'cross section.
  • the emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.
  • the drift region 18 is a first conductive type region provided on the semiconductor substrate 10.
  • the drift region 18 of this example is N-type as an example.
  • the drift region 18 may be a region remaining in the semiconductor substrate 10 without forming another doping region. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.
  • the field stop region 20 is a first conductive type region provided below the drift region 18.
  • the field stop region 20 of this example is N-type as an example.
  • the doping concentration in the field stop region 20 is higher than the doping concentration in the drift region 18.
  • the field stop region 20 prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductive type and the cathode region 82 of the first conductive type.
  • the field stop region 20 may have one or more peaks.
  • the field stop region 20 of this example has four peaks, a first peak P1 to a fourth peak P4.
  • the dopant for one or more peaks may be hydrogen.
  • the first peak P1 to the fourth peak P4 are provided in this order from the back surface 23. That is, the first peak P1 is the peak closest to the back surface 23.
  • the doping concentration of the first peak P1 may be higher than the doping concentration of the other peaks. This makes it possible to slowly and surely stop the depletion layer when a voltage is applied.
  • the collector region 22 is provided below the field stop region 20 in the transistor portion 70.
  • the cathode region 82 is provided below the field stop region 20 in the diode portion 80.
  • the boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80.
  • the collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10.
  • the collector electrode 24 is made of a conductive material such as metal.
  • the base region 14 is a second conductive type region provided above the base region 14 in the mesa portion 71, the mesa portion 91, and the mesa portion 81.
  • the base region 14 is provided in contact with the gate trench portion 40.
  • the base region 14 may be provided in contact with the dummy trench portion 30.
  • the emitter region 12 is provided between the base region 14 and the front surface 21 in the mesa portion 71.
  • the emitter region 12 is provided in contact with the gate trench portion 40.
  • the emitter region 12 may or may not be in contact with the dummy trench portion 30.
  • the emitter region 12 does not have to be provided in the mesa portion 91.
  • the contact region 15 is provided above the base region 14 in the mesa portion 91.
  • the contact region 15 is provided in the mesa portion 91 in contact with the gate trench portion 40.
  • the contact region 15 may be provided on the front surface 21 of the mesa portion 71.
  • the storage region 16 is a first conductive type region provided on the front surface 21 side of the semiconductor substrate 10 with respect to the drift region 18.
  • the storage area 16 of this example is N + type as an example.
  • the storage region 16 is provided in the transistor portion 70 and the diode portion 80.
  • the storage area 16 of this example is also provided at the boundary portion 90.
  • the storage area 16 is provided in contact with the gate trench portion 40.
  • the storage region 16 may or may not be in contact with the dummy trench portion 30.
  • the doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.
  • One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21.
  • Each trench portion is provided from the front surface 21 to the drift region 18.
  • each trench portion also penetrates these regions and reaches the drift region 18.
  • the fact that the trench portion penetrates the doping region is not limited to those manufactured in the order of forming the doping region and then forming the trench portion. Those in which the doping region is formed between the trench portions after the trench portion is formed are also included in those in which the trench portion penetrates the doping region.
  • the gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44.
  • the gate insulating film 42 is formed so as to cover the inner wall of the gate trench.
  • the gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench.
  • the gate conductive portion 44 is formed inside the gate trench and inside the gate insulating film 42.
  • the gate insulating film 42 insulates the gate conductive portion 44 and the semiconductor substrate 10.
  • the gate conductive portion 44 is formed of a conductive material such as polysilicon.
  • the gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21.
  • the gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side with the gate insulating film 42 interposed therebetween in the depth direction of the semiconductor substrate 10.
  • a predetermined voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed on the surface layer of the interface of the base region 14 in contact with the gate trench.
  • the dummy trench portion 30 may have the same structure as the gate trench portion 40.
  • the dummy trench portion 30 has a dummy trench formed on the front surface 21 side, a dummy insulating film 32, and a dummy conductive portion 34.
  • the dummy insulating film 32 is formed so as to cover the inner wall of the dummy trench.
  • the dummy conductive portion 34 is formed inside the dummy trench and inside the dummy insulating film 32.
  • the dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10.
  • the dummy trench portion 30 is covered with the interlayer insulating film 38 on the front surface 21.
  • the interlayer insulating film 38 is provided on the front surface 21.
  • An emitter electrode 52 is provided above the interlayer insulating film 38.
  • the interlayer insulating film 38 is provided with one or a plurality of contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, the contact hole 55 and the contact hole 56 may be provided so as to penetrate the interlayer insulating film 38.
  • FIG. 1D is a diagram showing an example of a doping concentration distribution in the depth direction at the position of the c-c'line in FIG. 1B.
  • the cc'line passes from the emitter region 12 to the collector region 22 in the transistor portion 70.
  • the vertical axis of FIG. 1D is a logarithmic axis.
  • the doping concentration distribution of the field stop region 20 in the transistor unit 70 will be described, but the field stop region 20 in the diode unit 80 may also have the same doping concentration distribution.
  • the doping concentration of the drift region 18 of this example is the bulk donor concentration Db.
  • the first conductive type (N type) bulk donors are distributed throughout.
  • the bulk donor is a donor due to a dopant contained in the ingot substantially uniformly at the time of manufacturing the ingot that is the source of the semiconductor substrate 10.
  • the bulk donor in this example is an element other than hydrogen.
  • Bulk donor dopants are, but are not limited to, for example phosphorus, antimony, arsenic, selenium, sulfur.
  • the bulk donor in this example is phosphorus. Bulk donors are also included in the P-shaped region.
  • the semiconductor substrate 10 may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by individualizing the wafer.
  • the semiconductor ingot may be manufactured by any one of a Czochralski method (CZ method), a magnetic field application type Czochralski method (MCZ method), and a float zone method (FZ method).
  • CZ method Czochralski method
  • MCZ method magnetic field application type Czochralski method
  • FZ method float zone method
  • the ingot in this example is manufactured by the MCZ method.
  • the bulk donor concentration Db may use the chemical concentration of the donor distributed throughout the semiconductor substrate 10, and may be a value between 90% and 100% of the chemical concentration.
  • the concentration peak is the peak of the donor concentration.
  • the plurality of concentration peaks can be formed by injecting an impurity such as hydrogen or phosphorus into a plurality of depth positions in the field stop region 20.
  • hydrogen may be used with the position of P1 as phosphorus and P2 to P4 as donors.
  • all of P1 to P4 are hydrogen as a donor.
  • the field stop region 20 may have a concentration peak of an impurity such as hydrogen or phosphorus at a position corresponding to the concentration peak. Impurity concentration peaks are peaks in the chemical concentration distribution of impurities.
  • FIG. 1E is an enlarged view of the doping concentration distribution in the field stop region 20 and the collector region 22 of FIG. 1C.
  • the vertical axis of FIG. 1E is a logarithmic axis.
  • the peak values of the doping concentrations of the plurality of concentration peaks P1, P2, P3, and P4 are d1, d2, d3, and d4, respectively.
  • the depth of the pn junction between the collector region 22 and the field stop region 20 is defined as J1.
  • the plurality of concentration peaks include the shallowest peak closest to the back surface 23 of the semiconductor substrate 10.
  • the concentration peak P1 corresponds to the shallowest peak.
  • the concentration peak P1 in this example is the concentration peak closest to the collector region 22.
  • the concentration peak P1 is the concentration peak closest to the cathode region 82.
  • the cathode region 82 may be formed by injecting an impurity different from the concentration peak.
  • the cathode region 82 has an impurity concentration peak such as phosphorus
  • the field stop region 20 has an impurity concentration peak such as hydrogen.
  • the plurality of concentration peaks include high concentration peaks arranged at positions farther from the back surface 23 than the shallowest peak (concentration peak P1).
  • the high concentration peak may be the concentration peak P2 closest to the shallowest peak, or may be another concentration peak.
  • the concentration peak P2 closest to the concentration peak P1 corresponds to the high concentration peak.
  • the plurality of concentration peaks are arranged at positions farther from the back surface 23 than the high concentration peak, and include a low concentration peak in which the peak value of the doping concentration is 1/5 or less of the peak value of the high concentration peak.
  • the low concentration peak may be the deepest peak (concentration peak P4 in this example) arranged farthest from the back surface 23 among the plurality of concentration peaks.
  • the low concentration peak may be a concentration peak other than the deepest peak. That is, the low concentration peak may be a concentration peak between the high concentration peak and the deepest peak.
  • two or more low concentration peaks may be provided.
  • the low concentration peaks are preferably arranged next to each other in the depth direction.
  • two or more concentration peaks arranged farthest from the back surface 23 may be low concentration peaks.
  • P2 is a low concentration peak.
  • a concentration peak other than the concentration peak closest to the back surface 23 may be regarded as a low concentration peak.
  • FIG. 1E the concentration peak P4 which is the deepest peak, the concentration peak P3 provided at a position away from the back surface 23 next to the deepest peak toward the back surface 23, and the concentration peak closest to the back surface 23 next to P3.
  • P2 is a low concentration peak.
  • a concentration peak other than the concentration peak closest to the back surface 23 may be regarded as a low concentration peak.
  • both the peak value d3 of the doping concentration of the concentration peak P3 and the peak value d4 of the doping concentration of the concentration peak P4 are 1/5 or less of the peak value d1 of the doping concentration of the concentration peak P1.
  • the concentration peaks d2 to d4 of the low concentration peaks P2 to P4 may be 1/10 or less of the peak value d1 of the concentration peak P1.
  • the peak value d3 of P3 is lower than the peak value d4 of P4.
  • the peak value d3 of P3 may be higher than the peak value d4 of P4. That is, the peak value of P2 to P4 may decrease toward the front surface 21.
  • a high voltage may be applied between the emitter / collector of the semiconductor device 100.
  • the electric field tends to concentrate in the vicinity of the deepest peak (concentration peak P4 in this example) in the field stop region 20. Therefore, if the doping concentration in the vicinity of the deepest peak is increased, as in the case of the concentration peak P3 and the concentration peak P4, the concentration of the electric field is promoted.
  • the gate voltage tends to vibrate at the time of turn-off of the semiconductor device 100 or the like.
  • the concentration peak of this example a low concentration peak having a sufficiently small doping concentration is provided at a position deeper than the high concentration peak (concentration peak P1). Therefore, the electric field concentration at the deep position of the field stop region 20 can be relaxed.
  • the number of low concentration peaks may be one or more, and a plurality of low concentration peaks may be provided.
  • the field stop region 20 having a relatively low concentration can be formed long on the drift region 18 side.
  • the field stop region 20 has three low concentration peaks, but in another example, the field stop region 20 may have four or more low concentration peaks.
  • the deepest peak may be provided on the front surface 21 side of the semiconductor substrate 10.
  • the peak value of the doping concentration of the low concentration peak may be 1/5 or less, 1/10 or less, or 1/20 or less of the peak value of the doping concentration of the high concentration peak.
  • the peak value of the doping concentration of the low concentration peak is higher than the bulk donor concentration Db.
  • the peak value of the doping concentration of the low concentration peak may be 50 times or less the bulk donor concentration Db of the semiconductor substrate 10.
  • the doping concentration of the drift region 18 may be used as the bulk donor concentration Db.
  • the peak value of the doping concentration of the low concentration peak may be 20 times or less of the bulk donor concentration Db, may be 10 times or less, may be 8 times or less, may be 5 times or less, and may be 3 times. It may be double or less, and may be double or less.
  • the minimum value of the doping concentration between the peaks of the low concentration peak may be higher than the bulk donor concentration Db, may be 5 times or less of the bulk donor concentration Db, and may be 3 times or less. It may be less than double.
  • the ratio of the minimum value between peaks to the peak concentration of either of the adjacent low concentration peaks may be 0.8 or less, 0.5 or less, 0.2 or less, and 0. .1 or more, 0.2 or more, 0.5 or more.
  • the positions of the concentration peaks P1, P2, P3, and P4 in the depth direction are Z1, Z2, Z3, and Z4, respectively.
  • the distance between the concentration peak P4 and the concentration peak P2 in the depth direction is Z4-Z2.
  • the distance between the concentration peak P1 and the concentration peak P2 in the depth direction is Z2-Z1.
  • the distance Z4-Z2 may be larger than the distance Z2-Z1.
  • the distance between the concentration peak P3 and the concentration peak P4 is Z4-Z3.
  • the distance between the concentration peak P3 and the concentration peak P2 is Z3-Z2.
  • the distance Z4-Z3 may be larger than the distance Z3-Z2. Further, the distance Z4-Z3 may be larger than the distance Z2-Z1.
  • the peak value of the doping concentration of the concentration peak P4 may be 1/5 or less, 1/10 or less, or 1/20 or less of the peak value of the doping concentration of the high concentration peak. ..
  • the peak value of the doping concentration of the concentration peak P4 is higher than the bulk donor concentration Db.
  • the average value of the peak values of the doping concentrations of the concentration peak P4 and the concentration peak P3 may be 50 times or less, 20 times or less, 10 times or less, and 8 times the bulk donor concentration Db. It may be double or less, may be 5 times or less, may be 3 times or less, and may be 2 times or less.
  • the donor concentration or acceptor concentration may be 1E16 / cm 3 or less, 5E15 / cm 3 or less, and 2E15 / cm. It may be 3 or less.
  • E is meant a power of 10, for example, 1E16 / cm 3 means 1 ⁇ 10 16 / cm 3.
  • FIG. 1F is a diagram showing an example of distribution of net doping concentration and hydrogen chemical concentration in the depth direction in the first concentration peak and the collector region 22.
  • the solid line represents an example of the distribution of the net doping concentration
  • the broken line represents an example of the distribution of the hydrogen chemical concentration.
  • the vertical axis of FIG. 1F is a logarithmic axis.
  • the region shown by diagonal lines in FIG. 1F is the integrated concentration of the collector region 22 in this example. That is, in the present specification, the integrated concentration of the collector region 22 is the concentration obtained by integrating the net doping concentration of the collector region 22 from the back surface to the pn junction position J1 with the field stop region 20 in the depth direction of the semiconductor substrate 10. Means.
  • the hydrogen chemical concentration Dh in the pn junction J1 between the collector region 22 and the field stop region 20 may be 1E18 / cm 3 or less, may be 1E17 / cm 3 or less, and may be 1E16 / cm 3 or more. It may be 1E15 / cm 3 or more.
  • FIG. 1G is an example of a top view of the semiconductor device 100 corresponding to the region B of FIG. 1A. In this example, an enlarged view of the end portion of the active region 110 is shown.
  • the region B is a region including the transistor portion 70 of the active region 110 and the gate runner 51.
  • the semiconductor device 100 of this example includes a dummy trench region 60 and a well contact region 65.
  • the dummy trench region 60 is an region having only the dummy trench portion 30 as the trench portion.
  • the dummy trench region 60 is provided between the gate trench portion 40 closest to the outer peripheral region 120 and the outer peripheral region 120 in the arrangement direction.
  • the dummy trench region 60 has a plurality of dummy trench portions 30 arranged apart from each other by a predetermined interval in the arrangement direction.
  • the well contact region 65 is provided in a part of the well region 17, and the hole injected from the collector region 22 is pulled out to the emitter electrode 52.
  • the well contact area 65 has a contact area 15.
  • a contact hole 54 is provided on the contact region 15 of the well contact region 65.
  • the contact region 15 is electrically connected to the emitter electrode 52 through a plurality of contact holes 54.
  • the semiconductor device 100 does not have to include the well contact region 65.
  • the mesa portion 61 is provided with a base region 14, a contact region 15, and a well region 17.
  • the contact region 15 is provided in the mesa portion 61 from one dummy trench portion 30 adjacent to each other in the arrangement direction to the other dummy trench portion 30. Since the mesa portion 61 of this example has the contact region 15, it becomes easier to pull out the hole as compared with the case where the contact region 15 is not provided. This prevents the semiconductor device 100 from being destroyed by the concentration of the avalanche current at the end of the well region 17.
  • the emitter electrode 52 is also provided above the dummy trench region 60 and the well contact region 65.
  • the emitter electrode 52 is electrically connected to the front surface 21 of the semiconductor substrate 10 in each of the dummy trench region 60, the well contact region 65, and the transistor portion 70 via the contact hole 54.
  • the well region 17 is provided on the outer peripheral side of the active region 110 in top view. The inner end of the well region 17 is shown by a broken line.
  • the storage region 16 is provided so as to extend from the transistor portion 70 to the dummy trench region 60.
  • the storage region 16 of this example is provided so as to extend from the transistor portion 70 to the mesa portion 61 in the middle of the dummy trench region 60.
  • FIG. 1H is a diagram showing an example of a'a'cross sections in FIG. 1A.
  • a cross-sectional view of a region straddling the active region 110 and the outer peripheral region 120 is shown.
  • the outer peripheral region 120 of this example has a guard ring structure and a channel stopper structure.
  • the guard ring structure may include a plurality of guard ring portions 92.
  • the guard ring structure of this example includes five guard ring portions 92.
  • Each guard ring portion 92 may be provided on the front surface 21 so as to surround the active region 110 and the pad region 130.
  • the guard ring structure may have a function of spreading the depletion layer generated in the active region 110 to the outside of the semiconductor substrate 10. This makes it possible to prevent electric field concentration inside the semiconductor substrate 10. Therefore, the withstand voltage of the semiconductor device 100 can be improved as compared with the case where the guard ring structure is not provided.
  • the guard ring portion 92 is a P + type semiconductor region formed by ion implantation in the vicinity of the front surface 21.
  • the guard ring portion 92 is electrically connected to the electrode layer 94.
  • the electrode layer 94 may be made of the same material as the gate metal layer 50 or the emitter electrode 52.
  • the plurality of guard ring portions 92 are electrically insulated from each other by the interlayer insulating film 38.
  • the depth of the bottom of the guard ring portion 92 may be the same as the depth of the bottom of the well region 17.
  • the depth of the bottom of the guard ring portion 92 may be deeper than the depth of the bottom of the gate trench portion 40 and the dummy trench portion 30.
  • the channel stopper structure has a channel stopper region 96 and an electrode layer 94.
  • the channel stopper region 96 is electrically connected to the electrode layer 94 through the opening of the interlayer insulating film 38.
  • the conductive type of the channel stopper region 96 may be the first conductive type or the second conductive type.
  • the conductive type of the channel stopper region 96 of this example is an N + type.
  • the channel stopper region 96 has a function of terminating the depletion layer generated in the active region 110 at the outer end portion of the semiconductor substrate 10.
  • the well region 17 may extend beyond the well contact region 65 in the arrangement direction and further to the outside.
  • the well region 17 of this example may be provided so that the innermost guard ring portion 92 in the outer peripheral region 120 and the outer end portion of the well region 17 are close to each other.
  • the base region 14 may be extended to the vicinity of the innermost guard ring portion 92 instead of the well region 17.
  • An oxide film 39 may be provided between the contact region 15 and the gate runner 51 above the well region 17.
  • the oxide film 39 may be formed in the same process as the dummy insulating film 32 or the gate insulating film 42.
  • the oxide film 39 may be formed by a process such as a field oxide film having a thicker film thickness.
  • FIG. 2A is an example of a circuit for a clamp withstand voltage test of the semiconductor device 100.
  • a gate voltage Vg is applied to the gate terminal of the semiconductor device 100 via a predetermined gate resistance Rg.
  • the rated current Ic is switched at a predetermined power supply voltage Vcc.
  • the power supply voltage Vcc may be about 60% of the rated voltage.
  • the stray inductance Ls is the stray inductance of the circuit to which the semiconductor device 100 is connected. Since the stray inductance Ls tries to maintain the current, a surge voltage is generated when the current is cut off. The stray inductance Ls is increased from a predetermined initial value for each switching, and the semiconductor device 100 is turned off. When the stray inductance Ls is increased, the jump voltage ⁇ V increases. By increasing the stray inductance Ls, the electric field strength inside the semiconductor device 100 increases, and the element is easily destroyed. Here, the result in the test immediately before the element is destroyed is referred to as the clamp energy (that is, the fracture tolerance).
  • FIG. 2B is a diagram for explaining the clamping energy of the semiconductor device 100.
  • the figure shows the behavior of the collector-emitter current Ice and the collector-emitter voltage Vce at turn-off.
  • the graph of this example shows the waveform immediately before the stray inductance Ls in which the element is destroyed by repeating the turn-off while increasing the stray inductance Ls in the clamp withstand voltage test. Due to the turn-off of the semiconductor device 100, the collector-emitter voltage Vce jumps up, and the voltage is held for a certain period of time. The period in which the voltage is constant is the clamping period.
  • Clamp energy is the integrated value in the range of current x voltage of 0 or more in the period from the jump of the collector-emitter voltage Vce to the settlement of the power supply voltage Vcc. That is, the clamp energy is represented by an integral value (that is, an energy value) of ⁇ Ice ⁇ Vce dt. The larger the clamp energy, the larger the fracture resistance at turn-off.
  • FIG. 3A shows the relationship between the doping concentration of the collector region 22 and the clamping energy.
  • the vertical axis represents the clamp energy [mJ]
  • the horizontal axis is the integrated value obtained by integrating the doping concentration of the collector region 22 over the depth from the back surface 23 to the PN junction between the collector region 22 and the field stop region 20 (hereinafter,). (Referred to as the integrated value of the doping concentration of the collector region 22) [cm -2 ] is shown.
  • the black square indicates the case where the acceleration energy of the proton is 400 keV.
  • the white square indicates the case where the acceleration energy of the proton is 300 keV.
  • Proton is one of the types of hydrogen ion. Hydrogen donors are formed, for example, by ion-implanting protons into a semiconductor substrate.
  • the integrated value of the doping concentration in the collector region 22 is about 1.00E + 14 [cm- 2 ], and the clamp energy becomes the maximum value.
  • the proton range of the first peak P1 is 3.13 ⁇ m.
  • 1.00E + 14 [cm -2 ] means 1.00 ⁇ 10 14 [cm -2 ].
  • the acceleration energy of the proton is 400 keV
  • the integrated value of the doping concentration in the collector region 22 is about 1.00E + 13 [cm -2 ], and the clamp energy becomes the maximum value.
  • the proton range is 4.52 ⁇ m.
  • the injection dose amount may be equal to the integrated value of the doping concentration in the collector region 22.
  • the clamp withstand voltage of the active region 110 is made smaller than the clamp withstand voltage of the outer peripheral region 120 by controlling the integrated concentration of the collector region 22 and the peak depth of the field stop region 20. Thereby, the clamping energy of the semiconductor device 100 can be improved.
  • FIG. 3B shows the relationship between the doping concentration of the collector region 22 and the withstand voltage of the device.
  • the vertical axis shows the withstand voltage [V] of the device, and the horizontal axis shows the doping concentration [cm -3 ] of the collector region 22.
  • the collector region 22 may comprise a doping concentration distribution with a peak.
  • the doping concentration in the collector region 22 may be the peak value of the doping concentration in the collector region 22.
  • the field stop region 20 has four peaks will be described.
  • Graph G1 shows an activity + edge model when the field stop region 20 has four peaks.
  • the activity + edge model is a simulation model that considers both the active region 110 and the outer peripheral region 120.
  • Graph G2 shows an activity model when the field stop region 20 has four peaks.
  • the activity model is a simulation model in which only the active region 110 is considered without considering the outer peripheral region 120.
  • the withstand voltage of the active region 110 is lower than the withstand voltage of the outer peripheral region 120. That is, the withstand voltage of the element is the withstand voltage of the active region 110. In this way, when the withstand voltage of the element is determined in the active region 110, the clamping energy increases.
  • the withstand voltage of the active region 110 is higher than the withstand voltage of the outer peripheral region 120. That is, the withstand voltage of the element is the withstand voltage of the outer peripheral region 120. In this way, when the withstand voltage of the element is determined in the outer peripheral region 120, the clamp energy is reduced.
  • the doping concentration of the collector region 22 may be 6 ⁇ 10 17 (/ cm 3 ) or less, and may be 5 ⁇ 10 17 (/ cm 3) or less.
  • FIG. 4A shows an example of the current-voltage characteristics of the semiconductor device 100 according to the embodiment.
  • the vertical axis shows the collector-emitter current Ice [A] and the collector-emitter voltage Vce [V], and the horizontal axis shows the time [s].
  • the regions where the electron current density is large are shown by broken lines at time T1 and time T2, respectively.
  • the doping concentration of the collector region 22 of this example is set in the range in which the clamp withstand voltage is determined in the active region 110 in FIG. 3B.
  • Time T1 is the time when the semiconductor device 100 is turned off and the collector-emitter voltage Vce rises. At time T1, the electron current is concentrated in the region indicated by the broken line in the active region 110. That is, the peak region of the electron current density is formed in a part of the region shown by the broken line of the active region 110.
  • Time T2 indicates the time when the collector-emitter voltage Vce rises and is clamped at around 800V.
  • the temperature of the avalanche breakdown point rises.
  • the lattice vibration becomes intense and electrons are scattered.
  • the peak region of the electron current density may move from the active region 110 toward the end of the well region 17 on the outer peripheral region 120 side.
  • the withstand voltage of the active region 110 is smaller than the withstand voltage of the outer peripheral region 120
  • the peak region of the electron current density formed on the active region 110 side moves to the outer peripheral region 120 side. This temporarily lowers the temperature of the active region 110.
  • the power that is, Ice ⁇ Vce
  • FIG. 4B shows an example of the current-voltage characteristics of the semiconductor device 500 according to the comparative example.
  • the vertical axis shows the collector-emitter current Ice [A] and the collector-emitter voltage Vce [V], and the horizontal axis shows the time [s]. Further, in this example, the peak regions of the electron current densities are shown by broken lines at time T3 and time T4, respectively.
  • the doping concentration of the collector region 22 of this example is set in the range in which the withstand voltage is determined in the outer peripheral region 120 in FIG. 3B.
  • the integrated concentration of the collector region 22 is set so that the withstand voltage of the outer peripheral region 120 is smaller than the withstand voltage of the active region 110. Due to the turn-off, avalanche breakdown occurs on the outer peripheral region 120 side of the well region 17, and the peak region of the electron current density is formed at the location indicated by the broken line. From time T3 to time T4, the peak region of the electron current density is stagnant at the position indicated by the broken line while the power is high. Therefore, the temperature continues to rise due to current concentration. As described above, in the semiconductor device 500, the element is easily broken and the clamp withstand capacity cannot be improved.
  • the carriers tend to concentrate on the contact hole end on the outer peripheral region 120 side, so that the avalanche breakdown is likely to occur.
  • the increase in the hole concentration on the back surface 23 side amplifies the avalanche breakdown during clamping.
  • the hole injection efficiency of the collector region 22 is lowered by appropriately setting the doping concentration of the collector region 22 and the depth of the first peak P1, and the clamp withstand voltage of the active region 110 is reduced. It is made smaller than the clamp withstand voltage of the outer peripheral region 120. As a result, after the avalanche breakdown occurs in the active region 110, the avalanche breakdown moves to the outer peripheral region 120, so that instantaneous fracture can be suppressed.
  • the doping concentration of the collector region 22 and the depth of the first peak P1 may be set so that the clamping energy is maximized. An appropriate range of the doping concentration of the collector region 22 and the depth of the first peak P1 will be described later.
  • the voltage is designed to have a withstand voltage higher than the surge voltage (the peak value of the voltage between the collector and emitter that is higher than the power supply voltage at turn-off) that is expected to prevent element destruction when the current is cut off. It is necessary to increase the thickness of the semiconductor substrate 10 in the depth direction and increase the area of the outer peripheral region 120.
  • the withstand voltage of the element may be designed to be lower than the surge voltage. In the semiconductor device 100 of this example, the avalanche breakdown is generated in the active region 110 at the time of turn-off, so that the chip cost can be reduced and the element destruction can be prevented.
  • the total dose amount of the field stop region 20 and the total dose amount of the collector region 22 may be determined so that the withstand voltage of the active region 110 is smaller than the withstand voltage of the outer peripheral region 120.
  • the total dose amount of the field stop region 20 may be 10 times or less the total dose amount of the collector region 22, and may be 5 times or less the total dose amount of the collector region 22.
  • FIG. 5A shows an example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the vertical axis shows the depth y1 [ ⁇ m] of the first peak P1
  • the horizontal axis shows the integrated concentration x [cm -2 ] of the collector region 22.
  • the next reference line L1 was calculated based on the data of the two points where the acceleration energy of the shallowest proton and the maximum clamp energy were obtained in FIG. 3A.
  • Reference line L1: y1 (-6.3067E-01) ln (x) + (2.2590E + 01) That is, the reference line L1 shows the relationship between the integrated concentration of the collector region 22 where the clamping energy is maximized and the depth of the first peak P1 where the clamping energy is maximized.
  • the region R1 indicates a region in the range of ⁇ 15% of the reference line L1.
  • the region R1 of this example is a region between the line A1 and the line B1.
  • the line A1 and the line B1 of this example are represented by the following equations.
  • Line A1: y1 (-7.4699E-01) ln (x) + (2.7810E + 01)
  • Line B1: y1 (-4.7772E-01) ln (x) + (1.7960E + 01)
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 belong to the region R1.
  • the hole injection efficiency of the collector region 22 can be suppressed and the clamp pressure resistance of the active region 110 can be made smaller than the clamp pressure resistance of the outer peripheral region 120.
  • Integral density of the collector region 22 may be at 1.00E16cm -2 or less, may be 8.00E15cm -2 or less.
  • the depth of the first peak P1 may be 0.5 ⁇ m or more and 7.2 ⁇ m or less.
  • the avalanche breakdown during clamping can be generated on the active region 110 side. This improves the clamp pressure resistance.
  • FIG. 5B shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the region R1 of this example indicates a region corresponding to ⁇ 10% of the reference line L1.
  • the reference line L1 is the same as the reference line L1 in FIG. 5A.
  • the line A1 and the line B1 of this example are represented by the following equations.
  • Line A1: y1 (-6.9487E-01) ln (x) + (2.5930E + 01)
  • Line B1: y1 (-5.2115E-01) ln (x) + (1.9540E + 01)
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 may be set so as to belong to the region R1.
  • FIG. 5C shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the region R1 of this example indicates a region corresponding to ⁇ 5% of the reference line L1.
  • the reference line L1 is the same as the reference line L1 in FIG. 5A.
  • the line A1 and the line B1 of this example are represented by the following equations.
  • Line A1: y1 (-6.4710E-01) ln (x) + (2.4190E + 01)
  • Line B1: y1 (-5.6458E-01) ln (x) + (2.1130E + 01)
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 may be set so as to belong to the region R1 of this example.
  • FIG. 6A shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the reference line L1, the line A, and the line B are the same as each line in FIG. 5A. That is, the region corresponding to ⁇ 15% of the reference line L1 is shown.
  • the region R1 of this example indicates a region in which the integrated concentration of the collector region 22 is 3.00E14 cm- 2 or less.
  • the depth of the first peak P1 may be 2.0 ⁇ m or more and 7.2 ⁇ m or less.
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 may be set so as to belong to the region R1 of this example.
  • FIG. 6B shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the reference line L1, the line A, and the line B are the same as each line in FIG. 5A. That is, the region corresponding to ⁇ 15% of the reference line L1 is shown.
  • the region R1 of this example indicates a region in which the integrated concentration of the collector region 22 is 2.00E 14 cm -2 or less.
  • the depth of the first peak P1 may be 2.2 ⁇ m or more and 7.2 ⁇ m or less.
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 may be set so as to belong to the region R1 of this example.
  • FIG. 6C shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the reference line L1, the line A, and the line B are the same as each line in FIG. 5A. That is, the region corresponding to ⁇ 15% of the reference line L1 is shown.
  • the region R1 of this example indicates a region in which the integrated concentration of the collector region 22 is 1.00E14 cm- 2 or less.
  • the depth of the first peak P1 may be 2.5 ⁇ m or more and 7.2 ⁇ m or less.
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 may be set so as to belong to the region R1 of this example.
  • FIG. 6D shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the reference line L1, the line A, and the line B are the same as each line in FIG. 5A. That is, the region corresponding to ⁇ 15% of the reference line L1 is shown.
  • the region R1 of this example indicates a region in which the integrated concentration of the collector region 22 is 5.00E13 cm- 2 or less.
  • the depth of the first peak P1 may be 3.0 ⁇ m or more and 7.2 ⁇ m or less.
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 may be set so as to belong to the region R1 of this example.
  • FIG. 6E shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the reference line L1, the line A, and the line B are the same as each line in FIG. 5A. That is, the region corresponding to ⁇ 15% of the reference line L1 is shown.
  • the region R1 of this example indicates a region in which the integrated concentration of the collector region 22 is 3.00E13 cm- 2 or less.
  • the depth of the first peak P1 may be 3.2 ⁇ m or more and 7.2 ⁇ m or less.
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 may be set so as to belong to the region R1 of this example.
  • FIG. 6F shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the first peak P1.
  • the reference line L1, the line A, and the line B are the same as each line in FIG. 5A. That is, the region corresponding to ⁇ 15% of the reference line L1 is shown.
  • the region R1 of this example indicates a region in which the integrated concentration of the collector region 22 is 1.00E13 cm- 2 or less.
  • the depth of the first peak P1 may be 3.6 ⁇ m or more and 7.2 ⁇ m or less.
  • the depth of the first peak P1 and the integrated concentration of the collector region 22 may be set so as to belong to the region R1 of this example.
  • the range of the integrated concentration of the collector region 22 may be limited as shown in FIGS. 6A to 6F.
  • the region R1 may be a region in which the integrated concentration of the collector region 22 is 1.00E14cm- 2 or less, may be a region of 5.00E13cm- 2 or less, and may be 3.00E13cm ⁇ . It may be a region of 2 or less, and may be a region of 1.00E 13 cm -2 or less.
  • FIG. 7A shows the relationship between the integrated concentration of the collector region 22 and the depth of the second peak P2.
  • the vertical axis shows the depth y2 [ ⁇ m] of the second peak P2, and the horizontal axis shows the integrated concentration x [cm -2 ] of the collector region 22.
  • the next reference line L2 was calculated based on the data of the two points where the acceleration energy of the shallowest proton and the maximum clamp energy were obtained in FIG. 3A.
  • Reference line L2: y2 (-2.4885E + 00) ln (x) + (9.1580E + 01) That is, the reference line L2 shows the relationship between the integrated concentration of the collector region 22 where the clamping energy is maximized and the depth of the second peak P2 where the clamping energy is maximized.
  • the region R2 indicates a region in the range of ⁇ 15% of the reference line L2.
  • the region R2 of this example is a region between the line A2 and the line B2.
  • the line A2 and the line B2 of this example are represented by the following equations.
  • Line A2: y2 (-3.1095E + 00) ln (x) + (1.1416E + 02)
  • Line B2: y2 (-1.9239E + 00) ln (x) + (7.1030E + 01)
  • the depth of the second peak P2 and the integrated concentration of the collector region 22 belong to the region R2.
  • the clamping energy is sufficiently high.
  • the depth of the second peak P2 may be 3.5 ⁇ m or more and 28 ⁇ m or less.
  • FIG. 7B shows another example of the relationship between the integrated concentration of the collector region 22 and the depth of the second peak P2.
  • the region R2 of this example indicates a region corresponding to ⁇ 10% of the reference line L2.
  • the reference line L2 is the same as the reference line L2 in FIG. 7A.
  • the line A2 and the line B2 of this example are represented by the following equations.
  • Line A2: y2 (-2.8924E + 00) ln (x) + (1.0629E + 02)
  • Line B2: y2 (-2.1020E + 00) ln (x) + (7.7530E + 01)
  • the depth of the second peak P2 and the integrated concentration of the collector region 22 may be set so as to belong to the region R2.
  • FIG. 7C shows the relationship between the integrated concentration of the collector region 22 and the depth of the second peak P2.
  • the region R2 of this example indicates a region corresponding to ⁇ 5% of the reference line L2.
  • the reference line L2 is the same as the reference line L2 in FIG. 7A.
  • the line A2 and the line B2 of this example are represented by the following equations.
  • Line A2: y2 (-2.4885E + 00) ln (x) + (9.1580E + 01)
  • Line B2: y2 (-2.2931E + 00) ln (x) + (8.4470E + 01)
  • the depth of the second peak P2 and the integrated concentration of the collector region 22 may be set so as to belong to the region R2.
  • the range of the integrated concentration of the collector region 22 may be limited as shown in FIGS. 6A to 6F.
  • the area R2 can be a region integration density of 1.00E14cm -2 or less of the collector region 22 may be a 5.00E13cm -2 following areas, 3.00E13cm - It may be a region of 2 or less, and may be a region of 1.00E 13 cm -2 or less.
  • FIG. 8A is a diagram for explaining the relationship between the stray inductance Ls and the collector current reduction rate dIce / dt.
  • the stray inductance Ls is Xc [nH]
  • the collector current reduction rate dIce / dt is Yc [A / ⁇ s].
  • the stray inductance Ls and the collector current reduction rate dIce / dt are set in a range larger than that of the line C1.
  • the range larger than the line C1 refers to a region located above the line C1 in the graph showing the relationship between the stray inductance Ls and the collector current reduction rate dIce / dt.
  • the area larger than the line C1 is the area filled with the pattern.
  • the stray inductance Ls and the collector current reduction rate dIce / dt may be set in a range larger than that of the line C2.
  • the line C2 is represented by the following equation.
  • Line C2: Yc 20000Xc -1
  • the stray inductance Ls and the collector current reduction rate dIce / dt may be set in a range larger than that of the line C3.
  • the line C3 is represented by the following equation.
  • Line C3: Yc 50000Xc -1
  • the semiconductor device 100 of this example can prevent instantaneous fracture even when the stray inductance Ls and the collector current reduction rate dIce / dt are set in a range larger than any of the wires C1 to C3.
  • FIG. 8B is a diagram for explaining the relationship between the specific stray inductance Ls ⁇ A and the current density dJce / dt.
  • the specific stray inductance Ls ⁇ A is Xd [nH cm 2 ]
  • the current density dJce / dt is Yd [A / (cm 2 ⁇ s)].
  • the specific stray inductance Ls ⁇ A is a unique value obtained by multiplying the stray inductance Ls by the area A (cm 2) of the active region 110.
  • the current density dJce / dt is a value obtained by dividing the collector current reduction rate dIce / dt by the area A (cm 2) of the active region 110.
  • the specific stray inductance Ls ⁇ A and the current density dJce / dt are set in a range larger than the line D1.
  • the line D1 is represented by the following equation.
  • Line D1: Yd 10000Xd -1
  • the specific stray inductance Ls ⁇ A and the current density dJce / dt may be set in a range larger than the line D2.
  • the line D2 is represented by the following equation.
  • Line D2: Yd 20000Xd -1
  • the specific stray inductance Ls ⁇ A and the current density dJce / dt may be set in a range larger than the line D3.
  • the line D3 is represented by the following equation.
  • Line D3: Yd 50000Xd -1
  • the semiconductor device 100 of this example can prevent instantaneous fracture even when the stray inductance Ls and the collector current reduction rate dIce / dt are set in a range larger than any of the wires D1 to D3.
  • FIG. 9 is a diagram for explaining the relationship between the specific stray inductance Ls ⁇ A and the specific gate resistance Rg ⁇ A.
  • the specific stray inductance Ls ⁇ A is Xe [nH cm 2 ]
  • the specific gate resistance Rg ⁇ A is Ye [ ⁇ cm 2 ].
  • the specific gate resistance Rg ⁇ A is a unique value obtained by multiplying the gate resistance Rg of the drive circuit of the semiconductor device 100 by the area A (cm 2) of the active region 110.
  • the collector current reduction rate dIce / dt changes not only with the stray inductance Ls but also with the gate resistance Rg of the drive circuit of the semiconductor device 100. As the gate resistance Rg decreases, the collector current decrease rate dIce / dt tends to increase.
  • the specific stray inductance Ls ⁇ A and the specific gate resistance Rg ⁇ A may be set in a range of the line E1 or less.
  • the line E1 is represented by the following equation.
  • Line E1: Ye (4.00E-01) Xe
  • the specific stray inductance Ls ⁇ A and the specific gate resistance Rg ⁇ A may be set in a range of the line E2 or less.
  • the line E2 is expressed by the following equation.
  • Line E2: Ye (2.00E-01) Xe
  • the specific stray inductance Ls ⁇ A and the specific gate resistance Rg ⁇ A may be set in a range of the line E3 or less.
  • the line E3 is represented by the following equation.
  • Line E3: Ye (8.00E-02) Xe
  • the semiconductor device 100 of this example can prevent instantaneous fracture even when the specific stray inductance Ls ⁇ A and the specific gate resistance Rg ⁇ A are set in the range of any of the wires E1 to E3 or less.

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