WO2021259204A1 - 显示面板及其驱动方法、显示装置 - Google Patents

显示面板及其驱动方法、显示装置 Download PDF

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Publication number
WO2021259204A1
WO2021259204A1 PCT/CN2021/101259 CN2021101259W WO2021259204A1 WO 2021259204 A1 WO2021259204 A1 WO 2021259204A1 CN 2021101259 W CN2021101259 W CN 2021101259W WO 2021259204 A1 WO2021259204 A1 WO 2021259204A1
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sub
data
time
pixels
time period
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PCT/CN2021/101259
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English (en)
French (fr)
Inventor
董甜
王博
王景泉
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京东方科技集团股份有限公司
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Priority to US17/794,400 priority Critical patent/US11996055B2/en
Publication of WO2021259204A1 publication Critical patent/WO2021259204A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
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    • G09G2320/00—Control of display operating conditions
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    • G09G2320/0252—Improving the response speed

Definitions

  • the present disclosure relates to the field of display technology, for example, to a display panel, a driving method thereof, and a display device.
  • VR Virtual Reality, virtual reality
  • Existing display panels can be used to implement VR display and game screen display.
  • both VR display and game mode require the display panel to increase a higher refresh rate.
  • a display panel in one aspect, includes a sub-pixel array, a plurality of gate lines, a plurality of first data lines, a plurality of second data lines, a pixel control circuit, and a time division multiplexing circuit.
  • the sub-pixel array includes a plurality of sub-pixels arranged in multiple rows and multiple columns. The sub-pixels in the same row are coupled to the pixel control circuit through at least one gate line. Sub-pixels located in odd-numbered rows in the same column of sub-pixels are coupled to a first data line, and sub-pixels located in even-numbered rows in the same column of sub-pixels are coupled to a second data line.
  • the time division multiplexing circuit is respectively coupled to the plurality of first data lines, the plurality of second data lines, and the data signal terminal.
  • the time-division multiplexing circuit is configured to electrically conduct the data signal terminal with the first data line and the second data line in a time-division manner.
  • the time division multiplexing circuit includes: at least two strobe branches, a first end of the strobe branch is coupled to the data signal end, and a second end of the strobe branch is coupled to at least One of the first data lines or at least one of the second data lines is coupled. All the gated branches are configured to be turned on in different time periods, and the conduction time periods of all the gated branches are arranged in sequence and do not overlap with each other.
  • the at least two gating branches include: a first gating branch and a second gating branch.
  • the first end of the first gating branch is coupled to the data signal end, and the second end of the first gating branch is coupled to all the first data lines.
  • the first strobe branch is configured to electrically conduct the data signal terminal with all the first data lines in a first time period.
  • the first end of the second strobe branch is coupled to the data signal end, the second end of the second strobe branch is coupled to all the second data lines, and the second strobe The branch is configured to electrically conduct the data signal terminal with all the second data lines in a second time period.
  • the first time period and the second time period are arranged in sequence and do not overlap.
  • the at least two gated branches include: a first gated branch, a second gated branch, a third gated branch, and a fourth gated branch.
  • the first end of the first gating branch is coupled to the data signal end, and the second end of the first gating branch is coupled to all the first data lines coupled to odd-numbered columns of sub-pixels .
  • the first strobe branch is configured to electrically conduct the data signal terminal and all the first data lines coupled to the odd-numbered column sub-pixels in a first time period.
  • the first end of the second gating branch is coupled to the data signal end, and the second end of the second gating branch is coupled to all the first data lines that are coupled to even-numbered columns of sub-pixels .
  • the second gate branch is configured to electrically conduct the data signal terminal and all the first data lines coupled to the even-numbered column sub-pixels in a second time period.
  • the first end of the third gating branch is coupled to the data signal end, and the second end of the third gating branch is coupled to all the second data lines coupled to odd columns of sub-pixels .
  • the third gate branch is configured to electrically conduct the data signal terminal and all the second data lines coupled to the odd-numbered column sub-pixels in a third time period.
  • the first end of the fourth gating branch is coupled to the data signal end, and the second end of the fourth gating branch is coupled to all the second data lines coupled to even-numbered columns of sub-pixels .
  • the fourth strobe branch is configured to electrically conduct the data signal terminal and all the second data lines coupled to the even-numbered column sub-pixels in a fourth time period.
  • the first time period, the second time period, the third time period, and the fourth time period are arranged in sequence without overlapping each other.
  • the data signal terminal includes a plurality of sub data signal terminals, and one sub data signal terminal is simultaneously coupled to one data line among all the data lines connected to each strobe branch.
  • the first data line connected to the sub-pixels in each column is located on the first side of the sub-pixels in the column, and the second data line connected to the sub-pixels in each column is located in the column. The second side of the sub-pixel.
  • the first data line connected to the sub-pixels in the odd-numbered column is located on the first side of the sub-pixel in the column
  • the second data line connected to the sub-pixels in the odd-numbered column is located in the Columns the second side of the sub-pixels.
  • the first data line connected to the sub-pixels of the even-numbered column is located on the second side of the sub-pixels of the column
  • the second data line connected to the sub-pixels of the even-numbered column is located on the second side of the sub-pixels of the column. The first side.
  • a display device comprising: the display panel described in any one of the above.
  • a method for driving a display panel for driving the display panel described in any one of the above, and the driving method includes: time-sharing the data signal terminal with the time-sharing multiplexing circuit through the time-division multiplexing circuit.
  • the first data line and the second data line are electrically connected, so that the data signal output by the data signal terminal is input to the first data line and the second data line in a time-division manner.
  • the pixel control circuit is used to input gate control signals to the sub-pixels in each row in a time-sharing manner, so that the pixel circuits in the sub-pixels in each row are turned on; and the gate control is input to the sub-pixels in two adjacent rows
  • the signal input period of the signal partially overlaps. According to the conduction status of the pixel circuits in the sub-pixels in each row, the data signal is input to the sub-pixels in each row in a time-sharing manner through the first data line and the second data line.
  • the time division multiplexing circuit includes: at least two strobe branches.
  • the data signal terminal is electrically connected to the first data line and the second data line in a time-division manner through the time-division multiplexing circuit, so that the data signal output by the data signal terminal is time-divisionally input
  • the first data line and the second data line include: controlling the conduction of different gate branches in different time periods, and the conduction time periods of all the gate branches are arranged in sequence and do not overlap each other.
  • the start time of the period of electrical conduction between the data line connected to the sub-pixel and the data signal terminal is before the start time of the signal input period of the gate control signal of the sub-pixel.
  • the end time of the period of electrical conduction between the data line connected to the sub-pixel and the data signal terminal is before the end of the signal input period of the gate control signal of the sub-pixel.
  • the data line is the first data line or the second data line.
  • the at least two gating branches include: a first gating branch and a second gating branch.
  • the data signal terminal is electrically connected to the first data line and the second data line in a time-division manner through the time-division multiplexing circuit, so that the data signal output by the data signal terminal is time-divisionally input
  • the first data line and the second data line include: in a first time period, the data signal terminal is electrically connected to all the first data lines through the first strobe branch, so that all the first data lines are electrically connected to each other.
  • the data signal output from the data signal terminal is input to all the first data lines.
  • the data signal terminal is electrically connected to all the second data lines through the second gating branch, so that the data signal output by the data signal terminal is input to all the second data lines .
  • the first time period and the second time period are arranged in sequence and do not overlap.
  • the start time of the first time period is before the start time of the signal input time period of the gate control signal of the sub-pixel in the first row
  • the end time of the first time period is Before the end time of the signal input period of the gate control signal of the sub-pixels in the first row
  • the start time of the second time period is before the start time of the signal input time period of the gate control signal of the sub-pixel in the second row, and the end time of the second time period is in the second row. Before the end of the signal input period of the gate control signal of the pixel.
  • the at least two gated branches include: a first gated branch, a second gated branch, a third gated branch, and a fourth gated branch.
  • the data signal terminal is electrically connected to the first data line and the second data line in a time division manner by the time division multiplexing circuit, so that the data signal output by the data signal terminal is input in a time division manner
  • the first data line and the second data line include: in a first time period, the data signal terminal is coupled to all the first sub-pixels in odd columns through the first strobe branch.
  • the data line is electrically turned on, so that the data signal output from the data signal terminal is input to all the first data lines coupled to the odd-numbered column sub-pixels.
  • the data signal terminal and all the first data lines coupled to the even-numbered column sub-pixels are electrically conducted through the second gating branch, so that the data signal output by the data signal terminal is input All the first data lines coupled to even-numbered columns of sub-pixels.
  • the data signal terminal and all the second data lines coupled to the odd-numbered column sub-pixels are electrically conducted through the third gating branch, so that the data signal output by the data signal terminal is input All the second data lines coupled to the odd columns of sub-pixels.
  • the data signal terminal and all the second data lines coupled to the even-numbered column sub-pixels are electrically conducted through the fourth gate branch, so that the data signal output from the data signal terminal is input to the even-numbered sub-pixels. All the second data lines coupled to the column sub-pixels.
  • the first time period, the second time period, the third time period, and the fourth time period are arranged in sequence without overlapping each other.
  • the start time of the first time period is before the start time of the signal input time period of the gate control signal of the sub-pixel in the first row.
  • the end time of the second time period is before the end time of the signal input time period of the gate control signal of the sub-pixel in the first row.
  • the start time of the third time period is before the start time of the signal input time period of the gate control signal of the sub-pixel in the second row.
  • the end time of the fourth time period is before the end time of the signal input time period of the gate control signal of the sub-pixel in the second row.
  • the end time of the first time period is before the start time of the signal input time period of the gate control signal of the sub-pixel in the first row.
  • the start time of the second time period is before the start time of the signal input time period of the gate control signal of the sub-pixel in the first row.
  • the end time of the third time period is before the start time of the signal input time period of the gate control signal of the sub-pixel in the second row.
  • the start time of the fourth time period is before the start time of the signal input time period of the gate control signal of the sub-pixel in the second row.
  • the end time of the signal input time period of the gate control signal of the sub-pixels in the first row is before the start time of the next first time period.
  • the end time of the signal input time period of the gate control signal of the sub-pixels in the second row is before the start time of the next third time period.
  • FIG. 1 is a structural diagram of a display device provided by some embodiments.
  • FIG. 2 is a structural diagram of a display panel provided by some embodiments.
  • FIG. 3 is a structural diagram of another display panel provided by some embodiments.
  • FIG. 4 is a structural diagram of yet another display panel provided by some embodiments.
  • FIG. 5 is a structural diagram of still another display panel provided by some embodiments.
  • FIG. 6 is a flowchart of a method for driving a display panel provided by some embodiments.
  • FIG. 7 is a signal timing diagram of the gate signal and the gate control signal corresponding to the display panel in FIG. 3;
  • FIG. 8 is a signal timing diagram of the gate signal and the gate control signal corresponding to the display panel in FIG. 4.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • an OLED Organic Light-Emitting Diode, organic light-emitting diode
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • each sub-pixel unit includes a pixel circuit
  • the threshold voltage Vth of the driving transistor in each pixel circuit Since the difference in the manufacturing process or the temperature change will cause a drift phenomenon, resulting in poor display, it is necessary to compensate the threshold voltage Vth of the driving transistor.
  • the compensation time is equal to the data writing time.
  • Both VR display and game modes require the display panel to provide a higher refresh frequency.
  • the display panel's refresh frequency is higher (for example, 120Hz)
  • the line cycle is shortened, the data writing time is shortened, and the Vth compensation time is greatly reduced, resulting in a significant impact on the pixel circuit.
  • the compensation of the Vth of the middle driving transistor is insufficient, which affects the display effect.
  • the number of data channels required for driver IC is increasing (each data channel corresponds to a data line), and some display panels (for example, medium-sized The display panel may require two ICs for driving, which greatly increases the cost of the display panel.
  • the display device 10 includes a display panel 1 provided by some embodiments of the present disclosure.
  • the display device 10 may be a mobile phone, a tablet computer, a notebook computer, an ultra-mobile personal computer (UMPC), a handheld computer, a netbook, a personal digital assistant (PDA), a wearable device, and a virtual reality device.
  • UMPC ultra-mobile personal computer
  • PDA personal digital assistant
  • the present disclosure does not specifically limit the use of the display device 10.
  • the display device 10 may be an electroluminescence display or a photoluminescence display.
  • the electroluminescent display may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED) .
  • the photoluminescence display may be a quantum dot photoluminescence display device.
  • the display panel 1 can be used in any of the above-mentioned display devices 10.
  • the display panel 1 includes: a sub-pixel array 101, a plurality of gate lines 102, a plurality of first data lines 103, a plurality of second data lines 104, a pixel control circuit 105 and a time division multiplexing circuit 106.
  • the sub-pixel array 101 includes a plurality of sub-pixels (Pixel as shown in FIG. 2) arranged in multiple rows and multiple columns; the sub-pixels in the same column are coupled to the pixel control circuit 105 through at least one gate line 102.
  • the sub-pixels in the odd-numbered rows of the same column are coupled to the first data line 103, and the sub-pixels in the even-numbered rows in the same column of sub-pixels are coupled to the second data line 104.
  • the time division multiplexing circuit 106 is respectively coupled to a plurality of first data lines 103, a plurality of second data lines 104, and a data signal terminal 107.
  • the time-division multiplexing circuit is configured to electrically conduct the data signal terminal with the first data line and the second data line in a time-division manner.
  • the data signal terminal 107 is arranged on the driver IC, and the data signal terminal 107 corresponds to the data channel of the driver IC and is used to output the data signal of the driver IC.
  • the display panel provided in some embodiments of the present disclosure can implement the time-division writing of the data signal output from the data signal terminal to the first data line and the second data line through
  • one data signal terminal can be coupled to multiple data lines.
  • Time operation realizes the driving of multiple data lines, thereby reducing the number of data channels of the driving IC or the number of driving ICs.
  • time division multiplexing circuit data signals can be written to multiple data lines at a time, thereby reducing the output frequency of the data signal of the driver IC, so as to achieve a higher refresh frequency of the display panel, which is more suitable for scenes with higher refresh frequency requirements .
  • the signal input time periods of the gate control signals of two adjacent rows of sub-pixels can be partially overlapped, thereby prolonging the compensation time for the threshold voltage Vth of the driving transistor. Solve the problem of insufficient compensation of the Vth of the driving transistor.
  • the time division multiplexing circuit 106 includes: at least two strobe branches, the first end of the strobe branch is coupled to the data signal terminal 107, and the second end of the strobe branch is coupled to at least one first end of the strobe branch.
  • a data line 103 or at least one second data line 104 is coupled.
  • the gated branches are configured to be turned on in different time periods respectively, and all the gated branches are arranged in turn on time periods without overlapping each other.
  • the time-division multiplexing circuit can time-division and conduct different strobe branches, thereby transmitting the data signal at the data signal end to the data line connected to the strobe branch in a time-division manner, and write data to the sub-pixels connected to the data line Signal.
  • Different strobe branches are turned on sequentially, and the turn-on time periods do not overlap, so that data signals can be sequentially written to different parts of the sub-pixels in a specific sequence in a cycle.
  • the above-mentioned "at least two strobe branches” include: the first strobe branch 108 (that is, the branch connected to the strobe signal MUX1 in FIG. 3) and the second strobe branch.
  • Branch 109 (that is, the branch connected to the strobe signal MUX2 in FIG. 3).
  • the first end of the first strobe branch 108 is coupled to the data signal terminal 107, and the second end of the first strobe branch 108 is coupled to all the first data lines 103.
  • the first strobe branch 108 is configured to electrically conduct the data signal terminal 107 with all the first data lines 103 during the first time period.
  • the first end of the second strobe branch 109 is coupled to the data signal terminal 107, the second end of the second strobe branch 109 is coupled to all the second data lines 104, and the second strobe branch 109 is configured as
  • the data signal terminal 107 is electrically connected to all the second data lines 104 in the second time period.
  • the first time period and the second time period are arranged in sequence and do not overlap.
  • FIG. 3 shows a four-row and four-column sub-pixel array and various circuits and connecting lines coupled to the sub-pixel array. It is only used as an example and is not used to limit the scope of the present disclosure. It can be understood in the art that The circuit connection relationship of can be extended to a sub-pixel array of m rows and n columns, and both m and n can be greater than 4.
  • one data channel of the driver IC can realize the time-sharing driving of two data lines (that is, a first data line and a second data line), so that the number of data channels can be reduced half.
  • the above-mentioned "at least two strobe branches” include: the first strobe branch 110 (that is, the branch connected to the strobe signal MUX1 in the figure), the second The gate branch 111 (that is, the branch connected to the gate signal MUX2 in the figure), the third gate branch 112 (that is, the branch connected to the gate signal MUX3 in the figure), and the fourth gate branch 113 ( That is, the branch connected to the strobe signal MUX4 in the figure).
  • the first end of the first strobe branch 110 is coupled to the data signal end 107, the second end of the first strobe branch 110 and all the first data coupled to the odd column sub-pixels Line 103 is coupled.
  • the first gate branch 110 is configured to electrically conduct the data signal terminal 107 and all the first data lines 103 coupled to the odd-numbered column sub-pixels in the first time period.
  • the first end of the second gating branch 111 is coupled to the data signal end 107, and the second end of the second gating branch 111 is coupled to all the first data lines 103 coupled to the sub-pixels of the even-numbered columns.
  • the second gate branch 111 is configured to electrically conduct the data signal terminal 107 and all the first data lines 103 coupled to the even-numbered column sub-pixels in the second time period.
  • the first end of the third gating branch 112 is coupled to the data signal end 107, and the second end of the third gating branch 112 is coupled to all the second data lines 104 coupled to the odd columns of sub-pixels.
  • the third gate branch 112 is configured to electrically conduct the data signal terminal 107 and all the second data lines 104 coupled to the odd-numbered column sub-pixels in the third time period.
  • the first end of the fourth gating branch 113 is coupled to the data signal end 107, and the second end of the fourth gating branch 113 is coupled to all the second data lines 104 coupled to the even-numbered columns of sub-pixels.
  • the fourth gate branch 113 is configured to electrically conduct the data signal terminal 107 and all the second data lines 104 coupled to the even-numbered column sub-pixels in the fourth time period.
  • the first time period, the second time period, the third time period, and the fourth time period are arranged in sequence and do not overlap.
  • one data channel of the driver IC can realize the time-sharing driving of four data lines (two first data lines and two second data lines), so that the two strobe branches can be driven in a time-sharing manner.
  • the number of data channels is further reduced by half.
  • the pixel control circuit 105 includes at least one scan signal shift register circuit (Gate Driver On Array, Gate GOA) for providing scan signals.
  • At least one scan signal shift register circuit is coupled to each sub-pixel row through a gate line (it can be one scan signal shift register circuit coupled to multiple rows of sub-pixels, or multiple scan signal shift register circuits are connected to multiple rows). Row sub-pixels are coupled) for driving each row of sub-pixels.
  • the pixel control circuit 105 includes a gate drive circuit R/G GOA_O for driving sub-pixels in odd rows and a gate drive circuit R/G GOA_E for driving sub-pixels in even rows .
  • R/G GOA_O and R/G GOA_E output a gate control signal (Gate signal) to drive the connected row of sub-pixels.
  • the pixel control circuit 105 also includes an emission control signal shift register circuit (EM GOA) for providing emission control signals.
  • the emission control signal shift register circuit (EM GOA) can pass The light emission control line 108 in the display panel is coupled to each sub-pixel unit in each sub-pixel row.
  • EM GOA light emitting control signal shift register circuit
  • EM GOA2 multiple emission control signal shift register circuits
  • EM GOA can be arranged in the same sub-pixel array 101, or can be separately arranged on both sides of the sub-pixel array 101 as shown in FIGS. 3 to 5.
  • each gating branch includes a plurality of gating devices 114, and the control terminal of each gating device 114 is coupled to a strobe signal control circuit to receive the selection.
  • the first end of each gating device 114 is coupled to the corresponding first data line 103 or the second data line 104, and the second end is coupled to the data signal end 107.
  • the control ends of the two gating devices 114 are coupled to the strobe signal control circuit, and receive the strobe signal MUX1;
  • a first end of a strobe device 114 is coupled to the first data line 103 of the first column (that is, the first data line 103 coupled to each sub-pixel in the odd-numbered row of the first column), and the second end is coupled to the Data1 end
  • the first end of the second strobe device 114 is coupled to the first data line 103 of the third column (that is, the first data line 103 coupled to each sub-pixel in the third column of odd rows), and the second end is coupled to Data2 terminal is coupled.
  • the connection modes of the strobe devices in the other strobe branches are the same, and will not be repeated here.
  • the gate device 114 may be a P-type or N-type transistor.
  • the display panel further includes a strobe signal control circuit for outputting a strobe signal.
  • the data line can store the data signal to be written.
  • the data signal can be written into the corresponding sub-pixel.
  • the data signal terminal 107 includes multiple sub-data signal terminals (ie Data1, Data2, Data3, and Data4 in FIG. 3, Data1 and Data2 in FIG. 4, and Data2 in FIG. 5).
  • Data1 and Data2 a sub-data signal terminal is simultaneously coupled to one of all the data lines connected to each strobe branch.
  • Each sub-data signal terminal corresponds to a data channel of the driver IC, and different data lines in a strobe branch are connected to different sub-data signal terminals, so that all data lines on a strobe branch are written differently in the same time period. Data signal.
  • the first strobe branch 108 is coupled to all the first data lines 103
  • the second strobe branch 109 is coupled to all the second data lines 104
  • the data signal terminal 107 includes four There are two sub-data signal terminals, namely Data1, Data2, Data3 and Data4 in Figure 3.
  • Data1 is simultaneously coupled to the first first data line 103 coupled to the first strobe branch 108 and the first second data line 104 coupled to the second strobe branch 109 at the same time.
  • Data2 is coupled to the second first data line 103 coupled to the first strobe branch 108 and the second second data line 104 coupled to the second strobe branch 109 at the same time.
  • Data3 is simultaneously coupled to the third first data line 103 coupled to the first strobe branch 108 and the third second data line 104 coupled to the second strobe branch 109.
  • Data4 is simultaneously coupled to the fourth first data line 103 coupled to the first strobe branch 108 and the fourth second data line 104 coupled to the second strobe branch 109 at the same time. This arrangement allows the sub-pixels in the same row to input different data signals.
  • the first gate branch 110 is coupled to all the first data lines 103 corresponding to the odd-numbered columns of sub-pixels
  • the second gate branch 111 corresponds to the even-numbered columns of sub-pixels. All the first data lines 103 are coupled to each other
  • the third gate branch 112 is coupled to all the second data lines 104 corresponding to the odd-numbered column sub-pixels
  • the fourth gate branch 113 is coupled to all the second data lines corresponding to the even-numbered column sub-pixels.
  • the data line 104 is coupled.
  • the data signal terminal 107 includes two sub data signal terminals, namely Data1 and Data2 in FIG. 4, and Data1 and Data2 in FIG.
  • Data1 is simultaneously coupled to the first first data line 103 coupled to the first strobe branch 110, and the first first data line 103 and third strobe branch 112 coupled to the second strobe branch 111.
  • the coupled first second data line 104 and the first second data line 104 coupled by the fourth strobe branch 113 are coupled.
  • Data2 is simultaneously coupled with the second first data line 103 coupled to the first strobe branch 110, the second first data line 103 coupled to the second strobe branch 111, and the third strobe branch 112 coupled at the same time
  • the second second data line 104 is coupled to the second second data line 104 coupled to the fourth strobe branch 113.
  • This setting method can write different data signals to the data lines connected to each strobe branch in the same time period.
  • the first data line 103 connected to each column of sub-pixels is located on the first side of the column of sub-pixels
  • the second data line 104 connected to each column of sub-pixels is located on the second side of the column of sub-pixels. side.
  • Each column of sub-pixels is connected to a first data line and a second data line, and the two data lines are respectively located on both sides of the column of sub-pixels.
  • Such a wiring layout can make multiple data lines arranged uniformly and orderly, and is beneficial to the actual Production production.
  • the first data line 103 connected to the sub-pixels in the odd-numbered column is located on the first side of the sub-pixels in the column
  • the second data line 104 connected to the sub-pixels in the odd-numbered column is located on the first side of the sub-pixels in the column.
  • the first data line 103 connected to the sub-pixels of the even-numbered column is located on the second side of the sub-pixels of the column
  • the second data line 104 connected to the sub-pixels of the even-numbered column is located on the first side of the sub-pixels of the column.
  • circuit connection relationship shown in FIG. 4 is the same as the circuit connection relationship shown in FIG. 5, and the difference lies only in the distribution of the data lines.
  • Some embodiments of the present disclosure provide a driving method of a display panel, which is used to drive the display panel provided in any of the above-mentioned embodiments. As shown in FIG. 6, the driving method includes:
  • the data signal terminal 107 is electrically connected to the first data line 103 and the second data line 104 in a time-division manner through the time-division multiplexing circuit 106, so that the data signal output from the data signal terminal 107 is time-divisionally input to the first data line 103 ⁇ 104 ⁇ And the second data line 104.
  • S302 Time-sharing input of gate control signals to each row of sub-pixels through the pixel control circuit 105, so that the pixel circuits in each row of sub-pixels are turned on.
  • the signal input time periods for inputting gate control signals to two adjacent rows of sub-pixels partially overlap.
  • the time-division multiplexing circuit can time-divisionally connect different data lines to the data signal terminal, the data signal can be written into the sub-pixels in a time-division manner. Based on this arrangement, two adjacent sub-pixel rows are input gate-level control The signal input time period of the signal can be set in a partially overlapping form, so that the compensation time for each sub-pixel can be prolonged, and the Vth compensation ability for each pixel can be improved.
  • the time division multiplexing circuit includes: at least two strobe branches.
  • the data signal terminal 107 is electrically connected to the first data line 103 and the second data line 104 in a time-division manner through a time-division multiplexing circuit, so that the data signal output from the data signal terminal 107 is time-divisionally input to the first data line 103 and the first data line 103 and the second data line.
  • the second data line 104 includes: controlling the conduction of different strobe branches in different time periods, and the conduction time periods of all strobe branches are arranged in sequence and do not overlap each other.
  • the time-division multiplexing circuit includes at least two strobe branches. Different strobe branches are coupled to different data lines, and different strobe branches are connected to different data lines in a time-sharing manner, so that they can be paired. Pixels write data signals in time sharing.
  • the start time of the electrical conduction period between the data line and the data signal terminal of the sub-pixel is before the start time of the signal input period of the gate control signal of the sub-pixel.
  • the end time of the period of electrical conduction between the data line and the data signal terminal of the sub-pixel is before the end of the signal input period of the gate control signal of the sub-pixel.
  • the data line is the first data line or the second data line.
  • the data signal is written first through the data line, and then the gate control signal is written through the gate line, and the data signal writing should be completed before the end of the gate signal, so that the corresponding sub-pixel can work normally.
  • the above-mentioned “at least two gate branches” include: the first gate branch 108 and the second gate branch 109.
  • S301 specifically includes the following process: in the first time period t 1 , the data signal terminal 107 is electrically connected to all the first data lines 103 through the first strobe branch 108, so that the data signal output by the data signal terminal 107 is input to all the first data lines 103.
  • the data signal terminal 107 is electrically connected to all the second data lines 104 through the second strobe branch 109, so that the data signal output by the data signal terminal 107 is input to all the second data lines 104;
  • the first time period t 1 and the second time period t 2 are arranged in sequence and do not overlap.
  • the start time of the first time period t 1 is in the signal input time period of the gate control signal of the first row of sub-pixels (that is, the third time period t 3 in FIG. 7).
  • the end time of the first time period t 1 is before the end time of the signal input time period of the gate control signal of the first row of sub-pixels (that is, the third time period t 3 in FIG. 7 ).
  • the start time of the second time period t 2 is before the start time of the signal input time period of the gate control signal to the second row of sub-pixels (that is, the fourth time period t 4 in FIG. 7 ), and the second time period t
  • the end time of 2 is before the end time of the signal input period of the gate control signal of the second row of sub-pixels (that is, the fourth period t 4 in FIG. 7 ).
  • This arrangement can ensure that the sub-pixel writes the data signal through the data line first, and then writes the gate control signal through the gate line, and the data signal writing should be completed before the gate signal ends, so that the corresponding sub-pixel is normal Work.
  • the gate device 114 uses a P-type transistor.
  • the MUX1 signal is at low level
  • the first strobe branch 108 connects the four sub-signal data terminals Data1, Data2, and Data3 after receiving the MUX1 signal.
  • the terminal and the Data4 terminal are respectively electrically connected to the first data line 103, and the data signals Data1, Data2, Data3, and Data4 are respectively written into the corresponding first data line 103 and stored.
  • the MUX1 signal is high
  • the MUX2 signal is low
  • the second strobe branch 109 receives
  • the four sub-signal data terminals Data1, Data2, Data3, and Data4 are respectively electrically connected to the second data line 104, and the data signals Data1, Data2, Data3, and Data4 are respectively written into the corresponding second data line 104 And store.
  • the gate control signal Gate1 output by the R/G GOA_O of the first row is low, so that each sub-pixel in the first row
  • the pixel circuit in the first row is turned on, and the first data line 103 connected to each sub-pixel in the first row writes the stored data signal Data1 into the first row and first column sub-pixels, and writes the stored data signal Data2 into the first row two.
  • the stored data signal Data3 is written into the first row and third column of sub-pixels
  • the stored data signal Data4 is written into the first row and fourth column of sub-pixels. Therefore, the data writing and Vth compensation operations of the first row of sub-pixel units can be completed in the third time period t 3.
  • the gate control signal Gate2 output by the R/G GOA_E of the second row is low, so that each of the second row
  • the pixel circuit in the sub-pixel is turned on, and the second data line 104 connected to each sub-pixel in the second row writes the stored data signal Data1 into the second row and first column sub-pixels, and writes the stored data signal Data2 into the second row and first column sub-pixels.
  • the data signal is written into the second row Data3 stored in the third sub-pixels
  • the data signal is written into the second row Data4 stored in the fourth sub-pixels, so as to be in the fourth time period t 4
  • the data signals Data1, Data2, Data3, and Data4 are written into the first strobe branch and the second strobe branch respectively according to the period H.
  • the third gate control signal line Gate3 R / G GOA_O output is low, the third row of each The pixel circuit in the sub-pixel is turned on, and the first data line 103 connected to each sub-pixel in the third row writes the stored data signal Data1 into the third row and first column sub-pixels, and writes the stored data signal Data2 into the third row and first column sub-pixels.
  • the second row sub-pixels the data signal written to a third row Data3 stored in the third sub-pixels, the data stored in the write signal Data4 fourth sub-pixels in the third row, so as to be in the fifth time period t 5 Inside, the data writing and Vth compensation operations of the third row of sub-pixel units are completed.
  • t 6 (t 5 partially overlap with) within the sixth time period after t 5, the fourth gate control signal line Gate4 R / G GOA_E output is low, the fourth row of each The pixel circuit in the sub-pixel is turned on, and the second data line 104 connected to each sub-pixel in the fourth row writes the stored data signal Data1 into the fourth row and first column sub-pixels, and writes the stored data signal Data2 into the fourth row and first column sub-pixels.
  • the second row sub-pixels the data signal written Data3 stored in the fourth row of the third sub-pixels, the data stored in the write signal Data4 fourth row in the fourth sub-pixels, so as to be at the sixth time period t 6 Inside, the data writing and Vth compensation operations of the fourth row of sub-pixel units are completed.
  • Figure 7 a, b, c, and H all represent time widths, where,
  • a represents the action time of the data signal input to the first strobe branch 108.
  • b represents the action time of the data signal input to the second strobe branch 109.
  • c represents the action time of the control signal of each row of the gate.
  • H represents the line period of the data signal.
  • FIG. 7 only shows the time sequence diagram of the action period of the gate control signals of each row in one cycle. It should be understood that the gate control signals of each row are also input in sequence according to a specific cycle.
  • the above example is the driving principle of the first four rows of sub-pixel units of the sub-pixel array, and the driving principle of each subsequent row is the same as the driving principle of the first four rows shown in FIG. 7, and will not be repeated here.
  • the above-mentioned "at least two gate branches” include: the first gate branch 110, the second gate branch 111, the third gate branch 112, and The fourth gate branch 113.
  • S301 specifically includes the following processes:
  • the data signal terminal 107 and all the first data lines 103 coupled to the odd-numbered column sub-pixels are electrically conducted through the first strobe branch 110, so that the data signal The data signal output from the terminal 107 is input to all the first data lines 103 coupled to the odd-numbered column sub-pixels.
  • the data signal terminal 107 and all the first data lines 103 coupled to the even-numbered column sub-pixels are electrically conducted through the second strobe branch 111, so that the data signal output from the data signal terminal 107 is input and All the first data lines 103 to which the sub-pixels of the even-numbered columns are coupled.
  • the data signal terminal 107 and all the second data lines 104 coupled to the odd-numbered column sub-pixels are electrically conducted through the third strobe branch 112, so that the data signal output from the data signal terminal is input to the odd-numbered sub-pixels. All the second data lines 104 coupled to the column sub-pixels.
  • the data signal terminal 107 and all the second data lines 104 coupled to the even-numbered column sub-pixels are electrically conducted through the fourth gate branch 113, so that the data signal output from the data signal terminal 107 is input and All the second data lines 104 to which the sub-pixels of the even-numbered columns are coupled.
  • the first time period t 1 ′, the second time period t 2 ′, the third time period t 3 ′, and the fourth time period t 4 ′ are arranged in sequence without overlapping each other.
  • the start time of the first time period t 1 ′ is in the signal input time period of the gate control signal of the first row of sub-pixels (that is, the fifth time period t 5 ′ in FIG. 8 ) Before the start time.
  • the end time of the second time period t 2 ′ is before the end time of the signal input time period of the gate control signal to the first row of sub-pixels (ie, the fifth time period t 5 ′ in FIG. 8 ).
  • the start time of the third time period t 3 ′ is before the start time of the signal input time period of the gate control signal of the second row of sub-pixels (that is, the sixth time period t 6 ′ in FIG. 8 ).
  • the end time of the fourth time period t 4 ′ is before the end time of the signal input time period of the gate control signal of the second row of sub-pixels (ie, the sixth time period t 6 ′ in FIG. 8 ).
  • the end time of the first time period t 1 ′ is in the signal input time period of the gate control signal of the first row of sub-pixels (that is, the fifth time period t 5 ′ in FIG. 8) Before the start moment.
  • the start time of the second time period t 2 ′ is before the start time of the signal input time period of the gate control signal of the first row of sub-pixels (that is, the fifth time period t 5 ′ in FIG. 8 ).
  • the end time of the third time period t 3 ′ is before the start time of the signal input time period of the gate control signal of the second row of sub-pixels (that is, the sixth time period t 6 ′ in FIG. 8 ).
  • the start time of the fourth time period is before the start time of the signal input time period of the gate control signal of the second row of sub-pixels (that is, the sixth time period t 6 ′ in FIG. 8 ).
  • the signal input time period of the gate control signal of the first row of sub-pixels ends at the next first time period t 1 Before the start time of'.
  • the end time of the signal input time period of the gate control signal of the second row of sub-pixels ie, the sixth time period t 6 ′ in FIG. 8) is before the start time of the next third time period t 3 ′.
  • the gate device 114 is a P-type transistor.
  • the MUX1 signal is low, and the first strobe branch 110 connects the Data1 and Data2 terminals to the corresponding odd rows after receiving the MUX1 signal.
  • the first data line 103 connected to the odd-column sub-pixel units is electrically turned on, and the data signal Data1 is written into the corresponding first data line 103 (the first data line 103 connected to the first-column sub-pixel units in FIG. 4) and stored, And write the data signal Data2 into the corresponding first data line 103 (in FIG. 4, the first data line 103 connected to the third column of sub-pixel units).
  • the MUX1 signal is high level
  • the MUX2 signal is low level
  • the second strobe support After the circuit 111 receives the MUX2 signal, the Data1 end and the Data2 end are respectively electrically connected to the first data line 103 connected to the corresponding odd-numbered row and even-numbered column sub-pixel units, and the data signal Data1 is written into the corresponding first data line 103 (Figure 4 is the first data line 103 connected to the sub-pixel unit in the second column) and stored, and writes the data signal Data2 into the corresponding first data line 103 (in FIG. 4, the first data line 103 connected to the sub-pixel unit in the fourth column Line 103).
  • the MUX1 signal and MUX2 signal are both high level, and the MUX3 signal is low level.
  • the Data1 terminal and the Data2 terminal are respectively electrically connected to the second data line 104 connected to the corresponding even-numbered row and odd-numbered column sub-pixel units, and the data signal Data1 is written into the corresponding second data.
  • Line 104 (in FIG. 4, the second data line 104 connected to the sub-pixel unit in the first column) and store it, and write the data signal Data2 into the corresponding second data line 104 (in FIG. 4, the second data line 104 connected to the sub-pixel unit in the third column) The second data line 104).
  • the gate control signal Gate2 output by the R/G GOA_E in the second row is low level ,
  • the pixel circuit in each sub-pixel unit in the second row is turned on, and the second data line 104 connected to each sub-pixel unit in the second row writes the stored data signal Data1 in the first column and second column of the second row.
  • Each sub-pixel unit writes the stored data signal Data2 into each sub-pixel unit in the second row, the third column and the fourth column.
  • the writing operation of the sub-pixel units in the other columns of the second row is the same, so that it can be used in the sixth time period.
  • the data writing and Vth compensation operations of the second row of sub-pixel units are completed.
  • the gate control signal Gate3 output by the R/G GOA_O in the third row is low level ,
  • the pixel circuit in each sub-pixel unit in the third row is turned on, and the first data line 103 connected to each sub-pixel unit in the third row writes the stored data signal Data1 in the first column and second column of the third row.
  • Each sub-pixel unit writes the stored data signal Data2 into each sub-pixel unit in the third row, third column and the fourth column.
  • the writing operation of the sub-pixel units in the third row and other columns is the same, so that it can be used in the seventh time period.
  • the data writing and Vth compensation operations of the third row of sub-pixel units are completed.
  • the gate control signal Gate4 output by the R/G GOA_E of the fourth row is low, making the fourth row
  • the pixel circuit in each sub-pixel unit is turned on, and the first data line 103 connected to each sub-pixel unit in the fourth row writes the stored data signal Data1 into each sub-pixel unit in the first column and second column of the fourth row.
  • Data2 stored data signal written to the fourth row and third column and fourth column of each sub-pixel units, and writes the same way the other sub-pixels of the fourth row of cells, so as to be 't8 at the eighth time period t 8 ,
  • the data writing and Vth compensation operations of the fourth row of sub-pixel units are completed.
  • the data writing time and Vth compensation time of the unit is
  • d represents the action time of the data signal input to the first gate branch 110 and input to the third gate branch 112.
  • e represents the action time of the data signal input to the second strobe branch 111 and input to the fourth strobe branch 113.
  • f represents the time difference between the start time of the data signal input time period of the first strobe branch 110 and the start time of the data signal input time period of the second strobe branch 111 in the same cycle (or the first time in the same cycle) The time difference between the start time of the data signal input period of the three-gate branch 112 and the start time of the data signal input period of the fourth gate branch 113).
  • g represents the time difference between the start time of the data signal input period of the first gate branch 110 and the start time of the input period of the corresponding first row of gate control signal Gate1 or the corresponding third row of gate control signal Gate3 (Or the time difference between the start time of the data signal input period of the third gate branch 112 and the start time of the input period of the corresponding second row gate control signal Gate2 or the corresponding fourth row gate control signal Gate4 ).
  • H' represents the line period of the data signals Data1 and Data2.
  • the size relationship and quantity relationship of each time width are shown in FIG. 8. in.
  • f>d means: the end time of the first time period t 1 ′ is before the start time of the second time period t 2 ′, and the end time of the third time period t 3 ′ is at the beginning of the fourth time period t 4 ′ Before the moment.
  • the start time of the second time period t 2 ′ is before the start time of the signal input time period of the gate control signal of the first row of sub-pixels (that is, the fifth time period t 5 ′); fourth The start time of the time period t 4 ′ is before the start time of the signal input time period of the gate control signal of the second row of sub-pixels (ie, the sixth time period t 6 ′).
  • g>d means that the end time of the first time period t 1 ′ is in the signal input time period of the gate control signal of the first row of sub-pixels (that is, the fifth time period t 5 ') before the start time; the end time of the third time period t 3 'is before the start time of the signal input time period of the gate control signal of the second row of sub-pixels (that is, the sixth time period t 6 ') .
  • FIG. 8 only shows the time sequence diagram of the action period of the gate control signals of each row in one cycle. It should be understood that the gate control signals of each row are also input in sequence according to a specific cycle.
  • the above example is the driving principle of the first four rows of sub-pixel units of the sub-pixel array, and the driving principle of each subsequent row is the same as the driving principle of the first four rows shown in FIG. 4 and FIG. 8, and will not be repeated here.
  • Some embodiments may be based on different data lines (first data line and second data line) and time-division multiplexing circuits respectively connected to sub-pixel units of odd and even rows, which can implement time-division writing of the data signal at the data signal end to each
  • the data line based on the pixel control circuit in the display panel, can control the pixel circuit of each row of sub-pixels to be turned on in time, so that the data signal written in each data line can be written to each sub-pixel connected to the data line in time ,
  • the signal input period of the gate control signal overlaps, which can extend the compensation time for each sub-pixel, Therefore, the ability to compensate the Vth of each pixel is improved, the uneven display of the display panel is improved, and the display panel maintains a better display effect at a higher refresh frequency.
  • the data signal terminal when a data signal is written into each data line, can be electrically connected to the first data line and the second data line in a time-division manner through a time-division multiplexing circuit, so as to realize the connection to the first data line.
  • the time-sharing data writing with the second data line can achieve a higher refresh frequency with a smaller number of IC channels, so that when the refresh frequency requirement is higher, It can effectively reduce the number of IC channels; in some embodiments, a first-level strobe branch (including two strobe branches) can be used to write data to data lines connected to sub-pixel units in the same row and different columns, which can be The number of data channels of the driver IC can be reduced by half; in other embodiments, two-level strobe branches (that is, four strobe branches) can be used to implement data writing on data lines connected to sub-pixel units in the same row and different columns. In, the number of data channels of the driver IC can be reduced by half.
  • Some embodiments are based on the cooperation of the time-division multiplexing circuit and the gate drive circuit. Before each row of sub-pixels receives the gate control signal, the data line (the first data line or the first data line or The data signal of the second data line) is written, so that when each row of sub-pixels receives the gate control signal, the data signal can be quickly written from the data line to the connected sub-pixels, thereby increasing the speed of data writing.

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Abstract

一种显示面板(1)，包括：子像素阵列(101)、多条栅线(102)、多条第一数据线(103)、多条第二数据线(104)、像素控制电路(105)和分时复用电路(106)；子像素阵列(101)包括呈多行多列排布的多个子像素(Pixel)；同一行子像素(Pixel)通过至少一条栅线(102)耦接至像素控制电路(105)；同一列子像素(Pixel)中位于奇数行的子像素(Pixel)与一条第一数据线(103)耦接，同一列子像素(Pixel)中位于偶数行的子像素(Pixel)与一条第二数据线(104)耦接；分时复用电路(106)分别与多条第一数据线(103)、多条第二数据线(104)以及数据信号端(107)耦接；分时复用电路(106)被配置为：将数据信号端(107)分时地与第一数据线(103)和第二数据线(104)电导通。

Description

显示面板及其驱动方法、显示装置
本申请要求于2020年06月24日提交的、申请号为202010592404.X的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，例如，涉及一种显示面板及其驱动方法、显示装置。
背景技术
VR(Virtual Reality，虚拟现实)显示给人们带来了全新的视觉感受，越来越受到人们的关注和喜爱，同时手机游戏也逐渐成为用户一项重要的娱乐休闲方式。现有的显示面板可以用于实现VR显示和游戏画面显示，通常，VR显示和游戏模式都需要显示面板提高较高的刷新频率。
发明内容
一方面，提供一种显示面板，所述显示面板包括：子像素阵列、多条栅线、多条第一数据线、多条第二数据线、像素控制电路和分时复用电路。所述子像素阵列包括呈多行多列排布的多个子像素。同一行子像素通过至少一条栅线耦接至所述像素控制电路。同一列子像素中位于奇数行的子像素与一条第一数据线耦接，同一列子像素中位于偶数行的子像素与一条第二数据线耦接。所述分时复用电路分别与所述多条第一数据线、所述多条第二数据线以及数据信号端耦接。所述分时复用电路被配置为：将所述数据信号端分时地与所述第一数据线和所述第二数据线电导通。
在一些实施例中，所述分时复用电路包括：至少两个选通支路，选通支路的第一端与所述数据信号端耦接，选通支路的第二端与至少一条所述第一数据线或至少一条所述第二数据线耦接。所有选通支路被配置为：分别在不同时间段内导通，所有选通支路的导通时间段依次排列且互不重叠。
在一些实施例中，所述至少两个选通支路包括：第一选通支路和第二选通支路。所述第一选通支路的第一端与所述数据信号端耦接，所述第一选通支路的第二端与所有所述第一数据线耦接。所述第一选通支路被配置为在第一时间段将所述数据信号端与所有所述第一数据线电导通。所述第二选通支路的第一端与所述数据信号端耦接，所述第二选通支路的第二端与所有所述第二数据线耦接，所述第二选通支路被配置为在第二时间段将所述数据信号端与 所有所述第二数据线电导通。其中，所述第一时间段和所述第二时间段依次排列且不重叠。
在一些实施例中，所述至少两个选通支路包括：第一选通支路、第二选通支路、第三选通支路和第四选通支路。所述第一选通支路的第一端与所述数据信号端耦接，所述第一选通支路的第二端和与奇数列子像素耦接的所有所述第一数据线耦接。所述第一选通支路被配置为在第一时间段将所述数据信号端和与奇数列子像素耦接的所有所述第一数据线电导通。所述第二选通支路的第一端与所述数据信号端耦接，所述第二选通支路的第二端和与偶数列子像素耦接的所有所述第一数据线耦接。所述第二选通支路被配置为在第二时间段将所述数据信号端和与偶数列子像素耦接的所有所述第一数据线电导通。所述第三选通支路的第一端与所述数据信号端耦接，所述第三选通支路的第二端和与奇数列子像素耦接的所有所述第二数据线耦接。所述第三选通支路被配置为在第三时间段将所述数据信号端和与奇数列子像素耦接的所有所述第二数据线电导通。所述第四选通支路的第一端与所述数据信号端耦接，所述第四选通支路的第二端和与偶数列子像素耦接的所有所述第二数据线耦接。所述第四选通支路被配置为在第四时间段将所述数据信号端和与偶数列子像素耦接的所有所述第二数据线电导通。其中，所述第一时间段、所述第二时间段、所述第三时间段和所述第四时间段依次排列且互不重叠。
在一些实施例中，所述数据信号端包括多个子数据信号端，一个子数据信号端同时与每个选通支路所连接的所有数据线中的一条数据线耦接。
在一些实施例中，每列所述子像素连接的所述第一数据线位于该列所述子像素的第一侧，每列所述子像素连接的所述第二数据线位于该列所述子像素的第二侧。
在一些实施例中，奇数列的所述子像素连接的所述第一数据线位于该列所述子像素的第一侧，奇数列的所述子像素连接的所述第二数据线位于该列所述子像素的第二侧。偶数列的所述子像素连接的所述第一数据线位于该列所述子像素的第二侧，偶数列的所述子像素连接的所述第二数据线位于该列所述子像素的第一侧。
又一方面，提供一种显示装置，所述显示装置包括：上述任一项所述的显 示面板。
再一方面，提供一种显示面板的驱动方法，用于驱动上述任一项所述的显示面板，所述驱动方法包括：通过所述分时复用电路将所述数据信号端分时地与所述第一数据线和所述第二数据线电导通，使所述数据信号端输出的数据信号分时地输入所述第一数据线和所述第二数据线。通过所述像素控制电路向各行所述子像素分时地输入栅极控制信号，使各行所述子像素中的像素电路导通；向相邻的两行所述子像素输入所述栅极控制信号的信号输入时间段部分重叠。根据各行所述子像素中的像素电路导通情况，通过所述第一数据线和所述第二数据线，将数据信号分时地输入各行所述子像素。
在一些实施例中，所述分时复用电路包括：至少两个选通支路。所述通过所述分时复用电路将所述数据信号端分时地与所述第一数据线和所述第二数据线电导通，使所述数据信号端输出的数据信号分时地输入所述第一数据线和所述第二数据线，包括：在不同时间段控制不同的选通支路导通，所有选通支路的导通时间段依次排列且互不重叠。
在一些实施例中，所述子像素连接的数据线与所述数据信号端电导通时间段的开始时刻在该子像素的栅极控制信号的信号输入时间段的起始时刻之前。所述子像素连接的数据线与所述数据信号端电导通时间段的结束时刻在该子像素的栅极控制信号的信号输入时间段的结束时刻之前。其中，所述数据线为所述第一数据线或所述第二数据线。
在一些实施例中，所述至少两个选通支路包括：第一选通支路和第二选通支路。所述通过所述分时复用电路将所述数据信号端分时地与所述第一数据线和所述第二数据线电导通，使所述数据信号端输出的数据信号分时地输入所述第一数据线和所述第二数据线，包括：在第一时间段，通过所述第一选通支路将所述数据信号端与所有所述第一数据线电导通，使所述数据信号端输出的数据信号输入所有所述第一数据线。在第二时间段，通过所述第二选通支路将所述数据信号端与所有所述第二数据线电导通，使所述数据信号端输出的数据信号输入所有所述第二数据线。其中，所述第一时间段和所述第二时间段依次排列且不重叠。
在一些实施例中，所述第一时间段的起始时刻在第一行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前，所述第一时间段的结束时刻 在第一行所述子像素的栅级控制信号的信号输入时间段的结束时刻之前。所述第二时间段的起始时刻在第二行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前，所述第二时间段的结束时刻在第二行所述子像素的栅级控制信号的信号输入时间段的结束时刻之前。
在一些实施例中，所述至少两个选通支路包括：第一选通支路、第二选通支路、第三选通支路和第四选通支路。所述通过所述分时复用电路分时地将所述数据信号端与所述第一数据线和所述第二数据线电导通，使所述数据信号端输出的数据信号分时地输入所述第一数据线和所述第二数据线，包括：在第一时间段，通过所述第一选通支路将所述数据信号端和与奇数列子像素耦接的所有所述第一数据线电导通，使所述数据信号端输出的数据信号输入与奇数列子像素耦接的所有所述第一数据线。在第二时间段，通过所述第二选通支路将所述数据信号端和与偶数列子像素耦接的所有所述第一数据线电导通，使所述数据信号端输出的数据信号输入与偶数列子像素耦接的所有所述第一数据线。在第三时间段，通过所述第三选通支路将所述数据信号端和与奇数列子像素耦接的所有所述第二数据线电导通，使所述数据信号端输出的数据信号输入与奇数列子像素耦接的所有所述第二数据线。在第四时间段，通过第四选通支路将所述数据信号端和与偶数列子像素耦接的所有所述第二数据线电导通，使所述数据信号端输出的数据信号输入与偶数列子像素耦接的所有所述第二数据线。所述第一时间段、所述第二时间段、所述第三时间段和所述第四时间段依次排列且互不重叠。
在一些实施例中，所述第一时间段的起始时刻在第一行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前。所述第二时间段的结束时刻在第一行所述子像素的栅级控制信号的信号输入时间段的结束时刻之前。所述第三时间段的起始时刻在第二行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前。所述第四时间段的结束时刻在第二行所述子像素的栅级控制信号的信号输入时间段的结束时刻之前。
在一些实施例中，所述第一时间段的结束时刻在第一行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前。所述第二时间段的起始时刻在第一行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前。所述第三时间段的结束时刻在第二行所述子像素的栅级控制信号的信号输入时 间段的起始时刻之前。所述第四时间段的起始时刻在第二行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前。
在一些实施例中，第一行所述子像素的栅级控制信号的信号输入时间段的结束时刻在下一个所述第一时间段的起始时刻之前。第二行所述子像素的栅级控制信号的信号输入时间段的结束时刻在下一个所述第三时间段的起始时刻之前。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为一些实施例提供的一种显示装置的结构图；
图2为一些实施例提供的一种显示面板的结构图；
图3为一些实施例提供的另一种显示面板的结构图；
图4为一些实施例提供的又一种显示面板的结构图；
图5为一些实施例提供的再一种显示面板的结构图；
图6为一些实施例提供的一种显示面板的驱动方法的流程图；
图7为图3中显示面板对应的选通信号和栅级控制信号的信号时序图；
图8为图4中显示面板对应的选通信号和栅级控制信号的信号时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、 “一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
本公开的发明人进行研究发现，OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置通常包括多个子像素单元，每个子像素单元中包括像素电路，各个像素电路中的驱动晶体管的阈值电压Vth由于制备工艺的差异或温度的变化会产生漂移现象，导致显示不良，因此需要对驱动晶体管的阈值电压Vth进行补偿。
传统的驱动方式，补偿时间等于数据写入时间。VR显示和游戏模式都需要显示面板提供较高的刷新频率，在显示面板的刷新频率较高(例如120Hz)时，行周期缩短，数据写入时间缩短，Vth补偿时间大幅减少，导致对像素电路中驱动晶体管的Vth的补偿不足，从而影响显示效果。
此外，随着分辨率的提升，驱动IC(Interated Circuit，集成电路)所需要的数据通道数越来越多(每个数据通道与一条数据线对应)，有的显示面板(例如是中尺寸的显示面板)可能需要两颗IC来进行驱动，这大大增加了显示面板的成本。
基于此本公开一些实施例提供了一种显示装置10，请参阅图1，显示 装置10包括本公开一些实施例提供的显示面板1。
显示装置10可以为手机、平板电脑、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer，UMPC)、手持计算机、上网本、个人数字助理(personal digital assistant，PDA)、可穿戴设备、虚拟现实设备等具有柔性屏幕的电子设备，本公开对显示装置10的用途不做具体限制。
示例性的，该显示装置10可以为电致发光显示器或光致发光显示器。在该显示装置10为电致发光显示器的情况下，电致发光显示器可以为有机电致发光显示器(Organic Light-Emitting Diode，OLED)或量子点电致发光显示器(Quantum Dot Light Emitting Diodes，QLED)。在该显示装置10为光致发光显示器的情况下，光致发光显示器可以为量子点光致发光显示装置。
请参阅图2，本公开一些实施例提供了一种显示面板1。该显示面板1可用于上述任一显示装置10中。
该显示面板1包括：子像素阵列101、多条栅线102、多条第一数据线103、多条第二数据线104、像素控制电路105和分时复用电路106。
子像素阵列101包括呈多行多列排布的多个子像素(如图2所示的Pixel)；同一列子像素通过至少一条栅线102耦接至像素控制电路105。同一列子像素位于奇数行的子像素与第一数据线103耦接，同一列子像素中位于偶数行的子像素与第二数据线104耦接。
分时复用电路106分别与多条第一数据线103、多条第二数据线104以及数据信号端107耦接。分时复用电路被配置为：将数据信号端分时地与第一数据线和第二数据线电导通。
需要说明的是，数据信号端107设置在驱动IC上，数据信号端107对应驱动IC的数据通道，用于输出驱动IC的数据信号。
本公开一些实施例中提供的显示面板，基于分时复用电路的分时电导通功能，可实现将数据信号端输出的数据信号分时地写入第一数据线和第二数据线，通过分时复用电路，一个数据信号端可以耦接多条数据线，与相关技术中一个数据信号端耦接一条数据线相比，在数据线条数相同时，可以以较少的数据通道通过分时操作实现对多条数据线的驱动，从而可减少驱动IC的数据通道数或减少驱动IC的数量。通过分时复用电路可以一次对多条数据线写入数据信号，从而可以降低驱动IC的数据信号的输出频率，以实现显示面板较高的刷新频率，更适用于刷新频率要求较高的场景。并且，通过分时复用电路的分时电导通功能，相邻的两行子像素输入栅极控制信号的信号输入时间段可以部分重叠，从而延长了对驱动晶体管 的阈值电压Vth的补偿时间，解决驱动晶体管的Vth的补偿不足的问题。
在一些实施例中，分时复用电路106包括：至少两个选通支路，选通支路的第一端与数据信号端107耦接，选通支路的第二端与至少一条第一数据线103或至少一条第二数据线104耦接。选通支路被配置为：分别在不同的时间段内导通，所有选通支路导通时间段依次排列且互不重叠。
分时复用电路可以将不同的选通支路分时导通，从而将数据信号端的数据信号分时地传输至选通支路连接的数据线中，对数据线连接的子像素写入数据信号。不同选通支路依次导通，且导通时间段不重叠，从而可以在一个周期中按照特定先后顺序对不同部分的子像素依次写入数据信号。
在一些实施例中，请参阅图3，上述“至少两个选通支路”包括：第一选通支路108(即图3中接入选通信号MUX1的支路)和第二选通支路109(即图3中接入选通信号MUX2的支路)。第一选通支路108的第一端与数据信号端107耦接，第一选通支路108的第二端与所有第一数据线103耦接。第一选通支路108被配置为在第一时间段将数据信号端107与所有第一数据线103电导通。第二选通支路109的第一端与数据信号端107耦接，第二选通支路109的第二端与所有第二数据线104耦接，第二选通支路109被配置为在第二时间段将数据信号端107与所有第二数据线104电导通。其中，第一时间段和第二时间段依次排列且不重叠。
图3示出了四行四列的子像素阵列及与该子像素阵列耦接的各电路和连接线，仅作为示例，并不用于限制本公开的范围，本领域可以理解，图中所示的电路连接关系可以扩展至m行n列的子像素阵列，m和n均可以大于4。
上述两个选通支路的方案，驱动IC的一个数据通道可实现对两条数据线(即一条第一数据线和一条第二数据线)的分时驱动，从而可将数据通道数可减少一半。
在一些实施例中，请参阅图4和图5，上述“至少两个选通支路”包括：第一选通支路110(即图中接入选通信号MUX1的支路)、第二选通支路111(即图中接入选通信号MUX2的支路)、第三选通支路112(即图中接入选通信号MUX3的支路)和第四选通支路113(即图中接入选通信号MUX4的支路)。
请参阅图4和图5，第一选通支路110的第一端与数据信号107端耦接，第一选通支路110的第二端和与奇数列子像素耦接的所有第一数据线103耦接。第一选通支路110被配置为在第一时间段将数据信号端107和 与奇数列子像素耦接的所有第一数据线103电导通。第二选通支路111的第一端与数据信号端107耦接，第二选通支路111的第二端和与偶数列子像素耦接的所有第一数据线103耦接。第二选通支路111被配置为在第二时间段将数据信号端107和与偶数列子像素耦接的所有第一数据线103电导通。第三选通支路112的第一端与数据信号端107耦接，第三选通支路112的第二端和与奇数列子像素耦接的所有第二数据线104耦接。第三选通支路112被配置为在第三时间段将数据信号端107和与奇数列子像素耦接的所有第二数据线104电导通。第四选通支路113的第一端与数据信号端107耦接，第四选通支路113的第二端和与偶数列子像素耦接的所有第二数据线104耦接。第四选通支路113被配置为在第四时间段将数据信号端107和与偶数列子像素耦接的所有第二数据线104电导通。其中，第一时间段、第二时间段、第三时间段和第四时间段依次排列且不重叠。
上述四个选通支路的方案，驱动IC的一个数据通道可实现对四条数据线(两条第一数据线和两条第二数据线)的分时驱动，从而可在两个选通支路的基础上将数据通道数再减少一半。
在一些示例中，请参阅图3～图5，像素控制电路105包括至少一个用于提供扫描信号的扫描信号移位寄存器电路(Gate Driver On Array，Gate GOA)。至少一个扫描信号移位寄存器电路通过栅线与各子像素行耦接(可以是一个扫描信号移位寄存器电路与多行子像素耦接，也可以是多个扫描信号移位寄存器电路分别与多行子像素耦接)，用于驱动各行子像素。
示例性的，请参阅图3～图5，像素控制电路105包括用于驱动奇数行子像素的栅极驱动电路R/G GOA_O和用于驱动偶数行子像素的栅极驱动电路R/G GOA_E。R/G GOA_O和R/G GOA_E通过输出栅极控制信号(Gate信号)来实现对所连接的一行子像素的驱动。
在一些示例中，请参阅3～图5，像素控制电路105还包括用于提供发光控制信号的发光控制信号移位寄存电路(EM GOA)，发光控制信号移位寄存电路(EM GOA)可通过显示面板中的发光控制线108与各子像素行中的每个子像素单元耦接。
示例性的，发光控制信号移位寄存电路(EM GOA)可以是一个，也可以是如图3～图5所示的多个(如图3～图5中的两个EM GOA1和两个EM GOA2)，多个发光控制信号移位寄存电路(EM GOA)可以设置在子像素阵列101的同一则，也可以如图3～图5所示分设在子像素阵列101的两侧。
在一些示例中，请参阅图3～图5，每个选通支路均包括多个选通器件114，每个选通器件114的控制端均与选通信号控制电路耦接，以接收选通信号控制电路发出的选通信号；每个选通器件114的第一端均与对应的第一数据线103或第二数据线104耦接，第二端与数据信号端107耦接。
示例性的，以图4所示的第一选通支路110的选通器件114为例，两个选通器件114的控制端与选通信号控制电路耦接，接收选通信号MUX1；第一个选通器件114的第一端与第一列的第一数据线103(即与第一列奇数行各子像素耦接的第一数据线103)耦接，第二端与Data1端耦接；第二个选通器件114的第一端与第三列的第一数据线103(即与第三列奇数行各子像素耦接的第一数据线103)耦接，第二端与Data2端耦接。请参阅图3～图5，，其它选通支路中的各选通器件的连接方式同理，此处不再赘述。
示例性的，选通器件114可以是P型或N型的晶体管。
在一些示例中，显示面板还包括选通信号控制电路，用于输出选通信号。
在一些示例中，当数据信号端的频率较大时，由于存在寄生电容，当数据信号端与数据线电导通断开时，数据线可存储待写入的数据信号，当数据线和对应的子像素电导通时，即可将数据信号写入对应的子像素。
在一些实施例中，请参阅图3～图5，数据信号端107包括多个子数据信号端(即图3中的Data1、Data2、Data3和Data4、图4中的Data1和Data2以及图5中的Data1和Data2)，一个子数据信号端同时与每个选通支路所连接的所有数据线中的一条数据线耦接。
每个子数据信号端对应驱动IC的一个数据通道，一个选通支路中不同的数据线连接至不同的子数据信号端，从而在同一时间段使一条选通支路上的所有数据线写入不同的数据信号。
在一些示例中，请参阅图3，第一选通支路108与所有第一数据线103耦接，第二选通支路109与所有第二数据线104耦接，数据信号端107包括四个子数据信号端，即图3中Data1、Data2、Data3和Data4。其中，Data1同时与第一选通支路108耦接的第一条第一数据线103以及第二选通支路109耦接的第一条第二数据线104耦接。Data2同时与第一选通支路108耦接的第二条第一数据线103以及第二选通支路109耦接的第二条第二数据线104耦接。Data3同时与第一选通支路108耦接的第三条第一数据线103以及第二选通支路109耦接的第三条第二数据线104耦接。Data4同时与第一选通支路108耦接的第四条第一数据线103以及第二选 通支路109耦接的第四条第二数据线104耦接。这种设置方式可以使同一行子像素输入不同的数据信号。
在另一些示例中，请参阅图4和图5，第一选通支路110和与奇数列子像素对应的所有第一数据线103耦接，第二选通支路111和与偶数列子像素对应的所有第一数据线103耦接，第三选通支路112和与奇数列子像素对应的所有第二数据线104耦接，第四选通支路113和与偶数列子像素对应的所有第二数据线104耦接。数据信号端107包括两个子数据信号端，即图4中的Data1和Data2，图5中的Data1和Data2。其中，Data1同时与第一选通支路110耦接的第一条第一数据线103、第二选通支路111耦接的第一条第一数据线103、第三选通支路112耦接的第一条第二数据线104以及第四选通支路113耦接的第一条第二数据线104耦接。Data2同时与第一选通支路110耦接的第二条第一数据线103、第二选通支路111耦接的第二条第一数据线103、第三选通支路112耦接的第二条第二数据线104以及第四选通支路113耦接的第二条第二数据线104耦接。这种设置方式可以在同一时间段对每个选通支路所连接的数据线写入不同的数据信号。
在一些实施例中，请参阅图3～图5，每列子像素连接的第一数据线103位于该列子像素的第一侧，每列子像素连接的第二数据线104位于该列子像素的第二侧。
每列子像素连接一条第一数据线和一条第二数据线，两条数据线分别位于该列子像素的两侧，这样排线布局，可以使多条数据线排列均匀整齐有序，并且有利于实际生产制作。
在一些实施例中，请参阅图5，奇数列的子像素连接的第一数据线103位于该列子像素的第一侧，奇数列的子像素连接的第二数据线104位于该列子像素的第二侧。偶数列的子像素连接的第一数据线103位于该列子像素的第二侧，偶数列的子像素连接的第二数据线104位于该列子像素的第一侧。
图4所示的电路连接关系与图5所示的电路连接关系相同，区别仅在于数据线的分布有差异。
本公开一些实施例提供了一种显示面板的驱动方法，用于驱动上述任一实施例提供的显示面板，如图6所示，该驱动方法包括：
S301，通过分时复用电路106将数据信号端107分时地与第一数据线 103和第二数据线104电导通，使数据信号端107输出的数据信号分时地输入第一数据线103和第二数据线104。
S302，通过像素控制电路105向各行子像素分时地输入栅极控制信号，使各行子像素中的像素电路导通。向相邻的两行子像素输入栅极控制信号的信号输入时间段部分重叠。
S303，根据各行子像素中的像素电路导通情况，通过第一数据线103和第二数据线104，将数据信号分时地输入各行子像素。
由于分时复用电路可以将不同数据线分时地与数据信号端导通，从而可以使数据信号分时写入子像素中，基于该种设置方式，相邻两个子像素行输入栅级控制信号的信号输入时间段可以设置为部分重叠的形式，从而可延长对每个子像素的补偿时间，提高对每个像素的Vth的补偿能力。
在一些实施例中，分时复用电路包括：至少两个选通支路。通过分时复用电路将数据信号端107分时地与第一数据线103和第二数据线104电导通，使数据信号端输107出的数据信号分时地输入第一数据线103和第二数据线104，包括：在不同时间段控制不同的选通支路导通，所有选通支路的导通时间段依次排列且互不重叠。
分时复用电路包括至少两个选通支路，不同的选通支路与不同的数据线耦接，不同的选通支路分时地的与不同的数据线导通，从而可以对子像素分时写入数据信号。
在一些实施例中，子像素耦接的数据线与数据信号端电导通时间段的开始时刻在该子像素的栅极控制信号的信号输入时间段的起始时刻之前。子像素耦接的数据线与数据信号端电导通时间段的结束时刻在该子像素的栅极控制信号的信号输入时间段的结束时刻之前。其中，数据线为第一数据线或第二数据线。
对于一个子像素来说，通过数据线先写入数据信号，再通过栅线写入栅级控制信号，并且在栅级信号结束之前应完成数据信号写入，从而使对应的子像素正常工作。
在一些实施例中，请参阅图3和图7，上述“至少两个选通支路”包括：第一选通支路108和第二选通支路109。S301具体包括以下过程：在第一时间段t 1，通过第一选通支路108将数据信号端107与所有第一数据线103电导通，使数据信号端107输出的数据信号输入所有第一数据线103；在第二时间段t 2，通过第二选通支路109将数据信号端107与所有第二数据线104电导通，使数据信号端107输出的数据信号输入所有第二数 据线104；其中，第一时间段t 1和第二时间t 2段依次排列且不重叠。
在一些实施例中，请参阅图7，第一时间段t 1的起始时刻在第一行子像素的栅级控制信号的信号输入时间段(即图7中第三时间段t 3)的起始时刻之前，第一时间段t 1的结束时刻在第一行子像素的栅级控制信号的信号输入时间段(即图7中第三时间段t 3)的结束时刻之前。第二时间段t 2的起始时刻在向第二行子像素的栅级控制信号的信号输入时间段(即图7中第四时间段t 4)的起始时刻之前，第二时间段t 2的结束时刻在第二行子像素的栅级控制信号的信号输入时间段(即图7中第四时间段t 4)的结束时刻之前。
这种设置方式可以保证：子像素通过数据线先写入数据信号，再通过栅线写入栅级控制信号，并且在栅级信号结束之前应完成数据信号写入，从而使对应的子像素正常工作。
在一些示例中，请参阅图3和图7，选通器件114采用P型晶体管。在第一时间段t 1(图7中时长为a)内，MUX1信号为低电平，第一选通支路108在接收到MUX1信号后将四个子信号数据端Data1端、Data2端、Data3端、Data4端分别与第一数据线103电导通，将数据信号Data1、Data2、Data3以及Data4分别写入对应的第一数据线103并存储。
请参阅图7，在t 1之后的第二时间段t 2(图7中时长为b)内，MUX1信号为高电平，MUX2信号为低电平，第二选通支路109在接收到MUX2信号后将四个子信号数据端Data1端、Data2端、Data3端、Data4端分别与第二数据线104电导通，将数据信号Data1、Data2、Data3以及Data4分别写入对应的第二数据线104并存储。
请参阅图7，在t 1之后的第三时间段t 3(时长为c)内，第一行的R/G GOA_O输出的栅极控制信号Gate1为低电平，使第一行各子像素内的像素电路导通，第一行各子像素所连接的第一数据线103将存储的数据信号Data1写入第一行第一列子像素中，将存储的数据信号Data2写入第一行二列子像素中，将存储的数据信号Data3写入第一行第三列子像素中，将存储的数据信号Data4写入第一行第四列子像素中。从而可在第三时间段t 3内，完成第一行子像素单元的数据写入和Vth补偿操作。
请参阅图7，在t 2之后的第四时间段t 4(与t 3部分重叠)内，第二行的R/G GOA_E输出的栅极控制信号Gate2为低电平，使第二行各子像素内的像素电路导通，第二行各子像素所连接的第二数据线104将存储的数据信号Data1写入第二行第一列子像素中，将存储的数据信号Data2写入 第二行第二列子像素中，将存储的数据信号Data3写入第二行第三列子像素中，将存储的数据信号Data4写入第二行第四列子像素中，从而可在第四时间段t 4内，完成第二行子像素单元的数据写入和Vth补偿操作。在整个工作时间段内，数据信号Data1、Data2、Data3以及Data4按照周期H分别写入第一选通支路和第二选通支路。
请参阅图7，在t 4之后的第五时间段t 5(与t 4部分重叠)内，第三行的R/G GOA_O输出的栅极控制信号Gate3为低电平，使第三行各子像素内的像素电路导通，第三行各子像素所连接的第一数据线103将存储的数据信号Data1写入第三行第一列子像素中，将存储的数据信号Data2写入第三行第二列子像素中，将存储的数据信号Data3写入第三行第三列子像素中，将存储的数据信号Data4写入第三行第四列子像素中，从而可在第五时间段t 5内，完成第三行子像素单元的数据写入和Vth补偿操作。
请参阅图7，在t 5之后的第六时间段t 6(与t 5部分重叠)内，第四行的R/G GOA_E输出的栅极控制信号Gate4为低电平，使第四行各子像素内的像素电路导通，第四行各子像素所连接的第二数据线104将存储的数据信号Data1写入第四行第一列子像素中，将存储的数据信号Data2写入第四行第二列子像素中，将存储的数据信号Data3写入第四行第三列子像素中，将存储的数据信号Data4写入第四行第四列子像素中，从而可在第六时间段t 6内，完成第四行子像素单元的数据写入和Vth补偿操作。
参照图7可知，t 3至t 6时间段两两之间有重叠，在对前一行子像素单元进行数据写入和Vth补偿操作的过程中，启动对后一行子像素单元进行数据写入和Vth补偿操作，而无需等到对前一行子像素单元进行数据写入和Vth补偿操作结束之后再对后一行子像素单元进行数据写入和Vth补偿操作，从而可延长对第一行子像素单元的数据写入时间和Vth补偿时间。
在一些示例中，请参阅图7，图7中的a、b、c和H均表示时间宽度，其中，
a表示输入第一选通支路108的数据信号的作用时间。
b表示输入第二选通支路109的数据信号的作用时间。
c表示每行栅级控制信号的作用时间。
H表示数据信号的行周期。
图7中只示出一个周期中各行栅级控制信号的作用时间段时序图，应该明白的是各行栅级控制信号也是按照特定周期依次输入。
上述示例为对子像素阵列的前四行子像素单元的驱动原理，后续各行 的驱动原理与图7所示的前四行的驱动原理同理，此处不再一一赘述。
在一些实施例中，请参阅图4和图8，上述“至少两个选通支路”包括：第一选通支路110、第二选通支路111、第三选通支路112和第四选通支路113。S301具体包括以下过程：
请参阅图4和图8，在第一时间段t 1＇，通过第一选通支路110将数据信号端107和与奇数列子像素耦接的所有第一数据线103电导通，使数据信号端107输出的数据信号输入与奇数列子像素耦接的所有第一数据线103。在第二时间段t 2＇，通过第二选通支路111将数据信号端107和与偶数列子像素耦接的所有第一数据线103电导通，使数据信号端107输出的数据信号输入与偶数列子像素耦接的所有第一数据线103。在第三时间段t 3＇，通过第三选通支路112将数据信号端107和与奇数列子像素耦接的所有第二数据线104电导通，使数据信号端输出的数据信号输入与奇数列子像素耦接的所有第二数据线104。在第四时间段t 4＇，通过第四选通支路113将数据信号端107和与偶数列子像素耦接的所有第二数据线104电导通，使数据信号端107输出的数据信号输入与偶数列子像素耦接的所有第二数据线104。第一时间段t 1＇、第二时间段t 2＇、第三时间段t 3＇和第四时间段t 4＇依次排列且互不重叠。
在一些实施例中，请参阅图8，第一时间段t 1＇的起始时刻在第一行子像素的栅级控制信号的信号输入时间段(即图8中第五时间段t 5＇)的起始时刻之前。第二时间段t 2＇的结束时刻在向第一行子像素的栅级控制信号的信号输入时间段(即图8中第五时间段t 5＇)的结束时刻之前。第三时间段t 3＇的起始时刻在第二行子像素的栅级控制信号的信号输入时间段(即图8中第六时间段t 6＇)的起始时刻之前。第四时间段t 4＇的结束时刻在第二行子像素的栅级控制信号的信号输入时间段(即图8中第六时间段t 6＇)的结束时刻之前。
在一些实施例中，请参阅图8，第一时间段t 1＇的结束时刻在第一行子像素的栅级控制信号的信号输入时间段(即图8中第五时间段t 5＇)的起始时刻之前。第二时间段t 2＇的起始时刻在第一行子像素的栅级控制信号的信号输入时间段(即图8中第五时间段t 5＇)的起始时刻之前。第三时间段t 3＇的结束时刻在第二行子像素的栅级控制信号的信号输入时间段(即图8中第六时间段t 6＇)的起始时刻之前。第四时间段的起始时刻在第二行子像素的栅级控制信号的信号输入时间段(即图8中第六时间段t 6＇)的起始时刻之前。
在一些实施例中，请参阅图8，第一行子像素的栅级控制信号的信号输入时间段(即图8中第五时间段t 5＇)的结束时刻在下一个第一时间段t 1＇的起始时刻之前。第二行子像素的栅级控制信号的信号输入时间段(即图8中第六时间段t 6＇)的结束时刻在下一个第三时间段t 3＇的起始时刻之前。
在一些示例中，请参阅图4和图8，选通器件114为P型晶体管。在第一时间段t 1＇(图8中时长为d)内，MUX1信号为低电平，第一选通支路110在接收到MUX1信号后将Data1端和Data2端分别与相应的奇数行奇数列子像素单元所连接的第一数据线103电导通，将数据信号Data1写入对应的第一数据线103(图4中为第一列子像素单元所连接的第一数据线103)并存储，并将数据信号Data2写入对应的第一数据线103(图4中为第三列子像素单元所连接的第一数据线103)。
请参阅图4和图8，在t 1＇之后的第二时间段t 2＇(图8中时长为e)内，MUX1信号为高电平，MUX2信号为低电平，第二选通支路111在接收到MUX2信号后将Data1端和Data2端分别与相应的奇数行偶数列子像素单元所连接的第一数据线103电导通，将数据信号Data1写入对应的第一数据线103(图4中为第二列子像素单元所连接的第一数据线103)并存储，并将数据信号Data2写入对应的第一数据线103(图4中为第四列子像素单元所连接的第一数据线103)。
请参阅图4和图8，在t 2＇之后的第三时间段t 3＇(图8中时长为d)内，MUX1信号和MUX2信号均为高电平，MUX3信号为低电平，第三选通支路112在接收到MUX3信号后将Data1端和Data2端分别与相应的偶数行奇数列子像素单元所连接的第二数据线104电导通，将数据信号Data1写入对应的第二数据线104(图4中为第一列子像素单元所连接的第二数据线104)并存储，并将数据信号Data2写入对应的第二数据线104(图4中为第三列子像素单元所连接的第二数据线104)。
请参阅图4和图8，在t 3＇之后的第四时间段t 4＇(图8中时长为e)内，MUX1至MUX3信号均为高电平，MUX4信号为低电平，第四选通支路113在接收到MUX4信号后将Data1端和Data2端分别与相应的偶数行偶数列子像素单元所连接的第二数据线104电导通，将数据信号Data1写入对应的第二数据线104(图4中为第二列子像素单元所连接的第二数据线104)并存储，并将数据信号Data2写入对应的第二数据线104(图4中为第四列子像素单元所连接的第二数据线104)。
请参阅图4和图8，在t 1＇之后的第五时间段t 5＇(图8中时长为h) 内，第一行的R/G GOA_O输出的栅极控制信号Gate1为低电平，使第一行各子像素单元内的像素电路导通，第一行各子像素单元所连接的第一数据线103将存储的数据信号Data1写入第一行第一列和第二列的各子像素单元，将存储的数据信号Data2写入第一行第三列和第四列的各子像素单元，第一行其它列子像素单元的写入操作同理，从而可在第五时间段t 5＇内，完成第一行子像素单元的数据写入和Vth补偿操作。
请参阅图4和图8，在t 3＇之后的第六时间段t 6＇(与t 5＇部分重叠)内，第二行的R/G GOA_E输出的栅极控制信号Gate2为低电平，使第二行各子像素单元内的像素电路导通，第二行各子像素单元所连接的第二数据线104将存储的数据信号Data1写入第二行第一列和第二列的各子像素单元，将存储的数据信号Data2写入第二行第三列和第四列的各子像素单元，第二行其它列子像素单元的写入操作同理，从而可在第六时间段t 6＇内，完成第二行子像素单元的数据写入和Vth补偿操作。
请参阅图4和图8，在t 4＇之后的第七时间段t 7＇(与t 6＇部分重叠)内，第三行的R/G GOA_O输出的栅极控制信号Gate3为低电平，使第三行各子像素单元内的像素电路导通，第三行各子像素单元所连接的第一数据线103将存储的数据信号Data1写入第三行第一列和第二列的各子像素单元，将存储的数据信号Data2写入第三行第三列和第四列的各子像素单元，第三行其它列子像素单元的写入操作同理，从而可在第七时间段t 7＇内，完成第三行子像素单元的数据写入和Vth补偿操作。
请参阅图4和图8，在第八时间段t 8＇(与t 7＇部分重叠)内，第四行的R/G GOA_E输出的栅极控制信号Gate4为低电平，使第四行各子像素单元内的像素电路导通，第四行各子像素单元所连接的第一数据线103将存储的数据信号Data1写入第四行第一列和第二列的各子像素单元，将存储的数据信号Data2写入第四行第三列和第四列的各子像素单元，第四行其它列子像素单元的写入操作同理，从而可在第八时间段t 8＇t8内，完成第四行子像素单元的数据写入和Vth补偿操作。
参照图8可知，t 5＇至t 8＇时间段两两之间有重叠，在对前一行子像素单元进行数据写入和Vth补偿操作的过程中，启动对后一行子像素单元进行数据写入和Vth补偿操作，而无需等到对前一行子像素单元进行数据写入和Vth补偿操作结束之后再对后一行子像素单元进行数据写入和Vth补偿操作，从而可延长对第一行子像素单元的数据写入时间和Vth补偿时间。
在一些示例中，请参阅图8，图8中的d、e、f、g、h、i和H＇均表示时间宽度，其中，
d表示输入第一选通支路110和输入第三选通支路112的数据信号的作用时间。
e表示输入第二选通支路111和输入第四选通支路113的数据信号的作用时间。
f表示在同一个周期中第一选通支路110数据信号输入时间段的起始时刻和第二选通支路111数据信号输入时间段的起始时刻的时间差(或在同一个周期中第三选通支路112数据信号输入时间段的起始时刻和第四选通支路113数据信号输入时间段的起始时刻的时间差)。
g表示第一选通支路110数据信号输入时间段的起始时刻与对应的第一行栅级控制信号Gate1或对应的第三行栅级控制信号Gate3的输入时间段的起始时刻的时间差(或第三选通支路112数据信号输入时间段的起始时刻与对应的第二行栅级控制信号Gate2或对应的第四行栅级控制信号Gate4的输入时间段的起始时刻的时间差)。
H＇表示数据信号Data1和Data2的行周期。
在一些示例中，各时间宽度大小关系以及数量关系如图8所示。其中，
f>d表示：第一时间段t 1＇的结束时刻在第二时间段t 2＇的起始时刻之前，第三时间段t 3＇的结束时刻在第四时间段t 4＇的起始时刻之前。
g>f表示：第二时间段t 2＇的起始时刻在第一行子像素的栅级控制信号的信号输入时间段(即第五时间段t 5＇)的起始时刻之前；第四时间段t 4＇的起始时刻在第二行子像素的栅级控制信号的信号输入时间段(即第六时间段t 6＇)的起始时刻之前。
由f>d和g>f可知g>d，g>d表示第一时间段t 1＇的结束时刻在第一行子像素的栅级控制信号的信号输入时间段(即第五时间段t 5＇)的起始时刻之前；第三时间段t 3＇的结束时刻在第二行子像素的栅级控制信号的信号输入时间段(即第六时间段t 6＇)的起始时刻之前。
h＝2H-g-i表示：第一行子像素的栅级控制信号的信号输入时间段(即第五时间段t 5＇)的结束时刻在下一个第一时间段t 1＇的起始时刻之前；第二行子像素的栅级控制信号的信号输入时间段(即第六时间段t 6＇)的结束时刻在下一个第三时间段t 3＇的起始时刻之前。
图8中只示出一个周期中各行栅级控制信号的作用时间段时序图，应该明白的是各行栅级控制信号也是按照特定周期依次输入。
上述示例为对子像素阵列的前四行子像素单元的驱动原理，后续各行的驱动原理与图4和图8所示的前四行的驱动原理同理，此处不再一一赘述。
值得指出的是，本公开一些实施例至少能够实现如下有益效果：
1)一些实施例可基于奇偶行子像素单元分别连接的不同数据线(第一数据线和第二数据线)和分时复用电路，可以实现将数据信号端的数据信号分时地写入各数据线，基于显示面板中的像素控制电路可控制各行子像素的像素电路分时导通，从而可实现将已写入各数据线的数据信号分时地写入与数据线连接的各子像素，以实现对各子像素的Vth的分时补偿；相邻两个子像素行在进行分时数据写入时，使栅极控制信号的信号输入时段重叠，可延长对每个子像素的补偿时间，从而提高对每个像素的Vth的补偿能力，改善显示面板显示不均匀的现象，使得显示面板在较高的刷新频率下保持较好的显示效果。
2)一些实施例在将数据信号写入各数据线时，可通过分时复用电路将数据信号端分时地与第一数据线和第二数据线电导通，以实现对第一数据线和第二数据线的分时数据写入，基于分时复用电路的该分时控制功能，可以较少的IC通道数量实现较高的刷新的频率，从而在刷新频率的要求较高时，可有效地减少IC通道的数量；在一些实施例中，可采用一级选通支路(包括两个选通支路)来实现同一行不同列子像素单元连接的数据线的数据写入，可将驱动IC的数据通道数可减少一半；在另一些实施例中，可采用两级选通支路(即四个选通支路)来实现同一行不同列子像素单元连接的数据线的数据写入，可将驱动IC的数据通道数再减少一半。
3)一些实施例基于分时复用电路和栅极驱动电路的配合，可在每一行子像素接收到栅极控制信号之前，开始或完成对该行所连接的数据线(第一数据线或第二数据线)的数据信号写入，从而在每一行子像素接收到栅极控制信号时，可快速将数据信号由数据线写入所连接的子像素，提高数据写入的速度。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种显示面板，包括：子像素阵列、多条栅线、多条第一数据线、多条第二数据线、像素控制电路和分时复用电路；
    所述子像素阵列包括呈多行多列排布的多个子像素；
    同一行子像素通过至少一条栅线耦接至所述像素控制电路；
    同一列子像素中位于奇数行的子像素与一条第一数据线耦接，同一列子像素中位于偶数行的子像素与一条第二数据线耦接；
    所述分时复用电路分别与所述多条第一数据线、所述多条第二数据线以及数据信号端耦接；
    所述分时复用电路被配置为：将所述数据信号端分时地与所述第一数据线和所述第二数据线电导通。
  2. 根据权利要求1所述的显示面板，其中，所述分时复用电路包括：
    至少两个选通支路，选通支路的第一端与所述数据信号端耦接，选通支路的第二端与至少一条所述第一数据线或至少一条所述第二数据线耦接；
    所有选通支路被配置为：分别在不同时间段内导通，所有选通支路的导通时间段依次排列且互不重叠。
  3. 根据权利要求2所述的显示面板，其中，所述至少两个选通支路包括：第一选通支路和第二选通支路；
    所述第一选通支路的第一端与所述数据信号端耦接，所述第一选通支路的第二端与所有所述第一数据线耦接；所述第一选通支路被配置为在第一时间段将所述数据信号端与所有所述第一数据线电导通；
    所述第二选通支路的第一端与所述数据信号端耦接，所述第二选通支路的第二端与所有所述第二数据线耦接，所述第二选通支路被配置为在第二时间段将所述数据信号端与所有所述第二数据线电导通；
    其中，所述第一时间段和所述第二时间段依次排列且不重叠。
  4. 根据权利要求2所述的显示面板，其中，所述至少两个选通支路包括：第一选通支路、第二选通支路、第三选通支路和第四选通支路；
    所述第一选通支路的第一端与所述数据信号端耦接，所述第一选通支路的第二端和与奇数列子像素耦接的所有所述第一数据线耦接；所述第一选通支路被配置为在第一时间段将所述数据信号端和与奇数列子像素耦接 的所有所述第一数据线电导通；
    所述第二选通支路的第一端与所述数据信号端耦接，所述第二选通支路的第二端和与偶数列子像素耦接的所有所述第一数据线耦接；所述第二选通支路被配置为在第二时间段将所述数据信号端和与偶数列子像素耦接的所有所述第一数据线电导通；
    所述第三选通支路的第一端与所述数据信号端耦接，所述第三选通支路的第二端和与奇数列子像素耦接的所有所述第二数据线耦接；所述第三选通支路被配置为在第三时间段将所述数据信号端和与奇数列子像素耦接的所有所述第二数据线电导通；
    所述第四选通支路的第一端与所述数据信号端耦接，所述第四选通支路的第二端和与偶数列子像素耦接的所有所述第二数据线耦接；所述第四选通支路被配置为在第四时间段将所述数据信号端和与偶数列子像素耦接的所有所述第二数据线电导通；
    其中，所述第一时间段、所述第二时间段、所述第三时间段和所述第四时间段依次排列且互不重叠。
  5. 根据权利要求1～4中任一项所述的显示面板，其中，
    所述数据信号端包括多个子数据信号端，一个子数据信号端同时与每个选通支路所连接的所有数据线中的一条数据线耦接。
  6. 根据权利要求1～5中任一项所述的显示面板，其中，
    每列所述子像素连接的所述第一数据线位于该列所述子像素的第一侧，每列所述子像素连接的所述第二数据线位于该列所述子像素的第二侧。
  7. 根据权利要求1～5中任一项所述的显示面板，其中，
    奇数列的所述子像素连接的所述第一数据线位于该列所述子像素的第一侧，奇数列的所述子像素连接的所述第二数据线位于该列所述子像素的第二侧；
    偶数列的所述子像素连接的所述第一数据线位于该列所述子像素的第二侧，偶数列的所述子像素连接的所述第二数据线位于该列所述子像素的第一侧。
  8. 一种显示装置，包括：
    如权利要求1～7中任一项所述的显示面板。
  9. 一种显示面板的驱动方法，用于驱动如权利要求1～7中任一项所述的显示面板；所述驱动方法包括：
    通过所述分时复用电路将所述数据信号端分时地与所述第一数据线和所述第二数据线电导通，使所述数据信号端输出的数据信号分时地输入所述第一数据线和所述第二数据线；
    通过所述像素控制电路向各行所述子像素分时地输入栅极控制信号，使各行所述子像素中的像素电路导通；向相邻的两行所述子像素输入所述栅极控制信号的信号输入时间段部分重叠；
    根据各行所述子像素中的像素电路导通情况，通过所述第一数据线和所述第二数据线，将数据信号分时地输入各行所述子像素。
  10. 根据权利要求9所述的驱动方法，其中，所述分时复用电路包括：至少两个选通支路；
    所述通过所述分时复用电路将所述数据信号端分时地与所述第一数据线和所述第二数据线电导通，使所述数据信号端输出的数据信号分时地输入所述第一数据线和所述第二数据线，包括：
    在不同时间段控制不同的选通支路导通，所有选通支路的导通时间段依次排列且互不重叠。
  11. 根据权利要求10所述的驱动方法，其中，
    所述子像素连接的数据线与所述数据信号端电导通时间段的开始时刻在该子像素的栅极控制信号的信号输入时间段的起始时刻之前；
    所述子像素连接的数据线与所述数据信号端电导通时间段的结束时刻在该子像素的栅极控制信号的信号输入时间段的结束时刻之前；
    其中，所述数据线为所述第一数据线或所述第二数据线。
  12. 根据权利要求10或11所述的驱动方法，其中，
    所述至少两个选通支路包括：第一选通支路和第二选通支路；
    所述通过所述分时复用电路将所述数据信号端分时地与所述第一数据线和所述第二数据线电导通，使所述数据信号端输出的数据信号分时地输入所述第一数据线和所述第二数据线，包括：
    在第一时间段，通过所述第一选通支路将所述数据信号端与所有所述第一数据线电导通，使所述数据信号端输出的数据信号输入所有所述第一数据线；
    在第二时间段，通过所述第二选通支路将所述数据信号端与所有所述第二数据线电导通，使所述数据信号端输出的数据信号输入所有所述第二数据线；
    其中，所述第一时间段和所述第二时间段依次排列且不重叠。
  13. 根据权利要求12所述的驱动方法，其中，
    所述第一时间段的起始时刻在第一行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前，所述第一时间段的结束时刻在第一行所述子像素的栅级控制信号的信号输入时间段的结束时刻之前；
    所述第二时间段的起始时刻在第二行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前，所述第二时间段的结束时刻在第二行所述子像素的栅级控制信号的信号输入时间段的结束时刻之前。
  14. 根据权利要求10或11所述的驱动方法，其中，
    所述至少两个选通支路包括：第一选通支路、第二选通支路、第三选通支路和第四选通支路；
    所述通过所述分时复用电路分时地将所述数据信号端与所述第一数据线和所述第二数据线电导通，使所述数据信号端输出的数据信号分时地输入所述第一数据线和所述第二数据线，包括：
    在第一时间段，通过所述第一选通支路将所述数据信号端和与奇数列子像素耦接的所有所述第一数据线电导通，使所述数据信号端输出的数据信号输入与奇数列子像素耦接的所有所述第一数据线；
    在第二时间段，通过所述第二选通支路将所述数据信号端和与偶数列子像素耦接的所有所述第一数据线电导通，使所述数据信号端输出的数据信号输入与偶数列子像素耦接的所有所述第一数据线；
    在第三时间段，通过所述第三选通支路将所述数据信号端和与奇数列子像素耦接的所有所述第二数据线电导通，使所述数据信号端输出的数据信号输入与奇数列子像素耦接的所有所述第二数据线；
    在第四时间段，通过第四选通支路将所述数据信号端和与偶数列子像 素耦接的所有所述第二数据线电导通，使所述数据信号端输出的数据信号输入与偶数列子像素耦接的所有所述第二数据线；
    所述第一时间段、所述第二时间段、所述第三时间段和所述第四时间段依次排列且互不重叠。
  15. 根据权利要求14所述的驱动方法，其中，
    所述第一时间段的起始时刻在第一行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前；
    所述第二时间段的结束时刻在第一行所述子像素的栅级控制信号的信号输入时间段的结束时刻之前；
    所述第三时间段的起始时刻在第二行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前；
    所述第四时间段的结束时刻在第二行所述子像素的栅级控制信号的信号输入时间段的结束时刻之前。
  16. 根据权利要求14或15所述的驱动方法，其中，
    所述第一时间段的结束时刻在第一行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前；
    所述第二时间段的起始时刻在第一行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前；
    所述第三时间段的结束时刻在第二行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前；
    所述第四时间段的起始时刻在第二行所述子像素的栅级控制信号的信号输入时间段的起始时刻之前。
  17. 根据权利要求14～16任一项所述的驱动方法，其中，
    第一行所述子像素的栅级控制信号的信号输入时间段的结束时刻在下一个所述第一时间段的起始时刻之前；
    第二行所述子像素的栅级控制信号的信号输入时间段的结束时刻在下一个所述第三时间段的起始时刻之前。
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