WO2021258463A1 - 数据驱动电路和显示面板 - Google Patents
数据驱动电路和显示面板 Download PDFInfo
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- WO2021258463A1 WO2021258463A1 PCT/CN2020/103179 CN2020103179W WO2021258463A1 WO 2021258463 A1 WO2021258463 A1 WO 2021258463A1 CN 2020103179 W CN2020103179 W CN 2020103179W WO 2021258463 A1 WO2021258463 A1 WO 2021258463A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
Definitions
- This application relates to the field of display technology, and in particular to a data driving circuit and a display panel.
- Time multiplexing is used to charge each column of data lines.
- Fig. 1 The structure of the existing time-division multiplexed data driving circuit is shown in Fig. 1, which includes a time-division multiplexed signal input module 10 and a plurality of switch modules 20.
- the data lines in the display panel are divided into two groups.
- the first group of data lines includes slave The first data line D1, the third data line D3,..., the 2n-1 data line D(2n-1) from left to right
- the second group of data lines includes the second data line from left to right D2, the 4th data line D4,..., the 2nth data line D(2n), for convenience of representation, only D1 to D4 are shown in FIG. 1, where the switch modules 20 corresponding to D1 to D4 include in turn The gates of the transistors T1, T2, T3, and T4, and the gates of T1 and T3 are connected to the Q point, and the gates of T2 and T4 are connected to the P point.
- the first time-division multiplexing input terminal 11 in the time-division multiplexing signal input module 10 is used to input to point Q the first time-division multiplexing signal MUX1 that controls the first group of data lines
- the second time-division multiplexing input terminal 12 is used
- the second time-division multiplexing signal MUX2 that controls the second group of data lines is input, and the first time-division multiplexing signal MUX1 and the second time-division multiplexing signal MUX2 are alternately input.
- the first time-division multiplexed signal MUX1 when the first time-division multiplexed signal MUX1 is high, T1 and T3 are turned on, Data1 and Data2 input signals to D1 and D3, and the output signals of D1 and D3 are Data1' and Data2' respectively.
- the first time-division multiplexed signal MUX1 is at a low level, T1 and T3 are closed, and the second time-division multiplexed signal MUX2 turns from a low level to a high level.
- T2 and T4 are turned on, and Data1 and Data2 are input signals to D2 and D4.
- the output signals of D2 and D4 are Data1' and Data2' respectively.
- the transistors in the switch module 20 mostly use NMOS transistors.
- the RC loading of the NMOS transistors will cause the delay of the data signal output to the data line, as shown in Figures 3 and 4, making the rising edge time of the output Data1' signal longer. It is longer, and the charging time of the corresponding data line is compressed, so that the pixel corresponding to the data line is undercharged.
- the existing display panel has a technical problem of insufficient pixel charging, which needs to be improved.
- the embodiment of the present application provides a data driving circuit and a display panel to alleviate the technical problem of insufficient pixel charging in the existing display panel.
- This application provides a data driving circuit, including:
- the time-division multiplexed signal input module includes at least two time-division multiplexed signal input terminals, which are used to alternately input the time-division multiplexed signal to different control points.
- Each control point corresponds to a group of data lines, and each group of data lines Including multiple data lines;
- each switch module is connected to a data line, and the first input terminals of the switch modules corresponding to the same group of data lines are all connected to the same control point, and the switch module is used for the potential at the corresponding control point And under the control of the first data signal, output the second data signal to the connected data line;
- the potential control module is set corresponding to at least one set of data lines, and the first input end of the potential control module is connected to the first time-division multiplexed signal input end corresponding to the set of data lines, and the output end of the potential control module is connected to The control points corresponding to this group of data lines are connected, and the potential control module is used in the first driving stage, under the control of the first time-division multiplexed signal input from the first time-division multiplexed signal input terminal, corresponding The potential of the control point is pulled up to the first high potential.
- the second driving stage under the control of the first time-division multiplexed signal and the first data signal, the potential of the corresponding control point is changed from the first The high potential is pulled up to the second high potential.
- the second input terminal of the potential control module is connected to the second time-division multiplexed signal input terminal corresponding to the lower group of data lines, and the potential control module is also used to In the stage, under the control of the first time-division multiplexing signal and the second time-division multiplexing signal input from the second time-division multiplexing signal input terminal, the potential of the control point is pulled low.
- the switch module includes a first transistor, the gate of the first transistor is connected to the first time-division multiplexed signal input terminal corresponding to the group of data lines to the control point, and the first transistor is connected to the control point.
- the first electrode of a transistor is connected to the first data signal, and the second electrode of the first transistor is connected to the data line.
- the potential control module includes a second transistor and a third transistor, and the gate and first electrode of the second transistor, and the first electrode of the third transistor are all connected to the first transistor.
- a time-division multiplexing signal, the second electrode of the second transistor and the second electrode of the third transistor are both connected to the gate of the first transistor at a control point, and the gate of the third transistor is connected to Into the second time-division multiplexed signal.
- the first transistor is an NMOS transistor.
- each group of data lines includes the same number of data lines.
- each group of data lines includes a plurality of data lines arranged at intervals, and the number of data lines spaced between each data line is equal.
- the second input terminal of the switch module corresponding to the i-th data line in each group of data lines is connected to the same first data signal.
- a potential control module is provided between the switch module and the time-division multiplexing signal output terminal of each group of data lines.
- the working time of the potential control modules corresponding to different groups of data lines does not overlap.
- the present application also provides a display panel including multiple columns of data lines and a data driving circuit, and the data driving circuit includes:
- the time-division multiplexed signal input module includes at least two time-division multiplexed signal input terminals, which are used to alternately input the time-division multiplexed signal to different control points.
- Each control point corresponds to a group of data lines, and each group of data lines Including multiple data lines;
- each switch module is connected to a data line, and the first input terminals of the switch modules corresponding to the same group of data lines are all connected to the same control point, and the switch module is used for the potential at the corresponding control point And under the control of the first data signal, output the second data signal to the connected data line;
- the potential control module is set corresponding to at least one set of data lines, and the first input end of the potential control module is connected to the first time-division multiplexed signal input end corresponding to the set of data lines, and the output end of the potential control module is connected to The control points corresponding to this group of data lines are connected, and the potential control module is used in the first driving stage, under the control of the first time-division multiplexed signal input from the first time-division multiplexed signal input terminal, corresponding The potential of the control point is pulled up to the first high potential.
- the second driving stage under the control of the first time-division multiplexed signal and the first data signal, the potential of the corresponding control point is changed from the first The high potential is pulled up to the second high potential.
- the second input terminal of the potential control module is connected to the second time-division multiplexed signal input terminal corresponding to the lower group of data lines, and the potential control module is also used to: Under the control of the first time-division multiplexing signal and the second time-division multiplexing signal input from the second time-division multiplexing signal input terminal, the potential of the control point is pulled low.
- the switch module includes a first transistor, the gate of the first transistor and the first time-division multiplexing signal input terminal corresponding to the group of data lines are connected to the control point, and the first The first electrode of the transistor is connected to the first data signal, and the second electrode of the first transistor is connected to the data line.
- the potential control module includes a second transistor and a third transistor.
- the gate and first electrode of the second transistor and the first electrode of the third transistor are all connected to the first transistor.
- Time-division multiplexing signals, the second electrode of the second transistor and the second electrode of the third transistor are both connected to the gate of the first transistor at a control point, and the gate of the third transistor is connected to The second time division multiplexed signal.
- the first transistor is an NMOS transistor.
- the number of data lines included in each group of data lines is equal.
- each group of data lines includes a plurality of data lines arranged at intervals, and the number of data lines spaced between each data line is equal.
- the second input terminal of the switch module corresponding to the i-th data line in each group of data lines is connected to the same first data signal.
- a potential control module is provided between the switch module and the time-division multiplexing signal output terminal of each group of data lines.
- the working time of the potential control modules corresponding to different groups of data lines does not overlap.
- the application provides a data driving circuit and a display panel.
- the data driving circuit includes a time-division multiplexing signal input module, a plurality of switch modules, and a potential control module; the time-division multiplexing signal input module includes at least two The time-division multiplexing signal input terminal is used to alternately input the time-division multiplexing signal to different control points.
- Each control point corresponds to a group of data lines, and each group of data lines includes multiple data lines; the output of each switch module
- the first input terminals of the switch modules corresponding to the same group of data lines are all connected to the same control point.
- the switch module is used to connect to the corresponding control point under the control of the corresponding control point potential and the first data signal.
- the data line outputs the second data signal;
- the potential control module is set corresponding to at least one set of data lines, and the first input end of the potential control module is connected to the first time-division multiplexed signal input end corresponding to the set of data lines, so
- the output terminal of the potential control module is connected to the control point corresponding to the group of data lines, and the potential control module is used for the first time-sharing multiplexer input at the first time-division multiplexing signal input terminal in the first driving stage. Under the control of the signal, the potential of the corresponding control point is pulled up to the first high potential.
- the corresponding control Under the control of the first time-division multiplexed signal and the first data signal, the corresponding control The electric potential of the point is pulled up from the first high electric potential to the second high electric potential.
- a potential control module is provided between the time-division multiplexed signal input module and the switch module, and the potential of the control point is pulled up twice, so that the switch module can be turned on more fully, and the second data signal input to the data line rises The edge time is shortened, and the charging rate of the corresponding pixel of the data line is improved.
- FIG. 1 is a schematic diagram of the structure of a data driving circuit in the prior art.
- FIG. 2 is a timing diagram of various signals in a data driving circuit in the prior art.
- FIG. 3 is a simulation diagram of various signals in a data driving circuit in the prior art.
- Fig. 4 is an enlarged schematic diagram of the Data1' signal in Fig. 3.
- FIG. 5 is a schematic structural diagram of a data driving circuit provided by an embodiment of the application.
- FIG. 6 is a timing diagram of various signals in the data driving circuit provided by an embodiment of the application.
- FIG. 7 is a simulation diagram of various signals in the data driving circuit provided by an embodiment of the application.
- Fig. 8 is an enlarged schematic diagram of the Data1' signal in Fig. 7.
- the embodiment of the present application provides a display panel to alleviate the technical problem of insufficient pixel charging in the existing display panel.
- the present application provides a data driving circuit, including a time-division multiplexing signal input module 100, a plurality of switch modules 200, and a potential control module 300;
- the time-division multiplexed signal input module 100 includes at least two time-division multiplexed signal input terminals, which are used to alternately input the time-division multiplexed signal to different control points.
- Each control point corresponds to a group of data lines, and each group of data lines Including multiple data lines;
- each switch module 200 is connected to a data line, and the first input terminals of the switch modules corresponding to the same group of data lines are all connected to the same control point.
- the switch module 200 is used to set the potential of the corresponding control point and the first data signal Under the control of, output the second data signal to the connected data line;
- the potential control module 300 is set corresponding to at least one set of data lines, and the first input end of the potential control module 300 is connected to the first time-division multiplexed signal input end corresponding to this set of data lines, and the output end of the potential control module 300 is connected to this set of data lines.
- the control point corresponding to the data line is connected, and the potential control module 300 is used to pull the potential of the corresponding control point under the control of the first time-division multiplexed signal input from the first time-division multiplexed signal input terminal in the first driving stage High to the first high potential, in the second driving stage, under the control of the first time-division multiplexed signal and the first data signal, the potential of the corresponding control point is pulled up from the first high potential to the second high potential.
- the display panel includes multiple columns of sub-pixels, each column of sub-pixels is connected to a data line, and the data signal written in the data line is used to drive and emit light.
- the data lines in the display panel are usually divided into at least two groups by time-division multiplexing.
- Each group of data lines includes multiple data lines, and each group of data lines includes the same number of data lines.
- Each group of data lines is controlled by a corresponding time-division multiplexed signal to control the time for writing the data signal, and the i-th data line in each group of data lines is controlled by a drive chip to input the data signal.
- Each group of data lines in the display panel includes multiple data lines, and each group of data lines includes multiple data lines arranged at intervals, and the number of data lines spaced between the data lines is equal.
- all data lines in the display panel include two When grouping data lines, the first group of data lines includes the first data line D1, the third data line D3,..., the 2n-1 data line D(2n-1) from left to right, and the second group The data lines include the second data line D2, the fourth data line D4, ..., and the 2n-th data line D(2n) from left to right.
- D1 to D4 are shown in FIG. 3.
- the time-division multiplexed signal input module 100 includes a first time-division multiplexed signal input terminal 101 and a second time-division multiplexed signal input terminal 102.
- the first time-division multiplexed signal input terminal 101 is used to correspond to the first group of data lines
- the first time-division multiplexed signal MUX1 is input to the control point of the second group of data lines.
- the second time-division multiplexed signal input terminal 102 is used to input the second time-division multiplexed signal MUX2 to the control point corresponding to the second group of data lines.
- the signal MUX1 is used to control the output of the data signal in the first group of data lines
- the second time-division multiplexed signal MUX2 is used to control the output of the data signal in the second group of data lines
- the time-division multiplexed signal input module 100 controls the second group of data signals.
- the one-time division multiplexing signal MUX1 and the second time-division multiplexing signal MUX2 are alternately input to different control points, thereby controlling each data line in the first group of data lines and each data line in the first group of data lines to correspond alternately Data signals are written in the sub-pixels of the column.
- each switch module 200 is connected to a data line, and the first input terminals of the switch module 200 corresponding to the same group of data lines are all connected to the same control point.
- the switch module 200 is used to set the corresponding control point potential and first data Under the control of the signal, the second data signal is input to the corresponding data line.
- the first input terminals of the switch module 200 corresponding to the first group of data lines are all connected to point Q, and the first input terminals of the switch module 200 corresponding to the second group of data lines are all connected to point P, where Q Point is the control point corresponding to the first group of data lines, and point P is the control point corresponding to the second group of data lines.
- the switch module 200 corresponding to the first group of data lines is used to write the first data lines D1, D3,..., D(2n-1) to the corresponding data lines D1, D3,..., D(2n-1) under the control of the Q point potential and the first input data signal Data1 Output data signal Data1'
- the switch module 200 corresponding to the second group of data lines is used to transmit data to the corresponding data lines D2, D4,..., D(2n) under the control of the P point potential and the second input data signal Data2.
- the first input data signal Data1 is the first data signal corresponding to the first group of data lines
- the first output data signal Data1' is the second data signal corresponding to the first group of data lines
- the second input data signal Data2 is the first data signal corresponding to the second group of data lines
- the second output data signal Data2' is the second data signal corresponding to the second group of data lines.
- the second input terminals of the switch module 200 corresponding to the i-th data line in each group of data lines are all connected to the same first data signal.
- D1 and D2 are the first data line in the first group of data lines and the first data line in the second group of data lines, respectively.
- the second input terminals of the switch modules 200 corresponding to both are connected to the first data line.
- An input data signal Data1, D3 and D4 are the second data line in the first group of data lines and the second data line in the second group of data lines respectively, and the second input terminals of the switch modules 200 corresponding to both are connected The second input data signal Data2.
- the potential control module 300 is set corresponding to at least one set of data lines, that is, only one potential control module 300 is provided between the time-division multiplexed signal input terminal corresponding to a set of data lines and the switch module 200, or each set of data lines corresponds to A potential control module 300 is provided between the time-division multiplexed signal input terminal and the switch module 200.
- a potential control module 300 is provided between the first time-division multiplexed signal input terminal 101 corresponding to the first group of data lines and the switch module 100, and the second time-division multiplexed signal input corresponding to the second group of data lines
- a potential control module 300 is also provided between the terminal 102 and the switch module 100.
- the second input terminal of the potential control module 300 is connected to the second time-division multiplexing signal input terminal 102 corresponding to the lower group of data lines. Under the control of the signal MUX1 and the second time-division multiplexed signal MUX2 input from the second time-division multiplexed signal input terminal 102, the potential of the control point is pulled low.
- the output terminal of the potential control module 300 is connected to the corresponding control point of the first group of data lines, that is, connected to point Q, the first input terminal of the potential control module 300 Connected to the corresponding first time-division multiplexed signal input terminal 101, and the second input terminal of the potential control module 300 is connected to the second time-division multiplexed signal input terminal 102 corresponding to the next set of data lines.
- the potential control module 300 is used for In the first driving stage, under the control of the first time-division multiplexed signal MUX1 input from the first time-division multiplexing signal input terminal 101, the potential of point Q is pulled up to the first high potential.
- the potential of point Q is pulled up from the first high potential to the second high potential.
- the first time-division multiplexing Under the control of the signal MUX1 and the second time-division multiplexing signal MUX2 input from the second time-division multiplexing signal input terminal 102, the potential of the Q point is pulled low.
- the working principle of the potential control module 300 corresponding to the second group of data lines is also the same, and will not be repeated here.
- the first time-division multiplexing signal MUX1 and the second time-division multiplexing signal MUX2 are alternately input, so the first group of data lines and the second group of data lines also alternately write the second data signal, when the first When the group of data lines is the current group of data lines, the second group of data lines is the next group of data lines, and when the second group of data lines is the current group of data lines, the first group of data lines is the next group of data lines.
- the number of data line groups is more than two groups, after the current time-division multiplexed signal work phase ends, the data line corresponding to the time-division multiplexed signal input at the next moment is the next set of data lines.
- the working time of the potential control module 300 corresponding to the first group of data lines and the potential control module 300 corresponding to the second group of data lines do not overlap, and the working time of the two is performed alternately.
- the switch module 200 includes a first transistor, the gate of the first transistor and the time-division multiplexed signal input terminal corresponding to the group of data lines are connected to the control point, and the first electrode of the first transistor is connected to the first data signal, The second electrode of the first transistor is connected to the data line.
- the potential control module 300 includes a second transistor and a third transistor.
- the gate and first electrode of the second transistor and the first electrode of the third transistor are all connected to the first time-division multiplexed signal, and the second electrode of the second transistor
- the second electrodes of the third transistor and the third transistor are both connected to the gate of the first transistor to the control point, and the gate of the third transistor is connected to the second time-division multiplexed signal corresponding to the other group of data lines.
- the first transistor is an NMOS transistor.
- the NMOS process requires 2 to 3 masks less, so the manufacturing process is simple, and it is widely used in high-resolution display panels.
- the data drive circuit includes transistors T1, T2, T3, T4, T-mux1, T-mux1', T-mux2, T-mux2', where T1 and T3 correspond to the first group of data lines
- the first transistor in the switch module 200, T2 and T4 are the first transistors in the switch module 200 corresponding to the second group of data lines
- T-mux1 and T-mux1' are the potential control modules 300 corresponding to the first group of data lines
- the second transistor and the third transistor in, T-mux2 and T-mux2' are respectively the second transistor and the third transistor in the potential control module 300 corresponding to the second group of data lines.
- Gate1 and Gate2 are the gate drive signals in the pixel drive circuit corresponding to the first row of sub-pixels and the second row of sub-pixels in the display panel, respectively. Control the opening of the first row of sub-pixels and the second row of sub-pixels.
- the first row of sub-pixels are turned on, the first time-division multiplexing signal MUX1 and the second time-division multiplexing signal MUX2 are turned on alternately, and the first group of data lines and the second group of data lines are controlled to alternate to the first group of data lines.
- One row of sub-pixels write data signals.
- the second row of sub-pixels are turned on, and the first time-division multiplexing signal MUX1 and the second time-division multiplexing signal MUX2 are alternately turned on to control the first group of data lines
- the write phase corresponding to each row of sub-pixels includes a first phase t1, a second phase t2, a third phase t3, and a fourth phase t4, where
- the first phase t1, the second phase t2, and the third phase t3 when Gate1 is at high potential are the first, second, and third driving phases corresponding to the first group of data lines, respectively.
- the third stage t3 and the fourth stage t4 are the first driving stage and the second driving stage corresponding to the second group of data lines, and the first stage t1 when Gate2 is at a high potential is the third driving stage corresponding to the second group of data lines.
- the first time-division multiplexed signal MUX1 is at high potential
- the second time-division multiplexed signal MUX2 is at low potential
- T-mux1 is turned on
- T-mux1' is turned off
- the first time-division multiplexed signal MUX1 The high potential of is input to the gates of transistors T1 and T3, and the potential of point Q is pulled up to the first high potential.
- the first time-division multiplexing signal MUX1 and the second time-division multiplexing signal MUX2 are both low. Due to the existence of T-mux1 and T-mux1' in the time-division multiplexing control module 300, these transistors The capacitance directly opposite to the gate of T1 is relatively large, so this capacitor will keep the gate potentials of T1 and T3 at the first high potential, that is, point Q maintains the first high potential, and at the same time, the first input data signal Data1 is at a high potential Based on the bootstrap effect of the floating capacitor, the gate potentials of T1 and T3 can be pulled up to the second high potential, that is, the Q point is pulled up from the first high potential to the second high potential.
- T1 and T3 are fully opened, the value of the first input data signal Data1 is 5V, and the value of the second input data signal Data2 is -5V.
- the corresponding first output data signal Data1' and second output data signal Data2' can be output with full swing, that is, the value of the first output data signal Data1' is also 5V, and the value of the second output data signal Data2' is also -5V, and
- the rising time of the two is also relatively short, so the charging time of each sub-pixel corresponding to the first group of data lines in the first row of sub-pixels is sufficient, and the charging rate is improved.
- the first time-division multiplexed signal MUX1 is at a low level
- the second time-division multiplexed signal MUX2 is at a high level
- T-mux2 is turned on
- T-mux2' is turned off
- the second time-division multiplexed signal MUX2 The high potential of is input to the gates of transistors T2 and T4, and the potential of point P is pulled up to the first high potential.
- the first time-division multiplexing signal MUX1 and the second time-division multiplexing signal MUX2 are both low. Due to the existence of T-mux2 and T-mux2' in the time-division multiplexing control module 300, these transistors The capacitance facing the gate of T2 is relatively large, so this capacitance will keep the gate potentials of T2 and T4 at the first high potential, that is, point P maintains the first high potential, and at the same time, the second input data signal Data2 is at a high potential Based on the bootstrap effect of the floating capacitor, the gate potentials of T2 and T4 can be pulled up to the second high potential, that is, point P is pulled up from the first high potential to the second high potential.
- T2 and T4 are fully opened, the value of the first input data signal Data1 is -5V, and the value of the second input data signal Data2 is 5V.
- T2 and T4 After the first input data signal Data1 and the second input data signal Data2 are input to T2 and T4, It can output the corresponding first output data signal Data1' and second output data signal Data2' in full swing, that is, the value of the first output data signal Data1' is also -5V, and the value of the second output data signal Data2' is also 5V, and
- the rising time of the two is also relatively short, so the charging time of each sub-pixel corresponding to the second group of data lines in the first row of sub-pixels is sufficient, and the charging rate is improved.
- the rising edge of the output waveform of Data1' drops from 1.3us to 0.9us, the highest voltage of Data1' It is also increased to 5V, that is, in this application, at least one potential control module 300 is provided between the time-division multiplexed signal input module 100 and the switch module 200, and the potential of the control point is raised twice, so that the switch module 200 is more open. Therefore, the on-state current Ion of the switch module 200 is increased, the rising edge time of the second data signal input to the data line is shortened, the charging rate of the pixel corresponding to the data line is improved, and this design has almost no effect on the frame size of the display panel , So the structure is simple, and the effect of increasing the charging rate is obvious.
- a data driving circuit including two time-division multiplexing signals is taken as an example for description, but the present application is not limited to this, and includes three or more time-division multiplexing signals.
- the signal data driving circuit can also be provided with a time-division multiplexing control module, and its working principle is applicable to any data driving circuit including a time-division multiplexing signal.
- the present application also provides a display panel including multiple columns of data lines and a data driving circuit, and the data driving circuit is the data driving circuit described in any one of the above.
- the display panel of the present application can be a liquid crystal display panel or an OLED display panel.
- a potential control module is provided between the time-division multiplexed signal input module and the switch module in the data driving circuit, and the potential of the control point is raised twice, so that The switch module is turned on more fully, the rising edge time of the second data signal input to the data line is shortened, and the charging rate of the pixel corresponding to the data line is improved.
- the data drive circuit includes a time-division multiplexed signal input module, a plurality of switch modules, and a potential control module;
- the time-division multiplexed signal input module includes at least two time-division multiplexed signal inputs Terminal, used to alternately input time-division multiplexed signals to different control points, each control point corresponding to control a group of data lines, each group of data lines includes multiple data lines;
- each switch module output terminal is connected to a data line , The first input terminals of the switch modules corresponding to the same group of data lines are all connected to the same control point, and the switch module is used to output the second input terminal to the connected data line under the control of the corresponding control point potential and the first data signal.
- the potential control module is set corresponding to at least one set of data lines, and the first input end of the potential control module is connected to the first time-division multiplexed signal input end corresponding to this set of data lines, and the output of the potential control module
- the terminal is connected to the control point corresponding to the group of data lines, and the potential control module is used in the first driving stage, under the control of the first time-division multiplexed signal input from the first time-division multiplexed signal input terminal, The potential of the corresponding control point is pulled up to the first high potential.
- the potential of the corresponding control point is changed from the The first high potential is pulled up to the second high potential.
- a potential control module is provided between the time-division multiplexed signal input module and the switch module, and the potential of the control point is pulled up twice, so that the switch module is turned on more fully, and the rising edge of the second data signal input to the data line The time is shortened, and the charging rate of the corresponding pixel of the data line is improved.
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Abstract
本申请提供一种数据驱动电路和显示面板，数据驱动电路中分时复用信号输入模块用于交替输入向不同的控制点输入分时复用信号，开关模块用于在控制点电位和第一数据信号的控制下，向对应的数据线输入第二数据信号；电位控制模块用于对控制点的电位进行两次拉高，因此使得开关模块打开更加充分，数据线对应像素充电率得到提升。
Description
本申请涉及显示技术领域，尤其涉及一种数据驱动电路和显示面板。
随着显示技术的迅速发展，人们对显示面板的分辨率要求越来越高，因此显示面板中的数据线较多，所需要的源驱动器也越多，为减少源驱动器的数量，通常采用分时复用的方式来实现对每列数据线的充电。现有的分时复用数据驱动电路结构如图1所示，包括分时复用信号输入模块10和多个开关模块20，显示面板中数据线分为两组，第一组数据线包括从左至右第1条数据线D1、第3条数据线D3、...、第2n-1条数据线D(2n-1)，第二组数据线包括从左至右第2条数据线D2、第4条数据线D4、...、第2n条数据线D(2n)，为方便表示，图1中仅示出了D1至D4，其中D1至D4对应的开关模块20中依次包括晶体管T1、T2、T3和T4，且T1和T3的栅极连接于Q点，T2和T4的栅极连接于P点。分时复用信号输入模块10中第一分时复用输入端11用于向Q点输入控制第一组数据线的第一分时复用信号MUX1，第二分时复用输入端12用于向P点输入控制第二组数据线的第二分时复用信号MUX2，第一分时复用信号MUX1和第二分时复用信号MUX2交替输入。如图2所示，当第一分时复用信号MUX1为高电位时，T1和T3打开，Data1和Data2给D1和D3输入信号，D1和D3的输出信号分别为Data1’和Data2’，之后第一分时复用信号MUX1为低电位，T1和T3关闭，第二分时复用信号MUX2由低电位转为高点位，此时T2和T4打开，Data1和Data2给D2和D4输入信号，D2和D4的输出信号分别为Data1’和Data2’。
然而，开关模块20中晶体管多采用NMOS晶体管，NMOS晶体管的RC loading会造成输出给数据线的数据信号的延迟，如图3和图4所示，使得输出的Data1’信号的上升沿的时间较长，进而压缩对应的数据线的充电时间，使得数据线对应的像素充电不足。
因此，现有的显示面板存在像素充电不足的技术问题，需要改进。
本申请实施例提供一种数据驱动电路和显示面板，用以缓解现有的显示面板中像素充电不足的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种数据驱动电路，包括：
分时复用信号输入模块，包括至少两个分时复用信号输入端，用于交替向不同的控制点输入分时复用信号，每个控制点对应控制一组数据线，每组数据线包括多条数据线；
多个开关模块，每个开关模块的输出端接入一条数据线，同组数据线对应的开关模块的第一输入端均连接于同一控制点，所述开关模块用于在对应的控制点电位和第一数据信号的控制下，向连接的数据线输出第二数据信号；
电位控制模块，对应至少一组数据线设置，且所述电位控制模块的第一输入端与本组数据线对应的第一分时复用信号输入端连接，所述电位控制模块的输出端与本组数据线对应的控制点连接，所述电位控制模块用于在第一驱动阶段，在所述第一分时复用信号输入端输入的第一分时复用信号的控制下，将对应控制点的电位拉高至第一高电位，在第二驱动阶段，在所述第一分时复用信号和所述第一数据信号的控制下，将对应控制点的电位由所述第一高电位拉高至第二高电位。
在本申请的数据驱动电路中，所述电位控制模块的第二输入端与下组数据线对应的第二分时复用信号输入端连接，所述电位控制模块还用于，在第三驱动阶段，在所述第一分时复用信号和所述第二分时复用信号输入端输入的第二分时复用信号的控制下，将所述控制点的电位拉低。
在本申请的数据驱动电路中，所述开关模块包括第一晶体管，所述第一晶体管的栅极与本组数据线对应的第一分时复用信号输入端连接于控制点，所述第一晶体管的第一电极接入第一数据信号，所述第一晶体管的第二电极与数据线连接。
在本申请的数据驱动电路中，所述电位控制模块包括第二晶体管和第三晶体管，所述第二晶体管的栅极和第一电极、以及第三晶体管的第一电极均接入所述第一分时复用信号，所述第二晶体管的第二电极和所述第三晶体管的第二电极均与所述第一晶体管的栅极连接于控制点，所述第三晶体管的栅极接入所述第二分时复用信号。
在本申请的数据驱动电路中，所述第一晶体管为NMOS晶体管。
在本申请的数据驱动电路中，各组数据线包括的数据线数量相等。
在本申请的数据驱动电路中，每组数据线包括多条间隔设置的数据线，且各数据线之间间隔的数据线数量相等。
在本申请的数据驱动电路中，各组数据线中第i条数据线对应的开关模块的第二输入端均接入相同的第一数据信号。
在本申请的数据驱动电路中，各组数据线的开关模块和分时复用信号输出端之间均设置有电位控制模块。
在本申请的数据驱动电路中，不同组数据线对应的电位控制模块，工作时间不重叠。
本申请还提供一种显示面板，包括多列数据线和数据驱动电路，所述数据驱动电路包括：
分时复用信号输入模块，包括至少两个分时复用信号输入端，用于交替向不同的控制点输入分时复用信号，每个控制点对应控制一组数据线，每组数据线包括多条数据线；
多个开关模块，每个开关模块的输出端接入一条数据线，同组数据线对应的开关模块的第一输入端均连接于同一控制点，所述开关模块用于在对应的控制点电位和第一数据信号的控制下，向连接的数据线输出第二数据信号；
电位控制模块，对应至少一组数据线设置，且所述电位控制模块的第一输入端与本组数据线对应的第一分时复用信号输入端连接，所述电位控制模块的输出端与本组数据线对应的控制点连接，所述电位控制模块用于在第一驱动阶段，在所述第一分时复用信号输入端输入的第一分时复用信号的控制下，将对应控制点的电位拉高至第一高电位，在第二驱动阶段，在所述第一分时复用信号和所述第一数据信号的控制下，将对应控制点的电位由所述第一高电位拉高至第二高电位。
在本申请的显示面板中，所述电位控制模块的第二输入端与下组数据线对应的第二分时复用信号输入端连接，所述电位控制模块还用于，在第三驱动阶段，在所述第一分时复用信号和所述第二分时复用信号输入端输入的第二分时复用信号的控制下，将所述控制点的电位拉低。
在本申请的显示面板中，所述开关模块包括第一晶体管，所述第一晶体管的栅极与本组数据线对应的第一分时复用信号输入端连接于控制点，所述第一晶体管的第一电极接入第一数据信号，所述第一晶体管的第二电极与数据线连接。
在本申请的显示面板中，所述电位控制模块包括第二晶体管和第三晶体管，所述第二晶体管的栅极和第一电极、以及第三晶体管的第一电极均接入所述第一分时复用信号，所述第二晶体管的第二电极和所述第三晶体管的第二电极均与所述第一晶体管的栅极连接于控制点，所述第三晶体管的栅极接入所述第二分时复用信号。
在本申请的显示面板中，所述第一晶体管为NMOS晶体管。
在本申请的显示面板中，各组数据线包括的数据线数量相等。
在本申请的显示面板中，每组数据线包括多条间隔设置的数据线，且各数据线之间间隔的数据线数量相等。
在本申请的显示面板中，各组数据线中第i条数据线对应的开关模块的第二输入端均接入相同的第一数据信号。
在本申请的显示面板中，各组数据线的开关模块和分时复用信号输出端之间均设置有电位控制模块。
在本申请的显示面板中，不同组数据线对应的电位控制模块，工作时间不重叠。
本申请的有益效果：本申请提供一种数据驱动电路和显示面板，数据驱动电路包括分时复用信号输入模块、多个开关模块和电位控制模块；分时复用信号输入模块包括至少两个分时复用信号输入端，用于交替向不同的控制点输入分时复用信号，每个控制点对应控制一组数据线，每组数据线包括多条数据线；每个开关模块的输出端接入一条数据线，同组数据线对应的开关模块的第一输入端均连接于同一控制点，所述开关模块用于在对应的控制点电位和第一数据信号的控制下，向连接的数据线输出第二数据信号；电位控制模块对应至少一组数据线设置，且所述电位控制模块的第一输入端与本组数据线对应的第一分时复用信号输入端连接，所述电位控制模块的输出端与本组数据线对应的控制点连接，所述电位控制模块用于在第一驱动阶段，在所述第一分时复用信号输入端输入的第一分时复用信号的控制下，将对应控制点的电位拉高至第一高电位，在第二驱动阶段，在所述第一分时复用信号和所述第一数据信号的控制下，将对应控制点的电位由所述第一高电位拉高至第二高电位。本申请通过在分时复用信号输入模块和开关模块之间设置电位控制模块，对控制点的电位进行两次拉高，可以使得开关模块打开更加充分，输入给数据线的第二数据信号上升沿时间缩短，数据线对应像素充电率得到提升。
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中数据驱动电路的结构示意图。
图2为现有技术的数据驱动电路中各信号的时序图。
图3为现有技术的数据驱动电路中各信号的仿真图。
图4为图3中Data1’信号的放大示意图。
图5为本申请实施例提供的数据驱动电路的结构示意图。
图6为本申请实施例提供的数据驱动电路中各信号的时序图。
图7为本申请实施例提供的数据驱动电路中各信号的仿真图。
图8为图7中Data1’信号的放大示意图。
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相近的单元是用以相同标号表示。
本申请实施例提供一种显示面板，用以缓解现有的显示面板中像素充电不足的技术问题。
如图5所示，本申请提供一种数据驱动电路，包括分时复用信号输入模块100、多个开关模块200和电位控制模块300；
分时复用信号输入模块100包括至少两个分时复用信号输入端，用于交替向不同的控制点输入分时复用信号，每个控制点对应控制一组数据线，每组数据线包括多条数据线；
每个开关模块200的输出端接入一条数据线，同组数据线对应的开关模块的第一输入端均连接于同一控制点，开关模块200用于在对应的控制点电位和第一数据信号的控制下，向连接的数据线输出第二数据信号；
电位控制模块300对应至少一组数据线设置，且电位控制模块300的第一输入端与本组数据线对应的第一分时复用信号输入端连接，电位控制模块300的输出端与本组数据线对应的控制点连接，电位控制模块300用于在第一驱动阶段，在第一分时复用信号输入端输入的第一分时复用信号的控制下，将对应控制点的电位拉高至第一高电位，在第二驱动阶段，在第一分时复用信号和第一数据信号的控制下，将对应控制点的电位由第一高电位拉高至第二高电位。
在显示面板中包括多列子像素，每列子像素连接一条数据线，通过数据线写入的数据信号进行驱动发光。为减少驱动芯片的数量，通常采用分时复用的方式，将显示面板中数据线分为至少两组，每组数据线包括多条数据线，且各组数据线包括的数据线数量相等，每组数据线由对应的分时复用信号控制写入数据信号的时间，各组数据线中第i条数据线均由一个驱动芯片控制输入数据信号。
在图5中，以分时复用信号输入模块100包括两个分时复用信号输入端，且电位控制模块300对应两组数据线设置为例，对各模块的工作原理进行说明。
显示面板中每组数据线中均包括多条数据线，每组数据线包括多条间隔设置的数据线，且各数据线之间间隔的数据线数量相等，当显示面板中所有数据线包括两组数据线时，第一组数据线包括从左至右第1条数据线D1、第3条数据线D3、...、第2n-1条数据线D(2n-1)，第二组数据线包括从左至右第2条数据线D2、第4条数据线D4、...、第2n条数据线D(2n)，为方便表示，图3中仅示出了D1至D4。
分时复用信号输入模块100包括第一分时复用信号输入端101和第二分时复用信号输入端102，第一分时复用信号输入端101用于向第一组数据线对应的控制点输入第一分时复用信号MUX1，第二分时复用信号输入端102用于向第二组数据线对应的控制点输入第二分时复用信号MUX2，第一分时复用信号MUX1用于控制第一组数据线中数据信号的输出，第二分时复用信号MUX2用于控制第二组数据线中数据信号的输出，分时复用信号输入模块100通过控制第一分时复用信号MUX1和第二分时复用信号MUX2交替输入至不同的控制点，进而控制第一组数据线中各条数据线和第一组数据线中各条数据线交替向对应列的子像素中写入数据信号。
每个开关模块200的输出端接入一条数据线，同组数据线对应的开关模块200的第一输入端均连接于同一控制点，开关模块200用于在对应的控制点电位和第一数据信号的控制下，向对应的数据线输入第二数据信号。在图5中，第一组数据线对应的开关模块200的第一输入端均连接于Q点，第二组数据线对应的开关模块200的第一输入端均连接于P点，其中，Q点为第一组数据线对应的控制点，P点为第二组数据线对应的控制点。
第一组数据线对应的开关模块200用于在Q点电位和第一输入数据信号Data1的控制下，向对应的数据线D1、D3、...、D(2n-1)写入第一输出数据信号Data1’，第二组数据线对应的开关模块200用于在P点电位和第二输入数据信号Data2的控制下，向对应的数据线D2、D4、...、D(2n)写入第二输出数据信号Data2’，其中，第一输入数据信号Data1为第一组数据线对应的第一数据信号，第一输出数据信号Data1’为第一组数据线对应的第二数据信号，第二输入数据信号Data2为第二组数据线对应的第一数据信号，第二输出数据信号Data2’为第二组数据线对应的第二数据信号。
各组数据线中第i条数据线对应的开关模块200的第二输入端均接入相同的第一数据信号。在图5中，D1和D2分别为第一组数据线中第1条数据线和第二组数据线中第1条数据线，两者对应的开关模块200的第二输入端均接入第一输入数据信号Data1，D3和D4分别为第一组数据线中第2条数据线和第二组数据线中第2条数据线，两者对应的开关模块200的第二输入端均接入第二输入数据信号Data2。
电位控制模块300对应至少一组数据线设置，即可仅在一组数据线对应的分时复用信号输入端和开关模块200之间设置一个电位控制模块300，也可以在每组数据线对应的分时复用信号输入端和开关模块200之间均设置一个电位控制模块300。本实施例中第一组数据线对应的第一分时复用信号输入端101和开关模块100之间设置有一个电位控制模块300，第二组数据线对应的第二分时复用信号输入端102和开关模块100之间也设置有一个电位控制模块300。
此外，电位控制模块300的第二输入端与下组数据线对应的第二分时复用信号输入端102连接，电位控制模块300还用于，在第三驱动阶段，在第一分时复用信号MUX1和第二分时复用信号输入端102输入的第二分时复用信号MUX2的控制下，将控制点的电位拉低。
以第一组数据线对应的电位控制模块300为例，该电位控制模块300的输出端与第一组数据线对应控制点连接，也即与Q点连接，电位控制模块300的第一输入端与对应的第一分时复用信号输入端101连接，电位控制模块300的第二输入端与下组数据线对应的第二分时复用信号输入端102连接，该电位控制模块300用于在第一驱动阶段，在第一分时复用信号输入端101输入的第一分时复用信号MUX1的控制下，将Q点的电位拉高至第一高电位，在第二驱动阶段，在第一分时复用信号MUX1和第一数据信号Data1的控制下，将Q点的电位由第一高电位拉高至第二高电位，在第三驱动阶段，在第一分时复用信号MUX1和第二分时复用信号输入端102输入的第二分时复用信号MUX2的控制下，将Q点的电位拉低。同样地，第二组数据线对应的电位控制模块300工作原理也相同，在此不再赘述。
在本实施例中，第一分时复用信号MUX1和第二分时复用信号MUX2交替输入，因此第一组数据线和第二组数据线也交替写入第二数据信号，当第一组数据线为本组数据线时，第二组数据线为下组数据线，当第二组数据线为本组数据线时，第一组数据线为下组数据线。依次类推，当数据线组数多于两组时，以当前分时复用信号工作阶段结束后，下一时刻输入的分时复用信号所对应的数据线为下组数据线。
需要说明的是，第一组数据线对应的电位控制模块300和第二组数据线对应的电位控制模块300工作时间不重叠，两者的工作时间交替进行。
具体地，开关模块200包括第一晶体管，第一晶体管的栅极与本组数据线对应的分时复用信号输入端连接于控制点，第一晶体管的第一电极接入第一数据信号，第一晶体管的第二电极与数据线连接。电位控制模块300包括第二晶体管和第三晶体管，第二晶体管的栅极和第一电极、以及第三晶体管的第一电极均接入第一分时复用信号，第二晶体管的第二电极和第三晶体管的第二电极均与第一晶体管的栅极连接于控制点，第三晶体管的栅极接入其他组数据线对应的第二分时复用信号。
在一种实施例中，第一晶体管为NMOS晶体管，NMOS工艺相较于CMOS工艺要少2张到3张光罩，因此制造工艺简单，在高分辨率的显示面板中广泛应用。
如图5所示，数据驱动电路中包括晶体管T1、T2、T3、T4、T-mux1、T-mux1’、T-mux2、T-mux2’，其中T1和T3为第一组数据线对应的开关模块200中的第一晶体管，T2和T4为第二组数据线对应的开关模块200中的第一晶体管，T-mux1和T-mux1’分别为第一组数据线对应的电位控制模块300中的第二晶体管和第三晶体管，T-mux2和T-mux2’分别为第二组数据线对应的电位控制模块300中的第二晶体管和第三晶体管。
如图6所示，为数据驱动电路中各信号的时序图，此外，Gate1和Gate2分别为显示面板中第一行子像素和第二行子像素对应的像素驱动电路中栅极驱动信号，分别控制第一行子像素和第二行子像素的打开。
当Gate1为高电位时，第一行子像素被打开，第一分时复用信号MUX1和第二分时复用信号MUX2交替打开，控制第一组数据线和第二组数据线交替向第一行子像素写入数据信号，当Gate2为高电位时，第二行子像素被打开，第一分时复用信号MUX1和第二分时复用信号MUX2交替打开，控制第一组数据线和第二组数据线交替向第二行子像素写入数据信号，每行子像素对应的写入阶段均包括第一阶段t1、第二阶段t2、第三阶段t3和第四阶段t4，其中Gate1为高电位时的第一阶段t1、第二阶段t2和第三阶段t3分别为第一组数据线对应的第一驱动阶段、第二驱动阶段和第三驱动阶段，Gate1为高电位时的第三阶段t3、第四阶段t4为第二组数据线对应的第一驱动阶段和第二驱动阶段，Gate2为高电位时的第一阶段t1为第二组数据线对应的第三驱动阶段。
在第一阶段t1，第一分时复用信号MUX1为高电位，第二分时复用信号MUX2为低电位，T-mux1打开，T-mux1’关断，第一分时复用信号MUX1的高电位输入至晶体管T1和T3的栅极，将Q点的电位拉高至第一高电位。
在第二阶段t2，第一分时复用信号MUX1和第二分时复用信号MUX2均为低电位，由于分时复用控制模块300中T-mux1和T-mux1’的存在，这些晶体管与T1的栅极的正对电容较大，因此这个电容会保持T1和T3的栅极电位为第一高电位，即Q点保持第一高电位，同时，第一输入数据信号Data1为高电位，基于悬浮电容的自举效应，可以将T1和T3的栅极电位拉高至第二高电位，即Q点由第一高电位被拉高至第二高电位。此时，T1和T3充分打开，第一输入数据信号Data1数值为5V，第二输入数据信号Data2数值为-5V，第一输入数据信号Data1和第二输入数据信号Data2输入至T1和T3后，可以全摆幅输出对应的第一输出数据信号Data1’和第二输出数据信号Data2’，即第一输出数据信号Data1’数值也为5V，第二输出数据信号Data2’数值也为-5V，且二者的上升沿时间也较短，因此第一行子像素中第一组数据线对应的各子像素充电时间充足，充电率得到提升。
在第三阶段t3，第一分时复用信号MUX1为低电位，第二分时复用信号MUX2为高电位，T-mux2打开，T-mux2’关断，第二分时复用信号MUX2的高电位输入至晶体管T2和T4的栅极，将P点的电位拉高至第一高电位。
在第四阶段t4，第一分时复用信号MUX1和第二分时复用信号MUX2均为低电位，由于分时复用控制模块300中T-mux2和T-mux2’的存在，这些晶体管与T2的栅极的正对电容较大，因此这个电容会保持T2和T4的栅极电位为第一高电位，即P点保持第一高电位，同时，第二输入数据信号Data2为高电位，基于悬浮电容的自举效应，可以将T2和T4的栅极电位拉高至第二高电位，即P点由第一高电位被拉高至第二高电位。此时，T2和T4充分打开，第一输入数据信号Data1数值为-5V，第二输入数据信号Data2数值为5V，第一输入数据信号Data1和第二输入数据信号Data2输入至T2和T4后，可以全摆幅输出对应的第一输出数据信号Data1’和第二输出数据信号Data2’，即第一输出数据信号Data1’数值也为-5V，第二输出数据信号Data2’数值也为5V，且二者的上升沿时间也较短，因此第一行子像素中第二组数据线对应的各子像素充电时间充足，充电率得到提升。
如图3和图4所示，在现有技术中，Data1’的上升沿时间是1.3us，最高充电电压是4.9V，而Data1输入的初始电压是5V，即Data1输入至T1后，输出波形产生了延迟，会造成对应子像素的充电时间不足。如图7和图8所示，在本申请中，Q和P点在Data1和Data2输入时被拉高了很多，Data1’的输出波形上升沿由1.3us下降到0.9us，Data1’的最高电压也升高至5V，即本申请通过在分时复用信号输入模块100和开关模块200之间设置至少一个电位控制模块300，对控制点的电位进行两次拉高，使得开关模块200打开更加充分，从而增大了开关模块200的开态电流Ion，输入给数据线的第二数据信号上升沿时间缩短，数据线对应像素充电率得到提升，且此设计对显示面板的边框尺寸几乎没有影响，因此结构简单，提升充电率效果明显。
此外，需要说明的是，本申请实施例中以包括两个分时复用信号的数据驱动电路为例进行说明，但本申请不以此为限，在包括三个或更多分时复用信号的数据驱动电路中也可设置分时复用控制模块，其工作原理对任意一种包括分时复用信号的数据驱动电路均适用。
本申请还提供一种显示面板，包括多列数据线和数据驱动电路，所述数据驱动电路为上述任一项所述的数据驱动电路。本申请的显示面板可以是液晶显示面板或OLED显示面板，通过在数据驱动电路中分时复用信号输入模块和开关模块之间设置电位控制模块，对控制点的电位进行两次拉高，使得开关模块打开更加充分，输入给数据线的第二数据信号上升沿时间缩短，数据线对应像素充电率得到提升。
根据以上实施例可知：
本申请提供一种数据驱动电路和显示面板，数据驱动电路包括分时复用信号输入模块、多个开关模块和电位控制模块；分时复用信号输入模块包括至少两个分时复用信号输入端，用于交替向不同的控制点输入分时复用信号，每个控制点对应控制一组数据线，每组数据线包括多条数据线；每个开关模块的输出端接入一条数据线，同组数据线对应的开关模块的第一输入端均连接于同一控制点，所述开关模块用于在对应的控制点电位和第一数据信号的控制下，向连接的数据线输出第二数据信号；电位控制模块对应至少一组数据线设置，且所述电位控制模块的第一输入端与本组数据线对应的第一分时复用信号输入端连接，所述电位控制模块的输出端与本组数据线对应的控制点连接，所述电位控制模块用于在第一驱动阶段，在所述第一分时复用信号输入端输入的第一分时复用信号的控制下，将对应控制点的电位拉高至第一高电位，在第二驱动阶段，在所述第一分时复用信号和所述第一数据信号的控制下，将对应控制点的电位由所述第一高电位拉高至第二高电位。本申请通过在分时复用信号输入模块和开关模块之间设置电位控制模块，对控制点的电位进行两次拉高，使得开关模块打开更加充分，输入给数据线的第二数据信号上升沿时间缩短，数据线对应像素充电率得到提升。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种数据驱动电路和显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。
Claims (20)
- 一种数据驱动电路，其包括：分时复用信号输入模块，包括至少两个分时复用信号输入端，用于交替向不同的控制点输入分时复用信号，每个控制点对应控制一组数据线，每组数据线包括多条数据线；多个开关模块，每个开关模块的输出端接入一条数据线，同组数据线对应的开关模块的第一输入端均连接于同一控制点，所述开关模块用于在对应的控制点电位和第一数据信号的控制下，向连接的数据线输出第二数据信号；电位控制模块，对应至少一组数据线设置，且所述电位控制模块的第一输入端与本组数据线对应的第一分时复用信号输入端连接，所述电位控制模块的输出端与本组数据线对应的控制点连接，所述电位控制模块用于在第一驱动阶段，在所述第一分时复用信号输入端输入的第一分时复用信号的控制下，将对应控制点的电位拉高至第一高电位，在第二驱动阶段，在所述第一分时复用信号和所述第一数据信号的控制下，将对应控制点的电位由所述第一高电位拉高至第二高电位。
- 如权利要求1所述的数据驱动电路，其中，所述电位控制模块的第二输入端与下组数据线对应的第二分时复用信号输入端连接，所述电位控制模块还用于，在第三驱动阶段，在所述第一分时复用信号和所述第二分时复用信号输入端输入的第二分时复用信号的控制下，将所述控制点的电位拉低。
- 如权利要求2所述的数据驱动电路，其中，所述开关模块包括第一晶体管，所述第一晶体管的栅极与本组数据线对应的第一分时复用信号输入端连接于控制点，所述第一晶体管的第一电极接入第一数据信号，所述第一晶体管的第二电极与数据线连接。
- 如权利要求3所述的数据驱动电路，其中，所述电位控制模块包括第二晶体管和第三晶体管，所述第二晶体管的栅极和第一电极、以及第三晶体管的第一电极均接入所述第一分时复用信号，所述第二晶体管的第二电极和所述第三晶体管的第二电极均与所述第一晶体管的栅极连接于控制点，所述第三晶体管的栅极接入所述第二分时复用信号。
- 如权利要求3所述的数据驱动电路，其中，所述第一晶体管为NMOS晶体管。
- 如权利要求1所述的数据驱动电路，其中，各组数据线包括的数据线数量相等。
- 如权利要求6所述的数据驱动电路，其中，每组数据线包括多条间隔设置的数据线，且各数据线之间间隔的数据线数量相等。
- 如权利要求7所述的数据驱动电路，其中，各组数据线中第i条数据线对应的开关模块的第二输入端均接入相同的第一数据信号。
- 如权利要求1所述的数据驱动电路，其中，各组数据线的开关模块和分时复用信号输出端之间均设置有电位控制模块。
- 如权利要求1所述的数据驱动电路，其中，不同组数据线对应的电位控制模块，工作时间不重叠。
- 一种显示面板，其包括多列数据线和数据驱动电路，所述数据驱动电路包括：分时复用信号输入模块，包括至少两个分时复用信号输入端，用于交替向不同的控制点输入分时复用信号，每个控制点对应控制一组数据线，每组数据线包括多条数据线；多个开关模块，每个开关模块的输出端接入一条数据线，同组数据线对应的开关模块的第一输入端均连接于同一控制点，所述开关模块用于在对应的控制点电位和第一数据信号的控制下，向连接的数据线输出第二数据信号；电位控制模块，对应至少一组数据线设置，且所述电位控制模块的第一输入端与本组数据线对应的第一分时复用信号输入端连接，所述电位控制模块的输出端与本组数据线对应的控制点连接，所述电位控制模块用于在第一驱动阶段，在所述第一分时复用信号输入端输入的第一分时复用信号的控制下，将对应控制点的电位拉高至第一高电位，在第二驱动阶段，在所述第一分时复用信号和所述第一数据信号的控制下，将对应控制点的电位由所述第一高电位拉高至第二高电位。
- 如权利要求11所述的显示面板，其中，所述电位控制模块的第二输入端与下组数据线对应的第二分时复用信号输入端连接，所述电位控制模块还用于，在第三驱动阶段，在所述第一分时复用信号和所述第二分时复用信号输入端输入的第二分时复用信号的控制下，将所述控制点的电位拉低。
- 如权利要求12所述的显示面板，其中，所述开关模块包括第一晶体管，所述第一晶体管的栅极与本组数据线对应的第一分时复用信号输入端连接于控制点，所述第一晶体管的第一电极接入第一数据信号，所述第一晶体管的第二电极与数据线连接。
- 如权利要求13所述的显示面板，其中，所述电位控制模块包括第二晶体管和第三晶体管，所述第二晶体管的栅极和第一电极、以及第三晶体管的第一电极均接入所述第一分时复用信号，所述第二晶体管的第二电极和所述第三晶体管的第二电极均与所述第一晶体管的栅极连接于控制点，所述第三晶体管的栅极接入所述第二分时复用信号。
- 如权利要求13所述的显示面板，其中，所述第一晶体管为NMOS晶体管。
- 如权利要求11所述的显示面板，其中，各组数据线包括的数据线数量相等。
- 如权利要求16所述的显示面板，其中，每组数据线包括多条间隔设置的数据线，且各数据线之间间隔的数据线数量相等。
- 如权利要求17所述的显示面板，其中，各组数据线中第i条数据线对应的开关模块的第二输入端均接入相同的第一数据信号。
- 如权利要求11所述的显示面板，其中，各组数据线的开关模块和分时复用信号输出端之间均设置有电位控制模块。
- 如权利要求11所述的显示面板，其中，不同组数据线对应的电位控制模块，工作时间不重叠。
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| KR20180012900A (ko) * | 2016-07-27 | 2018-02-07 | 엘지디스플레이 주식회사 | 표시장치와 이의 구동방법 |
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| CN102495503A (zh) * | 2011-11-22 | 2012-06-13 | 深圳市华星光电技术有限公司 | 阵列基板及其驱动方法 |
| KR20140099025A (ko) * | 2013-02-01 | 2014-08-11 | 삼성디스플레이 주식회사 | 액정 표시 장치 및 액정 표시 장치의 구동 방법 |
| CN110111754B (zh) * | 2015-07-17 | 2021-08-10 | 群创光电股份有限公司 | 栅极驱动电路 |
| KR102407980B1 (ko) * | 2015-10-27 | 2022-06-14 | 엘지디스플레이 주식회사 | 쉬프트레지스터 및 이를 포함하는 표시장치 |
| CN106601173B (zh) * | 2017-01-03 | 2019-12-17 | 京东方科技集团股份有限公司 | 时序控制器、像素驱动方法及触控显示装置 |
| CN107240374A (zh) * | 2017-07-21 | 2017-10-10 | 京东方科技集团股份有限公司 | 一种源极驱动电路、显示装置及其驱动方法 |
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