WO2021258346A1 - 自旋轨道扭矩磁随机存储单元、存储阵列及存储器 - Google Patents

自旋轨道扭矩磁随机存储单元、存储阵列及存储器 Download PDF

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WO2021258346A1
WO2021258346A1 PCT/CN2020/098167 CN2020098167W WO2021258346A1 WO 2021258346 A1 WO2021258346 A1 WO 2021258346A1 CN 2020098167 W CN2020098167 W CN 2020098167W WO 2021258346 A1 WO2021258346 A1 WO 2021258346A1
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layer
spin
gate
orbit torque
magnetic random
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PCT/CN2020/098167
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French (fr)
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邢国忠
林淮
刘明
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中国科学院微电子研究所
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Priority to PCT/CN2020/098167 priority Critical patent/WO2021258346A1/zh
Priority to US18/003,038 priority patent/US20230276637A1/en
Publication of WO2021258346A1 publication Critical patent/WO2021258346A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/80—Constructional details
    • H10N52/85—Magnetic active materials

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  • the present disclosure belongs to the field of magnetic random access memory, and relates to a spin-orbit torque magnetic random access memory unit, storage array and memory, in particular to a three-dimensional integrated spin-orbit torque magnetic random access memory unit, storage array and memory without external field directional magnetization reversal .
  • MRAM Magnetic Random Access Memory
  • the first generation of MRAM used pulse current to generate Oersted field as a way to drive information writing in the ferromagnetic layer.
  • this method causes great power consumption and unavoidable interference to adjacent memory cells, which is not conducive to high-density integration of devices. Therefore, the first-generation MRAM technology has not been extensively expanded in practical applications.
  • Spin Transfer Torque MRAM Spin Transfer Torque MRAM, STT-MRAM
  • STT-MRAM Spin Transfer Torque MRAM
  • the core of STT-MRAM is a "sandwich" structure of magnetic tunnel junction (Magnetic Tunnel Junction, MTJ), and its basic structure consists of upper and lower electrodes, as well as a reference layer between the electrodes, a tunneling layer, and a free layer for storing information.
  • the ultra-thin MTJ realizes the storage of information through spin injection. It has the same read and write speed as the traditional static random access memory (SRAM), while greatly reducing the size of the device and reducing the power consumption, and it is necessary for future storage devices Non-volatile characteristics. Therefore, in its development process, researchers have also positioned STT-MRAM on high-speed storage devices similar to SRAM, and continue to carry out innovative research and development. However, the writing process of STT-MRAM information requires a relatively large current to directly pass through the tunnel junction, which is not conducive to device stability and is accompanied by relatively high power consumption.
  • STT-MRAM Spin-Orbit Torque Magnetic Random Access Memory
  • SOT-MRAM Spin-Orbit Torque Magnetic Random Access Memory
  • SOT spin-orbit moment
  • STT spin-transfer moment
  • the present disclosure provides a spin-orbit torque magnetic random access memory cell, a memory array and a memory.
  • a spin-orbit torque magnetic random access memory cell includes: a gate, which is a two-dimensional material-based gate; a magnetic tunnel junction, which is arranged above or below the gate; and the magnetic tunnel junction includes antiferromagnetic Layer and free layer, the free layer is adjacent to the antiferromagnetic layer; the gate is turned on, the memory cell is turned on, a current generates a spin current and is injected into the free layer, in the free layer and the Under the action of the exchange bias effect of the antiferromagnetic layer, the magnetization direction of the free layer is reversed.
  • the magnetic tunnel junction further includes: a tunneling layer and a reference layer, the reference layer, the tunneling layer, the free layer, and the antiferromagnetic layer are stacked in sequence;
  • the strobe is adjacent to the antiferromagnetic layer or adjacent to the reference layer; or,
  • the magnetic tunnel junction further includes: a ferromagnetic layer, a tunneling layer, and a reference layer, the reference layer, the tunneling layer, the free layer, the antiferromagnetic layer, and the ferromagnetic layer are sequentially stacked;
  • the gate is adjacent to the ferromagnetic layer or adjacent to the reference layer.
  • the spin-orbit torque magnetic random access memory cell further includes a word line and a bit line, and the gate and the magnetic tunnel junction are arranged on the word line and the bit line. between.
  • the gate includes: a stacked unit, the stacked unit is a metal-two-dimensional semiconductor-metal structure, and the metal-two-dimensional semiconductor-metal structure includes: a two-dimensional semiconductor Layer, and metal layers respectively disposed on the upper and lower surfaces of the two-dimensional semiconductor layer; wherein, when the two-dimensional material gate is energized, the laminated unit includes two Schott Base diode structure.
  • the gate includes: M stacked units, M ⁇ 2, each stacked unit is a metal-two-dimensional semiconductor-metal structure, and the metal-two-dimensional semiconductor-metal structure
  • the structure includes: a two-dimensional semiconductor layer, and a metal layer respectively disposed on the upper and lower surfaces of the two-dimensional semiconductor layer; wherein, in each laminated unit, one of the metal-two-dimensional semiconductor interfaces forms an ohmic contact, and the other metal -The two-dimensional semiconductor interface forms a Schottky contact;
  • the M stacked units are arranged along a first direction, the first direction is parallel to the plane where the two-dimensional semiconductor layer is located, and the M stacked units
  • An insulating layer is provided between the sidewalls of two adjacent stacked units in the, and when the two-dimensional material-based gate is energized, the M stacked units are M anti-parallel Schottky Diode structure.
  • the reference layer has a magnetic polarization in the film plane or not in the film plane; the free layer has a magnetic polarization parallel or anti-parallel to the reference layer.
  • the gate material is a two-dimensional van der Waals material, selected from WS2 or WSe2; the turn-on voltage of the gate is -1V or 1V; the turn-on current density of the gate It is 10MA/cm2; the thickness of the gate is in the range of 2nm-7nm.
  • the material of the tunnel layer is one or more of MgO, Al 2 O 3 , MaAl 2 O 4 and h-BN or one of the two-dimensional van der Waals material h-BN One or more;
  • the free layer material is a two-dimensional ferromagnetic material, selected from Fe 3 GeTe 2 , FeCo, CrCoPt, CoFeB, CoFe 2 Al, Mn 3 Ga or a two-dimensional ferromagnetic material Ni 3 GeTe 2 , VSe 2 One or more of CrI 3
  • the material of the antiferromagnetic layer is selected from Fe 3 GeTe 2 , IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO, MnO One or more;
  • the antiferromagnetic layer is at least one layer; the material of the ferromagnetic layer is selected from Fe 3 GeTe 2 , IrMn, FeMn, NiMn,
  • the word line material is selected from any one or more of Ta, Pt, and ⁇ -W.
  • a spin-orbit torque magnetic random memory array includes: at least one layer of interleaved storage arrays, and each layer of interleaved storage arrays includes: a bit line array including a plurality of bit lines arranged in parallel along a first direction; a word line array including a bit line array along a second direction A plurality of word lines arranged in parallel; wherein there is an angle between the first direction and the second direction; and a plurality of memory cells arranged at the intersection of the word line array and the bit line array, so Each storage unit in the plurality of storage units is the aforementioned storage unit.
  • the memory array further includes: a transistor connected in series to each of the multiple word lines of the interleaved memory array of each layer for controlling the on-off of the corresponding word line .
  • a spin-orbit torque magnetic random access memory including the spin-orbit torque magnetic random access memory array as described above.
  • the above-mentioned spin-orbit torque magnetic random access memory unit, storage array, and memory have at least one or part of the following beneficial effects:
  • the gate provided by the present disclosure can provide the drive current of the selected memory cell and ensure the extremely small leakage current of the unselected part.
  • the selected two-dimensional material-based gate has nano-scale scalability, is compatible with the CMOS process, and is bidirectional. Threshold conduction characteristics, low turn-on voltage, high turn-on current density, low turn-on resistance, high nonlinearity and excellent thermal stability.
  • a cross-stacked array is adopted to realize three-dimensional integration and mass production, which greatly improves the storage capacity compared with the traditional two-dimensional storage array.
  • FIG. 1 is a schematic diagram of a storage unit according to an embodiment of the disclosure.
  • Fig. 2a is a schematic diagram of the band energy structure of the gate in Fig. 1.
  • Fig. 2b is a schematic diagram of the simulated volt-ampere characteristic curve of the gate in Fig. 1.
  • FIG. 3 is a schematic diagram of the structure of the ferromagnetic material of the magnetic tunnel junction of the memory cell according to the embodiment of the disclosure.
  • 4a is a schematic diagram of the spin direction of the ferromagnetic material in the free layer of the memory cell of the embodiment of the disclosure being opposite to that of the reference layer.
  • 4b is a schematic diagram of the spin direction of the ferromagnetic material in the free layer of the memory cell of the embodiment of the disclosure being the same as that of the reference layer.
  • FIG. 5 is a schematic diagram of a three-dimensional structure of a spin-orbit torque magnetic random access memory according to an embodiment of the disclosure.
  • the present disclosure provides a spin-orbit torque magnetic random access memory unit, a storage array, and a memory.
  • the spin-orbit torque magnetic random access memory unit includes a magnetic tunnel junction and a gate; the gate is a two-dimensional material-based gate The magnetic tunnel junction is arranged above or below the gate; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer, and the free layer is adjacent to the antiferromagnetic layer; the gate is turned on, When the memory cell is turned on, a current generates a spin current and is injected into the free layer. Under the action of the exchange bias effect of the free layer and the antiferromagnetic layer, the magnetization direction of the free layer is reversed.
  • the present disclosure has no external field and utilizes the exchange bias effect.
  • the deterministic magnetization reversal of the SOT-MRAM memory cell at room temperature and zero magnetic field can be realized, achieving the purpose of data writing, and realizing the SOT-MRAM of the double-ended structure Storage unit.
  • the above-mentioned magnetic tunnel junction may be a tunnel junction including an antiferromagnetic layer.
  • a conventional magnetic tunnel junction including a free layer, a tunneling layer and a reference layer will be taken as a whole Description, the antiferromagnetic layer will be described separately.
  • FIG. 1 is a schematic diagram of a storage unit according to an embodiment of the disclosure.
  • the spin-orbit torque magnetic random storage unit of this embodiment includes: a word line 140, a bit line 110, a magnetic tunnel junction 130 and a gate 120.
  • the gate 120 and the magnetic tunnel junction 130 are arranged between the word line 140 and the bit line 110.
  • the gate 120 is a two-dimensional material-based gate.
  • the magnetic tunnel junction 130 is arranged above or below the gate 120.
  • the magnetic tunnel junction 130 includes an antiferromagnetic layer 134 and a free layer 133, and the free layer 133 is adjacent to the antiferromagnetic layer 134.
  • the gate 120 is turned on, the memory cell is turned on, and a current generates a spin current that is injected into the free layer 133.
  • a current generates a spin current that is injected into the free layer 133.
  • the magnetization direction of the free layer 133 is reversed.
  • the spin-orbit torque magnetic random storage unit provided in this embodiment has a two-terminal structure.
  • the bit line 110 is connected to the gate 120, the bit line 110 is made of metal, and the gate 120 is formed of a two-dimensional material and a metal heterojunction.
  • the antiferromagnetic magnetic tunnel junction 130 of this embodiment includes: a reference layer 131, a tunneling layer 132, a free layer 133, and an antiferromagnetic layer 134.
  • the reference layer 131, the tunneling layer 132, and the free layer 133 And the antiferromagnetic layer 134 are stacked in sequence; the gate 120 is adjacent to the antiferromagnetic layer 134.
  • each layer is stacked in sequence, and other layers can be arranged between each layer, and the stacking sequence can be from bottom to top or from top to bottom.
  • the bottom of the antiferromagnetic layer 134 is coupled with the word line 140.
  • the transistor 150 of the memory cell is a select/strobe transistor, and its other end is connected to a control terminal, which can complete the write control of the spin-orbit torque magnetic random memory cell.
  • the gate 120 is composed of a metal-semiconductor-metal (MSM) structure in parallel, when a bias voltage is applied to both ends, as shown in FIG. 2a.
  • MSM metal-semiconductor-metal
  • FIG. 2a When the applied bias voltage is small, one side of the Schottky barrier is forward conducting and the other side is reversely conducting. At this time, its volt-ampere characteristics are shown in Figure 2b, the voltage is less than 1/2Vo, and the current is very small at this time, which can be regarded as the off state; when the applied bias voltage increases, the hot carrier emission, FN tunneling and direct The tunneling current density increases, and when the threshold voltage Vo is reached, the gate is turned on, the spin-orbit torque magnetic random memory cell is turned on, and read and write operations can be performed.
  • MCM metal-semiconductor-metal
  • the gate includes: a stacked unit, the stacked unit is a metal-two-dimensional semiconductor-metal structure, the metal-two-dimensional semiconductor-metal structure includes: a two-dimensional semiconductor layer, and are respectively arranged at The metal layer on the upper and lower surfaces of the two-dimensional semiconductor layer; wherein, when the two-dimensional material gate is energized, the stacked unit includes two anti-parallel Schottky diode structures.
  • the gate includes: M stacked units, M ⁇ 2, each stacked unit is a metal-two-dimensional semiconductor-metal structure, and the metal-two-dimensional semiconductor-metal structure includes: A two-dimensional semiconductor layer and a metal layer respectively disposed on the upper and lower surfaces of the two-dimensional semiconductor layer; wherein, in each stacked unit, one of the metal-two-dimensional semiconductor interfaces forms an ohmic contact, and the other metal-two-dimensional semiconductor interface forms an ohmic contact.
  • the semiconductor interface forms a Schottky contact;
  • the M stacked units are arranged along a first direction (x direction), and the first direction is parallel to the plane where the two-dimensional semiconductor layer is located.
  • An insulating layer is provided between the sidewalls of two adjacent stacked units in the unit, and when the two-dimensional material-based gate is electrically conductive, the M stacked units are M anti-parallel Schott Base diode structure.
  • the above-mentioned strobe can provide the drive current of the selected memory cell and ensure the minimal leakage current of the unselected part.
  • the selected two-dimensional material-based gate has nano-scale scalability, is compatible with the CMOS process, and has two-way threshold conduction characteristics. Turn-on voltage, high turn-on current density, low turn-on resistance, high non-linearity and excellent thermal stability.
  • FIG. 3 is a schematic diagram of the structure of the ferromagnetic material of the magnetic tunnel junction of the memory cell according to the embodiment of the disclosure.
  • the reference layer 131 and the free layer 133 include a two-dimensional van der Waals ferromagnetic material Fe 3 GeTe 2 (FGT).
  • FGT van der Waals ferromagnetic material
  • the free layer 133 and the reference layer 131 are Through van der Waals force connection, the material itself is compatible with modern integrated circuit technology, and can be obtained by chemical vapor deposition (CVD), atomic layer deposition (ALD) and other technical methods to obtain a few layers or even a single layer of two-dimensional materials; its atomic layer surface is smooth , Without additional dangling bonds, it has more excellent interface characteristics and reduces the loss caused by scattering during data writing.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • Other optional materials include one or more of FeCo, CrCoPt, CoFeB, CoFe 2 Al, Mn 3 Ga or two-dimensional ferromagnetic materials Ni 3 GeTe 2 , VSe 2 , and CrI 3 ; the material used for the tunnel layer 132 is MgO, alternative materials include one of Al 2 O 3 , MaAl 2 O 4 or two-dimensional van der Waals material h-BN.
  • the antiferromagnetic layer 134 can also use other antiferromagnetic materials, including IrMn, FeMn, NiMn, CoMn, PtMn, one or more layers of Co/Pt, or metal oxide antiferromagnetic materials FeO, CoO , NiO, MnO one or more layers.
  • a constant 1V-2V bias voltage can be applied to one side of the Fe 3 GeTe 2 material.
  • This voltage can induce electrons to sequentially fill up d z 2 , d xz and d yz derived from Fe.
  • the subband of the orbit leads to an increase in the density of edge electronic states, which in turn leads to an increase in the environmental stability temperature of the long-range ordered magnetic moment structure, that is, a significant increase in the Curie temperature.
  • FIG. 4a is a schematic diagram of the spin direction of the ferromagnetic material in the free layer of the memory cell of the embodiment of the disclosure being opposite to that of the reference layer.
  • a bias voltage +V 1 greater than the gate opening voltage
  • the gate 120 Turn on, and current flows through the memory cell.
  • the writing principle of the double-ended memory cell is dominated by SOT.
  • the material of the antiferromagnetic layer 134 is selected from one or more of Fe 3 GeTe 2 , IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO, and MnO.
  • the antiferromagnetic layer 134 can be coupled with the adjacent free layer 133, thereby generating an exchange bias field along the plane direction, which can replace the external magnetic field required by the traditional SOT-MRAM, that is, provide an in-plane field, Furthermore, the symmetry is broken, and the deterministic magnetization reversal in the ferromagnetic material of the free layer is realized.
  • the spin direction of the ferromagnetic material in the free layer 133 is opposite to that of the reference layer 131, and the magnetic tunnel junction 130 presents a high resistance state, for example, represents data "1".
  • the writing principle of the double-ended memory cell is dominated by SOT.
  • the current flows through the heavy metal layer of the word line 140, the current generates a spin current, which is injected into the free layer 133, the antiferromagnetic layer 134 and the iron layer.
  • the combined structure of the magnetic layer (not shown).
  • the material of the ferromagnetic layer is selected from one or more of Fe 3 GeTe 2 , IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO, and MnO. It should be noted that the materials involved in the present disclosure also include corresponding material systems achieved through component, surface and interface modulation or element doping.
  • FIG. 5 is a schematic diagram of a spin-orbit torque magnetic random access memory according to an embodiment of the disclosure.
  • the spin-orbit torque magnetic random access memory of the present disclosure includes: at least one layer of interleaved memory array, and each layer of interleaved memory array includes: a bit line array 11, a word line array 14 and memory cells.
  • the bit line array 11 includes a plurality of bit lines 110 arranged in parallel along a first direction (x direction).
  • the word line array 14 includes a plurality of word lines 140 arranged in parallel along a second direction (y direction); wherein there is an angle between the first direction and the second direction.
  • the word line array 14 includes three word lines 140 and transistors 150 connected in series at the ends. The transistors are connected in series on each word line 140 of the multiple word lines of each layer of the interleaved memory array to control the on-off of the corresponding word line.
  • Each word line 140 is used as a common word line, and multiple sub word lines 141 are provided on the same side, which are used to connect to memory cells to avoid interleaving memory cells on other word lines in the same layer of the memory array when writing data. Produce interference.
  • the three bit lines 110 are arranged equidistantly in a parallel array. In actual use, the number is not limited to three.
  • the three word lines 140 are arranged equidistantly in a parallel array, and a transistor 150 is connected in series at the end of each word line 140.
  • a select/gate transistor is used.
  • the number of word lines 140 is not limited to three.
  • multiple storage arrays are stacked in the vertical direction.
  • the number of layers is not limited to 2, and multiple layers are superimposed until the electronic circuit resolution or process of the spin-orbit torque magnetic random access memory reaches the upper limit of the number of layers.
  • cross-stacked arrays can achieve three-dimensional integration and large-scale production. Compared with traditional two-dimensional storage arrays, the storage capacity is greatly improved.
  • the embodiments of the present disclosure also provide a spin-orbit torque magnetic random access memory, which includes the aforementioned storage unit and/or storage array.
  • the shapes of the gate, the magnetic tunnel junction and the antiferromagnetic layer can also be replaced with simple shapes such as rectangles and rings.
  • the two-dimensional gate can be located above or below the magnetic tunnel junction.
  • the present disclosure provides a three-dimensional integrated spin-orbit torque magnetic random access memory unit, memory array, and memory without external field directional magnetization flipping, which has the advantages of high speed, high reliability, small size and low power consumption.
  • the field has a wide range of application prospects.

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Abstract

一种自旋轨道扭矩磁随机存储单元、存储阵列及存储器，其中，自旋轨道扭矩磁随机存储单元包括：磁隧道结和选通器；选通器为二维材料基选通器；磁隧道结布置在所述选通器的上方或下方；所述磁隧道结包括反铁磁层和自由层，所述自由层与所述反铁磁层邻接；所述选通器开启，所述存储单元导通，电流产生自旋流注入所述自由层，在所述自由层和所述反铁磁层的交换偏置效应作用下，所述自由层磁化方向翻转。无需加载外场，利用交换偏置效应，通过施加磁隧道结优化偏置电压可实现室温零磁场下的SOT-MRAM存储单元的确定性磁化翻转，达到数据写入的目的，实现双端结构的SOT-MRAM存储单元。

Description

自旋轨道扭矩磁随机存储单元、存储阵列及存储器 技术领域
本公开属于磁随机存储器领域，涉及一种自旋轨道扭矩磁随机存储单元、存储阵列及存储器，尤其是一种无外场定向磁化翻转三维集成的自旋轨道扭矩磁随机存储单元、存储阵列及存储器。
背景技术
全球信息化高速发展对数据处理芯片计算能力的空前需求给现有存储器架构带来了巨大的挑战，也驱使着新型存储技术的不断革新。传统的硅基存储技术趋近极限，凸显能耗、读写速度、可靠性和存储容量等方面的壁垒，促使各类新型存储器近年来得到快速发展。作为新型存储器之一，磁随机存储器(Magnetic Random Access Memory，MRAM)，具有高读写速度、低功耗、非易失性、抗辐照等优点，使其在信息领域受到全世界的广泛关注和深入研究。
信息处理对存储器读写速度、存储容量、功耗和可靠性等日益增长的技术需求，促进了MRAM研究成果的迭代。第一代的MRAM采用脉冲电流产生奥斯特场，作为驱动铁磁层信息写入的方式。然而这种方法导致极大的功耗，并且对邻近存储单元存在不可避免的干扰，不利于器件的高密度集成。因此，第一代的MRAM技术在实际应用中未得到大规模拓展。作为第二代MRAM，自旋转移扭矩磁随机存储器(Spin Transfer Torque MRAM，STT-MRAM)具有更优异的器件性能。STT-MRAM的核心为“三明治”结构的磁隧道结(Magnetic Tunnel Junction，MTJ)，其基本结构由上下电极，以及电极之间的参考层、隧穿层和存储信息的自由层组成。极薄的MTJ通过自旋的注入实现信息的存储，在具有与传统静态随机存储器(SRAM)相当的读写速度的同时，大大缩小了器件的尺寸并降低功耗，且具有未来存储器件必备的非易失性特性。因此，在其发展过程中，研究者们也将STT-MRAM定位在与SRAM相似的高速存储器件上，不断进行着创新研发。然而，STT-MRAM信息的写入过程需较大电流直接通过隧道结，不利于器件稳定且伴随着相对的高功耗。
针对STT-MRAM存储技术存在的不足，新一代的MRAM应运而生。2012年，自旋轨道扭矩磁随机存储器(Spin-Orbit Torque MRAM，SOT-MRAM)技术被提出。虽然SOT-MRAM核心结构同样是MTJ，却有着完全不同的信息写入方式。利用自旋-轨道矩效应(SOT)来翻转磁自由层，写入信息时不需大电流通过隧道结，实现信息的读、写分离，这可以极大提高器件的稳定性，且实验验证拥有比STT更快的磁化翻转速度和更低的翻转临界电流密度，有助于大幅降低功耗。
虽然自旋-轨道矩SOT有望解决自旋-转移矩(STT)所面临的速度、能耗和势垒可靠性的瓶颈，但SOT仍旧有亟待解决的问题。首先，数据写入时，要求SOT-MRAM需要外加辅助面内静磁场，这不利于SOT-MRAM的制造与小型化；其次，传统三端SOT-MRAM占有比STT-MRAM这类双端器件更大的面积，不利于存储容量的进一步提升。因此，如何在不依赖外加磁场的全电学驱动的条件下，实现SOT-MRAM高速、高可靠、低功耗的信息存储和读取，以及如何提高SOT-MRAM的存储容量，成为了可集成SOT-MRAM发展道路上亟待解决的关键核心问题。
发明内容
有鉴于此，本公开提供了一种自旋轨道扭矩磁随机存储单元、存储阵列及存储器。
根据本公开的一个方面，提供了一种自旋轨道扭矩磁随机存储单元。该自旋轨道扭矩磁随机存储单元包括：选通器，为二维材料基选通器；磁隧道结，其布置在所述选通器的上方或下方；所述磁隧道结包括反铁磁层和自由层，所述自由层与所述反铁磁层邻接；所述选通器开启，所述存储单元导通，电流产生自旋流注入所述自由层，在所述自由层和所述反铁磁层的交换偏置效应作用下，所述自由层磁化方向翻转。
在本公开的一些实施例中，所述磁隧道结还包括：隧穿层和参考层，所述参考层、所述隧穿层、所述自由层和所述反铁磁层依次层叠；所述选通器与所述反铁磁层邻接或者与所述参考层邻接；或者，
所述磁隧道结还包括：铁磁层、隧穿层和参考层，所述参考层、所述 隧穿层、所述自由层、所述反铁磁层和所述铁磁层依次层叠；所述选通器与所述铁磁层邻接或者与所述参考层邻接。
在本公开的一些实施例中，所述自旋轨道扭矩磁随机存储单元还包括：字线和位线，所述选通器和所述磁隧道结设置在所述字线和所述位线间。
在本公开的一些实施例中，所述选通器包括：叠层单元，所述叠层单元为金属-二维半导体-金属结构，所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所述二维半导体层上、下表面的金属层；其中，在所述二维材料选通器通电导通时，所述叠层单元包括两个反向并联的肖特基二极管结构。
在本公开的一些实施例中，所述选通器包括：M个叠层单元，M≥2，每个叠层单元为金属-二维半导体-金属结构，所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所述二维半导体层上、下表面的金属层；其中，每个叠层单元中，其中一个金属-二维半导体界面形成欧姆接触，另一个金属-二维半导体界面形成肖特基接触；所述M个叠层单元沿着第一方向排布，所述第一方向平行于所述二维半导体层所在平面，在所述M个叠层单元中相邻的两个叠层单元的侧壁之间设置有绝缘层，在所述二维材料基选通器通电导通时所述M个叠层单元为M个反向并联的肖特基二极管结构。
在本公开的一些实施例中，所述参考层具有在膜平面中或不在膜平面中的磁极化；所述自由层具有与所述参考层相平行或反平行的磁极化。
在本公开的一些实施例中，所述选通器材料为二维范德华材料，选自WS2或WSe2；所述选通器的开启电压为-1V或1V；所述选通器的开启电流密度为10MA/cm2；所述选通器厚度的范围为2nm-7nm。
在本公开的一些实施例中，所述隧穿层的材料为MgO、Al 2O 3、MaAl 2O 4和h-BN中的一种或多种或二维范德华材料h-BN中的一种或多种；所述自由层材料为二维铁磁材料，选自Fe 3GeTe 2、FeCo、CrCoPt、CoFeB、CoFe 2Al、Mn 3Ga或者二维铁磁材料Ni 3GeTe 2、VSe 2、CrI 3中的一种或多种；所述反铁磁层的材料选自Fe 3GeTe 2、IrMn、FeMn、NiMn、CoMn、PtMn，、Co/Pt、FeO、CoO、NiO、MnO中的一种或多种；所述反铁磁层为至少一层；所述铁磁层的材料选自Fe 3GeTe 2、IrMn、FeMn、NiMn、CoMn、 PtMn，、Co/Pt、FeO、CoO、NiO、MnO中的一种或多种；所述铁磁层为至少一层。
在本公开的一些实施例中，所述字线材料选自Ta、Pt、β-W中任一种或多种。
根据本公开的另一个方面，提供了一种自旋轨道扭矩磁随机存储阵列。其中，所述存储阵列包括：至少一层交叉存储阵列，每层交叉存储阵列包括：位线阵列，包括沿着第一方向平行设置的多条位线；字线阵列，包括沿着第二方向平行设置的多条字线；其中所述第一方向与所述第二方向之间具有夹角；以及设置于所述字线阵列和所述位线阵列交叉点处的多个存储单元，所述多个存储单元中每个存储单元为如上所述的存储单元。
根据本公开的实施例，所述存储阵列还包括：晶体管，所述晶体管串联于所述每层交叉存储阵列的多条字线的每条字线上，用于控制所对应字线的通断。
根据本公开的再一个方面，提供了一种自旋轨道扭矩磁随机存储器，包括如上所述的自旋轨道扭矩磁随机存储阵列。
根据本公开的实施例，上述自旋轨道扭矩磁随机存储单元、存储阵列、存储器至少具有以下有益效果其中之一或其中一部分：
(1)本公开中磁隧道结的自由层与反铁磁层的交换偏置效应，结合施加磁隧道结优化偏压实现室温无外加磁场下SOT-MRAM的信息写入，增加电荷流向自旋流的转换效率以及自由层磁性材料对自旋流的吸收率；本公开提供的磁隧道结具有高速、高可靠、小尺寸和低功耗的优势。
(2)本公开提供的选通器能够提供选中存储单元的驱动电流并保证未选中部分极小的漏电流，选用二维材料基选通器具有纳米级可微缩性、与COMS工艺兼容、双向阈值导通特性、低开启电压、高开启电流密度、低开启电阻和高非线性度及优异的热稳定性。
(3)本公开中采用交叉堆叠阵列，实现三维集成和大规模生产，相比传统的二维存储阵列，极大提高了存储容量。
附图说明
图1为本公开实施例存储单元的示意图。
图2a为图1中选通器的带能结构示意图。
图2b为图1中选通器的模拟伏安特性曲线示意图。
图3为本公开实施例存储单元的磁隧道结的铁磁材料的结构示意图。
图4a为本公开实施例存储单元的自由层中铁磁材料自旋方向与参考层相反的示意图。
图4b为本公开实施例存储单元的自由层中铁磁材料自旋方向与参考层相同的示意图。
图5为本公开实施例自旋轨道扭矩磁随机存储器的三维结构示意图。
附图标记说明
11-位线阵列；
110-位线；
120-选通器；
130-磁隧道结；
131-参考层；
132-隧穿层；
133-自由层；
134-反铁磁层；
14-字线阵列；
140-字线；
141-子字线；
150-晶体管；
200-存储阵列。
具体实施方式
本公开提供了一种自旋轨道扭矩磁随机存储单元、存储阵列、存储器，其自旋轨道扭矩磁随机存储单元包括：磁隧道结和选通器；选通器为二维材料基选通器；磁隧道结布置在所述选通器的上方或下方；所述磁隧道结包括反铁磁层和自由层，所述自由层与所述反铁磁层邻接；所述选通器开启，所述存储单元导通，电流产生自旋流注入所述自由层，在所述自由层和所述反铁磁层的交换偏置效应作用下，所述自由层磁化方向翻转。本公 开无外场利用交换偏置效应，通过施加MTJ优化偏置电压可实现室温零磁场下的SOT-MRAM存储单元的确定性磁化翻转，达到数据写入的目的，实现双端结构的SOT-MRAM存储单元。
上述磁隧道结可以是包括反铁磁层的隧道结，在实施例的具体描述中，有时候也会将常规的包括自由层、隧穿层和参考层的磁隧道结(MTJ)作为一个整体描述，将反铁磁层单独描述。
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
本公开某些实施例于后方将参照所附附图做更全面性地描述，其中一些但并非全部的实施例将被示出。实际上，本公开的各种实施例可以许多不同形式实现，而不应被解释为限于此数所阐述的实施例；相对地，提供这些实施例使得本公开满足适用的法律要求。
在本公开的第一个示例性实施例中，提供了一种自旋轨道扭矩磁随机存储单元。图1为本公开实施例存储单元的示意图。如图1所示，本实施例自旋轨道扭矩磁随机存储单元包括：字线140、位线110、磁隧道结130和选通器120。选通器120和磁隧道结130布置在字线140和位线110间。选通器120为二维材料基选通器。磁隧道结130布置在所述选通器120的上方或下方。所述磁隧道结130包括反铁磁层134和自由层133，所述自由层133与所述反铁磁层134邻接。所述选通器120开启，所述存储单元导通，电流产生自旋流注入所述自由层133，在所述自由层133和所述反铁磁层134的交换偏置效应作用下，所述自由层133磁化方向翻转。
本实施例中提供的自旋轨道扭矩磁随机存储单元为两端结构。其中，位线110与选通器120连接，位线110由金属制成，而选通器120则由二维材料与金属异质结形成。本实施例的反铁磁磁隧道结130包括：参考层131、隧穿层132、自由层133和反铁磁层134，所述参考层131、所述隧穿层132、所述自由层133和所述反铁磁层134依次层叠；所述选通器120与所述反铁磁层134邻接。这里需要说明的是，依次层叠的含义为各层之间按照顺序依次层叠，各层之间可以设置有其他层，层叠的顺序可以是自下而上，也可以自上而下。反铁磁层134底部与字线140耦合，本实施例中存储单元的晶体管150选用选择/选通晶体管，其另一端连接控制端子， 可以完成自旋轨道扭矩磁随机存储单元的写入控制。
以下分别对本实施例自旋轨道扭矩磁随机存储单元的各个组成部分进行详细描述。
选通器120由金属-半导体-金属(MSM)结构并联组成，在两端外加偏压时，如图2a所示。在外加偏压较小时，肖特基势垒一侧正向导通，另一侧反向截止。此时其伏安特性如图2b所示，电压小于1/2Vo，此时电流极小，可以视为截止状态；当外加偏压增大，半导体中热载流子发射、FN隧穿以及直接隧穿电流密度增加，达到开启的阈值电压Vo时，选通器开启，自旋轨道扭矩磁随机存储单元导通，可进行读写操作。
关于选通器120以下对其组成部分进行详细描述。在一种实施方式中选通器包括：叠层单元，所述叠层单元为金属-二维半导体-金属结构，所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所述二维半导体层上、下表面的金属层；其中，在所述二维材料选通器通电导通时，所述叠层单元包括两个反向并联的肖特基二极管结构。
在另一种实施方式中，选通器包括：M个叠层单元，M≥2，每个叠层单元为金属-二维半导体-金属结构，所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所述二维半导体层上、下表面的金属层；其中，每个叠层单元中，其中一个金属-二维半导体界面形成欧姆接触，另一个金属-二维半导体界面形成肖特基接触；所述M个叠层单元沿着第一方向(x方向)排布，所述第一方向平行于所述二维半导体层所在平面，在所述M个叠层单元中相邻的两个叠层单元的侧壁之间设置有绝缘层，在所述二维材料基选通器通电导通时所述M个叠层单元为M个反向并联的肖特基二极管结构。
上述选通器能够提供选中存储单元的驱动电流并保证未选中部分极小的漏电流，选用二维材料基选通器具有纳米级可微缩性、与COMS工艺兼容、双向阈值导通特性、低开启电压、高开启电流密度、低开启电阻和高非线性度及优异的热稳定性。
图3为本公开实施例存储单元的磁隧道结的铁磁材料的结构示意图。在本实施例中，参考层131以及自由层133包括二维范德华铁磁材料Fe 3GeTe 2(FGT)，其晶格结构示意图如图3中130所示，自由层133以及 参考层131层中通过范德华力连接，材料本身与现代集成电路工艺兼容，可通过化学气相沉积(CVD)、原子层沉积(ALD)等技术方法得到少层，甚至是单层的二维材料；其原子层表面平滑，无额外的悬挂键，具有更加优异的界面特性，减少数据写入时因散射造成的损耗。其他可选用的材料包括FeCo、CrCoPt、CoFeB、CoFe 2Al、Mn 3Ga或者二维铁磁材料Ni 3GeTe 2、VSe 2、CrI 3其中的一种或多种；隧穿层132所用材料为MgO，可替代材料包括Al 2O 3、MaAl 2O 4或二维范德华材料h-BN其中的一种。本实施例中的反铁磁层134使用具有反铁磁性的Fe 3GeTe 2，Fe 3GeTe 2存在的铁磁/反铁磁相，具有有效交换偏置磁场H EB，通过施加磁隧道结130优化偏置电压可实现室温无外加磁场下的自旋轨道扭矩磁随机存储单元的确定性翻转。反铁磁层134还可以使用其他具有反铁磁性的材料，包括IrMn、FeMn、NiMn、CoMn、PtMn，、Co/Pt的一层或者多层，或是金属氧化物反铁磁性材料FeO、CoO、NiO、MnO的一层或者多层构成。在材料Fe 3GeTe 2中，可在材料Fe 3GeTe 2的一侧施加恒定为1V-2V的偏置电压，该电压可诱导电子依次填满源自Fe的d z 2、d xz和d yz轨道的子带，导致边缘电子态密度的增加，进而致使长程有序态磁矩结构环境稳定温度的提高，即居里温度的显著增加。对于居里温度低于室温的铁磁性材料，或是尼尔温度低于室温的反铁磁性材料，也适用于同样外加偏压的方式对其进行调制，保证室温下通过偏置电压的优化进行二维材料铁磁和反铁磁性的可控调制。
图4a为本公开实施例存储单元的自由层中铁磁材料自旋方向与参考层相反的示意图。如图4a所示，自旋轨道扭矩磁随机存储单元进行写操作时，位线110与字线140之间加上偏压+V 1(大于选通器开启电压)，此时选通器120导通，电流流过存储单元。该双端存储单元的写入原理以SOT为主导，电流流过字线140的重金属层时，电流产生自旋流，注入自由层133与反铁磁层134的组合结构。反铁磁层134的材料选自Fe 3GeTe 2、IrMn、FeMn、NiMn、CoMn、PtMn，、Co/Pt、FeO、CoO、NiO、MnO中的一种或多种。此时，反铁磁层134可以与相邻的自由层133耦合，由此产生沿平面方向的交换偏置场，该场可以代替传统SOT-MRAM所需的外加磁场，即提供面内场，进而打破对称性破缺，实现自由层铁磁材料中确定性的磁化翻转。此时，自由层133中的铁磁材料自旋方向与参考层131相反，磁 隧道结130呈现高阻态，例如代表数据“1”。在另一实施例中，该双端存储单元的写入原理以SOT为主导，电流流过字线140的重金属层时，电流产生自旋流，注入自由层133、反铁磁层134和铁磁层(未示意)的组合结构。铁磁层的材料选自Fe 3GeTe 2、IrMn、FeMn、NiMn、CoMn、PtMn，、Co/Pt、FeO、CoO、NiO、MnO中的一种或多种。需要说明的是，本公开中所涉及材料同时包括通过组分、表面及界面调制或元素掺杂所实现得对应材料体系。
在写“0”时，如图4b所示，位线110与字线140之间加上外加电压-V 1，电流反向，同上所述，此时器件通过SOT效应以及交换偏置效应，将自由层133中自旋方向设置为与参考层131方向相同，磁隧道结130呈现低阻态，例如代表数据“0”。由此实现二进制数的编程存储。
由于磁隧道结的自由层与反铁磁层的交换偏置效应，结合施加磁隧道结优化偏压可以实现室温无外加磁场下SOT-MRAM的信息写入，增加电荷流向自旋流的转换效率以及自由层磁性材料对自旋流的吸收率。
本公开实施例还提供一种自旋轨道扭矩磁随机存储阵列。图5为本公开实施例自旋轨道扭矩磁随机存储器的示意图。如图5所示，本公开自旋轨道扭矩磁随机存储器包括：至少一层交叉存储阵列，每层交叉存储阵列包括：位线阵列11、字线阵列14和存储单元。位线阵列11包括沿着第一方向(x方向)平行设置的多条位线110。字线阵列14包括沿着第二方向(y方向)平行设置的多条字线140；其中所述第一方向与所述第二方向之间具有夹角。字线阵列14包括三条字线140及末端串联的晶体管150，晶体管串联于所述每层交叉存储阵列的多条字线的每条字线140上，用于控制所对应字线的通断。每条字线140作为公共字线，其同侧均设置有多个子字线141，用于与存储单元相连，避免写入数据时，对同一层交叉存储阵列中的其他字线上的存储单元产生干扰。如图5所示，三条位线110呈平行阵列等距排列。在实际运用中，其数量不仅限于三条。三条字线140呈平行阵列等距排列，每条字线140末端串联晶体管150，在本实施例中选择/选通晶体管。在实际运用中，字线140的数量不仅限于三条。存储阵列大于一个时，多个存储阵列沿垂直方向堆叠。其层数不限于2，多层叠加直至自旋轨道扭矩磁随机存储器的电子电路分辨率或者工艺达到层数 上限为止。
采用交叉堆叠阵列，可以实现三维集成和大规模生产，相比传统的二维存储阵列，极大提高了存储容量。
本公开实施例还提供一种自旋轨道扭矩磁随机存储器，其包括如前所述的存储单元和/或存储阵列。
至此，已经结合附图对本公开实施例进行了详细描述。需要说明的是，在附图或说明书正文中，未绘示或描述的实现方式，均为所属技术领域中普通技术人员所知的形式，并未进行详细说明。此外，上述对各元件和方法的定义并不仅限于实施例中提到的各种具体结构、形状或方式，本领域普通技术人员可对其进行简单地更改或替换，例如：
(1)选通器、磁隧道结和反铁磁层的形状还可以以长方形，环形等简单形状进行替换。
(2)选通器在阵列中存储单元位置的简单移动，二维选通器可以位于磁隧道结的上方或下方。
依据以上描述，本领域技术人员应当对本公开自旋轨道扭矩磁随机存储单元、存储阵列、存储器有了清楚的认识。
综上所述，本公开提供一种无外场定向磁化翻转三维集成的自旋轨道扭矩磁随机存储单元、存储阵列、存储器，具高速、高可靠、小尺寸和低功耗的优势，在随机存储器领域具有广泛的应用前景。
还需要说明的是，实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向，并非用来限制本公开的保护范围。贯穿附图，相同的元素由相同或相近的附图标记来表示。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。
并且图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。另外，在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。
除非有所知名为相反之意，本说明书及所附权利要求中的数值参数是近似值，能够根据通过本公开的内容所得的所需特性改变。具体而言，所有使用于说明书及权利要求中表示组成的含量、反应条件等等的数字，应理解为在所有情况中是受到「约」的用语所修饰。一般情况下，其表达的 含义是指包含由特定数量在一些实施例中±10％的变化、在一些实施例中±5％的变化、在一些实施例中±1％的变化、在一些实施例中±0.5％的变化。
再者，单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。
类似地，应当理解，为了精简本公开并帮助理解各个公开方面中的一个或多个，在上面对本公开的示例性实施例的描述中，本公开的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该公开的方法解释成反映如下意图：即所要求保护的本公开要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如下面的权利要求书所反映的那样，公开方面在于少于前面公开的单个实施例的所有特征。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本公开的单独实施例。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (11)

  1. 一种自旋轨道扭矩磁随机存储单元，包括：
    选通器，为二维材料基选通器；
    磁隧道结，其布置在所述选通器的上方或下方；所述磁隧道结包括反铁磁层和自由层，所述自由层与所述反铁磁层邻接；
    其中，所述选通器开启，所述存储单元导通，电流产生自旋流注入所述自由层，在所述自由层和所述反铁磁层的交换偏置效应作用下，所述自由层磁化方向翻转。
  2. 根据权利要求1所述的自旋轨道扭矩磁随机存储单元，其中，
    所述磁隧道结还包括：隧穿层和参考层，所述参考层、所述隧穿层、所述自由层和所述反铁磁层依次层叠；所述选通器与所述反铁磁层邻接或者与所述参考层邻接；或者，
    所述磁隧道结还包括：铁磁层、隧穿层和参考层，所述参考层、所述隧穿层、所述自由层、所述反铁磁层和所述铁磁层依次层叠；所述选通器与所述铁磁层邻接或者与所述参考层邻接。
  3. 根据权利要求1所述的自旋轨道扭矩磁随机存储单元，其中，所述自旋轨道扭矩磁随机存储单元还包括：
    字线和位线，所述选通器和所述磁隧道结设置在所述字线和所述位线间。
  4. 根据权利要求1所述的自旋轨道扭矩磁随机存储单元，其中，
    所述选通器包括：
    叠层单元，所述叠层单元为金属-二维半导体-金属结构，所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所述二维半导体层上、下表面的金属层；
    其中，在所述二维材料选通器通电导通时，所述叠层单元包括两个反向并联的肖特基二极管结构；或者，
    所述选通器包括：
    M个叠层单元，M≥2，每个叠层单元为金属-二维半导体-金属结构，所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所 述二维半导体层上、下表面的金属层；
    其中，在每个叠层单元中，其中一个金属-二维半导体界面形成欧姆接触，另一个金属-二维半导体界面形成肖特基接触；
    其中，所述M个叠层单元沿着第一方向排布，所述第一方向平行于所述二维半导体层所在平面，在所述M个叠层单元中相邻的两个叠层单元的侧壁之间设置有绝缘层，在所述二维材料基选通器通电导通时所述M个叠层单元为M个反向并联的肖特基二极管结构。
  5. 根据权利要求2所述的自旋轨道扭矩磁随机存储单元，其中，所述参考层具有在面内或面外的磁化方向；所述自由层具有与所述参考层相平行或反平行的磁化方向。
  6. 根据权利要求1所述的自旋轨道扭矩磁随机存储单元，其中，所述选通器材料为二维范德华材料，选自WS 2或WSe 2；所述选通器的开启电压为-1V或1V；所述选通器的开启电流密度为10MA/cm 2；所述选通器厚度的范围为2nm-7nm。
  7. 根据权利要求2所述的自旋轨道扭矩磁随机存储单元，其中，
    所述隧穿层的材料为MgO、Al 2O 3、MaAl 2O 4和h-BN中的一种或多种或二维范德华材料h-BN中的一种或多种；和/或，
    所述自由层材料为二维铁磁材料，选自Fe 3GeTe 2、FeCo、CrCoPt、CoFeB、CoFe 2Al、Mn 3Ga或者二维铁磁材料Ni 3GeTe 2、VSe 2、CrI 3中的一种或多种；和/或，
    所述反铁磁层的材料选自Fe 3GeTe 2、IrMn、FeMn、NiMn、CoMn、PtMn，、Co/Pt、FeO、CoO、NiO、MnO中的一种或多种；所述反铁磁层为至少一层；和/或，
    所述铁磁层的材料选自Fe 3GeTe 2、IrMn、FeMn、NiMn、CoMn、PtMn，、Co/Pt、FeO、CoO、NiO、MnO中的一种或多种；所述铁磁层为至少一层。
  8. 根据权利要求3所述的自旋轨道扭矩磁随机存储单元，其中，所述字线材料选自Ta、Pt、β-W中任一种或多种。
  9. 一种自旋轨道扭矩磁随机存储阵列，其中，所述存储阵列包括：
    至少一层交叉存储阵列，每层交叉存储阵列包括：
    位线阵列，包括沿着第一方向平行设置的多条位线；
    字线阵列，包括沿着第二方向平行设置的多条字线；其中所述第一方向与所述第二方向之间具有夹角；以及
    设置于所述字线阵列和所述位线阵列交叉点处的多个存储单元，所述多个存储单元中每个存储单元为权利要求1至8中任一项所述的自旋轨道扭矩磁随机存储单元。
  10. 根据权利要求9所述的自旋轨道扭矩磁随机存储阵列，还包括：晶体管，所述晶体管串联于所述每层交叉存储阵列的多条字线的每条字线上，用于控制所对应字线的通断。
  11. 一种自旋轨道扭矩磁随机存储器，包括权利要求9或10所述的自旋轨道扭矩磁随机存储阵列。
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