WO2021114571A1 - 二维材料基选通器、存储器单元、阵列及其操作方法 - Google Patents

二维材料基选通器、存储器单元、阵列及其操作方法 Download PDF

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WO2021114571A1
WO2021114571A1 PCT/CN2020/090618 CN2020090618W WO2021114571A1 WO 2021114571 A1 WO2021114571 A1 WO 2021114571A1 CN 2020090618 W CN2020090618 W CN 2020090618W WO 2021114571 A1 WO2021114571 A1 WO 2021114571A1
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voltage
dimensional
memory cell
dimensional material
based gate
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PCT/CN2020/090618
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English (en)
French (fr)
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林淮
邢国忠
刘明
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中国科学院微电子研究所
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Priority to PCT/CN2020/090618 priority Critical patent/WO2021114571A1/zh
Priority to US17/998,782 priority patent/US20230165014A1/en
Publication of WO2021114571A1 publication Critical patent/WO2021114571A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/10—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having two electrodes, e.g. diodes or MIM elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors

Definitions

  • the present disclosure belongs to the field of storage technology, and relates to a two-dimensional material-based gate, a memory cell, an array, and an operation method thereof.
  • Magnetic Random Access Memory is a new type of non-volatile memory.
  • the core part of MRAM is the Magnetic Tunnel Junction (MTJ).
  • the MTJ is composed of a reference layer (Reference Layer) based on ferromagnetic materials, a free layer (Free Layer), and a high-quality oxide tunnel barrier layer (Tunneling Barrier Layer) between the two.
  • Reference Layer Reference Layer
  • Free Layer free layer
  • Tuneling Barrier Layer high-quality oxide tunnel barrier layer
  • MRAM Compared with traditional static random access memory (SRAM), MRAM has a smaller volume and lower leakage, which can reduce static power consumption; compared to dynamic memory (DRAM), MRAM has faster reading Write operation speed and non-volatility. At the same time, MRAM also has the advantages of higher read and write times, compatibility with existing integrated circuit technology, and resistance to radiation.
  • SRAM static random access memory
  • DRAM dynamic memory
  • MRAM has faster reading Write operation speed and non-volatility.
  • MRAM also has the advantages of higher read and write times, compatibility with existing integrated circuit technology, and resistance to radiation.
  • SOT-MRAM Spin-Orbit Torque MRAM
  • This method separates the data writing and reading paths.
  • the power consumption can be further reduced, and the data writing speed and the number of reads and writes can be improved.
  • the SOT-MRAM memory cell of the three-terminal structure requires a larger cell area, which is not conducive to the high-density integration of the memory, and therefore cannot achieve large-capacity storage temporarily, which has become one of the main obstacles restricting the development of SOT-MRAM.
  • the use of the spin transfer torque magnetic memory STT-MRAM method for information writing is still a widely used method in the preparation of MRAM devices.
  • STT-MRAM is also recognized in the industry as the closest memory solution to replace Flash.
  • STT-MRAM also has the problems of low integration density and need to optimize energy consumption.
  • the existing memory array has a leakage current problem. When a certain memory cell in the array is selected, unselected memory cells located on the same bit line and word line as the selected memory cell are in a half-biased state, and there is a relatively large leakage current.
  • a gate in series with the memory cell usually using conventional transistors, conventional diodes, or conventional bidirectional threshold switches.
  • traditional silicon-based transistors and diodes have disadvantages such as large size, complex process, and high temperature limitation of threshold modulation, which are not conducive to high-density integration; in addition to the same high-temperature reliability as traditional Ovonic threshold switching (OTS) gates
  • Ovonic threshold switching (OTS) gates In addition to the problem, the thickness of the chalcogenide bidirectional threshold switch is thick, and the mobility is low, which affects the storage speed; varistor type gates, such as mixed ion-electron conductors (MIEC) gates and electric field-assisted super linear
  • MIEC mixed ion-electron conductors
  • FAST field-assisted superlinear threshold
  • the present disclosure provides a two-dimensional material-based gate, a memory cell, an array and an operation method thereof, so as to at least partially solve the above-mentioned technical problems.
  • a two-dimensional material-based gate includes a stacked unit, and the stacked unit is a metal-two-dimensional semiconductor-metal structure.
  • the metal-two-dimensional semiconductor-metal structure includes: a two-dimensional semiconductor layer and metal layers respectively disposed on the upper and lower surfaces of the two-dimensional semiconductor layer.
  • the two-dimensional material-based gate includes N stacked units, where N ⁇ 1.
  • N ⁇ 2 at least two stacked units are stacked along a first direction, and the first The direction is perpendicular to the plane where the two-dimensional semiconductor material layer is located.
  • a two-dimensional material-based gate includes M stacked units, M ⁇ 2.
  • Each stacked unit is a metal-two-dimensional semiconductor-metal structure.
  • the metal-two-dimensional semiconductor-metal structure includes: a two-dimensional semiconductor layer, and metal layers respectively disposed on the upper and lower surfaces of the two-dimensional semiconductor layer. Among them, in each stacked unit, one metal-two-dimensional semiconductor interface forms an ohmic contact, and the other metal-two-dimensional semiconductor interface forms a Schottky contact.
  • the M stacked units are arranged along the second direction, the second direction is parallel to the plane where the two-dimensional semiconductor layer is located, and is arranged between the sidewalls of two adjacent stacked units among the M stacked units There is an insulating layer, and when the two-dimensional material-based gate is energized, the M stacked units are M anti-parallel Schottky diode structures.
  • the material of the two-dimensional semiconductor layer includes one or a combination of the following materials: WS 2 , WSe 2 , and MoS 2 .
  • the thickness of the two-dimensional semiconductor layer is 2nm-10nm, including endpoint values, for example, it can be 2nm, 3nm, 4nm, 5nm, 6nm, 8nm, 10nm, etc.
  • the material of the metal layer is the following materials: Pt, Ta, W, Ir, Os, Re, Hf, Pd, Rh, Mo, Nb, Zr, Au, Tc, Cd, Pb, and Sn One kind of simple substance or several kinds of alloys.
  • the volt-ampere characteristic curve of the two-dimensional material-based gate is symmetrical and has a bidirectional switching characteristic.
  • the turn-on voltage of the two-dimensional material-based gate is 0.8V ⁇ 1.2V.
  • the on-off ratio of the two-dimensional material-based gate is not less than 10 3 .
  • the on-current density of the two-dimensional material-based gate is not less than 10 6 A/cm 2 .
  • a memory cell includes: any of the two-dimensional material-based gates mentioned above; and a magnetic tunnel junction; wherein the two-dimensional material-based gate and the magnetic tunnel junction are stacked along a first direction to form a selective memory cell,
  • the selected memory cell includes a first surface and a second surface oppositely arranged along a first direction. The first surface is used for connection with a word line, and the second surface is used for connection with a bit line.
  • the two-dimensional material-based gate is located above or below the magnetic tunnel junction.
  • a memory array includes: at least one layer of interleaved memory array.
  • Each layer of interleaved memory array includes: a bit line array, including a plurality of bit lines arranged in parallel along the second direction; a word line array, including a plurality of word lines arranged in parallel along a third direction; wherein the third direction is the same as the first The direction is vertical, and there is an angle between the third direction and the second direction; a plurality of memory cells arranged at the intersection of the word line array and the bit line array, each memory cell of the plurality of memory cells is any one of the above-mentioned Kind of memory unit.
  • the memory array further includes: a selection transistor.
  • the selection transistor is connected in series on each word line of the multiple word lines of each layer of the cross memory array, and is used to control the on-off of the corresponding word line.
  • an insulating layer is provided between two adjacent layers of the interleaved memory array in the multi-layer interleaved memory array.
  • an operation method related to the above-mentioned memory cell includes: applying a first voltage on the first surface of the selected memory cell, and applying a second voltage on the second surface of the selected memory cell.
  • the voltage drop caused by the first voltage and the second voltage on the selected memory cell The value of is greater than the voltage value of the turn-on voltage of the two-dimensional material-based gate to operate the magnetic tunnel junction, and the above-mentioned operation includes at least one of a read operation and a write operation.
  • the value of the voltage drop corresponding to the writing operation is greater than the value of the voltage drop corresponding to the reading operation.
  • an operating method related to the above-mentioned memory array includes: locating to the selected memory cell that needs to be operated; applying a first voltage V 1 on the word line where the selected memory cell that needs to be operated is located, and applies the first voltage V 1 to the location where the selected memory cell that needs to be operated is located.
  • a second voltage V 2 is applied to the line; a zero voltage is applied to the remaining word lines and the remaining bit lines; wherein the first voltage V 1 and the second voltage V 2 produce a voltage drop greater than the value of the selected memory cell that needs to be operated
  • the voltage values of the second voltage and the second voltage are both less than or equal to V on /2, so that the voltage drop of other selected memory cells that are on the same word line or the same bit line as the selected memory cell to be operated meets: make two of the other selected memory cells
  • the dimensional material-based gate is in the off state.
  • the value of the voltage drop corresponding to the writing operation is greater than the value of the voltage drop corresponding to the reading operation.
  • Two-dimensional material-based gates are connected in series with each magnetic tunnel junction to form a selective memory cell of one gate-to-magnetic tunnel junction (1S-1M). Due to the off state of the two-dimensional material-based gate The leakage current is small ( ⁇ 1pA), so that when a memory cell is read or written, the other memory cells are almost in the off state, which reduces the size of the leakage current and greatly reduces the power consumption of the three-dimensional STT-MRAM array .
  • the ultra-thin two-dimensional material has a low turn-on voltage of 1V, exhibits high nonlinearity and high turn-on current (over 10 6 A/cm 2 ) when the gate is turned on, and can quickly drive the free layer of the memory cell Magnetization reversal improves the switching speed of the three-dimensional memory array ( ⁇ 10ns).
  • the two-dimensional van der Waals material can be made into a few-layer or even a single-layer structure, its thickness is about 1nm, which is smaller than the gate made of transistors, series diodes, ordinary bidirectional switches, etc.
  • the thickness dimension provides favorable conditions for high-density integration.
  • Fig. 1 is a schematic structural diagram of a two-dimensional material-based gate according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of the energy band of a metal-two-dimensional semiconductor-metal structure according to an embodiment of the present disclosure, where (a) is a schematic diagram of the energy band without applying a bias voltage; (b) is a schematic diagram of the energy band when a voltage is applied Schematic diagram of the energy band in the case.
  • Fig. 3 is a volt-ampere characteristic curve of a two-dimensional material-based gate according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of the structure of a memory cell according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a magnetic tunnel junction according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of operating a memory unit according to an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of writing a "0" operation to the memory cell shown in FIG. 6 according to an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of writing a "1" operation to the memory cell shown in FIG. 6 according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of performing a read operation on the memory cell described in FIG. 6 according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of an equivalent circuit after a two-dimensional material-based gate is turned on according to an embodiment of the present disclosure.
  • Fig. 11 is a schematic structural diagram of a two-dimensional material-based gate according to another embodiment of the present disclosure.
  • Fig. 12 is a volt-ampere characteristic curve of a two-dimensional material-based gate according to another embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram of the structure of a memory cell and operations on the memory cell according to another embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram of writing a "0" operation to the memory cell shown in FIG. 12 according to another embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of writing a "1" operation to the memory cell shown in FIG. 12 according to another embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of performing a read operation on the memory cell shown in FIG. 12 according to another embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of an equivalent circuit after a two-dimensional material-based gate is turned on according to another embodiment of the present disclosure.
  • FIG. 18 is a schematic structural diagram of a two-dimensional memory array according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of a three-dimensional memory array according to an embodiment of the present disclosure.
  • the two-dimensional material-based gate provided by the embodiment of the present disclosure includes: a stacked unit, the stacked unit is a metal-two-dimensional semiconductor-metal structure, the metal-two-dimensional semiconductor-metal structure includes: a two-dimensional semiconductor layer, and The metal layers are respectively arranged on the upper and lower surfaces of the two-dimensional semiconductor layer.
  • the number of the above-mentioned laminated units is N, N ⁇ 1, and in each laminated unit, the two metal-two-dimensional semiconductor interfaces form Schottky contacts, and the two-dimensional material-based gate is electrically conductive.
  • the stacked unit includes two Schottky diode structures connected in reverse series.
  • the number of the above-mentioned laminated units is M, M ⁇ 2, and in each laminated unit, one of the two metal-two-dimensional semiconductor interfaces forms a Schottky contact, and the other interface forms an ohmic contact, And when the two-dimensional material-based gate is turned on, the M stacked units include M anti-parallel Schottky diode structures.
  • the memory cell provided by the embodiment of the present disclosure includes: the above-mentioned two-dimensional material-based gate; and a magnetic tunnel junction; wherein the two-dimensional material-based gate and the magnetic tunnel junction are stacked along a first direction to form a selective memory cell,
  • the selected memory cell includes a first surface and a second surface oppositely arranged along a first direction. The first surface is used for connection with a word line, and the second surface is used for connection with a bit line.
  • the first exemplary embodiment of the present disclosure provides a two-dimensional material-based gate.
  • Fig. 1 is a schematic structural diagram of a two-dimensional material-based gate according to an embodiment of the present disclosure.
  • the two-dimensional material-based gate in this embodiment is called the first gate, and the gate in another embodiment to be described later is called the second gate.
  • the first gate 100 of this embodiment includes: a stacked unit.
  • one stacked unit is used as an example, and the other stacked units can be arranged in the same manner.
  • the corresponding circuit can be equivalent to a series circuit of multiple stacked units.
  • the stacked unit is a metal-two-dimensional semiconductor-metal (M-S-M) structure.
  • the M-S-M structure includes a two-dimensional semiconductor layer and a metal layer respectively disposed on the upper and lower surfaces of the two-dimensional semiconductor layer.
  • the stacked unit includes: a two-dimensional semiconductor layer 102, a first metal layer 101 disposed above the two-dimensional semiconductor layer 102, and a second metal layer 103 disposed below the two-dimensional semiconductor layer 102.
  • FIG. 2 is a schematic diagram of the energy band of a metal-two-dimensional semiconductor-metal structure according to an embodiment of the present disclosure, where (a) is a schematic diagram of the energy band without applying a bias voltage; (b) is a schematic diagram of the energy band when a voltage is applied Schematic diagram of the energy band in the case.
  • Figure 2 In (a) the two-dimensional material layer is disassembled into two parts. When the applied voltage is 0 or the voltage is low, the MSM structure can be regarded as being in an off state with no current flowing.
  • One current generation mode is: under the action of the voltage V 0 , the hot carrier emission effect generated by the carrier crossing the Schottky barrier layer.
  • the other two current generation modes are: under the action of the voltage V 0 , the energy band in the semiconductor layer is bent, resulting in FN Tunneling and direct tunneling-based tunneling effects. (Tunneling Effect).
  • the two-dimensional material-based gate may include N stacked units, N ⁇ 1.
  • N the number of stacked units included in the two-dimensional material-based gate N ⁇ 2
  • at least two stacked units are stacked along a first direction, which is perpendicular to the plane where the two-dimensional semiconductor material layer is located. That is, when N stacked units are stacked along a plane perpendicular to the two-dimensional semiconductor layer, after the two-dimensional material-based gate is turned on, the N stacked units are equivalent to being connected in series.
  • each stacked unit When the two-dimensional material-based gate is turned on, each stacked unit includes two Schottky diode structures connected in reverse series.
  • Figure 10 illustrates the equivalent circuit after the two-dimensional material-based gate is turned on.
  • the metal-two-dimensional semiconductor-metal structure in each laminated unit has two metal-two
  • the two-dimensional semiconductor interface is the interface formed by the first metal layer 101 and the two-dimensional semiconductor layer 102, and the interface formed by the second metal layer 103 and the two-dimensional semiconductor layer 102.
  • these two interfaces are respectively described as the first The metal-two-dimensional semiconductor interface 100a and the second metal-two-dimensional semiconductor interface 100b. As shown in FIG.
  • each stacked unit includes two Schottky diode structures connected in reverse series.
  • the number of stacked units can be optimally set according to actual conditions, and too many stacked units may result in reduced switch performance.
  • the respective metal layers between two adjacent laminated units may also be served by the same metal layer.
  • the two stacked units can be a structure of a metal layer-a two-dimensional semiconductor layer-a metal layer-a metal layer-a two-dimensional semiconductor layer-a metal layer, or a metal layer-a two-dimensional semiconductor layer-a metal layer-a two-dimensional semiconductor Layer-the structure of the metal layer.
  • the material of the two-dimensional semiconductor layer includes one or a combination of the following materials: WS 2 , WSe 2 , MoS 2 , for example, the first two-dimensional semiconductor layer 102 is WS 2 , and the second two The material of the dimensional semiconductor layer 104 is WSe 2 .
  • the thickness of the two-dimensional semiconductor layer can be adjusted between 2 nm and 10 nm, for example, it can be 3 nm, 4 nm, 5 nm, 6 nm, 8 nm, and so on.
  • the material of the metal layer is the following materials: Pt, Ta, W, Ir, Os, Re, Hf, Pd, Rh, Mo, Nb, Zr, Au, Tc, Cd, Pb, and Sn One kind of simple substance or several kinds of alloys.
  • Fig. 3 is a volt-ampere characteristic curve of a two-dimensional material-based gate according to an embodiment of the present disclosure.
  • the volt-ampere characteristic curve of the two-dimensional material-based gate including a laminated unit is symmetrical and has a bidirectional switching characteristic.
  • the volt-ampere characteristics corresponding to positive and negative voltage loading are symmetrical. Described by the volt-ampere characteristic curve on one side, when the value of the loaded negative voltage gradually increases, the current density through the two-dimensional material-based gate gradually increases, as shown by the arc in Figure 3 It is shown that the current density at this time is 10 3 A/cm 2 , which reaches the half-bias voltage of the gate operation, which is shown as V 0 /2 in Fig. 3.
  • the current density of the current passing through the two-dimensional material-based gate continues to increase until it reaches the inflection point.
  • the line corresponding to V 0 is shown as the focus of the volt-ampere characteristic curve.
  • the process of increasing the current density is shown by the straight line with a larger slope in FIG. 3.
  • the current density at this time is about ⁇ 10 6 A/cm 2 , and this straight line corresponds to the opening process of the two-dimensional material-based gate.
  • the voltage when the gate switches from the initial high-resistance state to the low-resistance state is defined as the threshold voltage.
  • the threshold voltage (V 0 /2) is lower than 0.3V, and the smaller the corresponding device performance, the better.
  • the turn-on voltage (also called operating voltage) of the gate is the voltage corresponding to the current of the gate above a certain value (after stable turn-on). In this embodiment, the turn-on voltage is V 0 , and the current density of the corresponding gate reaches 10 6 A/cm 2 .
  • the turn-on voltage of the above-mentioned two-dimensional material-based gate can be any value between 0.8V and 1.2V, including the endpoint value.
  • the on-off ratio of the two-dimensional material-based gate is not less than 10 3 .
  • the on-current density of the two-dimensional material-based gate is not less than 10 6 A/cm 2 .
  • the two-dimensional material-based gate of this embodiment has a bidirectional conduction switching characteristic, and is suitable for read and write operations of STT-MRAM.
  • the above-mentioned two-dimensional material-based gate has a minimum threshold voltage of 0.3V, a high switching ratio ( ⁇ 10 3 ), and a high turn-on slope ( ⁇ 2mV/dec), showing better performance.
  • the second exemplary embodiment of the present disclosure provides a memory cell.
  • the memory unit in this embodiment is referred to as the first memory unit, and the memory unit in another embodiment to be described later is referred to as the second memory unit.
  • FIG. 4 is a schematic diagram of the structure of a memory cell according to an embodiment of the present disclosure.
  • the first memory unit 10 includes: a two-dimensional material-based gate, the two-dimensional material-based gate in this embodiment is the first gate 100 exemplified in the first embodiment; and a magnetic Tunnel knot 200.
  • the first gate 100 and the magnetic tunnel junction 200 are stacked along the first direction (z direction) to form a selective memory cell.
  • the on-off of the first gate 100 in the selective memory cell can be used for the magnetic tunnel junction 200 Control of read and write operations.
  • the selection storage unit includes a first surface (corresponding to the lower surface in FIG. 4) and a second surface (corresponding to the upper surface in FIG. 4) disposed oppositely along a first direction. The first surface is used to connect to the word line 400, and the second The surface is used to connect with the bit line 300.
  • the first memory cell 100 may also have a structure including a bit line 300 and a word line 400.
  • FIG. 5 is a schematic structural diagram of a magnetic tunnel junction according to an embodiment of the present disclosure.
  • the magnetic tunnel junction 200 includes a reference layer 201 formed of a ferromagnetic material, a barrier layer 202, and a free layer 203 whose magnetic moment can be flipped.
  • the free layer 203 is used for storage. information.
  • the reference layer 201 formed of ferromagnetic material has an easy magnetization axis along the first direction (or referred to as along the direction perpendicular to the film surface), which is beneficial to the miniaturization of the device.
  • the word line 400 may be composed of a ferromagnetic metal composite layer, and may include a pinned layer and a pinned layer formed of ferromagnetic metal.
  • the ferromagnetic metal material may include one or more of the following materials: CoFeB, CoFe 2 Al, and The Heusler alloy compound, and the Heusler alloy compound is, for example, Mn 3 Ga.
  • the two-dimensional material-based gate is located above the magnetic tunnel junction as an example.
  • the present disclosure is not limited to this.
  • two The dimensional material-based gate can be located above or below the magnetic tunnel junction.
  • the two-dimensional material-based gate can be transformed from the off state to the on state, and has a current density greater than 10 6 A/cm 2 (which can reach 10 7 A/cm 2 ), Can realize the fast reading and writing of STT-MRAM.
  • the current density of the above-mentioned two-dimensional material-based gate is 10 3 A/cm 2
  • the switching ratio is greater than 10 3
  • the third exemplary embodiment of the present disclosure provides an operating method of a memory cell.
  • the operating method of the memory cell of this embodiment includes: applying a first voltage on the first surface of the selected memory cell, and applying a second voltage on the second surface of the selected memory cell.
  • the first voltage and the second voltage are generated on the selected memory cell.
  • the value of the voltage drop is greater than the voltage value of the turn-on voltage of the two-dimensional material-based gate to operate the magnetic tunnel junction, and the above-mentioned operation includes at least one of a read operation and a write operation.
  • the value of the voltage drop corresponding to the writing operation is greater than the value of the voltage drop corresponding to the reading operation.
  • the operation of the first memory unit shown in the second embodiment is taken as an example below.
  • the first memory cell 10 includes: a first gate 100; and a magnetic tunnel junction 200.
  • the first gate 100 and the magnetic tunnel junction 200 are stacked along the first direction (z direction) to form a selected memory cell.
  • FIG. 6 is a schematic diagram of operating a memory unit according to an embodiment of the disclosure. Referring to FIG. 6, a first voltage V 1 is applied to the word line 400 and a second voltage V 2 is applied to the bit line 300. The application directions of the first voltage and the second voltage in FIG. 6 are only examples.
  • FIG. 7 is a schematic diagram of writing a "0" operation to the memory cell shown in FIG. 6 according to an embodiment of the disclosure. 6 and 7, the first voltage V 1 is applied to the first surface of the selected memory cell through the word line 400 , and the second voltage V 2 is applied to the second surface of the selected memory cell through the bit line 300.
  • the first voltage The value of the voltage drop generated by V 1 and the second voltage V 2 on the selected memory cell is greater than the voltage value of the turn-on voltage of the two-dimensional material-based gate, and the voltage drop generated on the selected memory cell is V W+ , the voltage drop is The value V W+ is, for example, 1V, and the current corresponding to this voltage is I W+ .
  • the voltage drop V W+ causes the two-dimensional material-based gate to be turned on.
  • the electrons in the bit line 300 are first injected into the reference layer 201 and pass through the reference layer 201.
  • the current produces a spin current.
  • the spin current passes through the barrier layer 202 and injects into the adjacent free layer 203 to transfer the spin moment to the free layer 203, thereby converting the magnetization direction of the free layer 203 into the same magnetization direction as the reference layer 201, so that the magnetic tunnel junction ( The MTJ) 200 presents a low-impedance state and realizes the operation of writing "0".
  • FIG. 8 is a schematic diagram of writing a "1" operation to the memory cell shown in FIG. 6 according to an embodiment of the present disclosure.
  • the first voltage V 1 is applied to the first surface of the selected memory cell through the word line 400
  • the second voltage is applied to the second surface of the selected memory cell through the bit line 300.
  • V 2 the voltage drop generated by the first voltage V 1 and the second voltage V 2 on the selected memory cell is greater than the voltage value of the turn-on voltage of the two-dimensional material-based gate, and the voltage drop generated on the selected memory cell is V W- , the value of voltage drop V W- is 1V, and the current corresponding to this voltage is I W- .
  • the electrons in the word line 400 are first injected into the free layer 203 in the magnetic tunnel junction 200. At this time, the current magnitude and polarization constant.
  • the current passes through the barrier layer 202 in the middle and reaches the reference layer 201, the electrons in the direction opposite to the spin magnetic moment of the reference layer 201 will be reflected, return to the free layer 203, and transfer the spin moment to the free layer 203. Thereby, the magnetization direction of the free layer 203 is reversed and is antiparallel to the reference layer 201, so that the magnetic tunnel junction 200 presents a high resistance state, and the operation of writing “1” is realized.
  • FIG. 9 is a schematic diagram of performing a read operation on the memory cell described in FIG. 6 according to an embodiment of the present disclosure.
  • the first voltage V 1 is applied to the first surface of the selected memory cell through the word line 400
  • the second voltage V 2 is applied to the second surface of the selected memory cell through the bit line 300.
  • the first voltage The value of the voltage drop generated by V 1 and the second voltage V 2 on the selected memory cell is greater than the voltage value of the turn-on voltage of the two-dimensional material-based gate.
  • the voltage drop generated on the selected memory cell is V R
  • the voltage drop is V
  • the value of R is , for example, 0.7V ⁇ 0.8V, so that the two-dimensional material-based gate is turned on to form a conductive channel.
  • Different resistance states pass through different current levels I R.
  • the output current level I R can be measured to store information. 0" state and "1" state read.
  • FIG. 10 is a schematic diagram of an equivalent circuit after a two-dimensional material-based gate is turned on according to an embodiment of the present disclosure.
  • the first gate 100 of this embodiment when the first gate 100 of this embodiment is turned on, two stacked stacked units form an inverted series structure, where the first stacked unit 100a and the second stacked unit 100b are in the circuit Is equivalent to two diodes in reverse series.
  • the voltage V or the current I that can turn on the first gate 100 is applied to the magnetic tunnel junction 200. Read and write operations.
  • the two-dimensional material-based gate of this embodiment is described as the second gate.
  • the difference between the second gate of this embodiment and the first embodiment is that the second gate of this embodiment includes M stacked units, M ⁇ 2, which is different from the first embodiment in that each stacked unit In the unit, one of the two interfaces forms an ohmic contact, and the other interface forms a Schottky contact, and the M stacked units include M anti-parallel Schottky diode structures.
  • Fig. 11 is a schematic structural diagram of a two-dimensional material-based gate according to another embodiment of the present disclosure.
  • the second gate 110 of this embodiment includes: M stacked units, M ⁇ 2, and each stacked unit is a metal-two-dimensional semiconductor-metal (M-S-M) structure.
  • the second gate 110 includes two stacked units as an example, and the two stacked units are described as the first stacked unit 111 and the second stacked unit 112, respectively.
  • the M-S-M structure of this embodiment is the same as that of the first embodiment, and also includes: a two-dimensional semiconductor layer and a metal layer respectively disposed on the upper and lower surfaces of the two-dimensional semiconductor layer.
  • at least two stacked units are arranged along a direction parallel to the surface where the two-dimensional semiconductor layer is located, here described as the second direction, the second direction is perpendicular to the first direction, in FIG. 11 the second direction
  • the example is the direction along the x-axis.
  • An insulating layer 113 is provided between the sidewalls of two adjacent stacked units among the M stacked units. Referring to FIG. 11, an insulating layer 113 is provided between the first stacked unit 111 and the second stacked unit 112.
  • the interface between the third metal layer 1111 and the first two-dimensional semiconductor layer 1112 forms an ohmic contact
  • the interface between the fifth metal layer 1113 and the first two-dimensional semiconductor layer 1112 forms an ohmic contact.
  • Schottky contact the interface between the fourth metal layer 1121 and the second two-dimensional semiconductor layer 1122
  • the interface between the sixth metal layer 1123 and the second two-dimensional semiconductor layer 1122 forms an ohmic contact. contact.
  • FIG. 17 a schematic diagram of the equivalent circuit after the two-dimensional material-based gate is turned on is shown.
  • the stacked unit 111 and the second stacked unit 112 can be equivalent to two anti-parallel Schottky diode structures in circuit. The same goes for the case where multiple stacked units are arranged along the second direction.
  • Fig. 12 is a volt-ampere characteristic curve of a two-dimensional material-based gate according to another embodiment of the present disclosure.
  • the volt-ampere characteristic curve of the two-dimensional material-based gate including two laminated units in anti-parallel in this embodiment is symmetrical and has a bidirectional switching characteristic.
  • the volt-ampere characteristic curves corresponding to positive voltage and negative voltage loading are symmetrical.
  • the current density gradually increases, and the increasing amplitude becomes larger and larger, corresponding to the tangent slope of the volt-ampere characteristic curve gradually increasing.
  • the current density of the two-dimensional material-based gate is greater than 10 6 A/cm 2
  • the applied forward voltage is, for example, 0.5V (V W+ /2)
  • the current density of the two-dimensional material-based gate is 10 2 A/cm 2
  • the on-off ratio is 104.
  • the above-mentioned voltage V W+ may correspond to the voltage of the programming operation. Also corresponds to the example in FIG. 12 corresponding to a read operation voltage V R, the value of the voltage V R is less than the voltage value V W +.
  • FIG. 13 is a schematic diagram of the structure of a memory cell and operations on the memory cell according to another embodiment of the present disclosure.
  • the second memory unit 11 of this embodiment includes: a two-dimensional material-based gate, and the two-dimensional material-based gate in this embodiment is the second gate 110 exemplified in the fourth embodiment. ; And the magnetic tunnel junction 200.
  • the second gate 110 and the magnetic tunnel junction 200 are stacked along the first direction (z direction) to form a selective memory cell.
  • the on-off of the second gate 110 in the selective memory cell can be used for the magnetic tunnel junction 200 Control of read and write operations.
  • the selection storage unit includes a first surface (corresponding to the lower surface in FIG. 13) and a second surface (corresponding to the upper surface in FIG. 13) disposed oppositely along the first direction. The first surface is used to connect to the word line 400, and the second The surface is used to connect with the bit line 300.
  • the second memory cell 110 may also have a structure including a bit line 300 and a word line 400.
  • the content of the magnetic tunnel junction 200 in this embodiment is the same as that of the first embodiment, and will not be repeated here.
  • the operation method of the memory unit in this embodiment will be described below with reference to FIGS. 12-16.
  • the operating method of this embodiment is the same as the method of operating the memory cell described in the third embodiment, except that the structure of the two-dimensional material-based gate (second gate) in this embodiment is the same as that of the third embodiment.
  • the structure of the first strobe in the example is different.
  • FIG. 14 is a schematic diagram of writing a "0" operation to the memory cell shown in FIG. 12 according to another embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of writing a "1" operation to the memory cell shown in FIG. 12 according to another embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of performing a read operation on the memory cell shown in FIG. 12 according to another embodiment of the present disclosure.
  • a first voltage V 1 is applied to the word line 400, and a second voltage V 2 is applied to the bit line 300.
  • the application directions of the first voltage and the second voltage in FIG. 12 are only For example, the magnitude of the first voltage and the second voltage described in this embodiment may be equal to or different from the magnitude of the first voltage and the second voltage described in the previous embodiment.
  • the first voltage V 1 is applied to the first surface of the selected memory cell through the word line 400
  • the second voltage V 2 is applied to the second surface of the selected memory cell through the bit line 300.
  • the first voltage The value of the voltage drop generated by V 1 and the second voltage V 2 on the selected memory cell is greater than the voltage value of the turn-on voltage of the second gate 110 , and the voltage drop generated on the selected memory cell is V W+ , the value of the voltage drop V W+ is, for example, 1V, and the current corresponding to this voltage is I W+ .
  • the voltage drop V W+ causes the second gate 110 to be turned on.
  • the electrons in the bit line 300 are first injected into the reference layer 201, and the current passing through the reference layer 201 generates The spin flow.
  • the spin current passes through the barrier layer 202 and injects into the adjacent free layer 203 to transfer the spin moment to the free layer 203, thereby converting the magnetization direction of the free layer 203 into the same magnetization direction as the reference layer 201, so that the magnetic tunnel junction ( The MTJ) 200 presents a low-impedance state and realizes the operation of writing "0".
  • the first voltage V 1 is applied to the first surface of the selected memory cell through the word line 400
  • the second voltage V 2 is applied to the second surface of the selected memory cell through the bit line 300.
  • the first voltage The value of the voltage drop generated by V 1 and the second voltage V 2 on the selected memory cell is greater than the voltage value of the turn-on voltage of the second gate 110
  • the voltage drop generated on the selected memory cell is V W-
  • the voltage drop is V
  • the value of W- is 1V
  • the current corresponding to this voltage is I W- .
  • the electrons in the word line 400 are first injected into the free layer 203 in the magnetic tunnel junction 200. At this time, the current magnitude and polarization remain unchanged.
  • the electrons in the direction opposite to the spin magnetic moment of the reference layer 201 will be reflected, return to the free layer 203, and transfer the spin moment to the free layer 203.
  • the magnetization direction of the free layer 203 is reversed and is antiparallel to the reference layer 201, so that the magnetic tunnel junction 200 presents a high resistance state, and the operation of writing “1” is realized.
  • the first voltage V 1 is applied to the first surface of the selected memory cell through the word line 400
  • the second voltage V 2 is applied to the second surface of the selected memory cell through the bit line 300.
  • the first voltage The value of the voltage drop generated by V 1 and the second voltage V 2 on the selected memory cell is greater than the voltage value of the turn-on voltage of the second gate 110 , the voltage drop generated on the selected memory cell is V R , and the voltage drop V R The value of is, for example, 0.7V ⁇ 0.8V, including the endpoint value, so that the two-dimensional material-based gate is turned on to form a conductive channel.
  • Different resistance states pass through different current levels I R.
  • the current level I R can be measured by measuring the output current level I R. Storage information "0" state and "1" state read.
  • the sixth exemplary embodiment of the present disclosure provides a memory array and an operating method of the memory array.
  • FIG. 18 is a schematic structural diagram of a two-dimensional memory array according to an embodiment of the present disclosure.
  • FIG. 19 is a schematic structural diagram of a three-dimensional memory array according to an embodiment of the present disclosure.
  • the memory array of this embodiment includes: at least one layer of interleaved memory array 20.
  • the memory array may be a two-dimensional memory array, and the memory array includes only one layer of interleaved memory array 20.
  • the interleaved memory array 20 includes: a bit line array 310, a word line array 410, and a plurality of memory cells arranged at the intersection of the bit line array 310 and the word line array 410.
  • Each of the plurality of memory cells may It is the first memory unit 10 or the second memory unit 11 described in the above embodiment.
  • the first gate 100/the second gate 110 and the magnetic tunnel junction 200 are stacked along the first direction (z direction) to form a selected memory cell.
  • the bit line array 310 may include m word lines arranged in parallel along the second direction (along the x direction), and m is a positive integer greater than or equal to 2.
  • the word line array 410 may include n word lines arranged in parallel along the third direction (along the y direction), and n is a positive integer greater than or equal to 2.
  • the third direction (along the y direction) is perpendicular to the first direction (along the z direction), and there is an included angle between the third direction and the second direction (along the x direction).
  • the included angle can be 90° or other suitable
  • the angle of, for example, can be a value between 60° and 120°, including the endpoint value.
  • the bit line array 310 and the word line array 410 form m ⁇ n intersections, and there are a total of m ⁇ n memory cells located at the intersections. Each memory cell is connected between the bit line and the word line at the intersection.
  • the two-dimensional memory array is a 3 ⁇ 3 array.
  • bit line array 310 three bit lines are exemplified, namely, the first bit line 311, the second bit line 312, and the third bit line. 313.
  • word line array 410 three word lines are taken as an example, which are the first word line 411, the second word line 412, and the third word line 413, respectively.
  • the above-mentioned two-dimensional memory array further includes a selection transistor 510.
  • the selection transistor is connected in series on each word line of the multiple word lines of each layer of the cross memory array, and is used to control the on-off of the corresponding word line.
  • a first selection transistor 511 is connected in series on the first word line 411, and the first selection transistor 511 is used to control the on and off of the first word line 411.
  • a second selection transistor 512 is connected in series to the second word line 412, and the second selection transistor 512 is used to control the on and off of the second word line 412.
  • a third selection transistor 513 is connected in series to the third word line 413, and the third selection transistor 513 is used to control the on and off of the third word line 413.
  • Locate the selected storage unit that needs to be operated For example, in the example of FIG. 18, locate the selected storage unit circled by the dotted line.
  • the coordinates of the selected storage unit are (1, 1, 1).
  • An example of the structure of the selection storage unit in the memory unit 10 is given.
  • the above selection storage unit may also be the selection storage unit in the second memory unit 11.
  • the positioning method may be addressing to the word line and bit line corresponding to the selected memory cell.
  • the above-mentioned operation includes at least one of a write operation and a read operation.
  • the first voltage V 1 is applied to the word line where the selected memory cell to be operated is located
  • the second voltage V 2 is applied to the bit line where the selected memory cell to be operated is located.
  • a first voltage V 1 is applied to the first word line 411 where the selected memory cell with coordinates (1, 1, 1) is located
  • a second voltage V 2 is applied to the first bit line 311 where it is located.
  • the directions of the first voltage and the second voltage illustrated in the figure are only examples. It should be noted that the values of the first voltage and the second voltage described in this embodiment and the values of the first voltage and the second voltage described in the previous embodiments may be equal or not equal.
  • the value of the voltage drop generated by the first voltage V 1 and the second voltage V 2 on the selected memory cell that needs to be operated is greater than the voltage value of the turn-on voltage V on of the two-dimensional material-based gate on the selected memory cell, so as to correct
  • the magnetic tunnel junction in the memory cell that needs to be operated is selected for operation.
  • the control of turning on the word line can be achieved by controlling the on and off of the select transistor connected in series with the word line.
  • a zero voltage is applied to the remaining word lines and the remaining bit lines, and the coordinates of the selected memory cell with the coordinates (1, 1, 1) on the same bit line (the first bit line 311) are (2, 1, 1) and The voltage drop generated on the remaining selected memory cells of (3, 1, 1) is: V 2 , at the coordinates of the selected memory cell with coordinates (1, 1, 1) on the same word line (first word line 411) The voltage drop generated on the remaining selected memory cells respectively ( 1, 2, 1) and (1, 3, 1) is : V 1.
  • the value of the voltage drop corresponding to the writing operation is greater than the value of the voltage drop corresponding to the reading operation.
  • the voltage drop corresponding to the write operation is 1V (see FIG. 12)
  • the voltage drop corresponding to the read operation is 0.6V to 0.8V (see FIG. 12).
  • the memory array may also be a three-dimensional memory array, and the three-dimensional memory array includes a multi-layer interleaved memory array 20.
  • a three-dimensional memory array can be obtained by stacking a plurality of the above-mentioned two-dimensional memory arrays 20 along the first direction (z-axis direction). Referring to FIG. 19, taking a three-layer interleaved memory array as an example, the three-layer interleaved memory array 20 is sequentially from bottom to top: a first interleaved memory array 20a, a second interleaved memory array 20b, and a third interleaved memory array 20c.
  • each layer of the interleaved memory array 20 may be the same as the two-dimensional memory array illustrated in FIG. 18, and each includes a selection transistor connected to a word line.
  • An insulating layer is arranged between two adjacent layers of the interleaved storage array in the multi-layer interleaved storage array.
  • an insulating layer is provided between the intersection of the word line array of the interleaved memory array of the upper layer and the bit line array of the interleaved memory array of the lower layer (not shown in FIG. 19).
  • the operation method of the three-dimensional memory array is the same as the operation method of the two-dimensional memory array, which will be briefly described below with reference to FIG. 19.
  • the above-mentioned operation includes at least one of a write operation and a read operation.
  • the first voltage V 1 is applied to the word line where the selected memory cell to be operated is located
  • the second voltage V 2 is applied to the bit line where the selected memory cell to be operated is located, as shown in FIG. 19.
  • the value of the voltage drop generated by the first voltage V 1 and the second voltage V 2 on the selected memory cell that needs to be operated is greater than the voltage value of the turn-on voltage V on of the two-dimensional material-based gate, so as to select the required operation
  • the magnetic tunnel junction in the memory cell operates.
  • a zero voltage is applied to the remaining word lines and the remaining bit lines.
  • the three-dimensional memory array 30 includes not only other selected memory cells that are on the same word line and on the same bit line as the selected memory cell that needs to be operated, but also other selected memory cells that do not need to be operated on.
  • the selected memory cells to be operated on are on different word lines and other selected memory cells that do not need to be operated on different bit lines.
  • the voltage drop of other selected memory cells that are on a different word line and different bit lines than (1, 1, 3) and do not need to be operated are zero, and the voltage drop is zero
  • the corresponding coordinates of the selected storage units in Figure 19 are (1,1,2,2), (1,2,2), (1,3,2), (2,1,2), (2,2,2). ), (2, 3, 2), (3, 1, 2), (3, 2, 2), (3, 3, 2), (1, 1, 1), (1, 2, 1), (1,3,1), (2,1,1), (2,2,1), (2,3,1), (3,1,1), (3,2,1), (3 , 3, 1), (2, 2, 3), (2, 3, 3), (3, 2, 3), (3, 3, 3).
  • V 2 The voltage drop generated on the remaining selected memory cells with coordinates (2, 1, 3) and (3, 1, 3) on the same bit line as the selected memory cell with coordinates (1, 1, 3) is: V 2 , the voltage generated on the remaining selected memory cells with coordinates (1, 2, 3) and (1, 3, 3) on the same word line as the selected memory cell with coordinates (1, 1, 3) Reduced to: V 1 .
  • the electrical characteristics of the first voltage V 1 and the voltage value of the second voltage V 2 can be set to be less than or equal to V on /2, and the selected memory cell to be operated is on the same word line or other bit line.
  • the voltage drop of the selected memory cell satisfies that the two-dimensional material-based gates in the other selected memory cells are turned off.
  • the value of the voltage drop corresponding to the writing operation is greater than the value of the voltage drop corresponding to the reading operation.
  • the voltage drop corresponding to the write operation is 1V
  • the voltage drop corresponding to the read operation is 0.6V-0.8V.
  • the shapes of the memory unit and the gate can also be replaced with cylindrical, circular, or other shapes, and are not limited to the examples in the embodiments and drawings.
  • the two-dimensional semiconductor material can be replaced by a two-dimensional material having the same physical and electrical properties as WSe 2 , WS 2 , MoS 2, etc.
  • the technical features in each of the above embodiments can be combined with each other to form a new embodiment, and all fall within the protection scope of the present disclosure.
  • the two-dimensional material-based gate provided by the embodiments of the present disclosure can realize high-speed and reliable bidirectional turn-on, the turn-on voltage is less than 1V, the leakage current is pA level, and it has a high turn-on current density (more than 10MA/ cm 2 ) and high non-linearity (on-off ratio exceeds 10 3 ).
  • the use of a two-dimensional material-based gate as the switch of the magnetic tunnel junction in the magnetic memory cell can realize the rapid reading and writing of STT-MRAM.
  • the two-dimensional or three-dimensional memory array composed of the above-mentioned magnetic memory cells is operated, based on the high switching ratio of the two-dimensional material-based gate, for the memory cells that are not gated (in the off state), the corresponding current pole Small (10 3 A/cm 2 ).
  • the arrangement of the above-mentioned two-dimensional material-based gates greatly suppresses the leakage current generated by other memory cells on the same word line or on the same bit line as the selected memory cell.
  • ordinal numbers used in the description and claims such as “first”, “second”, “third”, etc., are used to modify the corresponding element, which does not mean that the element has any ordinal number. It does not represent the order of an element and another element, or the order of the manufacturing method. The use of these ordinal numbers is only used to make a element with a certain name to be clearly distinguished from another element with the same name. .

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Abstract

一种二维材料基选通器、存储器单元、阵列及其操作方法，该选通器包括：叠层单元。叠层单元为金属-二维半导体-金属结构，包括二维半导体层，以及分别设置于二维半导体层上、下表面的金属层。其中，叠层单元的个数为N，N≥1，每个叠层单元中，两个金属-二维半导体的界面均形成肖特基接触，并且在二维材料基选通器通电导通时，该叠层单元包括两个反向串联的肖特基二极管结构。或者，叠层单元的个数为M个，M≥2，每个叠层单元中，两个金属-二维半导体的界面中的一个界面形成肖特基接触，另一个界面形成欧姆接触，并且在二维材料基选通器通电导通时，M个叠层单元包括M个反向并联的肖特基二极管结构。

Description

二维材料基选通器、存储器单元、阵列及其操作方法 技术领域
本公开属于存储技术领域，涉及一种二维材料基选通器、存储器单元、阵列及其操作方法。
背景技术
磁随机存储器(Magnetic Random Access Memory，MRAM)是一种新型非易失性存储器。MRAM的核心部分是磁隧道结(Magnetic Tunnel Junction，MTJ)。MTJ由铁磁材料基的参考层(Reference Layer)、自由层(Free Layer)以及两者中间的高质量氧化物隧道势垒层(Tunneling Barrier Layer)构成。参考层和自由层之间磁化方向反平行时，MTJ表现为高电阻态“1”；而当两者磁化方向平行时，则表现出低阻态“0”，从而通过驱动自由层磁化方向翻转完成MTJ高低阻态的变化进而实现信息的存储。相较于传统的静态随机存储器(SRAM)而言，MRAM具有更小的体积、更低的漏电，从而可降低静态功耗；相比于动态存储器(DRAM)而言，MRAM具有更快的读写操作速度和非易失性。同时MRAM还具有较高的读写次数、与现有集成电路工艺兼容和抗辐照等优点。
依据信息存储机制划分，现行MRAM有三种数据写入方式。最早的技术为磁场写入MARM，即利用脉冲电流产生的奥斯特场，实现自由层的磁化翻转，进而实现所需信息的存储。然而这种方式存在的技术问题是，所需脉冲电流较大，存取速度慢，且不易集成，难以满足现代信息器件的需求。现有采用自旋转移力矩技术的磁存储器(Spin Transfer Torque MRAM，STT-MRAM)，通过极化电流进行电子自旋注入，基于自旋转移力矩驱动自由层的磁化方向翻转完成信息的写入，可显著减小器件尺寸、降低功耗、提高速度，尤其在高性能嵌入式存储方面有重要应用。2012年，研究人员提出自旋轨道扭矩磁随机存储器(Spin-Orbit Torque MRAM，SOT-MRAM)的概念，该存储器采用自旋轨道耦合效应实现自旋注入，驱动自由层中材料磁化方向的翻转。该方法将数据写入和读取的路径分开。 原理上可进一步减小功耗、提高数据写入速度和读写次数。然而三端结构的SOT-MRAM存储单元需要更大的单元面积，不利于该存储器的高密度集成，因而暂时无法实现大容量的存储，也成为目前限制SOT-MRAM发展的主要障碍之一。
因此基于上述三种数据写入方式的优缺点，采用自旋转移力矩的磁存储器STT-MRAM方式进行信息写入，依然是MRAM器件制备中广泛采用的方法。STT-MRAM也是业界公认最接近替代Flash闪存的内存方案。然而，STT-MRAM同样存在集成密度偏低、能耗需要优化的问题。另一方面，现有的存储器阵列存在漏电流问题。当阵列中的某个存储单元被选中时，与选中存储单元位于同一位线、字线的未选中存储单元处于半偏压状态，存在较大的漏电流。
为了在增加存储密度的同时，减小交叉阵列器件在使用时存在的漏电流，研究者们通常在存储单元上串联一个选通器，通常使用常规的晶体管、常规二极管或者常规双向阈值开关等。但是，传统硅基的晶体管、二极管存在尺寸大、工艺复杂以及阈值调制高温限制等缺点，不利于高密度集成；除了与传统双向阈值开关(Ovonic threshold switching，OTS)选通器一样面临高温可靠性问题以外，硫族的双向阈值开关厚度较厚，迁移率低从而影响存储速度；变阻型选通器，如混合离子电子导体(mixed ion-electron conductors，MIEC)选通器和电场辅助超线性阈值(field-assisted superlinear threshold，FAST)选通器本身的开态电阻过高而无法与现有MTJ有效匹配兼容，从而使其受限应用于高密度集成STT-MRAM。
因此，需要提出一种新型选通器配置的存储器三维集成结构，具有高速、低功耗、高密度的性能，且能降低漏电流。
发明内容
本公开提供了一种二维材料基选通器、存储器单元、阵列及其操作方法，以至少部分解决以上所提出的技术问题。
根据本公开的第一个方面，提供了一种二维材料基选通器。该二维材料基选通器包括叠层单元，该叠层单元为金属-二维半导体-金属结构。金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于二维半导 体层上、下表面的金属层。其中，当该二维材料基选通器通电导通时，所述叠层单元包括两个反向串联的肖特基二极管结构。
在本公开的一实施例中，二维材料基选通器包括N个叠层单元，N≥1，当N≥2时，至少两个叠层单元沿着第一方向堆叠，所述第一方向垂直于所述二维半导体材料层所在平面。
根据本公开的第二个方面，提供了一种二维材料基选通器。该二维材料基选通器包括M个叠层单元，M≥2。每个叠层单元为金属-二维半导体-金属结构。所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所述二维半导体层上、下表面的金属层。其中，每个叠层单元中，其中一个金属-二维半导体界面形成欧姆接触，另一个金属-二维半导体界面形成肖特基接触。M个叠层单元沿着第二方向排布，第二方向平行于所述二维半导体层所在平面，在所述M个叠层单元中相邻的两个叠层单元的侧壁之间设置有绝缘层，在二维材料基选通器通电导通时M个叠层单元为M个反向并联的肖特基二极管结构。
在本公开的一实施例中，二维半导体层的材料包括以下材料中的一种或其组合：WS 2、WSe 2、MoS 2。
在本公开的一实施例中，二维半导体层的厚度为2nm-10nm，包含端点值，例如可以是2nm、3nm、4nm、5nm、6nm、8nm、10nm等。
在本公开的一实施例中，金属层的材料为以下材料：Pt、Ta、W、Ir、Os、Re、Hf、Pd、Rh、Mo、Nb、Zr、Au、Tc、Cd、Pb以及Sn中的一种形成的单质或几种形成的合金。
在本公开的一实施例中，二维材料基选通器的伏安特性曲线为对称的，具有双向导通开关特性。
在本公开的一实施例中，二维材料基选通器的开启电压为0.8V～1.2V。
在本公开的一实施例中，二维材料基选通器的开关比不小于10 3。
在本公开的一实施例中，二维材料基选通器的开启电流密度不小于10 6A/cm 2。
根据本公开的第三个方面，提供了一种存储器单元。该存储器单元包括：上述提及的任一种二维材料基选通器；以及磁隧道结；其中，二维材料基选通器与磁隧道结沿着第一方向堆叠以形成选择存储单元，该选择存 储单元包括沿着第一方向相对设置的第一表面和第二表面，第一表面用于与字线连接，第二表面用于与位线连接。
在本公开的一实施例中，存储器单元中，沿着第一方向，二维材料基选通器位于磁隧道结的上方或者下方。
根据本公开的第四个方面，提供了一种存储器阵列。该存储器阵列包括：至少一层交叉存储阵列。每层交叉存储阵列包括：位线阵列，包括沿着第二方向平行设置的多条位线；字线阵列，包括沿着第三方向平行设置的多条字线；其中第三方向与第一方向垂直，第三方向与第二方向之间具有夹角；设置于字线阵列和位线阵列交叉点处的多个存储器单元，多个存储器单元中每个存储器单元为上述提及的任一种存储器单元。
在本公开的一实施例中，存储器阵列还包括：选择晶体管。该选择晶体管串联于每层交叉存储阵列的多条字线的每条字线上，用于控制所对应字线的通断。
在本公开的一实施例中，当存储器阵列包括多层交叉存储阵列时，多层交叉存储阵列中相邻的两层交叉存储阵列之间设置有绝缘层。
根据本公开的第五个方面，提供了一种关于上述存储器单元的操作方法。该存储器单元的操作方法包括：在选择存储单元的第一表面施加第一电压，在选择存储单元的第二表面施加第二电压，第一电压与第二电压在选择存储单元上产生的电压降的值大于二维材料基选通器的开启电压的电压值，以对磁隧道结进行操作，上述操作包括读操作和写操作至少一个。
在本公开的一实施例中，上述存储器单元的操作方法中，进行写操作对应的电压降的值大于进行读操作对应的电压降的值。
根据本公开的第六个方面，提供了一种关于上述存储器阵列的操作方法。该存储器阵列的操作方法包括：定位至需要进行操作的选择存储单元；在需要进行操作的选择存储单元所在的字线上施加第一电压V 1，并在需要进行操作的选择存储单元所在的位线上施加第二电压V 2；在其余字线和其余位线施加零电压；其中，第一电压V 1和第二电压V 2在需要进行操作的选择存储单元上产生的电压降的值大于二维材料基选通器的开启电压V on的电压值，以对需要进行操作的选择存储器单元中的磁隧道结进行操作，该操作包括写操作和读操作至少一个；第一电压的电压值和第二电压的电 压值均小于等于V on/2，使得与需要进行操作的选择存储器单元处于同一字线或同一位线的其它选择存储单元的电压降满足：使得其它选择存储单元中的二维材料基选通器处于关断状态。
在本公开的一实施例中，进行写操作对应的电压降的值大于进行读操作对应的电压降的值。
从上述技术方案可以看出，本公开提供的二维材料基选通器、存储器单元、阵列及其操作方法，至少具有以下有益效果：
(1)通过设置金属-二维半导体-金属结构，在两个金属-二维半导体界面处形成了两个肖特基结，在该二维材料基选通器施加电压导通之后，两个肖特基结为反向串联结构，形成的反向串联的肖特基二极管结构具有双向导通开启的性能，具有较小的开启电压(为0.8～1.2V)，漏电流为pA级，同时具有高开启电流密度(超过10 6A/cm 2)和较高的非线性度(开关比超过10 3)，作为选通开关的开关特性优异。
(2)通过设置至少两个叠层结构沿着平行于二维半导体所在平面进行排布，中间并间隔有绝缘层，在每个叠层结构，其中一个金属-二维半导体形成欧姆接触，另一个形成肖特基接触，在该二维材料基选通器施加电压导通之后，至少两个叠层结构形成了若干个反向并联的肖特基二极管的结构，具有较小的开启电压(为0.8～1.2V)，漏电流为pA级，同时具有高开启电流密度(超过10 6A/cm 2)和较高的非线性度(开关比超过10 3)，作为选通开关的开关特性优异。
(3)使用二维材料基选通器分别与每个磁隧道结串联，形成一选通器一磁隧道结(1S-1M)的选择存储单元，由于二维材料基选通器的关态漏电流小(～1pA)，使得某个存储器单元进行读取或者写入操作时，其余存储单元几乎处于关断状态，降低了漏电流的大小，大大减小了三维STT-MRAM阵列的功耗。超薄的二维材料具有1V的低开启电压，在选通开启时表现出了高非线性度、极高的开启电流(超过10 6A/cm 2)，能够快速驱动存储单元中自由层的磁化翻转，提高了三维存储器阵列的开关速度(＜10ns)。
(4)由于二维范德华材料可制成少层甚至单层结构，其厚度在1nm左右，相比晶体管、串联二极管、普通的双向导通开关等制作的选通器而 言，具有更小的厚度尺寸，为高密度集成提供有利条件。
附图说明
图1为根据本公开一实施例所示的二维材料基选通器的结构示意图。
图2为根据本公开一实施例所示的金属-二维半导体-金属结构的能带示意图，其中(a)为不施加偏压的情况下的能带示意图；(b)为在施加电压的情况下的能带示意图。
图3为根据本公开一实施例所示的二维材料基选通器的伏安特性曲线。
图4为根据本公开一实施例所示的存储器单元的结构示意图。
图5为根据本公开一实施例所示的磁隧道结的结构示意图。
图6为根据公开一实施例所示的对存储器单元进行操作的示意图。
图7为根据公开一实施例所示的对图6所示的存储器单元进行写“0”操作的示意图。
图8为根据本公开一实施例所示的对图6所示的存储器单元进行写“1”操作的示意图。
图9为根据本公开一实施例所示的对图6所述的存储器单元进行读取操作的示意图。
图10为根据本公开一实施例所示的二维材料基选通器导通后的等效电路示意图。
图11为根据本公开另一实施例所示的二维材料基选通器的结构示意图。
图12为根据本公开另一实施例所示的二维材料基选通器的伏安特性曲线。
图13为根据本公开另一实施例所示的存储器单元的结构以及对该存储器单元进行操作的示意图。
图14为根据本公开另一实施例所示的对图12所示的存储器单元进行写“0”操作的示意图。
图15为根据本公开另一实施例所示的对图12所示的存储器单元进行写“1”操作的示意图。
图16为根据本公开另一实施例所示的对图12所示的存储器单元进行 读取操作的示意图。
图17为根据本公开另一实施例所示的二维材料基选通器导通后的等效电路示意图。
图18为根据本公开一实施例所示的二维存储器阵列的结构示意图。
图19为根据本公开一实施例所示的三维存储器阵列的结构示意图。
【符号说明】
10-第一存储器单元；
100-第一选通器；
101-第一金属层；              102-二维半导体层；
103-第二金属层；
100a-第一金属-二维半导体界面；
100b-第二金属-二维半导体界面；
200-磁隧道结；
201-参考层；                  202-隧穿势垒层；
203-自由层；
300-位线；
400-字线；
11-第二存储器单元；
110-第二选通器；
111-第一叠层单元；
1111-第三金属层；             1112-第一二维半导体层；
1113-第五金属层；
112-第二叠层单元；
1121-第四金属层；             1122-第二二维半导体层；
1123-第六金属层；
113-绝缘层；
20-二维存储器阵列；
310-位线阵列；
311-第一位线；                312-第二位线；
313-第三位线；
410-字线阵列；
411-第一字线；                 412-第二字线；
413-第三字线；
510-选择晶体管；
511-第一选择晶体管；           512-第二选择晶体管；
513-第三选择晶体管；
30-三维存储器阵列；
20a-第一二维存储器阵列；
20b-第二二维存储器阵列；
20c-第三二维存储器阵列。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本公开进一步详细说明。
本公开的实施例提供的二维材料基选通器包括：叠层单元，该叠层单元为金属-二维半导体-金属结构，金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于二维半导体层上、下表面的金属层。其中，上述叠层单元的个数为N，N≥1，每个叠层单元中，两个金属-二维半导体的界面均形成肖特基接触，并且在二维材料基选通器通电导通时，该叠层单元包括两个反向串联的肖特基二极管结构。或者，上述叠层单元的个数为M个，M≥2，每个叠层单元中，两个金属-二维半导体的界面中其中一个界面形成肖特基接触，另一个界面形成欧姆接触，并且在二维材料基选通器通电导通时，M个叠层单元包括M个反向并联的肖特基二极管结构。本公开的实施例提供的存储器单元包括：上述二维材料基选通器；以及磁隧道结；其中，二维材料基选通器与磁隧道结沿着第一方向堆叠以形成选择存储单元，该选择存储单元包括沿着第一方向相对设置的第一表面和第二表面，第一表面用于与字线连接，第二表面用于与位线连接。
本公开的第一个示例性实施例提供了一种二维材料基选通器。
图1为根据本公开一实施例所示的二维材料基选通器的结构示意图。为了描述方便，将本实施例的二维材料基选通器称为第一选通器，将后面 要描述的另一实施例中的选通器称为第二选通器。
参照图1所示，本实施例的第一选通器100，包括：叠层单元，图1中以一个叠层单元进行示例，其他更多个数的叠层单元按照相同的方式设置即可，对应的电路可以等效为多个叠层单元的串联电路。叠层单元为金属-二维半导体-金属(M-S-M)结构，该M-S-M结构包括：二维半导体层，以及分别设置于二维半导体层上、下表面的金属层。
参照图1所示的结构，叠层单元包括：二维半导体层102，设置于二维半导体层102上方的第一金属层101，以及设置于二维半导体层102下方的第二金属层103。
下面参照图2中(a)、(b)以及图3来介绍每个叠层单元的电学特性。
图2为根据本公开一实施例所示的金属-二维半导体-金属结构的能带示意图，其中(a)为不施加偏压的情况下的能带示意图；(b)为在施加电压的情况下的能带示意图。
参照图2中(a)所示，在对M-S-M结构不施加偏压的情况下，金属层与二维半导体层(为了简化描述，在本文有的描述中简称为二维材料层)接触时，由于金属和二维材料层之间存在功函数差φs，所以会在金属和二维材料层的接触界面产生肖特基势垒。在一个M-S-M结构中，形成两个肖特基势垒。势垒宽度尺寸表示为T SB，二维材料层的厚度表示为T S，其中二维材料层的厚度T S与势垒宽度T SB的二倍相当，为了突出显示上述尺寸关系，在图2中(a)将二维材料层拆开示意为两个部分。当外加电压为0或是电压较低时，该M-S-M结构可以视为处于无电流流过的关断状态。
参照图2中(b)所示，在对M-S-M结构施加电压V 0的情况下，该M-S-M结构中二维材料层的能带会发生弯曲，使得二维材料层的右侧的导带下降，达到与左侧金属层的能级对齐的位置。例如图2中(b)示意的能带弯曲情况对应的施加电压V 0的正负方向为右侧为正，左侧为负，这里的左右是参照图2中(b)的方向。
在上述M-S-M结构中存在三种电流产生模式。一种电流产生模式为：在电压V 0的作用下，载流子越过肖特基势垒层产生的热载流子发射效应。另两种电流产生模式为：在电压V 0的作用下，半导体层中能带发生弯曲， 由此发生富雷-诺特海姆式隧穿(F-N Tunneling)以及直接隧穿为主的隧道效应(Tunneling Effect)。
根据本公开的实施例，二维材料基选通器可以包括N个叠层单元，N≥1。当二维材料基选通器包括的叠层单元的个数N≥2时，至少两个叠层单元沿着第一方向堆叠，该第一方向垂直于二维半导体材料层所在平面。即，N个叠层单元沿着垂直于二维半导体层所在平面进行堆叠时，在该二维材料基选通器导通后，N个叠层单元相当于依次串联。
在二维材料基选通器导通的情况下，在每个叠层单元内部，包括两个反向串联的肖特基二极管结构。参照图1和图10所示，图10示意了二维材料基选通器导通后的等效电路，每个叠层单元中的金属-二维半导体-金属结构中具有两个金属-二维半导体界面，分别为第一金属层101和二维半导体层102形成的界面，以及第二金属层103与二维半导体层102形成的界面，在图10中这两个界面分别描述为第一金属-二维半导体界面100a和第二金属-二维半导体界面100b。参照图10所示，在该第一选通器100通电导通时，第一金属-二维半导体界面100a和第二金属-二维半导体界面100b等效于两个反向串联的肖特基二极管，因此，在二维材料基选通器导通的情况下，每个叠层单元包括两个反向串联的肖特基二极管结构。
对于多个叠层单元堆叠的情况按照串联的形式以此类推。当然，叠层单元的个数可以根据实际情况进行优化设置，叠层单元的个数过多可能会导致开关性能的降低。
在一实施例中，相邻的两个叠层单元之间的各自的金属层也可以由同一层金属层充当。例如，两个叠层单元可以是金属层-二维半导体层-金属层-金属层-二维半导体层-金属层的结构，也可以是金属层-二维半导体层-金属层-二维半导体层-金属层的结构。
在本公开的一实施例中，二维半导体层的材料包括以下材料中的一种或其组合：WS 2、WSe 2、MoS 2，例如第一二维半导体层102为WS 2，第二二维半导体层104的材料为WSe 2。
在本公开的一实施例中，二维半导体层的厚度在2nm-10nm之间可调控，例如可以是3nm、4nm、5nm、6nm、8nm等。在本公开的一实施例中，金属层的材料为以下材料：Pt、Ta、W、Ir、Os、Re、Hf、Pd、Rh、 Mo、Nb、Zr、Au、Tc、Cd、Pb以及Sn中的一种形成的单质或者几种形成的合金。
图3为根据本公开一实施例所示的二维材料基选通器的伏安特性曲线。
由图3可知，本实施例中，包含一个叠层单元的二维材料基选通器的伏安特性曲线为对称的，具有双向导通开关特性。参照图3所示，正向电压和负向电压加载对应的伏安特性是对称的。以其中一侧的伏安特性曲线进行描述，在加载的负向电压的值逐渐增大的情况下，通过二维材料基选通器的电流密度逐渐增大，如图3中的弧线所示，此时的电流密度为10 3A/cm 2，达到选通器操作的半偏电压，在图3中以V 0/2进行示意。之后随着电压值逐步增大，通过二维材料基选通器的电流的电流密度继续增大直至达到拐点，在图3中以V 0对应的直线与该伏安特性曲线的焦点所示意，该电流密度增大的过程以图3中的斜率较大的直线所示，此时的电流密度约为～10 6A/cm 2，该段直线对应二维材料基选通器的开启过程。在二维材料基选通器处于导通状态后，随着电压值的逐步增大，通过二维材料基选通器的电流的电流密度增大的幅度减小，如图3中斜率较小的直线段所示。该选通器由初始的高阻态转变为低阻态时的电压定义为阈值电压，本实施例中阈值电压(V 0/2)低于0.3V，并且越小对应的器件性能越好。选通器的开启电压(也称工作电压)为选通器的电流达到特定值以上(稳定开启后)对应的电压，本实施例中开启电压为V 0，对应选通器的电流密度达到10 6A/cm 2。
经过实验测试，上述二维材料基选通器的开启电压可以为0.8V～1.2V之间的任意数值，包括端点值。该二维材料基选通器的开关比不小于10 3。在本公开的一实施例中，二维材料基选通器的开启电流密度不小于10 6A/cm 2。
本实施例的二维材料基选通器具有双向导通开关特性，可适用于STT-MRAM的读写操作。在一些实施例，上述二维材料基选通器具有最小为0.3V的阈值电压、高开关比(≥10 3)，高开启斜率(≥2mV/dec)，体现出较好的性能。
本公开的第二个示例性实施例提供了一种存储器单元。为了描述方便，将本实施例的存储器单元称为第一存储器单元，将后面要描述的另一实施 例中的存储器单元称为第二存储器单元。
图4为根据本公开一实施例所示的存储器单元的结构示意图。参照图4所示，该第一存储器单元10包括：二维材料基选通器，本实施例中二维材料基选通器为第一实施例所示例的第一选通器100；以及磁隧道结200。其中，第一选通器100与磁隧道结200沿着第一方向(z方向)堆叠以形成选择存储单元，该选择存储单元中第一选通器100的通断可以用于磁隧道结200读写操作的控制。该选择存储单元包括沿着第一方向相对设置的第一表面(图4中对应下表面)和第二表面(图4中对应上表面)，第一表面用于与字线400连接，第二表面用于与位线300连接。
在一些实施例中，该第一存储器单元100也可以是包含位线300和字线400的结构。
上述磁隧道结200可以是现有技术中的磁隧道结。图5为根据本公开一实施例所示的磁隧道结的结构示意图。在一示例性实施例中，参照图5所示，磁隧道结200包括：铁磁材料形成的参考层201、势垒层202以及磁矩可以被翻转的自由层203，自由层203用于存储信息。其中铁磁材料形成的参考层201具有沿着第一方向(或者称为沿着垂直于膜面方向)的易磁化轴，有利于器件的微缩。
字线400可以由铁磁金属复合层组成，可以包括铁磁金属形成的钉扎层和被钉扎层，铁磁金属材料可以包括以下材料中的一种或几种：CoFeB、CoFe 2Al以及Heusler合金化合物，Heusler合金化合物例如为Mn 3Ga。
图4所示的示意图中，以二维材料基选通器位于磁隧道结的上方进行示例，本公开不以此为限，在本公开实施例的存储器单元中，沿着第一方向，二维材料基选通器可以位于磁隧道结的上方或者下方。
上述存储器单元在开启电压V 0下，二维材料基选通器可以由关断状态转变为开启状态，并且拥有大于10 6A/cm 2(可以达到10 7A/cm 2)的电流密度，可以实现STT-MRAM的快速读写。在关断状态下，上述二维材料基选通器的电流密度为10 3A/cm 2，开关比大于10 3，具有优良的双向导通开关特性。
本公开的第三个示例性实施例提供了一种存储器单元的操作方法。本实施例的存储器单元的操作方法包括：在选择存储单元的第一表面施加第 一电压，在选择存储单元的第二表面施加第二电压，第一电压与第二电压在选择存储单元上产生的电压降的值大于二维材料基选通器的开启电压的电压值，以对磁隧道结进行操作，上述操作包括读操作和写操作至少一个。
其中，上述存储器单元的操作方法中，进行写操作对应的电压降的值大于进行读操作对应的电压降的值。
下面以对第二实施例所示的第一存储器单元进行操作作为示例。
第一存储器单元10包括：第一选通器100；以及磁隧道结200。第一选通器100与磁隧道结200沿着第一方向(z方向)堆叠以形成选择存储单元。图6为根据公开一实施例所示的对存储器单元进行操作的示意图。参照图6所示，在字线400上施加第一电压V 1，在位线300上施加第二电压V 2，图6中第一电压和第二电压的施加方向仅作为示例。
下面参照图7～图9来描述对图6所示的存储器单元进行读写操作对应的过程。
图7为根据公开一实施例所示的对图6所示的存储器单元进行写“0”操作的示意图。参照图6和图7所示，通过字线400在选择存储单元的第一表面施加第一电压V 1，通过位线300在选择存储单元的第二表面施加第二电压V 2，第一电压V 1与第二电压V 2在选择存储单元上产生的电压降的值大于二维材料基选通器的开启电压的电压值，在选择存储单元上产生的电压降为V W+，电压降的值V W+例如为1V，该电压对应的电流为I W+，上述电压降V W+使得二维材料基选通器导通，位线300中的电子首先注入至参考层201，经过参考层201的电流产生了自旋流。自旋流穿过势垒层202注入邻近的自由层203，将自旋矩转移到自由层203，从而将自由层203的磁化方向转化为与参考层201的磁化方向相同，使得磁隧道结(MTJ)200呈现低阻态，实现写“0”的操作。
图8为根据本公开一实施例所示的对图6所示的存储器单元进行写“1”操作的示意图。参照图8所示，参照图6和图8所示，通过字线400在选择存储单元的第一表面施加第一电压V 1，通过位线300在选择存储单元的第二表面施加第二电压V 2，第一电压V 1与第二电压V 2在选择存储单元上产生的电压降的值大于二维材料基选通器的开启电压的电压值，在选择存 储单元上产生的电压降为V W-，电压降V W-的值为1V，该电压对应的电流为I W-，字线400中的电子首先注入磁隧道结200中的自由层203中，此时电流大小与极化不变。当电流穿过中间的势垒层202，到达参考层201时，与参考层201自旋磁矩方向相反的电子将被反射，回到自由层203，并将自旋矩转移给自由层203，从而翻转自由层203的磁化方向，并与参考层201反平行，使得磁隧道结200呈现高阻态，实现写“1”的操作。
图9为根据本公开一实施例所示的对图6所述的存储器单元进行读取操作的示意图。参照图6和图9所示，通过字线400在选择存储单元的第一表面施加第一电压V 1，通过位线300在选择存储单元的第二表面施加第二电压V 2，第一电压V 1与第二电压V 2在选择存储单元上产生的电压降的值大于二维材料基选通器的开启电压的电压值，在选择存储单元上产生的电压降为V R，电压降V R的值例如为0.7V～0.8V，使得二维材料基选通器开启，形成导电通道，不同的阻态通过的电流大小I R不同，通过测量输出的电流大小I R实现对存储信息“0”态和“1”态的读取。
图10为根据本公开一实施例所示的二维材料基选通器导通后的等效电路示意图。参照图10所示，本实施例的第一选通器100通电导通时，两个堆叠的叠层单元形成反向串联结构，其中第一叠层单元100a和第二叠层单元100b在电路中等效于两个反向串联的二极管，通过将第一选通器100与磁性隧道结200串联，通过施加可以使第一选通器100导通的电压V或者电流I实现对于磁性隧道结200的读写操作。
本公开的第四个示例性实施例提供了另一种二维材料基选通器。
为了与第一实施例的第一选通器进行区分，将本实施例的二维材料基选通器描述为第二选通器。本实施例的第二选通器与第一实施例的区别在于，本实施例的第二选通器包括M个叠层单元，M≥2，与第一实施例不同，在每个叠层单元中，两个界面中一个界面形成欧姆接触，另一个界面形成肖特基接触，并且M个叠层单元包括M个反向并联的肖特基二极管结构。
图11为根据本公开另一实施例所示的二维材料基选通器的结构示意图。
参照图11所示，本实施例的第二选通器110，包括：M个叠层单元， M≥2，每个叠层单元为金属-二维半导体-金属(M-S-M)结构。
本实施例中，以第二选通器110包括两个叠层单元进行示例，这两个叠层单元分别描述为第一叠层单元111和第二叠层单元112。本实施例的M-S-M结构与第一实施例的相同，同样包括：二维半导体层，以及分别设置于二维半导体层上、下表面的金属层。本实施例中，至少两个叠层单元沿着平行于二维半导体层所在表面的方向排布，这里描述为第二方向，该第二方向与第一方向垂直，在图11中第二方向示例为沿着x轴的方向。在M个叠层单元中相邻的两个叠层单元的侧壁之间设置有绝缘层113。参照图11所示，在第一叠层单元111和第二叠层单元112之间设置有绝缘层113。
参照图11所示，第一叠层单元111包括：第一二维半导体层1112，设置于第一二维半导体层1112上表面的第三金属层1111，以及设置于第一二维半导体层1112下表面的第五金属层1113。第二叠层单元112包括：第二二维半导体层1122，设置于第二二维半导体层1122上表面的第四金属层1121，以及设置于第二二维半导体层1122下表面的第六金属层1123。其中，每个叠层单元中，其中一个金属-二维半导体界面形成欧姆接触，另一个金属-二维半导体界面形成肖特基接触，在二维材料基选通器导通的情况下，第一叠层单元111和第二叠层单元112在电路上可以等效为两个反向并联的肖特基二极管结构。
例如，示例性的，在第一叠层单元111中，第三金属层1111和第一二维半导体层1112的界面形成欧姆接触，第五金属层1113和第一二维半导体层1112的界面形成肖特基接触。对应的，在第二叠层单元112中，第四金属层1121和第二二维半导体层1122的界面形成肖特基接触，第六金属层1123和第二二维半导体层1122的界面形成欧姆接触。参照图17所示，示意了二维材料基选通器导通后的等效电路示意图，在该第二选通器110上施加外电压使得该第二选通器110导通后，第一叠层单元111和第二叠层单元112在电路上可以等效为两个反向并联的肖特基二极管结构。对于多个叠层单元沿着第二方向排布的情况以此类推。
图12为根据本公开另一实施例所示的二维材料基选通器的伏安特性曲线。参照图12所示，本实施例中包含反向并联的两个叠层单元的二维 材料基选通器的伏安特性曲线为对称的，具有双向导通开关特性。具体而言，参照图12所示，正向电压和负向电压加载对应的伏安特性曲线是对称的。随着加载电压的取值逐渐增大，电流密度逐渐增加，且增加的幅度越来越大，对应该伏安特性曲线的切线斜率逐渐增加。在施加正向电压为V W+(例如为1V)和反向电压V W-(例如为-1V)的情况下，该二维材料基选通器的电流密度大于10 6A/cm 2，在施加正向电压例如为0.5V(V W+/2)的情况下，该二维材料基选通器的电流密度为10 2A/cm 2，开关比为104。上述电压V W+可以对应为编程操作的电压。对应在图12中还示例出了进行读取操作对应的电压V R，该电压V R的值小于电压V W+的值。
本公开的第五个示例性实施例提供了一种存储器单元，以及该存储器单元的操作方法。本实施例中，为了与第二实施例描述的第一存储器单元进行区分，本实施例的存储器单元称为第二存储器单元。本实施例中存储器单元与第一实施例的存储器单元的区别在于二维材料基选通器的结构发生了变化。
图13为根据本公开另一实施例所示的存储器单元的结构以及对该存储器单元进行操作的示意图。
参照图13所示，本实施例的第二存储器单元11包括：二维材料基选通器，本实施例中二维材料基选通器为第四实施例所示例的第二选通器110；以及磁隧道结200。其中，第二选通器110与磁隧道结200沿着第一方向(z方向)堆叠以形成选择存储单元，该选择存储单元中第二选通器110的通断可以用于磁隧道结200读写操作的控制。该选择存储单元包括沿着第一方向相对设置的第一表面(图13中对应下表面)和第二表面(图13中对应上表面)，第一表面用于与字线400连接，第二表面用于与位线300连接。
在一些实施例中，该第二存储器单元110也可以是包含位线300和字线400的结构。
本实施例中磁性隧道结200与第一实施例的内容相同，这里不再赘述。
下面结合图12～图16来描述本实施例中存储器单元的操作方法。本实施例的操作方法与第三实施例描述的对存储器单元进行操作的方法相同，区别之处在于本实施例中二维材料基选通器(第二选通器)的结构与第三 实施例中的第一选通器的结构存在差异。
图14为根据本公开另一实施例所示的对图12所示的存储器单元进行写“0”操作的示意图。图15为根据本公开另一实施例所示的对图12所示的存储器单元进行写“1”操作的示意图。图16为根据本公开另一实施例所示的对图12所示的存储器单元进行读取操作的示意图。
参照图12所示，本实施例中，在字线400上施加第一电压V 1，在位线300上施加第二电压V 2，图12中第一电压和第二电压的施加方向仅作为示例，本实施例中描述的第一电压和第二电压的大小与前面实施例描述的第一电压和第二电压的大小可以相等，也可以不相等。
参照图12和图14所示，通过字线400在选择存储单元的第一表面施加第一电压V 1，通过位线300在选择存储单元的第二表面施加第二电压V 2，第一电压V 1与第二电压V 2在选择存储单元上产生的电压降的值大于第二选通器110的开启电压的电压值，在选择存储单元上产生的电压降为V W+，电压降的值V W+例如为1V，该电压对应的电流为I W+，上述电压降V W+使得第二选通器110导通，位线300中的电子首先注入至参考层201，经过参考层201的电流产生了自旋流。自旋流穿过势垒层202注入邻近的自由层203，将自旋矩转移到自由层203，从而将自由层203的磁化方向转化为与参考层201的磁化方向相同，使得磁隧道结(MTJ)200呈现低阻态，实现写“0”的操作。
参照图12和图15所示，通过字线400在选择存储单元的第一表面施加第一电压V 1，通过位线300在选择存储单元的第二表面施加第二电压V 2，第一电压V 1与第二电压V 2在选择存储单元上产生的电压降的值大于第二选通器110的开启电压的电压值，在选择存储单元上产生的电压降为V W-，电压降V W-的值为1V，该电压对应的电流为I W-，字线400中的电子首先注入磁隧道结200中的自由层203中，此时电流大小与极化不变。当电流穿过中间的势垒层202，到达参考层201时，与参考层201自旋磁矩方向相反的电子将被反射，回到自由层203，并将自旋矩转移给自由层203，从而翻转自由层203的磁化方向，并与参考层201反平行，使得磁隧道结200呈现高阻态，实现写“1”的操作。
参照图12和图16所示，通过字线400在选择存储单元的第一表面施 加第一电压V 1，通过位线300在选择存储单元的第二表面施加第二电压V 2，第一电压V 1与第二电压V 2在选择存储单元上产生的电压降的值大于第二选通器110的开启电压的电压值，在选择存储单元上产生的电压降为V R，电压降V R的值例如为0.7V～0.8V，包含端点值，使得二维材料基选通器开启，形成导电通道，不同的阻态通过的电流大小I R不同，通过测量输出的电流大小I R实现对存储信息“0”态和“1”态的读取。
本公开的第六个示例性实施例提供了一种存储器阵列以及存储器阵列的操作方法。
图18为根据本公开一实施例所示的二维存储器阵列的结构示意图。图19为根据本公开一实施例所示的三维存储器阵列的结构示意图。
参照图18和图19所示，本实施例的存储器阵列包括：至少一层交叉存储阵列20。
参照图18所示，存储器阵列可以是二维存储器阵列，该存储器阵列只包括一层交叉存储器阵列20。该层交叉存储器阵列20包括：位线阵列310、字线阵列410以及设置于位线阵列310和字线阵列410交叉点处的多个存储器单元，这些多个存储器单元中的每个存储器单元可以是上述实施例中描述的第一存储器单元10或者是第二存储器单元11。第一存储器单元10/第二存储器单元11中，第一选通器100/第二选通器110与磁隧道结200沿着第一方向(z方向)堆叠以形成选择存储单元。
位线阵列310可以包括沿着第二方向(沿着x方向)平行设置的m条字线，m为大于等于2的正整数。字线阵列410可以包括沿着第三方向(沿着y方向)平行设置的n条字线，n为大于等于2的正整数。第三方向(沿着y方向)与第一方向(沿着z方向)垂直，第三方向与第二方向(沿着x方向)之间具有夹角，该夹角可以为90°或者其他合适的角度，例如可以是介于60°～120°之间的数值，包含端点值。位线阵列310和字线阵列410形成m×n个交叉点，位于交叉点处共有m×n个存储器单元。每个存储器单元连接于所处交叉点处的位线和字线之间。
在图18中示例性示意了该二维存储器阵列为3×3的阵列，位线阵列310中以3条位线示例，分别为第一位线311、第二位线312和第三位线313。字线阵列410中以3条字线示例，分别为第一字线411、第二字线 412和第三字线413。
在一实施例中，上述二维存储器阵列还包括：选择晶体管510。该选择晶体管串联于每层交叉存储阵列的多条字线的每条字线上，用于控制所对应字线的通断。参照图18所示，在第一字线411上串联有第一选择晶体管511，该第一选择晶体管511用于控制该第一字线411的通断。在第二字线412上串联有第二选择晶体管512，该第二选择晶体管512用于控制第二字线412的通断。在第三字线413上串联有第三选择晶体管513，第三选择晶体管513用于控制第三字线413的通断。
下面介绍该二维存储器阵列的操作方法。
定位至需要进行操作的选择存储单元，例如，在图18的示例中，定位至虚线圆圈圈出的选择存储单元，该选择存储单元的坐标为(1，1，1)，图18中以第一存储器单元10中的选择存储单元的结构进行示例，上述选择存储单元也可以是第二存储器单元11中的选择存储单元。定位的方式可以是选址到该选择存储单元对应的字线和位线。上述操作包括写操作和读操作至少一个。
在需要进行操作的选择存储单元所在的字线上施加第一电压V 1，并在需要进行操作的选择存储单元所在的位线上施加第二电压V 2。如图18所示，在坐标为(1，1，1)的选择存储单元所在的第一字线411上施加第一电压V 1，所在的第一位线311上施加第二电压V 2，图中示例的第一电压和第二电压的方向仅为示例。需要说明的是，本实施例描述的第一电压和第二电压与前面实施例的描述的第一电压和第二电压的值可以相等，也可以不相等。第一电压V 1和第二电压V 2在需要进行操作的选择存储单元上产生的电压降的值大于该选择存储单元上二维材料基选通器的开启电压V on的电压值，以对需要进行操作的选择存储器单元中的磁隧道结进行操作。在一实施例中，可以通过控制与字线串联的选择晶体管的通断来实现对于字线开启的控制。
在其余字线和其余位线施加零电压，在与坐标为(1，1，1)的选择存储单元处于同一位线(第一位线311)的坐标分别为(2，1，1)和(3，1，1)的其余选择存储单元上产生的电压降为：V 2，在与坐标为(1，1，1)的选择存储单元处于同一字线(第一字线411)的坐标分别为(1，2，1)和(1，3，1) 的其余选择存储单元上产生的电压降为：V 1。为了使得其余选择存储单元上产生的电压降不足以使上述其余选择存储单元中的二维材料基选通器开启，因此，根据前面实施例中描述的第一选通器或者第二选通器的电学特性，可以设置第一电压的电压值和第二电压的电压值均小于等于V on/2，则与需要进行操作的选择存储器单元处于同一字线或同一位线的其它不需要进行操作的选择存储单元的电压降满足：使得其它选择存储单元中的二维材料基选通器处于关断状态。在一实施例中，可以在位线上施加零电压，通过控制字线上的选择晶体管处于关断状态以实现在字线上施加零电压的效果。
其中，进行写操作对应的电压降的值大于进行读操作对应的电压降的值。例如在一实施例中，写操作对应的电压降为1V(可以参照图12所示)，读操作对应的电压降为0.6V～0.8V(可以参照图12所示)。
参照图19所示，为了提高存储密度，存储器阵列也可以是三维存储器阵列，该三维存储器阵列包括多层交叉存储器阵列20。由多个上述二维存储器阵列20沿着第一方向(z轴方向)可以进行堆叠得到三维存储器阵列。参照图19所示，以三层交叉存储器阵列作为示例，这三层交叉存储器阵列20自下而上依次为：第一交叉存储器阵列20a、第二交叉存储器阵列20b以及第三交叉存储器阵列20c。该三维存储器阵列中，每层交叉存储器阵列20可以与图18示例的二维存储器阵列相同，均包括与字线连接的选择晶体管。
在多层交叉存储阵列中相邻的两层交叉存储阵列之间设置有绝缘层。本实施例中，在上一层的交叉存储器阵列的字线阵列与下一层的交叉存储器阵列的位线阵列的交叉点之间设置有绝缘层(图19中未示意)。
该三维存储器阵列的操作方法与二维存储器阵列的操作方法相同，下面参照图19进行简要描述。
定位至需要进行操作的选择存储单元，参照图19所示，定位至坐标为(1，1，3)的选择存储单元；定位的方式可以是选址到该选择存储单元对应的字线和位线。上述操作包括写操作和读操作至少一个。
在需要进行操作的选择存储单元所在的字线上施加第一电压V 1，并在需要进行操作的选择存储单元所在的位线上施加第二电压V 2，参照图19 所示。第一电压V 1和第二电压V 2在需要进行操作的选择存储单元上产生的电压降的值大于二维材料基选通器的开启电压V on的电压值，以对需要进行操作的选择存储器单元中的磁隧道结进行操作。
在其余字线和其余位线施加零电压。参照图19所示，对于三维存储器阵列30而言，既包括与该需要进行操作的选择存储单元处于同一字线和处于同一位线的其它不需要进行操作的选择存储单元，又包括与该需要进行操作的选择存储单元处于不同字线且不同位线的其它不需要进行操作的选择存储单元。
通过在其余字线和其余位线施加零电压，使得与(1，1，3)处于不同字线且不同位线的其它不需要进行操作的选择存储单元的电压降为零，电压降为零的选择存储单元分别在图19中对应坐标为(1，1，2)、(1，2，2)、(1，3，2)、(2，1，2)、(2，2，2)、(2，3，2)、(3，1，2)、(3，2，2)、(3，3，2)、(1，1，1)、(1，2，1)、(1，3，1)、(2，1，1)、(2，2，1)、(2，3，1)、(3，1，1)、(3，2，1)、(3，3，1)、(2，2，3)、(2，3，3)、(3，2，3)、(3，3，3)。
在与坐标为(1，1，3)的选择存储单元处于同一位线的坐标分别为(2，1，3)和(3，1，3)的其余选择存储单元上产生的电压降为：V 2，在与坐标为(1，1，3)的选择存储单元处于同一字线的坐标分别为(1，2，3)和(1，3，3)的其余选择存储单元上产生的电压降为：V 1。为了使得其余选择存储单元上产生的电压降不足以使上述其余选择存储单元中的二维材料基选通器开启，因此，根据前面实施例中描述的第一选通器或者第二选通器的电学特性，可以设置第一电压V 1的电压值和第二电压V 2的电压值均小于等于V on/2，则与需要进行操作的选择存储器单元处于同一字线或同一位线的其它选择存储单元的电压降满足：使得其它选择存储单元中的二维材料基选通器处于关断状态。
在本公开的一实施例中，进行写操作对应的电压降的值大于进行读操作对应的电压降的值。例如在一实施例中，写操作对应的电压降为1V，读操作对应的电压降为0.6V～0.8V。
本公开的实施例中，存储器单元以及选通器的形状还可以以圆柱、环形等形状进行替换或者变形为其它形状，不局限于实施例和附图示例的情形。二维半导体材料可以采用与WSe 2、WS 2、MoS 2等具有相同物理和电 学特性的二维材料来代替。上述各个实施例中的技术特征可以相互组合以形成新的实施例，均在本公开的保护范围之内。
综上所述，本公开实施例提供的二维材料基选通器该可实现高速可靠的双向导通开启，开启电压小于1V，漏电流为pA级，同时具有高开启电流密度(超过10MA/cm 2)和较高的非线性度(开关比超过10 3)。采用二维材料基选通器作为磁存储器单元中的磁隧道结的开关，能够实现STT-MRAM的快速读写。由上述磁存储器单元构成的二维或三维存储器阵列操作时，基于二维材料基选通器的高开关比，对于未被选通(处于关断状态)的存储单元而言，相应的电流极小(10 3A/cm 2)。上述二维材料基选通器的设置大大抑制了与选中的存储器单元处于同字线或同位线上的其它存储器单元产生的漏电流。
需要说明的是，在附图或说明书的描述中，相似或相同的部分都使用相同的图号。附图中未绘示或描述的实现方式，为所属技术领域中普通技术人员所知的形式。另外，虽然本文可提供包含特定值的参数的示范，但应了解，参数无需确切等于相应的值，而是可在可接受的误差容限或设计约束内近似于相应的值。实施例中提到的方向用语，例如“上”、“下”、“前”、“后”、“左”、“右”等，仅是参考附图的方向。因此，使用的方向用语是用来说明并非用来限制本公开的保护范围。
并且，为实现图面整洁的目的，一些习知惯用的结构与组件在附图可能会以简单示意的方式绘示之。另外，本案的附图中部分的特征可能会略为放大或改变其比例或尺寸，以达到便于理解与观看本公开的技术特征的目的，但这并非用于限定本公开。依照本公开所公开的内容所制造的产品的实际尺寸与规格应是可依据生产时的需求、产品本身的特性、及搭配本公开如下所公开的内容据以调整，于此先进行声明。
此外，说明书与权利要求中所使用的序数例如“第一”、“第二”、“第三”等的用词，以修饰相应的元件，其本身并不意味着该元件有任何的序数，也不代表某一元件与另一元件的顺序、或是制造方法上的顺序，该些序数的使用仅用来使具有某命名的一元件得以和另一具有相同命名的元件能做出清楚区分。
以上所述的具体实施例，对本公开的目的、技术方案和有益效果进行 了进一步详细说明，所应理解的是，以上所述仅为本公开的具体实施例而已，并不用于限制本公开，凡在本公开的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (17)

  1. 一种二维材料基选通器，其特征在于，包括：
    叠层单元，所述叠层单元为金属-二维半导体-金属结构，所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所述二维半导体层上、下表面的金属层；
    其中，在所述二维材料基选通器通电导通时，所述叠层单元包括两个反向串联的肖特基二极管结构。
  2. 根据权利要求1所述的二维材料基选通器，其特征在于，所述二维材料基选通器包括N个叠层单元，N≥1，当N≥2时，至少两个叠层单元沿着第一方向堆叠，所述第一方向垂直于所述二维半导体材料层所在平面。
  3. 一种二维材料基选通器，其特征在于，包括：
    M个叠层单元，M≥2，每个叠层单元为金属-二维半导体-金属结构，所述金属-二维半导体-金属结构包括：二维半导体层，以及分别设置于所述二维半导体层上、下表面的金属层；
    其中，每个叠层单元中，其中一个金属-二维半导体界面形成欧姆接触，另一个金属-二维半导体界面形成肖特基接触；
    所述M个叠层单元沿着第二方向排布，所述第二方向平行于所述二维半导体层所在平面，在所述M个叠层单元中相邻的两个叠层单元的侧壁之间设置有绝缘层，在所述二维材料基选通器通电导通时所述M个叠层单元为M个反向并联的肖特基二极管结构。
  4. 根据权利要求1-3中任一项所述的二维材料基选通器，其特征在于，所述二维半导体层的材料包括以下材料中的一种或其组合：WS 2、WSe 2、MoS 2。
  5. 根据权利要求1-3中任一项所述的二维材料基选通器，其特征在于，所述二维半导体层的厚度为2nm-10nm。
  6. 根据权利要求1-3中任一项所述的二维材料基选通器，其特征在于，所述金属层的材料为以下材料：Pt、Ta、W、Ir、Os、Re、Hf、Pd、Rh、Mo、Nb、Zr、Au、Tc、Cd、Pb以及Sn中的一种形成的单质或几种形成 的合金。
  7. 根据权利要求1-3中任一项所述的二维材料基选通器，其特征在于，所述二维材料基选通器的伏安特性曲线为对称的，具有双向导通开关特性。
  8. 根据权利要求1-3中任一项所述的二维材料基选通器，其特征在于，
    所述二维材料基选通器的开启电压为0.8V～1.2V；和/或，
    所述二维材料基选通器的开关比不小于10 3；和/或，
    所述二维材料基选通器的开启电流密度不小于10 6A/cm 2。
  9. 一种存储器单元，其特征在于，包括：
    权利要求1-8中任一项所述的二维材料基选通器；以及
    磁隧道结；
    其中，所述二维材料基选通器与所述磁隧道结沿着第一方向堆叠以形成选择存储单元，所述选择存储单元包括沿着所述第一方向相对设置的第一表面和第二表面，所述第一表面用于与字线连接，所述第二表面用于与位线连接。
  10. 根据权利要求9所述的存储器单元，其特征在于，沿着所述第一方向，所述二维材料基选通器位于所述磁隧道结的上方或者下方。
  11. 一种存储器阵列，其特征在于，所述存储器阵列包括：
    至少一层交叉存储阵列，每层交叉存储阵列包括：
    位线阵列，包括沿着第二方向平行设置的多条位线；
    字线阵列，包括沿着第三方向平行设置的多条字线；其中所述第三方向与所述第一方向垂直，所述第三方向与所述第二方向之间具有夹角；
    设置于所述字线阵列和所述位线阵列交叉点处的多个存储器单元，所述多个存储器单元中每个存储器单元为权利要求9或10所述的存储器单元。
  12. 根据权利要求11所述的存储器阵列，其特征在于，还包括：选择晶体管，所述选择晶体管串联于所述每层交叉存储阵列的多条字线的每条字线上，用于控制所对应字线的通断。
  13. 根据权利要求11所述的存储器阵列，其特征在于，当所述存储器阵列包括多层交叉存储阵列时，多层交叉存储阵列中相邻的两层交叉存储阵列之间设置有绝缘层。
  14. 一种如权利要求9所述的存储器单元的操作方法，其特征在于，包括：
    在所述选择存储单元的所述第一表面施加第一电压，在所述选择存储单元的所述第二表面施加第二电压，所述第一电压与所述第二电压在所述选择存储单元上产生的电压降的值大于所述二维材料基选通器的开启电压的电压值，以对所述磁隧道结进行操作，所述操作包括读操作和写操作至少一个。
  15. 根据权利要求14所述的操作方法，其特征在于，进行写操作对应的电压降的值大于进行读操作对应的电压降的值。
  16. 一种如权利要求11-13中任一项所述的存储器阵列的操作方法，其特征在于，包括：
    定位至需要进行操作的选择存储单元；
    在所述需要进行操作的选择存储单元所在的字线上施加第一电压V 1，并在所述需要进行操作的选择存储单元所在的位线上施加第二电压V 2；
    在其余字线和其余位线施加零电压；
    其中，所述第一电压V 1和所述第二电压V 2在所述需要进行操作的选择存储单元上产生的电压降的值大于所述二维材料基选通器的开启电压V on的电压值，以对所述需要进行操作的选择存储器单元中的磁隧道结进行操作，所述操作包括写操作和读操作至少一个；所述第一电压的电压值和所述第二电压的电压值均小于等于V on/2，使得与所述需要进行操作的选择存储器单元处于同一字线或同一位线的其它选择存储单元的电压降满足：使得所述其它选择存储单元中的二维材料基选通器处于关断状态。
  17. 根据权利要求16所述的操作方法，其特征在于，进行写操作对应的电压降的值大于进行读操作对应的电压降的值。
PCT/CN2020/090618 2020-05-15 2020-05-15 二维材料基选通器、存储器单元、阵列及其操作方法 WO2021114571A1 (zh)

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CN105449099A (zh) * 2015-10-15 2016-03-30 上海磁宇信息科技有限公司 交叉矩阵列式磁性随机存储器及其读写方法
US20190214429A1 (en) * 2018-01-08 2019-07-11 Spin Transfer Technologies, Inc. Devices including magnetic tunnel junctions integrated with selectors
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CN110676288A (zh) * 2019-10-21 2020-01-10 上海磁宇信息科技有限公司 磁性隧道结结构及磁性随机存储器

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