WO2021057179A1 - 存储器、存储器的写入方法和读取方法 - Google Patents

存储器、存储器的写入方法和读取方法 Download PDF

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Publication number
WO2021057179A1
WO2021057179A1 PCT/CN2020/100912 CN2020100912W WO2021057179A1 WO 2021057179 A1 WO2021057179 A1 WO 2021057179A1 CN 2020100912 W CN2020100912 W CN 2020100912W WO 2021057179 A1 WO2021057179 A1 WO 2021057179A1
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memory
bit line
line
writing
bit
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PCT/CN2020/100912
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English (en)
French (fr)
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殷标
孟皓
迟克群
李州
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浙江驰拓科技有限公司
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/18—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using Hall-effect devices

Definitions

  • the present application relates to the field of memory, and in particular to a memory, a writing method and a reading method of the memory.
  • SOT-MRAM Spin-Orbit Torque Magnetic Random Access Memory
  • STT Spin-Transfer Torque Magnetic Random Access Memory
  • SOT-MRAM is based on the spin Hall effect. Spin currents of different polarization directions accumulate on the opposite edges of the SOT-MRAM heavy metal layer and are written into the magnetic tunnel junctions (MTJ).
  • MTJ magnetic tunnel junctions
  • FIG. 1 shows a schematic diagram of the structure of a SOT-MRAM in the related technology, as shown in Figure 1, 01: free layer, 02: Tunneling layer, 03: Reference layer, 04: Source line, 05: Read word line, 06: Write word line, 07: Spin orbit moment providing layer, 08: Bit line, where MTJ consists of 01, 02 and 03 constitute.
  • the memory cell has a three-terminal structure, which requires two transistors, and the memory cell has a large area, which limits the improvement of integration.
  • two MTJs in SOT-MRAM are vertically stacked (in series), and their resistance values cannot be read independently; in some SOT-MRAM, two MTJs connected in parallel cannot be written independently, and there are errors in writing. phenomenon.
  • the SOT-MRAM has the problems that the memory cell area is large, the integration level is low, and the SOT-MRAM memory cell cannot realize independent reading and writing.
  • the embodiments of the present application provide a memory, a writing method and a reading method of the memory, so as to at least solve the technical problems of large storage unit area and low integration of the memory in the related art, and independent reading and writing cannot be realized.
  • a memory includes a spin orbit moment providing layer, two storage bits, two diodes, a first bit line, a second bit line, a word line, a source Line and transistor, wherein one end of the spin orbit moment providing layer is connected to the first bit line, the other end of the spin orbit moment providing layer is connected to the transistor, and the transistor is connected to the word line respectively Connected to the source line, two of the storage bits are arranged on the surface of the spin orbit moment providing layer at intervals, and one end of the storage bit away from the spin orbit moment providing layer is connected to the diode
  • the first ends of the diodes are connected in series in a one-to-one correspondence, and the electrodes corresponding to the first ends of the diodes connected to the two storage bits are different in positive and negative polarity, and the second ends of the diodes are respectively connected to the second bit line.
  • the spin-orbit moment providing layer is a heavy metal layer.
  • the storage bit is MTJ.
  • the MTJ includes a free layer, and the thickness of the free layer is 0.5 to 1.5 nm.
  • the MTJ includes a tunneling layer, and the thickness of the tunneling layer is 1.0 to 10 nm.
  • a method for writing the memory as described in any one of the above includes: between the first bit line and the source line of the memory and/ Or a write voltage is applied between the second bit line and the source line of the memory to write at least one storage bit of the memory.
  • applying a write voltage between at least one bit line of the memory and a source line to write at least one storage bit of the memory includes: applying a first bit line to the source line and the first bit line. A write voltage keeps the second bit line in a floating state.
  • applying a write voltage between at least one bit line of the memory and a source line to write at least one storage bit of the memory includes: applying a first bit line to the source line and the first bit line. A write voltage, a second write voltage is applied to the source line and the second bit line.
  • the first writing voltage and/or the second writing voltage include a first direction and a second direction, wherein the first direction and the second direction are opposite in direction.
  • the reading method includes: applying a read between the second bit line and the source line of the memory. Voltage to read at least one storage bit of the memory.
  • applying a read voltage between the second bit line and the source line of the memory to read at least one memory bit of the memory includes: the read voltage includes a first direction and a second direction, wherein , The directions of the first direction and the second direction are opposite.
  • the memory includes a spin-orbital moment providing layer, two storage bits, two diodes, a first bit line, a second bit line, a word line, a source line, and a transistor, wherein the spin One end of the orbital moment providing layer is connected to the first bit line, the other end of the spin orbital moment providing layer is connected to the transistor, and the transistor is respectively connected to the word line and the source line, and the two
  • the storage bits are arranged on the surface of the spin orbit moment providing layer at intervals, and one end of the storage bits away from the spin orbit moment providing layer is connected in series with the first end of the diode in a one-to-one correspondence,
  • the positive and negative electrodes corresponding to the first ends of the diodes connected to the two storage bits are different, and the second ends of the diodes are respectively connected to the second bit line.
  • the memory includes two storage bits, the storage density can be improved, and the two storage bits share the spin orbit moment providing layer, bit line, word line, etc., which can improve the integration of the memory; in addition, the diode can be stacked vertically
  • the storage bit does not increase the area of the storage unit.
  • each of the two storage bits connected in parallel in the memory of the present application can realize independent reading and writing, thereby solving the storage unit of the memory in the related art.
  • Figure 1 shows a schematic structural diagram of a SOT-MRAM in the related art
  • FIG. 2 shows a schematic structural diagram of a memory according to an embodiment of the present application
  • FIG. 3 shows a schematic structural diagram of a memory of a preferred embodiment of the present application
  • Fig. 4(a) shows a schematic diagram of a first writing method of a memory in a preferred embodiment of the present application
  • FIG. 4(b) shows a schematic diagram of the state of the first writing method of the memory of the preferred embodiment of the present application
  • Fig. 5(a) shows a schematic diagram of a second writing method of a memory in a preferred embodiment of the present application
  • FIG. 5(b) shows a schematic diagram of the state of the second writing method of the memory of the preferred embodiment of the present application
  • Fig. 6(a) shows a schematic diagram of a third writing method of the memory of the preferred embodiment of the present application
  • FIG. 6(b) shows a schematic diagram of the state of the third writing method of the memory of the preferred embodiment of the present application
  • Fig. 7(a) shows a schematic diagram of a fourth writing method of the memory of the preferred embodiment of the present application
  • FIG. 7(b) shows a schematic diagram of the state of the fourth writing method of the memory of the preferred embodiment of the present application.
  • FIG. 8(a) shows a schematic diagram of a fifth writing method of a memory in a preferred embodiment of the present application
  • FIG. 8(b) shows a schematic diagram of the state of the fifth writing method of the memory of the preferred embodiment of the present application.
  • Fig. 9(a) shows a schematic diagram of a sixth writing method of the memory of the preferred embodiment of the present application.
  • FIG. 9(b) shows a schematic diagram of the state of the sixth writing method of the memory of the preferred embodiment of the present application.
  • Fig. 10(a) shows a schematic diagram of a seventh method for writing to a memory in a preferred embodiment of the present application
  • FIG. 10(b) shows a state schematic diagram of the seventh writing method of the memory of the preferred embodiment of the present application.
  • FIG. 11(a) shows a schematic diagram of an eighth writing method of a memory in a preferred embodiment of the present application
  • FIG. 11(b) shows a schematic diagram of the state of the eighth writing method of the memory of the preferred embodiment of the present application.
  • Fig. 12(a) shows a schematic diagram of a ninth writing method of the memory of the preferred embodiment of the present application
  • Figure 12(b) shows a schematic diagram of the state of the ninth writing method of the memory of the preferred embodiment of the present application
  • FIG. 13 shows a schematic diagram of the first reading method of the memory of the preferred embodiment of the present application.
  • Fig. 14 shows a schematic diagram of a second reading method of a memory in a preferred embodiment of the present application.
  • this application proposes a memory, a writing method and a reading method for the memory. ⁇ Take the method.
  • FIG. 2 shows a schematic structural diagram of the memory of an embodiment of the present application.
  • the memory includes a spin orbit moment providing layer 10, two Two storage bits 20, two diodes 30, a first bit line 40, a second bit line 50, a word line 60, a source line 70 and a transistor 80, wherein one end of the spin orbit moment providing layer 10 is connected to the first bit line 40 is connected, the other end of the spin orbit moment providing layer is connected to the transistor 80, and the transistor 80 is respectively connected to the word line 60 and the source line 70, and two storage bits 20 are arranged on the surface of the spin orbit moment providing layer 10 at intervals
  • the end of the storage bit 20 away from the spin-orbit moment providing layer is connected in series with the first end of the diode 30 in a one-to-one correspondence, and the polarity of the electrode corresponding to the first end of the diode 30 connected to the two storage bits 20 is different.
  • the two storage bits can be realized.
  • the elements are connected in parallel on the surface of the spin-orbit moment providing layer. Further, the two parallel storage bits can be independently read and written.
  • the independent reading and writing of this application does not mean that two parallel storage bits can be read or written at the same time, but each of the two parallel storage bits can be read or written.
  • the two storage bits included in the memory in this application are storage bit A and storage bit B.
  • the reading or writing of storage bit A can be implemented separately, or the storage bit can be implemented separately.
  • Bit B is read or written.
  • the above-mentioned transistor is a triode, which is respectively connected to the source line, the spin-orbit moment providing layer and the word line, wherein the transistor acts as a control switch and can be turned on or off by the function of the word line. It should be noted that when the word line turns on the transistor, the storage bits of the memory can be independently read and written.
  • the memory includes two storage bits, the storage density can be improved, and the two storage bits share the spin orbit moment providing layer, bit line, word line, etc., which can improve the integration of the memory; in addition, the diode can be stacked vertically
  • the storage bit does not increase the area of the storage unit.
  • each of the two storage bits connected in parallel in the memory of the present application can realize independent reading and writing, thereby solving the storage unit of the memory in the related art.
  • the spin-orbit moment providing layer is a heavy metal layer.
  • the spin-orbit moment providing layer is a heavy metal layer, and its material can be selected from at least one of non-magnetic heavy metal materials, topological insulator materials, and antiferromagnetic conductor materials.
  • the above-mentioned non-magnetic heavy metal material includes at least one of Pt, Ta, W, Ir, Hf, Ru, Ti, Bi, Au, and Os
  • the above-mentioned topological insulator material includes at least two of Bi, Te, and Se.
  • the above-mentioned antiferromagnetic conductor material includes an alloy formed of at least two of Pt, Mn, and Ir.
  • the topological insulator material or the antiferromagnetic conductor material may include multiple alloys.
  • the material of the spin-orbit moment providing layer is a topological insulator material. These materials can not only better ensure that the magnetization direction of the free layer is a predetermined direction, but also achieve ultra-low write current density and reduce the energy consumption of the memory cell.
  • the storage bit is MTJ.
  • the storage bit is MTJ
  • the memory includes two MTJs connected in parallel, and each MTJ is connected in series with a diode, and two MTJs are connected in series.
  • the directions of the diodes corresponding to the parallel MTJs are opposite.
  • two parallel MTJs share switches, heavy metal layers and bit lines, etc., which can improve the integration of the memory.
  • independent reading and writing of two parallel MTJs can be realized.
  • the MTJ includes a free layer, and the thickness of the free layer is 0.5 to 1.5 nm.
  • the MTJ includes a tunneling layer, and the thickness of the tunneling layer is 1.0 to 10 nm.
  • the MTJ of the present application also includes a pinned layer, wherein the magnetization direction of the pinned layer remains unchanged.
  • the magnetization directions of the pinned layers of the two MTJs are opposite, for example, the first MTJ
  • the magnetization direction of the pinned layer is up
  • the magnetization direction of the pinned layer of the second MTJ is down.
  • the magnetization direction is not limited to up or down, but can also be left or right, front or back, etc., which will not be repeated here.
  • the MTJ includes a first MTJ and a second MTJ, wherein the switching current threshold of the first MTJ is greater than the switching current threshold of the second MTJ, and the switching voltage of the first MTJ is greater than the switching voltage of the second MTJ.
  • the magnetization direction of the free layer of one of the MTJs may be changed. It should be noted that in this application, only when the applied voltage or current is sufficient to cause the magnetization direction of the free layer of the MTJ to change, can the write state of the MTJ change.
  • the change of the magnetization direction of the free layer is also related to the magnetization direction of the free layer or the direction of electron flow.
  • the spintronic polarization direction of the free layer is consistent with the spintronic polarization direction corresponding to the applied voltage or current, the free layer does not change its magnetization direction under the action of the applied voltage or current.
  • a write voltage can be applied between the first bit line and the source line of the memory to realize the Write; a write voltage can be applied between the second bit line and the source line of the memory to realize the writing of the memory bit; it can also be between the first bit line and the source line of the memory and the second bit line of the memory Simultaneously apply a writing voltage between the source line and the source line to realize the writing of the storage bit.
  • the memory in the embodiment of the present application may have two storage bits.
  • the two storage bits may be two MTJs.
  • applying a write voltage between at least one bit line of the memory and a source line to write at least one memory bit of the memory includes: applying a first write voltage to the source line and the first bit line, and maintaining the first write voltage.
  • the two-bit line is in a floating state.
  • the present application may apply a first write voltage to the source line and the first bit line to implement writing to at least one storage bit of the memory.
  • the memory includes two MTJs.
  • the first write voltage By applying the first write voltage, the memory can be written from 00 to 10, from 10 to 11, from 11 to 01, from 01 to 00, from 00 to 01, and from 11 is written as 10, and any one of the above writing methods can be freely implemented in specific implementation. It should be noted that during the above-mentioned writing operation, one of the MTJs performs writing, and the other MTJ remains unchanged.
  • applying a write voltage between at least one bit line of the memory and a source line to write at least one memory bit of the memory includes: applying a first write voltage to the source line and the first bit line, and applying a first write voltage to the source line and the first bit line.
  • the second write voltage is applied to the second bit line and the second bit line.
  • the present application can apply a first write voltage to the source line and the first bit line, and apply a second write voltage to the source line and the second bit line, so as to perform the operation on at least one storage bit of the memory.
  • Write It should be noted that the application of the first writing voltage and the second writing voltage are performed simultaneously.
  • the memory includes two MTJs. By applying the first write voltage and the second write voltage at the same time, the memory can be written from 01 to 11 and from 10 to 00.
  • the above writing methods can be freely implemented. Any kind. It should be noted that during the above-mentioned writing operation, one of the MTJs performs writing, and the other MTJ remains unchanged.
  • the first writing voltage and/or the second writing voltage include a first direction and a second direction, wherein the first direction and the second direction are opposite in direction.
  • the direction of the first write voltage is the direction of the voltage flowing between the source line and the first bit line, that is, the current direction between the source line and the first bit line, where the first write voltage
  • the source line can flow to the first bit line, or the first bit line can flow to the source line.
  • the above-mentioned flow direction can be divided into a first direction and a second direction. Further, the first direction and the second direction are opposite.
  • the direction of the second write voltage is the direction of the voltage flowing between the source line and the second bit line, that is, the current direction between the source line and the second bit line, where the second write voltage
  • the source line can flow to the second bit line, or the second bit line can flow to the source line.
  • the above-mentioned flow direction can be divided into a first direction and a second direction, and further, the first direction and the second direction are opposite.
  • different directions of the above-mentioned first write voltage and/or second write voltage can be implemented independently for each MTJ through different MTJs. It should be noted that, for the different directions of the first writing voltage and/or the second writing voltage, any one of the voltage flow directions or the combination of the two voltage flow directions can achieve different writing states.
  • the reading method includes: applying a read voltage between the second bit line and the source line of the memory, and At least one of the storage bits is read.
  • the first bit line is always in a floating state, that is, no power is applied to the first bit line.
  • a read voltage can be applied between the second bit line and the source line of the memory. Due to the different directions of the diodes, it is possible to read the memory bits in which the diode is turned on.
  • the memory in this application includes but is not limited to two storage bits.
  • the memory has two storage bits. In related technologies, only these two storage bits can be implemented. While reading the bits at the same time, in this application, independent reading of any storage bit can be realized.
  • applying a read voltage between the second bit line and the source line of the memory to read at least one memory bit of the memory includes: the read voltage includes a first direction and a second direction, wherein the first direction The direction is opposite to the second direction.
  • the direction of the read voltage is the direction of the voltage flowing between the second bit line and the source line, that is, the direction of the current between the second bit line and the source line, where the read voltage can be changed from the second bit line to the source line.
  • the flow of the bit line to the source line may also flow from the source line to the second bit line.
  • the above-mentioned flow direction may be divided into a first direction and a second direction. Further, the first direction and the second direction are opposite.
  • the memory includes two storage bits as two MTJs, where the first direction of the read voltage is from the source line to the second bit line. At this time, the read voltage passes through the first MTJ. Read the first MTJ; the second direction of the read voltage is to flow from the second bit line to the source line. At this time, when the read voltage passes through the second MTJ, the second MTJ can be read; it can be seen that, Different MTJs in different directions of the reading voltage can realize independent reading of each MTJ.
  • the gate transistor can be used to open the channel by applying a voltage to the word line, where the transistor is in a conducting state when the memory is read or written.
  • the memory includes a spin orbit moment providing layer 10, two storage bits 20, two diodes 30, a first bit line 40, a second bit line 50, a word line 60, and a source line 70. And a transistor 80.
  • Two MTJs are arranged on the surface of the spin-orbit moment providing layer 10 of the memory at intervals.
  • the MTJ includes at least a free layer 21, a tunneling layer 22 and a pinned layer 23 stacked in sequence.
  • the free layer 21 is in contact with the spin
  • the orbital moment providing layer 10 is provided on the surface, the fixed layer 23 is provided away from the surface of the spin orbital moment providing layer 10, and the tunneling layer 22 is provided between the free layer 21 and the fixed layer 23. Wherein, the magnetization direction of the fixed layer 23 remains unchanged, and the magnetization direction of the free layer 21 can be changed.
  • the magnetization direction of the pinned layer of the first MTJ is a small circle (dot)
  • the magnetization direction of the pinned layer of the second MTJ is a small circle (cross)
  • the magnetization directions of the free layer of the first MTJ and the second MTJ can both include Either small circle (dot) or small circle (cross).
  • the memory includes four states: 00, 01, 10, and 11, which involve a variety of mutual conversion methods. Among them, the left side is used to express the state of the first MTJ, and the right side is used to State the status of the second MTJ.
  • the upper circle is used to express the magnetization direction of the corresponding MTJ fixed layer, and the lower circle is used to express the corresponding MTJ free layer The direction of magnetization.
  • Figure 3 shows a schematic structural diagram of the memory of the preferred embodiment of the present application.
  • the heavy metal layer is connected to a bit line, and the upper side is two parallel MTJs.
  • the MTJ structure is free from bottom to top.
  • Two MTJ cells are connected in series with a diode respectively, and the directions of the two diodes are opposite and connected to the same bit line.
  • the switching current threshold of the first MTJ is greater than the switching current threshold of the second MTJ.
  • the SOT switching voltages of the first MTJ and the second MTJ are V w0 and V w1 , respectively, where V w0 >V w1 .
  • the memory includes two MTJs connected in parallel; the memory also includes two diodes, which are respectively connected in series with the two MTJs.
  • the spin transfer torque assisted writing method two MTJs can be written independently and two parallel MTJs can also be read independently.
  • the above-mentioned two parallel MTJs share transistors, heavy metal layers and bit lines, etc., which improves integration.
  • the material of the free layer of the MTJ is a ferromagnetic material with perpendicular anisotropy, which may be a single-layer structure or a multilayer composite structure.
  • the free layer material of the single-layer structure can be iron (Fe), cobalt (Co), nickel (Ni), gadolinium (Gd), terbium (Tb), dysprosium (Dy), boron (B) or alloys of these elements, such as CoFeB, NiFe, FeB, etc.
  • the material of the multilayer composite structure may be a composite layer structure composed of elements such as cobalt (Co) platinum (Pt), cobalt (Co) nickel (Ni), cobalt (Co) palladium (Pd) and the like.
  • the thickness dimension of the free layer of the aforementioned MTJ may be 0.5 nm-1.5 nm.
  • the tunneling layer of the MTJ is an insulating material with magnetic tunneling conditions at a specific thickness, and these insulating materials can be magnesium oxide, aluminum oxide, magnesium, or a combination of the three.
  • the thickness of the tunnel layer of the MTJ can be 1.0 nm-10 nm.
  • the fixing layer of the above-mentioned MTJ may be a single layer or a composite multi-layer structure.
  • the fixed layer of the single-layer structure can be realized by ferromagnetic materials such as iron (Fe), cobalt (Co), nickel (Ni), or an alloy of these elements.
  • the fixed layer of the multilayer composite structure can be a composite layer structure of ferromagnetic materials and metal materials, such as cobalt (Co) platinum (Pt), cobalt (Co) nickel (Ni), cobalt (Co) palladium (Pd), etc.
  • two parallel MTJs can be used for independent writing and independent reading.
  • the writing method and the reading method are respectively described in detail below, which are specifically as follows:
  • Figure 4(a) shows a schematic diagram of the first writing method of the memory of the preferred embodiment of the present application
  • Figure 4(b) shows the first writing method of the memory of the preferred embodiment of the present application Schematic diagram of the state of the input method; as shown in Figures 4(a) and 4(b), the first writing method of the memory is: 00 ⁇ 10; among them, WL:V, the first bit line: V w0 , the first Two-bit line: floating.
  • Figure 5(a) shows a schematic diagram of the second writing method of the memory of the preferred embodiment of the present application
  • Figure 5(b) shows the second writing method of the memory of the preferred embodiment of the present application Schematic diagram of the state of the input method; as shown in Figures 5(a) and 5(b), the second writing method of the memory is: 10 ⁇ 11; among them, the word line: V, the first bit line: -V w1 , The second line: floating.
  • FIG. 6(a) shows a schematic diagram of a third writing method of the memory of the preferred embodiment of the present application
  • FIG. 6(b) shows the third writing method of the memory of the preferred embodiment of the present application
  • the state diagram of the input method; as shown in Figure 6(a) and 6(b), the third writing method of the memory is: 11 ⁇ 01; among them, the word line: V, the first bit line: -V w0 , The second line: floating.
  • FIG. 7(a) shows a schematic diagram of a fourth writing method of the memory of the preferred embodiment of the present application
  • FIG. 7(b) shows the fourth writing method of the memory of the preferred embodiment of the present application
  • the state diagram of the input method; as shown in Figure 7(a) and 7(b), the fourth writing method of the memory is: 01 ⁇ 00; among them, the word line: V, the first bit line: V w1 , The second line: floating.
  • Figure 8(a) shows a schematic diagram of a fifth writing method of the memory of the preferred embodiment of the present application
  • Figure 8(b) shows the fifth writing method of the memory of the preferred embodiment of the present application
  • the state diagram of the input method; as shown in Figure 8(a) and 8(b), the fifth writing method of the memory is: 00 ⁇ 01; among them, the word line: V, the first bit line: -V w1 , The second line: floating.
  • Figure 9(a) shows a schematic diagram of a sixth writing method of the memory of the preferred embodiment of the present application
  • Figure 9(b) shows the sixth writing method of the memory of the preferred embodiment of the present application
  • the state diagram of the input method; as shown in Figures 9(a) and 9(b), the sixth writing method of the memory is: 11 ⁇ 10; among them, the word line: V, the first bit line: V w1 , The second line: floating.
  • Figure 10 (a) shows a schematic diagram of the seventh writing method of the memory of the preferred embodiment of the present application
  • Figure 10 (b) shows the seventh writing method of the memory of the preferred embodiment of the present application
  • the state diagram of the input method; as shown in Figures 10(a) and 10(b), the seventh writing method of the memory is: 10 ⁇ 00; among them, the word line: V, the first bit line: -V w10 , The second line: -V 10 . Note: V w10 ⁇ V w1 ⁇ V w0 .
  • Figure 11 (a) shows a schematic diagram of the eighth writing method of the memory of the preferred embodiment of the present application
  • Figure 11 (b) shows the eighth writing method of the memory of the preferred embodiment of the present application
  • the state diagram of the input method; as shown in Figures 11(a) and 11(b), the eighth writing method of the memory is: 10 ⁇ 01; among them, the word line: V, the first bit line: -V w0 , The second line: floating.
  • Figure 12 (a) shows a schematic diagram of a ninth writing method of the memory of the preferred embodiment of the present application
  • Figure 12 (b) shows the ninth writing method of the memory of the preferred embodiment of the present application
  • the state diagram of the input method; as shown in Figure 12(a) and 12(b), the ninth writing method of the memory is: 01 ⁇ 10; among them, the word line: V, the first bit line: V w0 , The second line: floating.
  • FIG. 13 shows a schematic diagram of the first reading method of the memory according to the preferred embodiment of the present application.
  • the first reading method of the memory is: reading the first MTJ; Line: V, first bit line: floating, second bit line: -V r .
  • FIG. 14 shows a schematic diagram of the second reading method of the memory of the preferred embodiment of the present application.
  • the second reading method of the memory is: reading the second MTJ; Line: V, first bit line: floating, second bit line: V r .
  • the memory of the present application can achieve the following effects:
  • the memory contains two MTJs, which improves the storage density
  • the two MTJs in the memory share heavy metal layers, bit lines, transistors, etc., which is beneficial to improve integration;
  • the diode of the memory can be stacked vertically on the MTJ without increasing the area of the memory cell;
  • Two parallel MTJs in the memory can be read and written independently.

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Abstract

一种存储器、存储器的写入方法和读取方法。其中，存储器包括自旋轨道矩提供层（10）、两个存储位元（20）、两个二极管（30）、第一位线（40）、第二位线（50）、字线（60）、源线（70）和晶体管（80），其中，自旋轨道矩提供层（10）的一端与第一位线（40）连接，自旋轨道矩提供层（10）的另一端与晶体管（80）连接，且晶体管（80）分别与字线（60）和源线（70）连接，两个存储位元（20）间隔地设置在自旋轨道矩提供层（10）的表面上，存储位元（20）远离自旋轨道矩提供层（10）的一端与二极管（30）的第一端一一对应地串联，与两个存储位元（20）连接的二极管（30）的第一端对应的电极正负不同，二极管（30）的第二端分别与第二位线（50）连接。可实现存储器的存储单元独立读写。

Description

存储器、存储器的写入方法和读取方法 技术领域
本申请涉及存储器领域，具体而言，涉及一种存储器、存储器的写入方法和读取方法。
背景技术
自旋-轨道力矩磁阻式随机存储器(Spin-Orbit Torque Magnetic Random Access Memory，简称为SOT-MRAM)，与自旋转移力矩磁阻式随机存储器(Spin-Transfer Torque Magnetic Random Access Memory，简称为STT-MRAM)是完全不同的。SOT-MRAM是基于自旋霍尔效应，不同的极化方向的自旋流在SOT-MRAM重金属层的相反边缘积聚，并向磁性隧道结(Magnetic Tunnel Junctions，简称为MTJ)中写入。SOT-MRAM具有低功耗、高性能的优点，在物联网、云计算和航空航天等方面具备广阔的市场前景。
而在相关技术中，SOT-MRAM还存在的各种各样的问题：例如，图1示出了相关技术中的一种SOT-MRAM的结构示意图，如图1所示，01：自由层，02：隧穿层，03：参考层，04：源线，05：读字线，06：写字线，07：自旋轨道矩提供层，08：位线，其中，MTJ由01、02和03构成。在SOT-MRAM中，其存储单元为三端结构，需要两个晶体管，存储单元面积较大，限制了集成度的提高。又例如，在SOT-MRAM中的两个MTJ垂直堆叠(串联)，其阻值不可以分别独立读取；还有一些SOT-MRAM中两个并联的MTJ不能实现分别独立写入，存在误写现象。
因此，在相关技术中，SOT-MRAM存在存储单元面积大、集成度低，以及SOT-MRAM存储单元不能实现独立读写的问题。
针对上述的问题，目前尚未提出有效的解决方案。
发明内容
本申请实施例提供了一种存储器、存储器的写入方法和读取方法，以至少解决相关技术中存储器的存储单元面积大、集成度低，且不能实现独立读写的技术问题。
根据本申请实施例的一个方面，提供了一种存储器，所述存储器包括自旋轨道矩提供层、两个存储位元、两个二极管、第一位线、第二位线、字线、源线和晶体管， 其中，所述自旋轨道矩提供层的一端与第一位线连接，所述自旋轨道矩提供层的另一端与所述晶体管连接，且所述晶体管分别与所述字线和所述源线连接，两个所述存储位元间隔地设置在所述自旋轨道矩提供层的表面上，所述存储位元远离所述自旋轨道矩提供层的一端与所述二极管的第一端一一对应地串联，与两个所述存储位元连接的所述二极管的第一端对应的电极正负不同，所述二极管的第二端分别与第二位线连接。
可选地，所述自旋轨道矩提供层为重金属层。
可选地，所述存储位元为MTJ。
可选地，所述MTJ包括自由层，所述自由层的厚度为0.5至1.5nm。
可选地，所述MTJ包括隧穿层，所述隧穿层的厚度为1.0至10nm。
根据本申请实施例的另一方面，还提供了一种上述中任意一项所述的存储器的写入方法，所述写入方法包括：在存储器的第一位线和源线之间和/或在存储器的第二位线和源线之间施加写电压，对所述存储器的至少一个存储位元进行写入。
可选地，在存储器的至少一个位线和源线之间施加写电压，对所述存储器的至少一个存储位元进行写入，包括：在所述源线和所述第一位线施加第一写电压，保持所述第二位线处于浮空状态。
可选地，在存储器的至少一个位线和源线之间施加写电压，对所述存储器的至少一个存储位元进行写入，包括：在所述源线和所述第一位线施加第一写电压，在所述源线和所述第二位线施加第二写电压。
可选地，所述第一写电压和/或第二写电压包括第一方向和第二方向，其中，所述第一方向和所述第二方向的方向相反。
根据本申请实施例的另一方面，还提供了一种上述中任意一项所述的存储器的读取方法，所述读取方法包括：在存储器的第二位线和源线之间施加读电压，对所述存储器的至少一个存储位元进行读取。
可选地，在存储器的第二位线和源线之间施加读电压，对所述存储器的至少一个存储位元进行读取，包括：所述读电压包括第一方向和第二方向，其中，所述第一方向和所述第二方向的方向相反。
在本申请实施例中，存储器包括自旋轨道矩提供层、两个存储位元、两个二极管、第一位线、第二位线、字线、源线和晶体管，其中，所述自旋轨道矩提供层的一端与第一位线连接，所述自旋轨道矩提供层的另一端与所述晶体管连接，且所述晶体管分 别与所述字线和所述源线连接，两个所述存储位元间隔地设置在所述自旋轨道矩提供层的表面上，所述存储位元远离所述自旋轨道矩提供层的一端与所述二极管的第一端一一对应地串联，与两个所述存储位元连接的所述二极管的第一端对应的电极正负不同，所述二极管的第二端分别与第二位线连接。由于该存储器包括两个存储位元，可以提高存储密度，且两个存储位元共享自旋轨道矩提供层、位线、字线等，可以提高存储器的集成度；另外，二极管可以垂直堆叠在存储位元，没有增加存储单元的面积，进一步地，本申请的存储器中并联的两个存储位元中每一个存储位元均可以实现独立的读写，进而解决了相关技术中存储器的存储单元面积大、集成度低，且不能实现独立读写的技术问题。
附图说明
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1示出了相关技术中的一种SOT-MRAM的结构示意图；
图2示出了本申请实施例的存储器的结构示意图；
图3示出了本申请的优选的实施例的存储器的结构示意图；
图4(a)示出了本申请的优选的实施例的存储器的第一种写入方法的示意图；
图4(b)示出了本申请的优选的实施例的存储器的第一种写入方法的状态示意图；
图5(a)示出了本申请的优选的实施例的存储器的第二种写入方法的示意图；
图5(b)示出了本申请的优选的实施例的存储器的第二种写入方法的状态示意图；
图6(a)示出了本申请的优选的实施例的存储器的第三种写入方法的示意图；
图6(b)示出了本申请的优选的实施例的存储器的第三种写入方法的状态示意图；
图7(a)示出了本申请的优选的实施例的存储器的第四种写入方法的示意图；
图7(b)示出了本申请的优选的实施例的存储器的第四种写入方法的状态示意图；
图8(a)示出了本申请的优选的实施例的存储器的第五种写入方法的示意图；
图8(b)示出了本申请的优选的实施例的存储器的第五种写入方法的状态示意图；
图9(a)示出了本申请的优选的实施例的存储器的第六种写入方法的示意图；
图9(b)示出了本申请的优选的实施例的存储器的第六种写入方法的状态示意图；
图10(a)示出了本申请的优选的实施例的存储器的第七种写入方法的示意图；
图10(b)示出了本申请的优选的实施例的存储器的第七种写入方法的状态示意图；
图11(a)示出了本申请的优选的实施例的存储器的第八种写入方法的示意图；
图11(b)示出了本申请的优选的实施例的存储器的第八种写入方法的状态示意图；
图12(a)示出了本申请的优选的实施例的存储器的第九种写入方法的示意图；
图12(b)示出了本申请的优选的实施例的存储器的第九种写入方法的状态示意图；
图13示出了本申请的优选的实施例的存储器的第一种读取方法的示意图；
图14示出了本申请的优选的实施例的存储器的第二种读取方法的示意图。
具体实施方式
应该指出，以下详细说明都是例示性的，旨在对本申请提供进一步的说明。除非另有指明，本文使用的所有技术和科学术语具有与本申请所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本申请的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用术语“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
应该理解的是，当元件(诸如层、膜、区域、或衬底)描述为在另一元件“上”时，该元件可直接在该另一元件上，或者也可存在中间元件。而且，在说明书以及权利要求书中，当描述有元件“连接”至另一元件时，该元件可“直接连接”至该另一元件，或者通过第三元件“连接”至该另一元件。
正如背景技术所介绍的，相关技术中存储器的存储单元面积大、集成度低，且不能实现独立读写，为了解决如上的技术问题，本申请提出了一种存储器、存储器的写入方法与读取方法。
本申请的一种典型的实施方式中，提供了一种存储器，图2示出了本申请实施例 的存储器的结构示意图，如图2所示，该存储器包括自旋轨道矩提供层10、两个存储位元20、两个二极管30、第一位线40、第二位线50、字线60、源线70和晶体管80，其中，自旋轨道矩提供层10的一端与第一位线40连接，自旋轨道矩提供层的另一端与晶体管80连接，且晶体管80分别与字线60和源线70连接，两个存储位元20间隔地设置在自旋轨道矩提供层10的表面上，存储位元20远离自旋轨道矩提供层的一端与二极管30的第一端一一对应地串联，与两个存储位元20连接的二极管30的第一端对应的电极正负不同，二极管30的第二端分别与第二位线50连接。
作为一种可选的实施方式，由于两个存储位元间隔地设置在自旋轨道矩提供层的表面上，当两个存储位元为两个存储位元时，可以实现这两个存储位元在自旋轨道矩提供层的表面上并联，进一步地，两个并联的存储位元，分别可以进行独立的读写。
需要说明的是，本申请的独立的读写，并不是两个并联的存储位元同时进行读取或者写入，而是两个并联的存储位元中每个存储位元可以实现读取或者写入。例如，本申请中存储器包括的两个存储位元为存储位元A和存储位元B，其中，可以单独的实现对存储位元A进行读取或者写入，还可以是单独的实现对存储位元B进行读取或者写入。
进一步地，上述晶体管为三极管，分别连接源线、自旋轨道矩提供层以及字线，其中，晶体管作为控制开关，可以通过字线的作用使其导通或者关闭。需要说明的是，在字线导通晶体管时，可以实现存储器的存储位元分别进行独立读写。
由于该存储器包括两个存储位元，可以提高存储密度，且两个存储位元共享自旋轨道矩提供层、位线、字线等，可以提高存储器的集成度；另外，二极管可以垂直堆叠在存储位元，没有增加存储单元的面积，进一步地，本申请的存储器中并联的两个存储位元中每一个存储位元均可以实现独立的读写，进而解决了相关技术中存储器的存储单元面积大、集成度低，且不能实现独立读写的技术问题。
可选地，自旋轨道矩提供层为重金属层。
作为一种可选的实施方式，自旋轨道矩提供层为重金属层，其材料可以选自非磁性重金属材料、拓扑绝缘体材料与反铁磁导体材料中的至少一种。需要说明的是，上述非磁性重金属材料包括Pt、Ta、W、Ir、Hf、Ru、Ti、Bi、Au与Os中的至少一种，上述拓扑绝缘体材料包括Bi、Te与Se中的至少两种形成的合金，上述反铁磁导体材料包括Pt、Mn与Ir中的至少两种形成的合金。其中，拓扑绝缘体材料或者反铁磁导体材料中均可以包括多种合金。
上述自旋轨道矩提供层的材料为拓扑绝缘体材料，这些材料不仅可以更好地保证 自由层的磁化方向为预定方向，还能实现超低写电流密度，降低了存储单元的能耗。
可选地，存储位元为MTJ。
作为一种可选的实施方式，上述存储器包括两个存储位元，且存储位元为MTJ时，也即是该存储器包括两个并联的MTJ，且每个MTJ分别串联一个二极管，且两个并联的MTJ对应的二极管的方向相反，另外，两个并联的MTJ共享开关、重金属层和位线等，可以提高存储器的集成度。另外，可以实现对两个并联的MTJ分别进行独立的读取和写入。
可选地，MTJ包括自由层，自由层的厚度为0.5至1.5nm。
可选地，MTJ包括隧穿层，隧穿层的厚度为1.0至10nm。
需要说明的是，本申请的MTJ还包括固定层，其中，固定层的磁化方向保持不变，在本申请实施中，两个MTJ的固定层的磁化方向是相反的，例如，第一MTJ的固定层的磁化方向为上，则第二MTJ的固定层的磁化方向为下。在具体实施实施过程中，磁化方向并不仅限于上或者下，还可以是左或者右、前或者后等，在此不再一一赘述。
可选地，MTJ包括第一MTJ和第二MTJ，其中，第一MTJ的翻转电流阈值大于第二MTJ的翻转电流阈值，第一MTJ的翻转电压大于第二MTJ的翻转电压。
作为一种可选的实施方式，在施加的电压或者电流达到存储位元对应的翻转电压或者翻转电流阈值时，才可能使得其中一个MTJ的自由层的磁化方向发生改变。需要说明的是，在本申请中只有施加的电压或者电流足够使得MTJ的自由层的磁化方向发生改变，MTJ的写入状态才会发生改变。
需要说明的是，上述自由层的磁化方向发生改变，还与自由层的磁化方向或者电子流方向有关。例如，自由层的自旋电子极化方向与施加电压或者电流对应的自旋电子极化方向一致时，则自由层在施加电压或者电流的作用下其磁化方向不发生改变。
根据本申请实施例的另一方面，还提供了一种上述中任意一项的存储器的写入方法，写入方法包括：在存储器的第一位线和源线之间和/或在存储器的第二位线和源线之间施加写电压，对存储器的至少一个存储位元进行写入。
作为一个可选的实施方式，在对存储器的至少一个存储位元进行写入时，至少包括以下情形：可以在存储器的第一位线和源线之间施加写电压，实现对存储位元的写入；可以在存储器的第二位线和源线之间施加写电压，实现对存储位元的写入；还可以在存储器的第一位线和源线之间和存储器的第二位线和源线之间同时施加写电压，实现对存储位元的写入。
作为一个可选的实施方式，本申请实施例中的存储器可以为两个存储位元。优选的，两个存储位元可以为两个MTJ。
可选地，在存储器的至少一个位线和源线之间施加写电压，对存储器的至少一个存储位元进行写入，包括：在源线和第一位线施加第一写电压，保持第二位线处于浮空状态。
作为一个可选的实施方式，上述保持第二位线处于浮空状态，即对第二位线不施加电。
作为一个可选的实施方式，本申请可以在源线和第一位线施加第一写电压，实现对存储器的至少一个存储位元进行写入。例如，存储器包括两个MTJ，可以通过施加第一写电压，可以将存储器由00写为10，由10写为11，由11写为01，由01写为00，由00写为01，由11写为10，在具体实施中可以自由实现上述写入方式中的任意一种。需要说明的是，在进行上述写入操作时，其中一个MTJ进行写入，另一个MTJ保持不变。
可选地，在存储器的至少一个位线和源线之间施加写电压，对存储器的至少一个存储位元进行写入，包括：在源线和第一位线施加第一写电压，在源线和第二位线施加第二写电压。
作为一个可选的实施方式，本申请可以在源线和第一位线施加第一写电压，以及在源线和第二位线施加第二写电压，实现对存储器的至少一个存储位元进行写入。需要说明的是，施加第一写电压和第二写电压同时进行。例如，存储器包括两个MTJ，可以通过同时施加第一写电压和第二写电压，可以将存储器由01写为11，由10写为00，在具体实施中可以自由实现上述写入方式中的任意一种。需要说明的是，在进行上述写入操作时，其中一个MTJ进行写入，另一个MTJ保持不变。
可选地，第一写电压和/或第二写电压包括第一方向和第二方向，其中，第一方向和第二方向的方向相反。
作为一个优选的实施方式，上述第一写电压的方向为电压在源线和第一位线之间流向，也即是在源线和第一位线之间电流方向，其中，第一写电压可以由源线流向第一位线，也可以由第一位线流向源线，可以将上述的流向划分为第一方向和第二方向，进一步地，第一方向和第二方向的方向相反。
作为一个优选的实施方式，上述第二写电压的方向为电压在源线和第二位线之间流向，也即是在源线和第二位线之间电流方向，其中，第二写电压可以由源线流向第二位线，也可以由第二位线流向源线，可以将上述的流向划分为第一方向和第二方向， 进一步地，第一方向和第二方向的方向相反。
在具体实施过程中，上述第一写电压和/或第二写电压的不同方向经过不同的MTJ可以实现对每个MTJ进行独立的写入。需要说明的是，第一写电压和/或第二写电压的不同方向，其中任意一种电压流向或者两种电压流向的组合均可以实现不同的写入状态。
根据本申请实施例的另一方面，还提供了一种上述中任意一项的存储器的读取方法，读取方法包括：在存储器的第二位线和源线之间施加读电压，对存储器的至少一个存储位元进行读取。
需要说明的是，本申请的存储器在在进行读取时，其中的第一位线始终处于浮空状态，也即是，第一位线不施加电。此时，在存储器进行读取时，可以通过控制在存储器的第二位线和源线之间施加读电压，由于二极管的方向不同，可以实现对二极管导通的存储位元进行读取。
作为一个优选的实施方式，在本申请中存储器包括但不限于两个存储位元，在具体实施过程中，例如，存储器存在两个存储位元，在相关技术中，只能够实现这两个存储位元的同时读取，而在本申请中则可以实现任意一个存储位元的独立读取。
可选地，在存储器的第二位线和源线之间施加读电压，对存储器的至少一个存储位元进行读取，包括：读电压包括第一方向和第二方向，其中，第一方向和第二方向的方向相反。
作为一个优选的实施方式，上述读电压的方向为电压在第二位线和源线之间流向，也即是在第二位线和源线之间电流方向，其中，读电压可以由第二位线流向源线，也可以由源线流向第二位线，可以将上述的流向划分为第一方向和第二方向，进一步地，第一方向和第二方向的方向相反。
在具体实施过程中，例如，存储器包括两个存储位元为两个MTJ，其中，读电压的第一方向为由源线流向第二位线，此时该读电压经过第一MTJ，则可以实现对第一MTJ进行读取；读电压的第二方向为由第二位线流向源线，此时该读电压经过第二MTJ，则可以实现对第二MTJ进行读取；由此可见，读电压的不同方向经过不同的MTJ可以实现对每个MTJ进行独立的读取。
在本申请实施过程中，无论是存储器的读取还是写入，均是通过位线和源线之间的电压差实现的，这种电压差在存储器的读取时为读电压，在存储器的写入时为写电压。需要说明的是，可以通过对字线施加电压用于选通晶体管打开通道，其中，在存储器的读取或者写入时，晶体管处于导通状态。
下面对本申请优选的实施方式进行说明。
在本申请优选的实施例中，存储器包括自旋轨道矩提供层10、两个存储位元20、两个二极管30、第一位线40、第二位线50、字线60、源线70和晶体管80，该存储器的自旋轨道矩提供层10表面上间隔设置两个MTJ，其中，MTJ至少包括依次叠置的自由层21、隧穿层22和固定层23，自由层21接触自旋轨道矩提供层10表面设置，固定层23远离自旋轨道矩提供层10表面设置，隧穿层22设置在自由层21和固定层23之间。其中，固定层23的磁化方向保持不变，自由层21的磁化方向可以改变。
在下面的实施例所涉及的存储器的结构示意图中，针对MTJ来说，左侧的MTJ为第一MTJ，右侧的MTJ为第二MTJ，虚线箭头则是存储器的电流方向。需要说明的是，为了便于描述存储器的MTJ的磁化方向，在本申请中利用小圆圈(点)或者小圆圈(叉)用于表示两种不同的磁化方向。第一MTJ的固定层的磁化方向为小圆圈(点)，第二MTJ的固定层的磁化方向为小圆圈(叉)，而第一MTJ和第二MTJ的自由层的磁化方向均可以包括的小圆圈(点)或者小圆圈(叉)中的任意一个。
对于存储器的结构示意图对应的状态示意图，该存储器包括四种状态：00、01、10和11，涉及多种相互转化的方式，其中，左侧用于表述第一MTJ的状态，右侧用于表述第二MTJ的状态。对于任意一个MTJ而言，在该状态图中，对于每一种状态，其上面的小圆圈用于表述对应的MTJ的固定层的磁化方向，下面的小圆圈用于表述对应的MTJ的自由层的磁化方向。
图3示出了本申请的优选的实施例的存储器的结构示意图，如图3所示，重金属层与一根位线相连，上方为两个并联的MTJ，MTJ结构从下而上依次是自由层、隧穿层、固定层。两个MTJ单元分别与一个二极管串联，两个二极管的方向相反，连接着同一根位线。第一MTJ的翻转电流阈值大于第二MTJ的翻转电流阈值大。第一MTJ和第二MTJ的SOT翻转电压分别为V w0和V w1，其中V w0>V w1。
其中，该存储器包含两个相互并联的MTJ；该存储器还包含两个二极管，分别与两个MTJ串联。通过自旋转移力矩辅助写入方法，两个MTJ可以分别独立写入且两个并联的MTJ还可以分别独立读取。
其中，上述两个并联的MTJ共享晶体管、重金属层和位线等，提高了集成度。
进一步地，上述MTJ的自由层的材料为具有垂直各向异性的铁磁材料，可以是单层结构或是多层复合式结构。单层结构的自由层材料可以是铁(Fe)、钴(Co)、镍(Ni)、钆(Gd)、铽(Tb)、镝(Dy)、硼(B)或这些元素的合金，如CoFeB、NiFe、FeB等。多层复合结构的材料可以是钴(Co)铂(Pt)、钴(Co)镍(Ni)、钴(Co)钯(Pd)等元素组成的复 合层结构。
需要说明的是，上述MTJ的自由层的厚度尺寸可以为0.5nm-1.5nm。
进一步地，上述MTJ的隧穿层为特定厚度下具备磁隧穿条件的绝缘材料，这些绝缘材料可以为氧化镁、氧化铝、镁或三者的组合。
需要说明的是，上述MTJ的隧穿层厚度尺寸可以为1.0nm-10nm。
进一步地，上述MTJ的固定层可以是单层或复合式多层结构。其中，单层结构的固定层可通过例如铁(Fe)、钴(Co)、镍(Ni)等铁磁材料或这些元素的合金来实现。多层复合式结构的固定层则可为铁磁材料与金属材料的复合层结构，例如钴(Co)铂(Pt)、钴(Co)镍(Ni)、钴(Co)钯(Pd)等元素组成的复合层结构。
进一步地，基于上述存储器可以实现两个并联的MTJ进行独立写入和独立读取，下面分别对写入方法和读取方法进行详细的说明，具体如下：
图4(a)示出了本申请的优选的实施例的存储器的第一种写入方法的示意图，以及图4(b)示出了本申请的优选的实施例的存储器的第一种写入方法的状态示意图；如图4(a)和4(b)所示，该存储器的第一种写入方法为：00→10；其中，WL:V，第一位线:V w0，第二位线:floating。
图5(a)示出了本申请的优选的实施例的存储器的第二种写入方法的示意图，以及图5(b)示出了本申请的优选的实施例的存储器的第二种写入方法的状态示意图；如图5(a)和5(b)所示，该存储器的第二种写入方法为：10→11；其中，字线:V，第一位线:-V w1，第二位线:floating。
图6(a)示出了本申请的优选的实施例的存储器的第三种写入方法的示意图，以及图6(b)示出了本申请的优选的实施例的存储器的第三种写入方法的状态示意图；如图6(a)和6(b)所示，该存储器的第三种写入方法为：11→01；其中，字线:V，第一位线:-V w0，第二位线:floating。
图7(a)示出了本申请的优选的实施例的存储器的第四种写入方法的示意图，以及图7(b)示出了本申请的优选的实施例的存储器的第四种写入方法的状态示意图；如图7(a)和7(b)所示，该存储器的第四种写入方法为：01→00；其中，字线:V，第一位线:V w1，第二位线:floating。
图8(a)示出了本申请的优选的实施例的存储器的第五种写入方法的示意图，以及图8(b)示出了本申请的优选的实施例的存储器的第五种写入方法的状态示意图；如图8(a)和8(b)所示，该存储器的第五种写入方法为：00→01；其中，字线:V， 第一位线:-V w1，第二位线:floating。
图9(a)示出了本申请的优选的实施例的存储器的第六种写入方法的示意图，以及图9(b)示出了本申请的优选的实施例的存储器的第六种写入方法的状态示意图；如图9(a)和9(b)所示，该存储器的第六种写入方法为：11→10；其中，字线:V，第一位线:V w1，第二位线:floating。
图10(a)示出了本申请的优选的实施例的存储器的第七种写入方法的示意图，以及图10(b)示出了本申请的优选的实施例的存储器的第七种写入方法的状态示意图；如图10(a)和10(b)所示，该存储器的第七种写入方法为：10→00；其中，字线:V，第一位线:-V w10，第二位线:-V 10。注：V w10<V w1<V w0。
图11(a)示出了本申请的优选的实施例的存储器的第八种写入方法的示意图，以及图11(b)示出了本申请的优选的实施例的存储器的第八种写入方法的状态示意图；如图11(a)和11(b)所示，该存储器的第八种写入方法为：10→01；其中，字线:V，第一位线:-V w0，第二位线:floating。
图12(a)示出了本申请的优选的实施例的存储器的第九种写入方法的示意图，以及图12(b)示出了本申请的优选的实施例的存储器的第九种写入方法的状态示意图；如图12(a)和12(b)所示，该存储器的第九种写入方法为：01→10；其中，字线:V，第一位线:V w0，第二位线:floating。
图13示出了本申请的优选的实施例的存储器的第一种读取方法的示意图，如图13所示，该存储器的第一种读取方法为：读取第一MTJ；其中，字线:V，第一位线:floating，第二位线:-V r。
图14示出了本申请的优选的实施例的存储器的第二种读取方法的示意图，如图14所示，该存储器的第二种读取方法为：读取第二MTJ；其中，字线:V，第一位线:floating，第二位线:V r。
基于此，本申请的存储器可以实现以下效果：
1、该存储器含有两个MTJ，提高了存储密度；
2、该存储器中两个MTJ共享重金属层、位线、晶体管等，有利于提高集成度；
3、该存储器的二极管可以垂直堆叠在MTJ上，没有增加存储单元的面积；
4、该存储器中两个并联的MTJ可以分别实现独立读写。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技 术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种存储器，所述存储器包括自旋轨道矩提供层、两个存储位元、两个二极管、第一位线、第二位线、字线、源线和晶体管，其中，所述自旋轨道矩提供层的一端与第一位线连接，所述自旋轨道矩提供层的另一端与所述晶体管连接，且所述晶体管分别与所述字线和所述源线连接，两个所述存储位元间隔地设置在所述自旋轨道矩提供层的表面上，所述存储位元远离所述自旋轨道矩提供层的一端与所述二极管的第一端一一对应地串联，与两个所述存储位元连接的所述二极管的第一端对应的电极正负不同，所述二极管的第二端分别与第二位线连接。
  2. 根据权利要求1所述的存储器，其中，所述自旋轨道矩提供层为重金属层。
  3. 根据权利要求1所述的存储器，其中，所述存储位元为MTJ。
  4. 根据权利要求3所述的存储器，其中，所述MTJ包括隧穿层，所述隧穿层的厚度为1.0至10nm。
  5. 一种权利要求1至4中任意一项所述的存储器的写入方法，所述写入方法包括：
    在存储器的第一位线和源线之间和/或在存储器的第二位线和源线之间施加写电压，对所述存储器的至少一个存储位元进行写入。
  6. 根据权利要求5所述的写入方法，其中，在存储器的至少一个位线和源线之间施加写电压，对所述存储器的至少一个存储位元进行写入，包括：
    在所述源线和所述第一位线施加第一写电压，保持所述第二位线处于浮空状态。
  7. 根据权利要求6所述的写入方法，其中，在存储器的至少一个位线和源线之间施加写电压，对所述存储器的至少一个存储位元进行写入，包括：
    在所述源线和所述第一位线施加第一写电压，在所述源线和所述第二位线施加第二写电压。
  8. 根据权利要求6至7中任意一项所述的写入方法，其中，
    所述第一写电压和/或第二写电压包括第一方向和第二方向，其中，所述第一方向和所述第二方向的方向相反。
  9. 一种权利要求1至4中任意一项所述的存储器的读取方法，所述读取方法包括：
    在存储器的第二位线和源线之间施加读电压，对所述存储器的至少一个存储位元进行读取。
  10. 根据权利要求9所述的读取方法，其中，在存储器的第二位线和源线之间施加读电压，对所述存储器的至少一个存储位元进行读取，包括：
    所述读电压包括第一方向和第二方向，其中，所述第一方向和所述第二方向的方向相反。
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