WO2021253284A1 - 一种外延片、led芯片及显示屏 - Google Patents

一种外延片、led芯片及显示屏 Download PDF

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Publication number
WO2021253284A1
WO2021253284A1 PCT/CN2020/096587 CN2020096587W WO2021253284A1 WO 2021253284 A1 WO2021253284 A1 WO 2021253284A1 CN 2020096587 W CN2020096587 W CN 2020096587W WO 2021253284 A1 WO2021253284 A1 WO 2021253284A1
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Prior art keywords
layer
epitaxial wafer
light
improvement
lattice defect
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PCT/CN2020/096587
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English (en)
French (fr)
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颜玺轩
向朝
魏海标
丁见华
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华为技术有限公司
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Priority to CN202080100169.8A priority Critical patent/CN115443521A/zh
Priority to PCT/CN2020/096587 priority patent/WO2021253284A1/zh
Publication of WO2021253284A1 publication Critical patent/WO2021253284A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof

Definitions

  • This application relates to the field of semiconductor technology, in particular to an epitaxial wafer, an LED chip and a display screen.
  • LED display screens have advantages such as long life and high color stability, and are increasingly widely used.
  • the LED display screen usually includes a plurality of LED chips, and the LED chips are obtained by processing an epitaxial wafer.
  • the substrate is usually prepared first, and then the epitaxial wafer is grown on the substrate.
  • the material of the substrate is usually sapphire, and the material of the epitaxial wafer is usually gallium nitride (GaN). ).
  • GaN gallium nitride
  • the upper two layers are GaN lattices, and the lower two layers are sapphire lattices.
  • the lattice constant of GaN is relatively small, while that of sapphire
  • the lattice constant is relatively large, and there is a relatively large lattice constant mismatch between GaN and sapphire.
  • the upper three layers are GaN lattices, and the lower two layers are sapphire lattices. Because the lattice constants of GaN and sapphire do not match, the epitaxial wafer There will be lattice defects, which will affect the luminous efficiency of the LED chip, and further affect the display effect of the LED chip display.
  • the first method is to provide a buffer layer between the substrate and the epitaxial wafer.
  • the lattice constant of the buffer layer is between the lattice constant of the substrate and the epitaxial wafer, so as to alleviate the relationship between the substrate and the epitaxial wafer.
  • the lattice constants of the slices do not match.
  • the second method is to perform patterned sapphire substrate (PSS) on the sapphire substrate.
  • PSS patterned sapphire substrate
  • the defect density of the epitaxial wafer's lattice defects is above 1E8 ⁇ 1E9/cm 2
  • the defect density of the epitaxial wafer's lattice defects is still 1E18/cm 2 or more.
  • the embodiments of the present application disclose an epitaxial wafer, a light emitting diode, a display screen, and a preparation method thereof to reduce the epitaxial wafer.
  • the crystal lattice defect of the chip improves the luminous efficiency of the LED chip.
  • an embodiment of the present application discloses an epitaxial wafer, including:
  • the improvement layer is disposed above the substrate, and the improvement layer includes a solid part and at least one void part;
  • the first buffer layer, the first conductive layer, the light emitting layer, and the second conductive layer are sequentially disposed above the improvement layer, and the at least one gap portion faces the first buffer layer;
  • the light-emitting layer is all located in a region directly above the physical part of the improvement layer;
  • the lattice defect between the void portion of the improvement layer and the area in contact with the substrate includes a first lattice defect and a second lattice defect, and the first lattice defect extends along the growth direction of the epitaxial wafer.
  • a lattice defect, the second lattice defect is a lattice defect extending to both sides of the void portion;
  • the second crystal lattice defect is located in the first buffer layer, or the second crystal lattice defect is located in the first buffer layer and the first conductive layer.
  • the first crystal lattice defect and the second crystal lattice defect do not reach the light-emitting layer, and therefore do not affect the light-emitting recombination of electrons and holes in the light-emitting layer. Therefore, the light-emitting layer of the epitaxial wafer disclosed in the embodiments of the present application has fewer lattice defects, and correspondingly, the luminous efficiency of the epitaxial wafer is higher.
  • a gap layer is included between the physical part of the improvement layer and the substrate;
  • a gap layer is included between the improvement layer and the first buffer layer.
  • the physical part of the improvement layer when the physical part of the improvement layer is not in close contact with the substrate, or the improvement layer is not in close contact with the first buffer layer, the physical part of the improvement layer is not in close contact with the substrate. Generate lattice defects. Compared with the epitaxial wafer in the prior art, the epitaxial wafer disclosed in the embodiments of the present application has a smaller number of lattice defects, so that the luminous efficiency can be further improved.
  • An optional design also includes:
  • the first electrode layer and the second electrode layer are The first electrode layer and the second electrode layer;
  • the first electrode layer is disposed above the first conductive layer
  • the second electrode layer is disposed above the second conductive layer.
  • the first electrode layer is located in the area directly above the void portion and the solid portion of the improvement layer at the same time;
  • all of the first electrode layer is located in a region directly above the void portion of the improvement layer.
  • the width of the light-emitting layer The area that can be occupied by the cross-section is relatively large, and the area of the region that can be used to realize the light-emitting recombination of electrons and holes is increased accordingly, so that the area utilization rate of the epitaxial wafer can be improved, and further, the luminous efficiency of the epitaxial wafer can be improved.
  • the first electrode layer is located at most in a region directly above a gap portion of the improvement layer.
  • the first electrode layer is at most affected by the first lattice defect of one void portion.
  • At least one of the first conductive layers occupies the same first electrode layer.
  • An optional design also includes:
  • a sacrificial layer provided in the first buffer layer
  • the sacrificial layer is used to reduce damage to the epitaxial wafer during the peeling process.
  • the sacrificial layer can damage other structures in the epitaxial wafer, so as to protect other structures in the epitaxial wafer and improve the yield of LED chips.
  • An optional design also includes:
  • the insulating coating layer is a dielectric material
  • the insulating coating layer is located on the surface of the area where the target layer is not in contact with other layers, and the target layer is at least any of the first conductive layer, the light emitting layer, the second conductive layer, the first electrode layer, and the second electrode layer layer.
  • the insulating coating layer Through the insulating coating layer, defects on the surface of the epitaxial wafer can be repaired, the probability of electric leakage can be reduced, the safety of the epitaxial wafer can be improved, and the probability of light-emitting recombination of electron holes can be increased, thereby further improving the luminous efficiency of the epitaxial wafer.
  • the contact surface between the first buffer layer and the improvement layer is a concave-convex surface
  • the surface of the first buffer layer for contacting the improvement layer is convex.
  • the surface of the first buffer layer for contacting the improvement layer is convex, the light extraction efficiency and collimation of the epitaxial wafer can be improved.
  • the two or more void parts present a regular periodic arrangement, including a stripe arrangement, a mesh arrangement and/or a honeycomb arrangement.
  • the embodiments of the present application disclose an LED chip
  • the LED chip includes the epitaxial wafer described in the first aspect.
  • an embodiment of the present application discloses a display screen
  • the display screen includes the LED chip described in the second aspect.
  • an epitaxial wafer, an LED chip, and a display screen are disclosed.
  • the epitaxial wafer includes: an improvement layer, a first buffer layer, a first conductive layer, a light emitting layer, and a second conductive layer.
  • the improved layer includes a solid part and at least one void part, the at least one void part faces the first buffer layer, and the light-emitting layer is all located on the front side of the solid part of the improved layer.
  • the epitaxial wafer disclosed in the embodiment of the present application includes a first lattice defect and a second lattice defect generated between the void portion of the improvement layer and the region in contact with the substrate.
  • the first lattice defect extends along the growth direction of the epitaxial wafer
  • the second lattice defect is located in the first buffer layer
  • the second lattice defect is located in the first buffer layer and the The first conductive layer.
  • the first lattice defect extends along the growth direction of the epitaxial wafer, and the light-emitting layer is all located in the area directly above the physical part of the improvement layer, the first lattice defect does not reach the entire area.
  • the light-emitting layer correspondingly, the first lattice defect does not affect the light-emitting recombination of electrons and holes in the light-emitting layer.
  • the second crystal lattice defect is located in the first buffer layer, or the second crystal lattice defect is located in the first buffer layer and the first conductive layer, therefore, the second crystal lattice Defects will not reach the light-emitting layer.
  • the second lattice lattice defects will not affect the light-emitting recombination of electrons and holes in the light-emitting layer. Therefore, compared with the prior art, the light-emitting layer of the epitaxial wafer disclosed in the embodiments of the present application has fewer lattice defects, and correspondingly, the luminous efficiency of the epitaxial wafer is higher.
  • Figure 1(a) is a schematic diagram of the connection relationship between an epitaxial wafer and a substrate disclosed in the prior art
  • Figure 1(b) is a schematic diagram of the connection relationship between an epitaxial wafer and a substrate disclosed in the prior art
  • FIG. 2 is a schematic diagram of the structure of an epitaxial wafer disclosed in the prior art
  • FIG. 3 is a schematic diagram of the structure of an epitaxial wafer disclosed in an embodiment of the application.
  • FIG. 4 is a schematic diagram of a crystal lattice defect of an epitaxial wafer disclosed in an embodiment of the application;
  • Fig. 5 is a schematic structural diagram of another epitaxial wafer disclosed in an embodiment of the application.
  • Fig. 6 is a schematic structural diagram of another epitaxial wafer disclosed in an embodiment of the application.
  • Fig. 7 is a schematic structural diagram of another epitaxial wafer disclosed in an embodiment of the application.
  • FIG. 8 is a top view of an epitaxial wafer disclosed in an embodiment of the application.
  • Figure 9 (a) is a front view of an epitaxial wafer disclosed in an embodiment of the application.
  • Figure 9(b) is a top view of an epitaxial wafer disclosed in an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of another epitaxial wafer disclosed in an embodiment of the application.
  • Figure 11 (a) is a schematic diagram of the structure of an epitaxial wafer disclosed in an embodiment of the application.
  • Fig. 11(b) is a schematic diagram of a scene of an epitaxial wafer receiving laser irradiation disclosed in an embodiment of the application;
  • FIG. 11(c) is a schematic diagram of the structure of an epitaxial wafer separated from the substrate according to an embodiment of the application;
  • Fig. 12(a) is a schematic structural diagram of an epitaxial wafer disclosed in an embodiment of the application.
  • Fig. 12(b) is a schematic diagram of a scene of an epitaxial wafer receiving laser irradiation disclosed in an embodiment of the application;
  • Figure 12(c) is a schematic structural diagram of an epitaxial wafer separated from a substrate according to an embodiment of the application.
  • Fig. 13(a) is a schematic structural diagram of an epitaxial wafer disclosed in an embodiment of the application.
  • Fig. 13(b) is a schematic structural diagram of another epitaxial wafer disclosed in an embodiment of the application.
  • Figure 14 (a) is a top view of an improved layer in an epitaxial wafer disclosed in an embodiment of the application;
  • Figure 14(b) is a top view of an improved layer in another epitaxial wafer disclosed in an embodiment of the application.
  • Fig. 14(c) is a top view of an improved layer in another epitaxial wafer disclosed in an embodiment of the application.
  • the epitaxial wafer used in the prior art is generally as shown in FIG. 2.
  • the epitaxial wafer in the prior art generally includes: a buffer layer 120 and a first conductive layer 130 sequentially disposed on the substrate 110 , The light emitting layer 140 and the second conductive layer 150.
  • the material of each layer in the epitaxial wafer is usually gallium nitride (GaN), indium gallium nitride (InGaN) or other compound semiconductor materials.
  • the lattice defects extend in the growth direction of the epitaxial wafer.
  • the curve in the figure represents lattice defects, where the epitaxial wafer grows in the vertical direction, and the lattice defects also extend in the vertical direction.
  • a large number of lattice defects The light-emitting layer 140 in the epitaxial wafer will pass through, that is, a large number of lattice defects are usually present in the light-emitting layer 140 of the epitaxial wafer in the prior art.
  • electrons and holes In an ideal state, during the application of a light emitting diode (LED) chip, electrons and holes (electron holes) will recombine and form light when they pass through the epitaxial wafer in the LED chip.
  • the electrons and holes The recombination can also be called luminescent recombination, where the recombination of electrons and holes usually occurs in the luminescent layer of the epitaxial wafer.
  • the total number of electrons and holes that reach the epitaxial wafer in the LED chip is small.
  • the lack of light caused by the lattice defects in the light-emitting layer The ratio between the number of electrons and holes and the total number of electrons and holes reaching the epitaxial wafer is larger, and the lattice defects of the light-emitting layer have a greater impact on the luminous efficiency of the LED chip.
  • the embodiments of the present application disclose an epitaxial wafer, a light emitting diode, a display screen and a preparation method thereof, so as to reduce the crystal size of the epitaxial wafer.
  • Lattice defects can improve the luminous efficiency of LED chips.
  • words such as “exemplary” or “for example” are used as examples, illustrations, or illustrations. Any embodiment or design solution described as “exemplary” or “for example” in the embodiments of the present application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as “exemplary” or “for example” are used to present related concepts in a specific manner.
  • the embodiment of the application discloses an epitaxial wafer.
  • the epitaxial wafer includes: an improvement layer 210, a first buffer layer 220, a first conductive layer 230, a light emitting layer 240 and a second conductive layer 250.
  • the improvement layer 210 is disposed above the substrate 260. And, referring to the schematic diagram shown in FIG. 3, the improvement layer includes a physical part 211 and at least one void part 212.
  • the first buffer layer 220, the first conductive layer 230, the light emitting layer 240, and the second conductive layer 250 are sequentially disposed above the improvement layer 210.
  • the at least one gap portion 212 faces the first buffer layer 220.
  • the first buffer layer 220 is used to decompose under the action of the external force, so that the first conductive layer 230, the light emitting layer 240 and the The second conductive layer 250 is separated from the substrate.
  • the first buffer layer 220 can be vaporized and decomposed after absorbing the laser, so as to realize the separation of the epitaxial wafer and the substrate.
  • the first buffer layer 220 is usually made of a material that is easy to decompose.
  • the first buffer layer 220 is usually made of a material with a high absorption rate for laser light.
  • the material of the improvement layer 210 is usually different from the material of the first buffer layer 220.
  • the improvement layer 210 is usually made of a material that is not easy to decompose during the process of peeling the epitaxial wafer and the substrate, so as to avoid the process of peeling the epitaxial wafer and the substrate from decomposing the improvement layer 210.
  • the first conductive layer 230, the light emitting layer 240, and the second conductive layer 250 cause pollution.
  • the material of the improvement layer 210 may be silicon oxide SiOx or silicon nitride SiNx.
  • the material of the improvement layer 210 may also be other materials that are not easily decomposed, which is not limited in the embodiment of the present application.
  • the improvement layer 210 may be made of a material with a low absorption rate of laser light.
  • the at least one void portion 212 in the improvement layer 210 faces the first buffer layer 220.
  • the first buffer layer 220 may pass through the at least one gap portion 212 to contact the substrate 260.
  • the first conductive layer 230 is generally an N-type semiconductor
  • the second conductive layer 250 is generally a P-type semiconductor
  • the light-emitting layer 240 generally includes structures such as a pn junction and a quantum well. It may be a single-layer quantum well or a multilayer quantum well, which is not limited in the embodiment of the present application.
  • the light-emitting layer 240 is all located in a region directly above the physical part of the improvement layer 210.
  • the light-emitting layer 240 and the improvement layer 210 are projected in a vertical direction, and the projection surface of the light-emitting layer 240 is within the range of the projection surface of the solid part of the improvement layer 210.
  • each embodiment of the present application includes the description of "above”, for example, A is arranged above B.
  • “above” in the embodiments of the present application generally refers to the growth direction of the epitaxial wafer.
  • FIG. 1 Exemplarily, in the schematic structural diagram shown in FIG.
  • the growth direction of the epitaxial wafer is: improvement layer-first buffer layer-first conductive layer-light-emitting layer-second conductive layer, it can be considered that the first buffer layer is located in Above the improvement layer; the first conductive layer is located above the improvement layer and the first buffer layer; the light-emitting layer is located above the improvement layer, the first buffer layer and the first conductive layer; the second conductive layer is located above the improvement layer and the first buffer layer , Above the first conductive layer and the light-emitting layer.
  • FIG. 4 also discloses the lattice defects generated by the epitaxial wafers disclosed in the embodiments of this application.
  • the lattice defects generated in the epitaxial wafers pass the curve Express.
  • an improvement layer 210 is provided between the substrate 260 and the first buffer layer 220.
  • the improvement layer 210 includes a solid part 211 and at least one void part 212. Vacancies occur in the positions where atoms should be in the epitaxial wafer, and therefore, lattice defects are generated between the void portion 211 and the area where the substrate 260 is in contact.
  • the lattice defect generated in the void portion extends in the growth direction of the epitaxial wafer, and the lattice defect also extends to the solid part 211 on both sides of the void portion 212.
  • the lattice defects between the void portion of the improvement layer and the region in contact with the substrate include a first lattice defect 270 and a second lattice defect 280.
  • the first lattice defect 270 is a lattice defect extending along the growth direction of the epitaxial wafer
  • the second lattice defect 280 is a lattice defect extending to both sides of the void portion.
  • the second lattice defect 280 is located in the first buffer layer 220.
  • the second lattice defect 280 is located in the first buffer layer 220 and the first conductive layer 230.
  • the height of the second lattice defect 280 in the epitaxial wafer can be adjusted by controlling the manufacturing process parameters of the epitaxial wafer.
  • the manufacturing process parameters include the temperature and/or of the epitaxial wafer during the manufacturing process. Or stress. Therefore, the second lattice defect 280 in the epitaxial wafer of the embodiment of the present application can be controlled to be located in the first buffer layer 220, or located in the first buffer layer 220 and the first conductive layer 230. In other words, the second lattice defect 280 will not reach the light-emitting layer 240.
  • the light-emitting layer 240 is a region where electrons and holes perform light-emitting recombination.
  • the second lattice defect 280 does not reach the light-emitting layer 240, the second lattice defect 280 will not affect the electrons and holes in the light-emitting layer 240.
  • the luminous compound is a region where electrons and holes perform light-emitting recombination.
  • the first lattice defect 270 extends along the growth direction of the epitaxial wafer.
  • the first lattice defect 270 will not affect the light-emitting recombination of electrons and holes in the light-emitting layer 240, so that the luminous efficiency of the LED chip can be further improved.
  • the first conductive layer 230 may all be located in an area directly above the physical portion 211 of the improvement layer 210.
  • the first conductive layer 230 since the first conductive layer 230 is not used for the recombination of electrons and holes, the first conductive layer 230 may be located in the area directly above the physical portion 211 and the void portion 212 of the improved layer 210 at the same time, In this case, since the first conductive layer 230 is not a region for light-emitting recombination, it will not affect the luminous efficiency of the LED chip.
  • an epitaxial wafer in the embodiment of the present application, includes: an improvement layer, a first buffer layer, a first conductive layer, a light emitting layer, and a second conductive layer.
  • the improved layer includes a solid part and at least one void part, the at least one void part faces the first buffer layer, and the light-emitting layer is all located on the front side of the solid part of the improved layer.
  • the epitaxial wafer disclosed in the embodiment of the present application includes a first lattice defect and a second lattice defect generated between the void portion of the improvement layer and the region in contact with the substrate.
  • the first lattice defect extends along the growth direction of the epitaxial wafer
  • the second lattice defect is located in the first buffer layer
  • the second lattice defect is located in the first buffer layer and the The first conductive layer.
  • the first lattice defect extends along the growth direction of the epitaxial wafer, and the light-emitting layer is all located in the area directly above the physical part of the improvement layer, the first lattice defect does not reach the entire area.
  • the light-emitting layer correspondingly, the first lattice defect does not affect the light-emitting recombination of electrons and holes in the light-emitting layer.
  • the second crystal lattice defect is located in the first buffer layer, or the second crystal lattice defect is located in the first buffer layer and the first conductive layer, therefore, the second crystal lattice Defects will not reach the light-emitting layer.
  • the second lattice lattice defects will not affect the light-emitting recombination of electrons and holes in the light-emitting layer. Therefore, compared with the prior art, the light-emitting layer of the epitaxial wafer disclosed in the embodiments of the present application has fewer lattice defects, and correspondingly, the luminous efficiency of the epitaxial wafer is higher.
  • a gap layer is included between the physical portion 211 of the improved layer 210 and the substrate 260; or, the improved layer 210 and the first buffer A gap layer is included between the layers 220.
  • the heights of the above two types of void layers are relatively small.
  • the height of the gap layer between the physical portion 211 and the substrate 260 is less than a first threshold, or the height of the gap layer between the improvement layer 210 and the first buffer layer 220 is less than a second threshold .
  • the first threshold and the second threshold can be set according to empirical values, and can also be set according to the requirements of the epitaxial wafer.
  • the improvement layer 210 is There is a gap layer between the first buffer layer 220, which indicates that the improvement layer 210 and the first buffer layer 220 are not in close contact or completely adhered to each other.
  • the improvement layer 210 When the physical part 211 of the improvement layer 210 is not in close contact or completely attached to the substrate, or the improvement layer 210 and the first buffer layer 220 are not in close contact or completely attached, the improvement layer 210 The physical part 211 of the crystal lattice does not generate lattice defects. Compared with the epitaxial wafer in the prior art, the epitaxial wafer disclosed in the embodiments of the present application has a smaller number of lattice defects, so that the luminous efficiency can be further improved.
  • an epitaxial wafer including the improvement layer 210, the first buffer layer 220, the first conductive layer 230, the light emitting layer 240, and the second conductive layer 250 is disclosed. Further, the epitaxial wafer can also be processed, and electrodes can be arranged on the epitaxial wafer.
  • the present application also discloses another embodiment.
  • the epitaxial wafer disclosed in this embodiment further includes:
  • the first electrode layer 310 and the second electrode layer 320 are identical to each other.
  • the first electrode layer 310 is disposed above the first conductive layer 230;
  • the second electrode layer 320 is disposed above the second conductive layer 250.
  • the first conductive layer 230 is not used for the recombination of electrons and holes. Therefore, the first conductive layer 230 may all be located in the area directly above the physical portion 211 of the improvement layer 210, or the first conductive layer 230 A conductive layer 230 can be located in the area directly above the physical portion 211 and the void portion 212 of the improvement layer 210 at the same time. In this case, even if the first lattice defect 270 passes through the first conductive layer 230, As long as the first lattice defect 270 does not pass through the light-emitting layer 240, the first lattice defect 270 will not affect the luminous efficiency of the LED chip.
  • the position of the first electrode layer 320 can also be flexibly set.
  • the first electrode layer 310 is all located in a region directly above the physical part of the improvement layer.
  • micro-LED chips ie, Micro-LED chips
  • the advantages of higher brightness, lower power consumption and longer service life Therefore, Micro-LEDs are used in LED chip displays. Chips are an ideal technology. Among them, the Micro-LED chip usually refers to an LED chip with a size of tens of micrometers or even several micrometers.
  • LED display screens often include multiple LED chips. The smaller the size of the LED chip, the higher the ratio between the area of the gap of each LED chip and the total area of each LED chip. The light-emitting performance of the LED chip has no effect. The higher the ratio, the more serious the area waste caused by the gap of the LED chip.
  • the first electrode layer 310 is located at the same time directly above the void portion 212 and the physical portion 211 of the improved layer 210. Within the area. In this case, compared with the epitaxial wafer in FIG. 6, under the condition that the size of the epitaxial wafer remains unchanged, the area occupied by the cross section of the light-emitting layer 240 is increased. For example, in FIG. 6, the side length of one side in the cross-section of the light-emitting layer 240 is L, and in FIG.
  • the side length of this side in the cross-section of the light-emitting layer 240 can reach L+1, and the corresponding light emission
  • the area of the cross section of the layer 240 increases.
  • the cross-section of the light-emitting layer 240 may be the side where the light-emitting layer 240 is in contact with the physical part of the improvement layer.
  • the light-emitting layer 240 is a region used to realize the light-emitting recombination of electrons and holes.
  • the first electrode layer 310 is all located in a region directly above the void portion of the improvement layer.
  • the cross-sectional area of the light-emitting layer 240 can be at most equal to the cross-sectional area of the solid part of the improvement layer.
  • the cross-sectional area of the light-emitting layer 240 is increased in this implementation manner, the area of the region that can be used to realize the light-emitting recombination of electrons and holes is increased, and the light-emitting efficiency of the epitaxial wafer is further improved.
  • the first electrode layer 310 is located at most in a region directly above a gap portion of the improvement layer.
  • the first electrode layer 310 may be arranged in a region directly above the void portion of the improvement layer.
  • the void portion of the improvement layer will produce first lattice defects extending along the growth direction of the epitaxial wafer.
  • the present application In an embodiment, the first electrode layer 310 is only located in a region directly above a gap portion of the improvement layer, that is, the first electrode layer 310 will only be affected by the first lattice defect of one gap portion. Influence.
  • At least one of the first conductive layers 230 occupies the same first electrode layer 310.
  • one first conductive layer 230 may occupy one first electrode layer 310 alone, or two or more first conductive layers 230 may occupy the same first electrode layer 310.
  • the side view of the epitaxial wafer may be as shown in FIGS. 6 and 7, and the top view of the epitaxial wafer may be as shown in FIG. 8.
  • different first electrode layers 310 are respectively provided on different first conductive layers 230.
  • first conductive layers 230 When two or more first conductive layers 230 occupy the same first electrode layer 310, see the front view of the epitaxial wafer shown in FIG. 9(a), and the front view of the epitaxial wafer shown in FIG. 9(b) In a top view, different parts of the same first electrode layer 310 are respectively disposed above different first conductive layers 230, and the different first conductive layers 230 share the same electrode layer. For example, in FIGS. 9(a) and 9(b), four first conductive layers 230 occupy the same first electrode layer 310.
  • the epitaxial wafer disclosed in the embodiment of the present application further includes an insulating coating layer, and the insulating coating layer is a dielectric material.
  • the insulating coating layer is located on the surface of the area where the target layer is not in contact with other layers, and the target layer is one of the first conductive layer, the light emitting layer, the second conductive layer, the first electrode layer, and the second electrode layer. At least any layer.
  • the preparation process of the epitaxial wafer usually includes the following steps: first, an improved layer located above the substrate is made by etching technology, and a first buffer layer, a first conductive layer, a light-emitting layer, and a second layer are sequentially arranged on the improved layer. Conductive layer; then, through etching technology, the first conductive layer and part of the second conductive layer are exposed respectively, and the first electrode layer is provided in the exposed area of the first conductive layer, and the second conductive layer is provided in the exposed area of the second conductive layer. Two electrode layer.
  • the etching step in this preparation process is likely to cause defects on the surface of each layer of the epitaxial wafer.
  • the electrons and holes can be combined on the surface of the light-emitting layer of the epitaxial wafer.
  • the surface of each layer of the epitaxial wafer produces defects, it will reduce the probability of electrons and holes reaching the light-emitting layer, and reduce the electron holes in the light-emitting layer.
  • the probability of light-emitting recombination on the surface of the surface and will also increase the probability of leakage of the epitaxial wafer.
  • the epitaxial wafer disclosed in the embodiment of the present application is also provided with an insulating coating layer.
  • the insulating coating layer is made of a dielectric material. Safety, and increase the probability of electron hole recombination, thereby further improving the luminous efficiency of the epitaxial wafer.
  • the insulating coating layer is located on the surface of the area where the target layer is not in contact with other layers, and the target layer is the first conductive layer, the light emitting layer, the second conductive layer, the first electrode layer, and the At least any one of the second electrode layers, that is, the non-electrical connection area of the epitaxial wafer disclosed in the embodiments of the present application can be provided with an insulating coating layer.
  • the insulating coating layer can be made of dielectric materials such as silicon oxide SiOx or silicon nitride SiNx.
  • the insulating coating layer can also be made of other dielectric materials, which is not limited in the embodiment of the present application.
  • the epitaxial wafer disclosed in the embodiment of the present application further includes:
  • the sacrificial layer 330 is provided in the first buffer layer 220.
  • the sacrificial layer 330 is used to reduce damage to the epitaxial wafer during the peeling process.
  • the external force may cause damage to the epitaxial wafer.
  • the commonly used lift-off technology is laser lift-off technology.
  • the epitaxial wafer is peeled off by the laser lift-off technique, an adhesive layer 340 is provided on the epitaxial wafer, and the epitaxial wafer is adhered to the first substrate 350 through the adhesive layer 340. Then, referring to the schematic diagram shown in FIG. 11(b), the laser light irradiates the epitaxial wafer from the direction of the substrate.
  • the first buffer layer 220 absorbs the laser light, and vaporizes and decomposes under the action of the laser light, so as to realize the separation of the epitaxial wafer and the substrate, and obtain the epitaxial wafer as shown in FIG. 11(c).
  • the size of the LED chip is small, for example, when the LED chip is a Micro-LED chip, the size of the epitaxial wafer is correspondingly smaller.
  • the first buffer layer is vaporized and decomposed by the laser irradiation.
  • the force of ⁇ may damage the structure of the epitaxial wafer, and may also cause the epitaxial wafer to be displaced on the first substrate 350, thereby affecting the yield of the LED chip.
  • the epitaxial wafer disclosed in the embodiment of the present application further includes a sacrificial layer 330 provided in the first buffer layer 220.
  • the sacrificial layer 330 can be made of a material with poor resistance to external forces, so that during the process of peeling off the substrate and the epitaxial wafer, the sacrificial layer 330 replaces other structures in the epitaxial wafer and is damaged, so as to protect the epitaxial wafer. Other structures.
  • the sacrificial layer 330 can also be made of a material with a higher laser absorptivity. In this case, during the lift-off process, the sacrificial layer 330 absorbs most of the laser light and preferentially vaporizes and decomposes. , which can reduce the damage of other structures in the epitaxial wafer.
  • the epitaxial wafer and the substrate are peeled off by the laser lift-off technology
  • the epitaxial wafer is adhered to the first substrate 350 through the adhesive layer 340, and is in the first buffer of the epitaxial wafer.
  • a sacrificial layer 330 is provided in the layer 220.
  • the laser irradiates the epitaxial wafer from the direction of the substrate.
  • the sacrificial layer 330 absorbs most of the laser light, and vaporizes and decomposes under the action of the laser, thereby obtaining the epitaxial wafer shown in FIG. Most of the laser, thus reducing the damage to the epitaxial wafer.
  • the sacrificial layer provided in the first buffer layer 220 can reduce the damage to the epitaxial wafer during the peeling process, it can also improve the yield of the LED chip.
  • the contact between the first buffer layer 220 and the improvement layer 210 is The surface is concave and convex.
  • the surface of the first buffer layer 220 for contacting the improvement layer 210 is a convex surface.
  • the improvement layer 210 is usually made of silicon oxide SiOx or silicon nitride SiNx
  • the other layers in the epitaxial wafer are usually made of It is made of gallium nitride GaN. Therefore, the absorption rate of the improvement layer 210 for laser light is often lower than that of the first buffer layer 220.
  • the first buffer layer 220 faces the laser-irradiated surface layer. Prone to vaporization and decomposition. Therefore, setting the surface of the first buffer layer 220 for the contact improvement layer 210 to be a convex surface helps prevent other layers above the first buffer layer 220 from being vaporized and decomposed when the laser lift-off technology is applied.
  • the underside of the epitaxial wafer is usually used as the light-emitting surface.
  • the convex light-emitting surface facilitates light exiting the epitaxial wafer and improves the light-emitting efficiency and collimation of the epitaxial wafer. Therefore, the first buffer layer 220 may also be used to contact the improvement layer 210 with a convex surface.
  • the first buffer layer 220 is used to contact one side of the improvement layer 210, and may be a convex surface in various forms.
  • the convex surface of the first buffer layer is a convex surface in the form of a polygon, or, in practical applications, the convex surface may also be an arc-shaped convex surface with different curvatures. This is not limited.
  • an improvement layer is provided.
  • the material of the improvement layer is usually silicon oxide or silicon nitride.
  • the improved layer includes a void portion, and when the improved layer includes two or more void portions, the two or more void portions may be arranged in various forms. It is feasible that the two or more gap portions exhibit a regular periodic arrangement, including a stripe arrangement, a mesh arrangement and/or a honeycomb arrangement.
  • the two or more void portions 221 are arranged in strips; or, referring to the top view of the improved layer shown in FIG. 14(b), the two or more void portions The void portions 221 are arranged in a net shape; or, referring to the top view of the improved layer shown in FIG. 14(c), the two or more void portions 221 are arranged in a honeycomb shape.
  • the two or more gap portions 221 may also be arranged in other ways, which is not limited in the embodiment of the present application.
  • an LED chip is also disclosed, and the LED chip includes the epitaxial wafer disclosed in each of the above embodiments.
  • the luminous efficiency of the epitaxial wafer is improved, the luminous efficiency of the LED chip disclosed in the embodiments of the present application is also improved correspondingly.
  • a display screen is also disclosed, and the display screen includes the LED chip disclosed in the foregoing embodiment of the present application.
  • the LED chips used in the display screens disclosed in the embodiments of the present application have higher luminous efficiency. Therefore, the luminous efficiency of the display screens disclosed in the embodiments of the present application is also improved correspondingly.
  • the embodiments of the present application disclose an epitaxial wafer, a corresponding LED chip, and a display screen using the LED chip.
  • the epitaxial wafer includes a first lattice defect and a second lattice defect, and the first lattice defect and the second lattice defect will not reach the light-emitting layer, and the light-emitting layer is carried out by electrons and holes. Defects of luminescent recombination. Therefore, compared with the epitaxial wafer in the prior art, the epitaxial wafer of the embodiment of the present application has fewer lattice defects in the light-emitting layer, and further, the luminous efficiency of the epitaxial wafer is higher. Correspondingly, the luminous efficiency of the LED chip obtained through the epitaxial wafer of the embodiment of the present application is relatively high.

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Abstract

一种外延片、LED芯片及显示屏，该外延片包括：改善层（210）、第一缓冲层（220）、第一导电层（230）、发光层（240）和第二导电层（250），改善层（210）包括实体部分（211）和至少一个空隙部分（212），该空隙部分（212）朝向第一缓冲层（220），发光层（240）全部位于改善层（210）的实体部分（211）的正上方的区域范围内。外延片包括改善层（210）的空隙部分（212）与衬底（260）相接触的区域之间生成的第一晶格缺陷（270）和第二晶格缺陷（280）。第一晶格缺陷（270）沿外延片生长方向延伸，第二晶格缺陷（280）位于第一缓冲层（220）中，或者位于第一缓冲层（220）和第一导电层（230）中。第一晶格缺陷（270）和第二晶格缺陷（280）不会到达发光层（240），不会影响电子和电洞在发光层（240）的发光复合。因此，所述外延片的发光层（240）中的晶格缺陷较少，相应的，所述外延片的发光效率较高。

Description

一种外延片、LED芯片及显示屏 技术领域
本申请涉及半导体技术领域，具体涉及一种外延片、LED芯片及显示屏。
背景技术
发光二极管(light emitting diode，LED)显示屏具有高寿命和高色彩稳定度等优势，应用日益广泛。其中，LED显示屏中通常包括多个LED芯片，所述LED芯片通过对外延片的加工获取。
在外延片的制备工程中，通常首先准备衬底，然后再在衬底之上成长外延片，其中，衬底的材质通常为蓝宝石，而外延片的材质通常为氮化镓(gallium nitride，GaN)。参见图1(a)，在图1(a)中，上两层为GaN晶格，下两层为蓝宝石晶格，根据图1(a)可知，GaN的晶格常数较小，而蓝宝石的晶格常数较大，GaN与蓝宝石之间存在较大的晶格常数不匹配度。这种情况下，参见图1(b)所示的示意图，在该示意图中，上三层为GaN晶格，下两层为蓝宝石晶格，由于GaN与蓝宝石的晶格常数不匹配，外延片会出现晶格缺陷，影响LED芯片的发光效率，进一步的会影响LED芯片显示屏的显示效果。
为了减少晶格缺陷，目前通常采用两种方式。第一种方式为在衬底与外延片之间设置一层缓冲层，所述缓冲层的晶格常数在衬底的晶格常数与外延片的晶格常数之间，以缓解衬底与外延片的晶格常数不匹配度。第二种方式为对蓝宝石衬底进行图形化处理(patterned sapphire substrate，PSS)。
但是，发明人在本申请的研究过程中发现，虽然上述两种方式有助于减少外延片的晶格缺陷，但是采用上述两种方式的外延片仍然存在较多晶格缺陷，从而导致发光效率降低。例如，当采用第一种方式时，外延片的晶格缺陷的缺陷密度在1E8～1E9/cm 2以上，当采用第二种方式时，外延片的晶格缺陷的缺陷密度仍然在1E18/cm 2以上。
发明内容
为了解决在现有技术中，外延片存在较多晶格缺陷，导致LED芯片的发光效率降低的问题，本申请实施例公开一种外延片、发光二极管、显示屏及其制备方法，以减少外延片的晶格缺陷，提高LED芯片的发光效率。
第一方面，本申请实施例公开一种外延片，包括：
改善层、第一缓冲层、第一导电层、发光层和第二导电层；
所述改善层设置在衬底上方，所述改善层包括实体部分和至少一个空隙部分；
所述第一缓冲层、第一导电层、发光层和第二导电层依次设置在所述改善层的上方，所述至少一个空隙部分朝向所述第一缓冲层；
所述发光层全部位于所述改善层的实体部分的正上方的区域范围内；
所述改善层的空隙部分与所述衬底相接触的区域之间的晶格缺陷包括第一晶格缺陷和第二晶格缺陷，所述第一晶格缺陷为沿外延片生长方向延伸的晶格缺陷，所述第 二晶格缺陷为向所述空隙部分两侧延伸的晶格缺陷；
所述第二晶格缺陷位于所述第一缓冲层中，或者所述第二晶格缺陷位于所述第一缓冲层和所述第一导电层中。
本申请实施例公开的外延片中，第一晶格缺陷和第二晶格缺陷不会到达所述发光层，因此不会影响电子和电洞在所述发光层的发光复合。因此，本申请实施例公开的外延片的发光层中的晶格缺陷较少，相应的，所述外延片的发光效率较高。
一种可选的设计中，所述改善层的实体部分与所述衬底之间包括空隙层；
或者，所述改善层与所述第一缓冲层之间包括空隙层。
在本申请实施例公开的外延片中，改善层的实体部分与衬底并未紧密接触，或所述改善层与第一缓冲层并未紧密接触时，则所述改善层的实体部分不会生成晶格缺陷。与现有技术中的外延片相比，本申请实施例公开的外延片的晶格缺陷数量较少，从而能够进一步提高发光效率。
一种可选的设计中，还包括：
第一电极层和第二电极层；
所述第一电极层设置在所述第一导电层的上方；
所述第二电极层设置在所述第二导电层的上方。
一种可选的设计中，所述第一电极层同时位于所述改善层的空隙部分和实体部分的正上方的区域范围内；
或者，所述第一电极层全部位于所述改善层的空隙部分的正上方的区域范围内。
由于所述第一电极层位于位于所述改善层的空隙部分和实体部分的正上方的区域范围内，或者位于所述改善层的空隙部分的正上方的区域范围内，因此，发光层的横截面可占据的面积较大，相应的可用于实现电子和电洞的发光复合的区域面积增加，从而能够提高外延片的面积的利用率，进一步的，还能够提高外延片的发光效率。
一种可选的设计中，所述第一电极层最多位于所述改善层的一个空隙部分的正上方的区域范围内。
这种情况下，所述第一电极层最多受到一个空隙部分的第一晶格缺陷的影响。
一种可选的设计中，至少一个所述第一导电层占用同一个所述第一电极层。
这种情况下，在外延片的面积不变的情况下，发光层的横截面可占用的面积增大，从而能够进一步提高外延片的发光效率。
一种可选的设计中，还包括：
设置在所述第一缓冲层中的牺牲层；
当剥离所述衬底和所述外延片时，所述牺牲层用于减少剥离过程对所述外延片的破坏。
在剥离衬底和外延片的过程中，所述牺牲层能够外延片中的其他结构被损坏，以便保护外延片中的其他结构，提高LED芯片的良品率。
一种可选的设计中，还包括：
绝缘被覆层；
所述绝缘被覆层为介电材料；
所述绝缘被覆层位于目标层未与其他层接触的区域表面，所述目标层为所述第一 导电层、发光层、第二导电层、第一电极层和第二电极层中的至少任意一层。
通过所述绝缘被覆层，能够修复所述外延片表面的缺陷，减少漏电几率，提高外延片的安全性，以及提高电子电洞进行发光复合的几率，从而进一步提高外延片的发光效率。
一种可选的设计中，所述第一缓冲层与所述改善层之间的接触面为凹凸面；
所述第一缓冲层用于接触所述改善层的一面为凸面。
当第一缓冲层用于接触所述改善层的一面为凸面时，能够提高外延片的出光效率与准直性。
一种可选的设计中，当所述改善层包括两个以上空隙部分时，所述两个以上空隙部分呈现有规则周期排列，包括条状排列、网状排列和/或蜂窝状排列。
第二方面，本申请实施例公开一种LED芯片，
所述LED芯片包括第一方面所述的外延片。
第三方面，本申请实施例公开一种显示屏，
所述显示屏包括第二方面所述的LED芯片。
在本申请实施例中，公开一种外延片、LED芯片及显示屏，该外延片包括：改善层、第一缓冲层、第一导电层、发光层和第二导电层。在该外延片中，所述改善层包括实体部分和至少一个空隙部分，所述至少一个空隙部分朝向所述第一缓冲层，并且，所述发光层全部位于所述改善层的实体部分的正上方的区域范围内。
在本申请实施例公开的外延片中，包括所述改善层的空隙部分与所述衬底相接触的区域之间生成的第一晶格缺陷和第二晶格缺陷。其中，所述第一晶格缺陷沿外延片生长方向延伸，所述第二晶格缺陷位于所述第一缓冲层中，或者所述第二晶格缺陷位于所述第一缓冲层和所述第一导电层中。
由于所述第一晶格缺陷沿外延片生长方向延伸，而所述发光层全部位于所述改善层的实体部分的正上方的区域范围内，因此，所述第一晶格缺陷不会到达所述发光层，相应的，所述第一晶格缺陷不会影响电子和电洞在所述发光层的发光复合。另外，所述第二晶格缺陷位于所述第一缓冲层中，或者所述第二晶格缺陷位于所述第一缓冲层和所述第一导电层中，因此，所述第二晶格缺陷也不会到达所述发光层，相应的，所述第二晶格晶格缺陷也不会影响电子和电洞在所述发光层的发光复合。因此，与现有技术相比，本申请实施例公开的外延片的发光层中的晶格缺陷较少，相应的，所述外延片的发光效率较高。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1(a)为现有技术公开的一种外延片与衬底的连接关系示意图；
图1(b)为现有技术公开的一种外延片与衬底的连接关系示意图；
图2为现有技术公开的一种外延片的结构示意图；
图3为本申请实施例公开的一种外延片的结构示意图；
图4为本申请实施例公开的一种外延片的晶格缺陷的示意图；
图5为本申请实施例公开的另一种外延片的结构示意图；
图6为本申请实施例公开的另一种外延片的结构示意图；
图7为本申请实施例公开的另一种外延片的结构示意图；
图8为本申请实施例公开的一种外延片的俯视图；
图9(a)为本申请实施例公开的一种外延片的正视图；
图9(b)为本申请实施例公开的一种外延片的俯视图；
图10为本申请实施例公开的另一种外延片的结构示意图；
图11(a)为本申请实施例公开的一种外延片的结构示意图；
图11(b)为本申请实施例公开的一种接收激光照射的外延片的场景示意图；
图11(c)为本申请实施例公开的一种与衬底分离后的外延片的结构示意图；
图12(a)为本申请实施例公开的一种外延片的结构示意图；
图12(b)为本申请实施例公开的一种接收激光照射的外延片的场景示意图；
图12(c)为本申请实施例公开的一种与衬底分离后的外延片的结构示意图；
图13(a)为本申请实施例公开的一种外延片的结构示意图；
图13(b)为本申请实施例公开的另一种外延片的结构示意图；
图14(a)为本申请实施例公开的一种外延片中的改善层的俯视图；
图14(b)为本申请实施例公开的另一种外延片中的改善层的俯视图；
图14(c)为本申请实施例公开的另一种外延片中的改善层的俯视图。
具体实施方式
为了下述各实施例的描述清楚简洁，首先给出相关技术的简要介绍：
在现有技术中所应用的外延片的通常如图2所示，参见图2，现有技术中的外延片通常包括：依次设置在衬底110之上的缓冲层120、第一导电层130、发光层140和第二导电层150。其中，外延片中各层的材质通常采用氮化镓(gallium nitride，GaN)、氮化铟镓(indium gallium nitride，InGaN)或其他化合物半导体材料。
另外，在现有技术中的外延片中，由于外延片的材质与衬底的材质之间存在较大的晶格常数不匹配度，因此，外延片的晶体与衬底的晶体在排列时，往往会出现晶格错位。当外延片的晶体与衬底的晶体数量较多时，晶格错位现象发生累积，导致外延片出现晶格缺陷，该晶格缺陷也可称为晶体缺陷。在图2所示的外延片的基础上，即使外延片与衬底之间增设缓冲层，或者，对衬底进行图形化处理，外延片内仍存在较大晶格缺陷。并且，该晶格缺陷向外延片的成长方向延伸。例如，参见图2所示的示意图，该图中的曲线表示晶格缺陷，其中，外延片沿竖直方向成长，晶格缺陷也会向竖直方向延伸，这种情况下，大量晶格缺陷将穿过外延片中的发光层140，即现有技术的外延片的发光层140中通常存在大量晶格缺陷。
在理想状态下，发光二极管(light emitting diode，LED)芯片在应用过程中，电子和电洞(electron hole)在通过LED芯片中的外延片时，会发生复合并形成光线，该电子和电洞的复合也可称为发光复合，其中，电子和电洞的复合通常发生在外延片的发光层中。
这种情况下，如果发光层中存在晶格缺陷，当电子和电洞经过发光层中的晶格缺陷所在区域时，电子和电洞将不会在该区域发生发光复合，因此，这部分电子和电洞 将不会用于形成光线，这部分电子和电洞的电位能往往被转化成热能或其他能量，导致电位能浪费，并降低了LED芯片的发光效率，即现有技术中的外延片中，发光层中存在的较多的晶格缺陷，导致LED芯片的发光效率降低。
特别的，当LED芯片应用于低电流的场景时，到达LED芯片中的外延片的电子和电洞的总数量较少，这种情况下，发光层中的晶格缺陷所导致的无法发光的电子和电洞的数量，与到达外延片的电子和电洞的总数量之间的比例较大，发光层的晶格缺陷对LED芯片的发光效率的影响更大。
为了解决在现有技术中，外延片与衬底之间的晶格缺陷较大的问题，本申请实施例公开一种外延片、发光二极管、显示屏及其制备方法，以减少外延片的晶格缺陷，提高LED芯片的发光效率。
本申请说明书和权利要求书及附图说明中的术语“第一”、“第二”和“第三”等是用于区别不同对象，而不是用于限定特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请实施例公开一种外延片。参见图3所示的结构示意图，所述外延片包括：改善层210、第一缓冲层220、第一导电层230、发光层240和第二导电层250。
其中，所述改善层210设置在衬底260上方。并且，参见图3所示的示意图，所述改善层包括实体部分211和至少一个空隙部分212。
所述第一缓冲层220、第一导电层230、发光层240和第二导电层250依次设置在所述改善层210的上方。并且，所述至少一个空隙部分212朝向所述第一缓冲层220。
当将外延片从衬底上剥离时，通常会对外延片施加外力，所述第一缓冲层220用于在外力的作用下进行分解，从而使所述第一导电层230、发光层240和第二导电层250与所述衬底分离。例如，当通过激光剥离技术从衬底上剥离外延片时，所述第一缓冲层220能够在吸收激光后汽化分解，从而实现外延片与衬底的分离。
为了便于实现所述第一缓冲层220的分解，所述第一缓冲层220通常采用易于分解的材质。例如，当通过激光剥离技术从衬底上剥离外延片时，所述第一缓冲层220通常采用对激光的吸收率较高的材质。
另外，在本申请实施例中，所述改善层210的材质通常与所述第一缓冲层220的材质不同。其中，所述改善层210通常采用在剥离外延片和衬底的过程中，不易发生分解的材质，以避免在剥离外延片和衬底的过程中，所述改善层210由于分解，对所述第一导电层230、发光层240和第二导电层250造成污染。
示例性的，所述改善层210的材质可以为氧化硅SiOx或氮化硅SiNx。或者，所述改善层210的材质也可为其他不易发生分解的材质，本申请实施例对此不做限定。例如，如果采用激光剥离技术从衬底上剥离外延片，所述改善层210可采用对激光的吸收率较低的材质。
另外，在本申请实施例中，改善层210中的所述至少一个空隙部分212朝向所述第一缓冲层220。在一种可行的实现方式中，所述第一缓冲层220可通过所述至少一个空隙部分212，与所述衬底260相接触。
所述第一导电层230通常为N型半导体，所述第二导电层250通常为P型半导体，所述发光层240通常包括p-n接面和量子阱(quantum well)等结构，所述量子阱可以为单层量子阱或多层量子阱，本申请实施例对此不做限定。
另外，在本申请实施例公开的外延片中，所述发光层240全部位于所述改善层210的实体部分的正上方的区域范围内。也就是说，将所述发光层240和所述改善层210在垂直方向投影，所述发光层240的投影面在所述改善层210的实体部分的投影面的范围内。
在本申请各个实施例的描述中，包括“上方”的描述，例如A设置在B的上方。这种情况下，本申请实施例中的“上方”通常表示的是外延片的生长方向。示例性的，在图3所示的结构示意图中，外延片的生长方向为：改善层-第一缓冲层-第一导电层-发光层-第二导电层，即可认为第一缓冲层位于改善层的上方；第一导电层位于改善层和第一缓冲层的上方；发光层位于改善层、第一缓冲层和第一导电层的上方；第二导电层位于改善层、第一缓冲层、第一导电层和发光层的上方。
为了明确本申请实施例公开的外延片的优势，在图4中还公开了本申请实施例公开的外延片所生成的晶格缺陷，在图4中，外延片内生成的晶格缺陷通过曲线表示。
在本申请实施例的外延片中，衬底260与第一缓冲层220之间设置有改善层210，所述改善层210包括实体部分211和至少一个空隙部分212，由于该空隙部分212会导致外延片中应有原子的位置发生空缺，因此，会导致所述空隙部分211与衬底260相接触的区域之间产生晶格缺陷。
在所述空隙部分产生的晶格缺陷延所述外延片的成长方向延伸，并且所述晶格缺陷还会向所述空隙部分212两侧的实体部分211延伸。也就是说，所述改善层的空隙部分与所述衬底相接触的区域之间的晶格缺陷包括第一晶格缺陷270和第二晶格缺陷280。其中，所述第一晶格缺陷270为沿外延片生长方向延伸的晶格缺陷，所述第二晶格缺陷280为向所述空隙部分两侧延伸的晶格缺陷。
参见图4，在本申请实施例公开的外延片中，所述第二晶格缺陷280位于所述第一缓冲层220中。或者，所述第二晶格缺陷280位于所述第一缓冲层220和所述第一导电层230中。
其中，在外延片的制备过程中，可通过控制外延片的制造工艺参数，调整第二晶格缺陷280在外延片中的高度，所述制造工艺参数包括外延片在制造过程中的温度和/或压力。因此，可控制本申请实施例的外延片中的第二晶格缺陷280位于第一缓冲层220中，或者位于所述第一缓冲层220和所述第一导电层230中。也就是说，所述第二晶格缺陷280不会到达所述发光层240。
由于所述第二晶格缺陷280不会到达所述发光层240，因此，所述第二晶格缺陷280不会对发光层240造成影响。而发光层240为电子和电洞进行发光复合的区域，当第二晶格缺陷280不会到达发光层240时，则所述第二晶格缺陷280不会影响电子和电洞在发光层240的发光复合。
进一步的，参见图4所示的晶格缺陷，在本申请实施例中，所述第一晶格缺陷270延所述外延片的成长方向延伸。这种情况下，当所述发光层240全部位于所述改善层210的实体部分211的正上方的区域范围内时，即使第一晶格缺陷270延所述外延片的成长方向延伸，也会避开所述发光层240，因此，所述第一晶格缺陷270不会影响电子和电洞在所述发光层240的发光复合，从而能够进一步提高LED芯片的发光效率。
另外，所述第一导电层230可全部位于所述改善层210的实体部分211的正上方的区域范围内。或者，由于所述第一导电层230不用于电子和电洞的复合，所述第一导电层230可同时位于所述改善层210的实体部分211和空隙部分212的正上方的区域范围内，这种情况下，由于所述第一导电层230并非进行发光复合的区域，因此也不会对LED芯片的发光效率造成影响。
在本申请实施例中，公开一种外延片，该外延片包括：改善层、第一缓冲层、第一导电层、发光层和第二导电层。在该外延片中，所述改善层包括实体部分和至少一个空隙部分，所述至少一个空隙部分朝向所述第一缓冲层，并且，所述发光层全部位于所述改善层的实体部分的正上方的区域范围内。
在本申请实施例公开的外延片中，包括所述改善层的空隙部分与所述衬底相接触的区域之间生成的第一晶格缺陷和第二晶格缺陷。其中，所述第一晶格缺陷沿外延片生长方向延伸，所述第二晶格缺陷位于所述第一缓冲层中，或者所述第二晶格缺陷位于所述第一缓冲层和所述第一导电层中。
由于所述第一晶格缺陷沿外延片生长方向延伸，而所述发光层全部位于所述改善层的实体部分的正上方的区域范围内，因此，所述第一晶格缺陷不会到达所述发光层，相应的，所述第一晶格缺陷不会影响电子和电洞在所述发光层的发光复合。另外，所述第二晶格缺陷位于所述第一缓冲层中，或者所述第二晶格缺陷位于所述第一缓冲层和所述第一导电层中，因此，所述第二晶格缺陷也不会到达所述发光层，相应的，所述第二晶格晶格缺陷也不会影响电子和电洞在所述发光层的发光复合。因此，与现有技术相比，本申请实施例公开的外延片的发光层中的晶格缺陷较少，相应的，所述外延片的发光效率较高。
进一步的，在本申请另一实施例公开的外延片中，所述改善层210的实体部分211与所述衬底260之间包括空隙层；或者，所述改善层210与所述第一缓冲层220之间包括空隙层。
上述两种空隙层的高度较小。示例性的，所述实体部分211与所述衬底260之间的空隙层的高度小于第一阈值，或所述改善层210与第一缓冲层220之间的空隙层的高度小于第二阈值。所述第一阈值和第二阈值可根据经验值进行设定，也可根据对外延片的需求进行设置。
其中，所述实体部分211与所述衬底260之间存在空隙层，表明所述实体部分211与所述衬底260之间并未紧密接触或完全贴合；另外，所述改善层210与第一缓冲层220之间存在空隙层，表明所述改善层210与第一缓冲层220之间并未紧密接触或完全贴合。
当所述改善层210的实体部分211与衬底并未紧密接触或完全贴合，或所述改善层210与第一缓冲层220并未紧密接触或完全贴合时，则所述改善层210的实体部分 211不会生成晶格缺陷。与现有技术中的外延片相比，本申请实施例公开的外延片的晶格缺陷数量较少，从而能够进一步提高发光效率。
在本申请的上述实施例中，公开了包括改善层210、第一缓冲层220、第一导电层230、发光层240和第二导电层250的外延片。进一步的，还可以对该外延片进行加工，在该外延片上设置电极。
这种情况下，本申请还公开另一实施例，参见图5所示的结构示意图，该实施例所公开的外延片还包括：
第一电极层310和第二电极层320。
所述第一电极层310设置在所述第一导电层230的上方；
所述第二电极层320设置在所述第二导电层250的上方。
所述第一导电层230不用于电子和电洞的复合，因此，所述第一导电层230可全部位于所述改善层210的实体部分211的正上方的区域范围内，或者，所述第一导电层230可同时位于所述改善层210的实体部分211和空隙部分212的正上方的区域范围内，这种情况下，即使第一晶格缺陷270穿过所述第一导电层230，只要所述第一晶格缺陷270不穿过所述发光层240，所述第一晶格缺陷270就不会影响LED芯片的发光效率。
另外，在本申请实施例中，所述第一电极层320的位置也可灵活设置。在其中一种可行的实现方式中，参见图5和图6，所述第一电极层310全部位于所述改善层的实体部分的正上方的区域范围内。
另外，与普通尺寸的LED芯片相比，微型LED芯片(即Micro-LED芯片)具有亮度更高、功耗更低和使用寿命更长等优势，因此，在LED芯片显示屏中应用Micro-LED芯片，是一种比较理想的技术。其中，Micro-LED芯片通常指尺寸为十数微米甚至数微米的LED芯片。但是，LED显示屏中往往包括多个LED芯片，LED芯片的尺寸越小，各个LED芯片的间隙的面积与所述各个LED芯片的总面积之间的比例越高，而该LED芯片的间隙对LED芯片的发光性能没有作用，该比例越高，则表示LED芯片的间隙所导致的面积浪费越严重。
为了提高面积利用率，参见图7所示的示意图，在另一种可行的实现方式中，所述第一电极层310同时位于所述改善层210的空隙部分212和实体部分211的正上方的区域范围内。这种情况下，与图6中的外延片相比，在外延片的尺寸不变情况下，发光层240的横截面可占据的面积增大。例如，在图6中，发光层240的横截面中一条边的边长为L，而在图7中，发光层240的横截面中这一条边的边长可达到L+l，相应的发光层240的横截面的面积增大。其中，所述发光层240的横截面可为所述发光层240与所述改善层的实体部分相接触的一面。
发光层240为用于实现电子和电洞的发光复合的区域，发光层240的横截面的面积越大，可用于实现电子和电洞的发光复合的区域面积越大，相应的，外延片的发光效率越高。因此，通过本申请实施例的方案，能够提高外延片的面积的利用率，进一步的，还能够提高外延片的发光效率。
或者，在另一种可行的实现方式中，所述第一电极层310全部位于所述改善层的空隙部分的正上方的区域范围内。这种情况下，所述发光层240的横截面的面积最大 可与所述改善层的实体部分的横截面的面积相等。相应的，由于这一实现方式中，所述发光层240的横截面的面积增加，可用于实现电子和电洞的发光复合的区域面积增加，所述外延片的发光效率进一步提高。
进一步的，在一种可行的实现方式中，所述第一电极层310最多位于所述改善层的一个空隙部分的正上方的区域范围内。
为了保障发光层240的利用面积，可将所述第一电极层310设置在改善层的空隙部分的正上方的区域范围。而所述改善层的空隙部分会产生沿外延片的生长方向延伸的第一晶格缺陷，这种情况下，为了减少第一晶格缺陷对所述第一电极层310的影响，在本申请实施例中，所述第一电极层310只位于所述改善层的一个空隙部分的正上方的区域范围内，即所述第一电极层310只会受到一个空隙部分的第一晶格缺陷的影响。
进一步的，在本申请实施例公开的外延片中，至少一个所述第一导电层230占用同一个所述第一电极层310。也就是说，一个所述第一导电层230可单独占用一个第一电极层310，或者，两个或两个以上的第一导电层230占用同一个第一电极层310。
其中，当一个第一导电层230单独占用一个第一电极层310时，外延片的侧视图可如图6和图7所示，外延片的俯视图可如图8所示。这种情况下，不同的第一导电层230的上方分别设置不同的第一电极层310。
当两个或两个以上的第一导电层230占用同一个第一电极层310时，参见图9(a)所示的外延片的正视图，以及图9(b)所示的外延片的俯视图，同一个第一电极层310的不同部分，分别设置在不同的第一导电层230的上方，所述不同的第一导电层230共用同一个电极层。例如，在图9(a)和图9(b)中，四个第一导电层230占用同一个第一电极层310。
当两个或两个以上的第一导电层230占用同一个第一电极层310时，在外延片的面积不变的情况下，发光层240的横截面可占用的面积增大，相应的，用于实现电子和电洞的发光复合的区域面积增大，导致外延片的发光效率增加。因此，通过本申请实施例的方案，能够提高外延片的面积的利用率，进一步的，还能够提高外延片的发光效率。
另外，在本申请实施例公开的外延片中，还包括：绝缘被覆层，所述绝缘被覆层为介电材料。
其中，所述绝缘被覆层位于目标层未与其他层接触的区域表面，所述目标层为所述第一导电层、发光层、第二导电层、第一电极层和第二电极层中的至少任意一层。
在外延片的制备过程中，通常包括以下步骤：首先，通过蚀刻技术制作位于衬底上方的改善层，以及依次在改善层的上方设置第一缓冲层、第一导电层、发光层和第二导电层；然后，通过蚀刻技术，分别使第一导电层和第二导电层的部分区域裸露，并在第一导电层裸露的区域设置第一电极层，在第二导电层裸露的区域设置第二电极层。这一制备过程中的蚀刻步骤很可能会导致外延片各层材料的表面产生缺陷。
而电子和电洞可在外延片的发光层的表面进行发光复合，当外延片各层材料的表面产生缺陷时，会减少电子和电洞到达发光层的几率，以及减少电子电洞在发光层的表面进行发光复合的几率，并且还会增加外延片的漏电几率。
这种情况下，本申请实施例公开的外延片中还设置绝缘被覆层，所述绝缘被覆层 由介电材料制成，能够修复所述外延片表面的缺陷，减少漏电几率，提高外延片的安全性，以及提高电子电洞进行发光复合的几率，从而进一步提高外延片的发光效率。
并且，在本申请实施例中，所述绝缘被覆层位于目标层未与其他层接触的区域表面，该目标层为所述第一导电层、发光层、第二导电层、第一电极层和第二电极层中的至少任意一层，也就是说，本申请实施例公开的外延片的非电性连接区域均可设置绝缘被覆层。
其中，该绝缘被覆层可由氧化硅SiOx或氮化硅SiNx等介电材料制成，当然，该绝缘被覆层也可由其他介电材料制成，本申请实施例对此不做限定。
在有些应用场景下，需要将外延片和衬底剥离。这种情况下，参见图10所示的示意图，在本申请实施例公开的外延片中，还包括：
设置在所述第一缓冲层220中的牺牲层330。
当剥离所述衬底和所述外延片时，所述牺牲层330用于减少剥离过程对所述外延片的破坏。
在剥离所述衬底和外延片的过程中，通常需要对所述衬底和外延片施加外力，这一过程中，外力可能会对外延片造成破坏。
例如，目前常用的剥离技术为激光剥离技术。参见图11(a)所示的示意图，当通过激光剥离技术剥离外延片时，在外延片的上方设置黏着层340，并通过黏着层340将外延片黏着在第一基板350上。然后，参见图11(b)所示的示意图，激光从衬底方向照射外延片。在照射过程中，第一缓冲层220吸收激光，并在激光作用下汽化分解，从而实现外延片与衬底的分离，获取图11(c)所示的外延片。
当LED芯片尺寸较小，例如LED芯片为Micro-LED芯片时，外延片的尺寸相应较小，这种情况下，激光照射外延片时，第一缓冲层受激光照射而汽化分解的瞬间所产生的力量可能对外延片的结构产生破坏，并且还可能使外延片在第一基板350上产生位移，进而影响LED芯片的良品率。
这种情况下，在本申请实施例公开的外延片中，还包括设置在第一缓冲层220中的牺牲层330。该牺牲层330可采用对外力的抵抗能力较差的材质，从而在剥离所述衬底和外延片的过程中，该牺牲层330代替外延片中的其他结构被损坏，以便保护外延片中的其他结构。
例如，当采用的剥离技术为激光剥离技术时，该牺牲层330还可采用激光吸收率较高的材质，这种情况下，在剥离过程中，该牺牲层330吸收大部分激光，优先汽化分解，从而能够减少对外延片中的其他结构的破坏。
示例性的，当通过激光剥离技术剥离外延片和衬底时，参见图12(a)所示的示意图，外延片通过黏着层340黏着在第一基板350上，并且在外延片的第一缓冲层220中设置有牺牲层330。然后，参见图12(b)所示的示意图，激光从衬底方向照射外延片。在照射过程中，牺牲层330吸收大部分激光，并在激光作用下汽化分解，从而获取图12(c)所示的外延片，实现外延片与衬底的分离，并且由于牺牲层330吸收了大部分激光，因此减少了对外延片的破坏。
进一步的，由于设置在第一缓冲层220中的牺牲层能够减少剥离过程中对外延片的破坏，因此还能够提高LED芯片的良品率。
另外，在一种可行的设计中，参见图13(a)所示的示意图，在本申请实施例所公开的外延片中，所述第一缓冲层220与所述改善层210之间的接触面为凹凸面。
并且，参见图13(b)所示的示意图，所述第一缓冲层220用于接触所述改善层210的一面为凸面。
由于改善层210通常由氧化硅SiOx或氮化硅SiNx制成，而外延片中其他各层(例如第一缓冲层220、第一导电层230、发光层240和第二导电层250)通常由氮化镓GaN制成，因此，改善层210对激光的吸收率往往低于第一缓冲层220，当通过激光剥离技术剥离外延片和衬底时，第一缓冲层220面向激光照射的表层较易发生汽化分解。因此，将第一缓冲层220用于接触改善层210的一面设置为凸面，在应用激光剥离技术时，有助于避免第一缓冲层220上方的其他各层被汽化分解。
另外，在将外延片从衬底上剥离之后，外延片的下方通常作为出光面，出光面为凸面有利于光线射出外延片，提高外延片的出光效率与准直性。因此，也可将所述第一缓冲层220用于接触所述改善层210的一面为凸面。
所述第一缓冲层220用于接触所述改善层210的一面，可为多种形式的凸面。其中，在图13(b)所示的示意图中，第一缓冲层的凸面为多边形形式的凸面，或者，在实际应用中，该凸面还可以为不同曲率的弧形凸面，本申请实施例对此不做限定。
在本申请实施例公开的外延片中，设置有改善层。所述改善层的材质通常为氧化硅或氮化硅等。
另外，所述改善层中包括空隙部分，当所述改善层包括两个以上空隙部分时，所述两个以上空隙部分可通过多种形式排列。可行的，所述两个以上空隙部分呈现有规则周期排列，包括条状排列、网状排列和/或蜂窝状排列。
例如，参见图14(a)所示的改善层的俯视图，所述两个以上空隙部分221呈现条状排列；或者，参见图14(b)所示的改善层的俯视图，所述两个以上空隙部分221呈现网状排列；或者，参见图14(c)所示的改善层的俯视图，所述两个以上空隙部分221呈现蜂巢状排列。
当然，所述两个以上空隙部分221还可以通过其他方式排列，本申请实施例对此不做限定。
相应的，在本申请另一实施例中，还公开一种LED芯片，该LED芯片包括上述各个实施例中公开的外延片。
由于所述外延片的发光效率提高，因此，本申请实施例公开的LED芯片的发光效率也相应提高。
另外，在本申请另一实施例中，还公开一种显示屏，所述显示屏包括本申请上述实施例公开的LED芯片。与现有技术中的显示屏相比，本申请实施例所公开的显示屏中应用的LED芯片的发光效率较高，因此，本申请实施例公开的显示屏的发光效率也相应提高。
综上所述，本申请实施例公开一种外延片、相应的LED芯片及应用该LED芯片 的显示屏。其中，该外延片中包括第一晶格缺陷和第二晶格缺陷，并且所述第一晶格缺陷和第二晶格缺陷不会到达发光层，而所述发光层为电子和电洞进行发光复合的缺陷。因此，与现有技术中的外延片相比，本申请实施例的外延片的发光层中的晶格缺陷较少，进一步的，外延片的发光效率较高。相应的，通过本申请实施例的外延片获取的LED芯片的发光效率较高。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种外延片，其特征在于，包括：
    改善层、第一缓冲层、第一导电层、发光层和第二导电层；
    所述改善层设置在衬底上方，所述改善层包括实体部分和至少一个空隙部分；
    所述第一缓冲层、第一导电层、发光层和第二导电层依次设置在所述改善层的上方，所述至少一个空隙部分朝向所述第一缓冲层；
    所述发光层全部位于所述改善层的实体部分的正上方的区域范围内；
    所述改善层的空隙部分与所述衬底相接触的区域之间的晶格缺陷包括第一晶格缺陷和第二晶格缺陷，所述第一晶格缺陷为沿外延片生长方向延伸的晶格缺陷，所述第二晶格缺陷为向所述空隙部分两侧延伸的晶格缺陷；
    所述第二晶格缺陷位于所述第一缓冲层中，或者所述第二晶格缺陷位于所述第一缓冲层和所述第一导电层中。
  2. 根据权利要求1所述的外延片，其特征在于，
    所述改善层的实体部分与所述衬底之间包括空隙层；
    或者，所述改善层与所述第一缓冲层之间包括空隙层。
  3. 根据权利要求1或2所述的外延片，其特征在于，还包括：
    第一电极层和第二电极层；
    所述第一电极层设置在所述第一导电层的上方；
    所述第二电极层设置在所述第二导电层的上方。
  4. 根据权利要求3所述的外延片，其特征在于，
    所述第一电极层同时位于所述改善层的空隙部分和实体部分的正上方的区域范围内；
    或者，所述第一电极层全部位于所述改善层的空隙部分的正上方的区域范围内。
  5. 根据权利要求4所述的外延片，其特征在于，
    所述第一电极层最多位于所述改善层的一个空隙部分的正上方的区域范围内。
  6. 根据权利要求3至5任一项所述的外延片，其特征在于，
    至少一个所述第一导电层占用同一个所述第一电极层。
  7. 根据权利要求1至6任一项所述的外延片，其特征在于，还包括：
    设置在所述第一缓冲层中的牺牲层；
    当剥离所述衬底和所述外延片时，所述牺牲层用于减少剥离过程对所述外延片的破坏。
  8. 根据权利要求3至6任一项所述的外延片，其特征在于，还包括：
    绝缘被覆层；
    所述绝缘被覆层为介电材料；
    所述绝缘被覆层位于目标层未与其他层接触的区域表面，所述目标层为所述第一导电层、发光层、第二导电层、第一电极层和第二电极层中的至少任意一层。
  9. 根据权利要求1至8任一项所述的外延片，其特征在于，
    所述第一缓冲层与所述改善层之间的接触面为凹凸面；
    所述第一缓冲层用于接触所述改善层的一面为凸面。
  10. 根据权利要求1至8任一项所述的外延片，其特征在于，
    当所述改善层包括两个以上空隙部分时，所述两个以上空隙部分呈现有规则周期排列，包括条状排列、网状排列和/或蜂窝状排列。
  11. 一种LED芯片，其特征在于，
    所述LED芯片包括权利要求1至10任意一项所述的外延片。
  12. 一种显示屏，其特征在于，
    所述显示屏包括权利要求11所述的LED芯片。
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CN1258094A (zh) * 1998-11-26 2000-06-28 索尼株式会社 氮化物半导体的生长方法、半导体器件及其制造方法
US6475882B1 (en) * 1999-12-20 2002-11-05 Nitride Semiconductors Co., Ltd. Method for producing GaN-based compound semiconductor and GaN-based compound semiconductor device
CN1516238A (zh) * 1997-04-11 2004-07-28 ���ǻ�ѧ��ҵ��ʽ���� 氮化物半导体的生长方法、氮化物半导体衬底及器件
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CN1516238A (zh) * 1997-04-11 2004-07-28 ���ǻ�ѧ��ҵ��ʽ���� 氮化物半导体的生长方法、氮化物半导体衬底及器件
CN1258094A (zh) * 1998-11-26 2000-06-28 索尼株式会社 氮化物半导体的生长方法、半导体器件及其制造方法
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