WO2021244607A1 - 感测电路及其校正方法、像素驱动模组及其感测方法、以及显示装置 - Google Patents

感测电路及其校正方法、像素驱动模组及其感测方法、以及显示装置 Download PDF

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Publication number
WO2021244607A1
WO2021244607A1 PCT/CN2021/098116 CN2021098116W WO2021244607A1 WO 2021244607 A1 WO2021244607 A1 WO 2021244607A1 CN 2021098116 W CN2021098116 W CN 2021098116W WO 2021244607 A1 WO2021244607 A1 WO 2021244607A1
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switch
terminal
signal
transistor
gate
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PCT/CN2021/098116
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English (en)
French (fr)
Inventor
杨飞
王糖祥
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京东方科技集团股份有限公司
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Priority to US17/771,946 priority Critical patent/US11961470B2/en
Publication of WO2021244607A1 publication Critical patent/WO2021244607A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
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Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a sensing circuit and a correction method thereof, a pixel driving module and a sensing method thereof, and a display device.
  • OLED display devices have been widely cited due to their wide color gamut, wide viewing angle, thin profile, light weight, low energy consumption, high contrast, and flexibility, etc., and they are gradually becoming The development direction of future display technology.
  • OLED Organic Light-Emitting Diode
  • the characteristics of the transistors or light-emitting devices in the formed pixel circuit are unstable due to the process defects of the oxide caused during the manufacturing process.
  • external sensing is generally used to compensate for the aging of the transistors or light-emitting devices in the pixel circuit, so as to ensure the normal display of the organic light-emitting diode display device.
  • a sensing circuit including: an operational amplifier, an integrating capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a sixth switch; wherein the operational amplifier The non-inverting input terminal is connected to the first node through the first switch, the inverting input terminal is connected to the second node, and the output terminal is connected to the third node; the first pole of the integrating capacitor is connected to the second node , The second pole is connected to the third node; the first node is connected to the sensing line through the second switch, and the first node is connected to the first signal terminal through the third switch; The two nodes are connected to the sensing line through the fourth switch, the second node is connected to the second signal terminal through the fifth switch; the third node is connected to the signal output terminal of the sensing circuit And the second node is connected to the third node through the sixth switch.
  • the sensing circuit further includes: an analog-to-digital converter, the first terminal of which is connected to the third node, and the second terminal of which is connected to the signal output terminal of the sensing circuit.
  • the first signal terminal provides a constant voltage signal
  • the second signal terminal provides a constant current signal
  • a pixel driving module including the above-mentioned sensing circuit and pixel circuit
  • the pixel circuit includes a driving unit, a light emitting unit, a data writing unit, a storage unit, and a sensing unit, wherein, The control terminal of the driving unit, the second terminal of the data writing unit and the first terminal of the storage unit are connected to a fifth node, the first terminal is connected to the first voltage terminal, and the second terminal is connected to the light emitting device.
  • the first end of the unit, the first end of the sensing unit, and the second end of the storage unit are connected to the fourth node;
  • the control end of the data writing unit is connected to the first gate line end, and the first end Connected with the data line terminal;
  • the second terminal of the light emitting unit is connected with the second voltage terminal;
  • the control terminal of the sensing unit is connected with the second gate line terminal, and the second terminal is connected with the sensing line.
  • the driving unit includes: a first transistor whose gate is connected to the fifth node as the control terminal of the driving unit, and whose first pole is connected to the fifth node as the first terminal of the driving unit.
  • the data writing unit includes: a second transistor whose gate serves as the control terminal of the data writing unit Connect the first gate line terminal, the first pole of which serves as the first terminal of the data writing unit to connect to the data line terminal, and the second pole of which serves as the second terminal of the data writing unit to connect to the first terminal Five nodes
  • the storage unit includes: a storage capacitor, the first pole of which is connected to the fifth node as the first end of the storage unit, and the second pole of which is connected to the fourth node as the second end of the storage unit Node; the first pole of the light-emitting unit is connected to the fourth node as the first end of the light-emitting unit, and the second pole is connected to the
  • a display device including the pixel driving module described above, the display device further includes a display panel, a timing controller, a source driver, a gate driver, and a memory, wherein the display panel Is connected to the source driver and the gate driver, the timing controller is connected to the source driver, the gate driver, and the memory, and the sensing circuit in the pixel driving module is located In the source driver, the pixel circuit in the pixel driving module is located in the display panel, and the memory stores the threshold voltage and mobility of the first transistor and the luminous efficiency of the light-emitting unit.
  • a method for calibrating the aforementioned sensing circuit including: controlling the second switch, the third switch, the fourth switch, and the sixth switch to close; The first switch and the fifth switch are turned off, and a first voltage signal is provided to the inverting input terminal and the output terminal of the operational amplifier through the first signal terminal; the second signal of the analog-to-digital converter is obtained And calculating the correction value of the analog-to-digital converter based on the first digitized voltage signal after digitizing the first voltage signal and the first digitized output voltage signal.
  • the correction method further includes calculating a correction value of the operational amplifier, wherein calculating the correction value of the operational amplifier includes: controlling the first switch, the third switch, and the sixth switch. The switch is closed and the second switch, the fourth switch, and the fifth switch are controlled to open, and a second voltage signal is provided to the non-inverting input end of the operational amplifier through the first signal terminal; and the modulus is obtained A second digitized output voltage signal at the second end of the digital converter; and a correction based on the second digitized voltage signal after digitizing the second voltage signal, the second digitized output voltage signal, and the analog-to-digital converter Value, calculate the correction value of the operational amplifier.
  • the correction method further includes calculating a correction value of the integrating capacitor, wherein calculating the correction value of the integrating capacitor includes: controlling the first switch, the third switch, and the fifth switch.
  • calculating the correction value of the integrating capacitor includes: controlling the first switch, the third switch, and the fifth switch.
  • a third voltage signal is provided to the non-inverting input end of the operational amplifier through the first signal terminal, and the third voltage signal is provided through the second signal terminal Providing a first current signal to the integrating capacitor and the inverting input terminal of the operational amplifier; acquiring a third digitized output voltage signal at the second terminal of the analog-to-digital converter and a third digitized input voltage signal at the first terminal; And according to the third digitized voltage signal after digitizing the third voltage signal, the digitized third output voltage signal, the third digitized input voltage signal, and the capacitance of the integrating capacitor, calculate the value of the integrating capacitor Correction value.
  • a method for calibrating the above-mentioned sensing circuit including: controlling the first switch, the third switch, and the sixth switch to close and controlling the second switch, the fourth switch, and the fifth switch to open , Providing a second voltage signal to the non-inverting input terminal of the operational amplifier through the first signal terminal; acquiring the second output voltage signal of the output terminal of the operational amplifier; and according to the second voltage signal and the second output voltage signal, Calculate the correction value of the operational amplifier.
  • a method for calibrating the above-mentioned sensing circuit including: controlling the first switch, the third switch and the fifth switch to be closed and the second switch, the fourth switch and the sixth switch to open,
  • the third voltage signal is provided to the non-inverting input terminal of the operational amplifier through the first signal terminal, and the first current signal is provided to the integrating capacitor and the inverting input terminal of the operational amplifier through the second signal terminal;
  • a method for sensing the threshold voltage of the pixel driving module described above includes: a first reset stage, through a first gate line terminal and a second gate line terminal to the second The gate of the transistor and the gate of the third transistor input a turn-on signal, and control the second switch and the third switch to close and the first switch, the fourth switch, the fifth switch and the sixth switch to open, through the data line
  • the terminal inputs the first data signal to the first electrode of the second transistor to write the signal provided by the first signal terminal into the sensing line to reset the sensing line and write the first data signal
  • the storage capacitor the first charging stage, through the first gate line terminal and the second gate line terminal to input a turn-on signal to the gate of the second transistor and the gate of the third transistor, respectively,
  • the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to be turned off to write the signal provided by the first voltage terminal The sensing line; and the first sensing stage, controlling the fourth switch and the sixth switch to close
  • the sensing method further includes inputting the output terminal voltage signal of the operational amplifier to an analog-to-digital converter to convert the output terminal voltage signal of the operational amplifier into a digitized voltage signal, and according to the The first digitized data signal after the digitization of the first data signal and the digitized voltage signal of the output terminal of the operational amplifier calculate the threshold voltage of the first transistor.
  • a method for sensing the mobility of the pixel driving module described above includes: a second reset stage: The gate of the transistor and the gate of the third transistor input a turn-on signal, and control the second switch and the third switch to close and the first switch, the fourth switch, the fifth switch and the sixth switch to open, through the data line
  • the terminal inputs a second data signal to the first electrode of the second transistor to write the signal provided by the first signal terminal into the sensing line and write the second data signal into the storage capacitor; in the second charging stage, through The second gate line terminal inputs a turn-on signal to the gate of the third transistor, does not input a turn-on signal to the gate of the second transistor through the first gate line terminal, and controls the first
  • the switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are turned off to write the signal provided by the first voltage terminal to the sensing line ;
  • the second sensing stage controlling the first switch, the third switch and the fourth switch to close and the second switch, the fifth
  • the sensing method further includes inputting the output terminal voltage signal of the operational amplifier to an analog-to-digital converter to convert the output terminal voltage signal of the operational amplifier into a digitized voltage signal, and according to the The digitized second digitized data signal of the second data signal and the digitized voltage signal of the output terminal of the operational amplifier calculate the mobility of the first transistor.
  • a method for sensing the luminous efficiency of the light-emitting unit of the pixel driving module described above includes: a third reset stage, controlling the second switch and the third switch to be closed, The switch, the fifth switch and the sixth switch are turned off, and the conduction signal is input to the gate of the second transistor through the first gate line terminal, and the conduction signal is not input to the gate of the third transistor through the second gate line terminal.
  • a pass signal inputting a third data signal to the first electrode of the second transistor through the data line terminal, so as to write the signal provided by the first signal terminal into the sensing line, and write the third data signal into the storage capacitor;
  • the first gate line terminal and the second gate line terminal are not used to input turn-on signals to the gate of the second transistor and the gate of the third transistor, respectively, to control the first A switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are turned off to write the signal provided by the first voltage terminal to the fourth node;
  • a turn-on signal is input to the gate of the second transistor through the first gate line end, and a turn-on signal is not input to the gate of the third transistor through the second gate line end to control all
  • the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are turned off, and the first switch of the second transistor is connected to the first switch through the data line terminal.
  • a fourth data signal is input to the fourth node to keep the voltage of the fourth node stable; and in the third sensing stage, a turn-on signal is input to the gate of the third transistor through the second gate line terminal, and the gate of the third transistor is not passed through.
  • the first gate line terminal inputs a conduction signal to the gate of the second transistor to control the first switch, the third switch, and the fourth switch to close, and the second switch, the fifth switch.
  • the switch and the sixth switch are disconnected, the voltage of the fourth node is written into the integrating capacitor, and the luminous efficiency of the light-emitting unit is calculated according to the capacitance of the integrating capacitor and the voltage of the fourth node.
  • FIG. 1 is a schematic structural diagram of a sensing circuit according to an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of a calibration method of a sensing circuit according to an embodiment of the disclosure
  • FIG. 3 is a schematic diagram of a calibration method of a sensing circuit according to an embodiment of the disclosure
  • FIG. 4 is a schematic diagram of a calibration method of a sensing circuit according to an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a reset stage of a sensing circuit according to an embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of a pixel driving module according to an embodiment of the disclosure.
  • FIG. 7a is a flowchart of sensing a threshold voltage of a pixel driving module according to an embodiment of the disclosure
  • FIG. 7b is a schematic diagram of sensing the threshold voltage of a pixel driving module according to an embodiment of the disclosure.
  • FIG. 7c is a timing diagram of sensing the threshold voltage of the pixel driving module of FIG. 7b;
  • FIG. 8a is a flow chart of sensing the mobility of a pixel driving module according to an embodiment of the present disclosure
  • 8b is a schematic diagram of sensing the mobility of a pixel driving module according to an embodiment of the disclosure.
  • FIG. 8c is a timing diagram for sensing the mobility of the pixel driving module of FIG. 8b;
  • FIG. 9a is a flow chart of sensing the luminous efficiency of a pixel driving module according to an embodiment of the disclosure.
  • FIG. 9b is a schematic diagram of sensing the luminous efficiency of a pixel driving module according to an embodiment of the disclosure.
  • FIG. 9c is a timing diagram of sensing the luminous efficiency of the pixel driving module of FIG. 9b.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the disclosure.
  • the external sensing circuit in the related art cannot satisfy the sensing of the transistor or the light-emitting device in the pixel circuit, which affects the super-large organic light emitting diode display device.
  • the display performance of the LED display device due to the large sensing line resistance and parasitic capacitance, the external sensing circuit in the related art cannot satisfy the sensing of the transistor or the light-emitting device in the pixel circuit, which affects the super-large organic light emitting diode display device.
  • the display performance of the LED display device due to the large sensing line resistance and parasitic capacitance
  • the sensing circuit includes an operational amplifier AMP, an integrating capacitor Cfb, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a sixth switch S6.
  • the non-inverting input terminal of the operational amplifier AMP is connected to the first node N1 through the first switch S1, the inverting input terminal is connected to the second node N2, and the output terminal is connected to the third node N3.
  • the first pole of the integrating capacitor Cfb is connected to the second node N2, and the second pole of the integrating capacitor Cfb is connected to the third node N3.
  • the first node N1 is connected to the sensing line SL through the second switch S2, and the first node N1 is connected to the first signal terminal Vref through the third switch S3.
  • the second node N2 is connected to the sensing line SL through the fourth switch S4, and the second node N2 is connected to the second signal terminal Iref through the fifth switch S5.
  • the third node N3 is connected to the signal output terminal of the sensing circuit.
  • the second node N2 is connected to the third node N3 through the sixth switch S6.
  • each of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 can be realized, so that the sensing line can be realized.
  • Different connection states between SL, operational amplifier AMP and integrating capacitor Cfb Further, according to the signal provided from the first signal terminal Vref and the second signal terminal Iref, and the combined state of each switch on and off, the operational amplifier AMP and the integrating capacitor Cfb can be corrected. The correction of the operational amplifier AMP and the integrating capacitor Cfb will be described in detail below.
  • the sensing circuit further includes: an analog-to-digital converter ADC, the first end of which is connected to the third node N3, and the second end of which is connected to the signal output end of the sensing circuit for analog-to-digital conversion of the signal from the third node N3. Number conversion.
  • ADC analog-to-digital converter
  • a constant voltage signal is provided through the first signal terminal Vref, and a constant current signal is provided through the second signal terminal Iref.
  • the sensing circuit of this embodiment can be applied to an organic light emitting diode display device, and is especially suitable for a larger size organic light emitting diode display device. It can sense transistors or light emitting devices in the pixel circuit of the organic light emitting diode display device. Therefore, the display performance of the organic light emitting diode display device is ensured.
  • the sensing of the transistor or the light emitting device in the pixel circuit of the organic light emitting diode display device will be described in detail below.
  • a method for calibrating a sensing circuit is also provided for calibrating the analog-to-digital converter ADC therein.
  • the method for correcting the analog-to-digital converter ADC includes: controlling the second switch S2, the third switch S3, the fourth switch S4, and the sixth switch S6 to be closed, and the first The switch S1 and the fifth switch S5 are disconnected, and the first voltage signal V1 is provided to the inverting input terminal and output terminal of the operational amplifier AMP through the first signal terminal Vref; then the second terminal (signal output terminal) of the analog-to-digital converter ADC is obtained.
  • the output digitized first digitized output voltage D1' The output digitized first digitized output voltage D1'.
  • the correction value C ADC of the analog-to-digital converter ADC is calculated according to the first digitized voltage signal D1 and the first output voltage signal D1' after digitizing the first voltage signal V1.
  • the first digitized voltage signal D1 is obtained through idealized analog-to-digital processing of the first voltage signal V1.
  • the first switch S1 and the fifth switch S5 off, and keep the second switch S2, the third switch S3, the fourth switch S4, and the sixth switch S6 is closed.
  • the first voltage signal V1 from the first signal terminal Vref sequentially passes through the third switch S3, the second switch S2, the fourth switch S4, and the sixth switch S6 to the third node N3.
  • the third node N3 is the first voltage signal V1, that is, the input signal of the analog-to-digital converter ADC is the first voltage signal V1.
  • the first voltage signal V1 from the first signal terminal Vref is converted into an ideal first digitized output voltage D1 after digital-to-analog conversion.
  • the present disclosure also provides a method for calibrating the sensing circuit, which is used to calibrate the operational amplifier AMP therein.
  • the correction method of the operational amplifier AMP includes: controlling the first switch S1, the third switch S3, and the sixth switch S6 to close, and the second switch S2 and the fourth switch S4
  • the fifth switch S5 is disconnected, and the second voltage signal V2 is provided to the non-inverting input terminal of the operational amplifier AMP through the first signal terminal Vref; then the second digitized output voltage D2' of the second terminal of the analog-to-digital converter ADC is obtained; finally,
  • the correction value C AMP of the operational amplifier AMP is calculated according to the second digitized voltage signal D2, the second digitized output voltage signal D2' and the correction value of the analog-to-digital converter ADC after the digitization of the second voltage signal V2.
  • the operational amplifier AMP outputs the second output voltage to the first terminal (input terminal) of the analog-to-digital converter ADC in a voltage following manner.
  • the second voltage signal V2 at the first signal terminal Vref corresponds to the second digitized ideal output voltage D2
  • the present disclosure also provides a correction method of the sensing circuit for calculating the correction value of the integrating capacitor Cfb.
  • the method of calculating the correction value of the integrating capacitor Cfb includes: controlling the first switch S1, the third switch S3, and the fifth switch S5 to be closed, and the second switch S2, the fourth switch S2, and the fourth switch S5 are closed.
  • the switch S4 and the sixth switch S6 are disconnected, and the first current signal is provided to the integrating capacitor Cfb and the inverting input terminal of the operational amplifier AMP through the second signal terminal Iref, and the non-inverting input terminal of the operational amplifier AMP is provided through the first signal terminal Vref
  • the third voltage signal V3 then, the third digitized output voltage signal d3' at the second end of the analog-to-digital converter ADC and the third digitized input voltage signal d3 at the first end (that is, the third output voltage of the output of the operational amplifier AMP is obtained) v3 corresponding digitized output voltage); finally, according to the third digitized voltage signal D3 after digitizing the third voltage signal V3, the third digitized output voltage signal d3', the third digitized input voltage signal d3 and the capacitance of the integrating capacitor Cfb , Calculate the correction value of the integrating capacitor Cfb.
  • the third digitized input voltage signal d3 is obtained by performing idealized analog
  • the first current signal I1 is written into the integrating capacitor Cfb.
  • the third voltage signal V3 is sequentially supplied to the non-inverting input terminal of the operational amplifier AMP through the third switch S3 and the first switch S1, and from the second signal terminal Iref, the first current signal I1 is passed through the fifth switch S5 Provided to the integrating capacitor Cfb.
  • the output terminal of the operational amplifier AMP outputs a third output voltage v3 to the analog-to-digital converter ADC, and the analog-to-digital converter ADC outputs a digitized third output voltage d3'.
  • the third output voltage v3 corresponds to the third ideal output voltage d3.
  • the present disclosure also provides a method for calibrating the sensing circuit, which is used to calibrate the operational amplifier AMP therein.
  • the correction method of the operational amplifier AMP includes: controlling the first switch S1, the third switch S3, and the sixth switch S6 to be closed, and the second switch S2, the fourth switch S4 and the fifth switch S5 are disconnected, and the second voltage signal V2 is provided to the non-inverting input terminal of the operational amplifier AMP through the first signal terminal Vref; then the second output voltage of the output terminal of the operational amplifier AMP is obtained; finally, according to the second voltage signal And the second output voltage signal to calculate the correction value C AMP of the operational amplifier AMP.
  • This method does not require an analog-to-digital converter ADC to digitize the voltage signal.
  • the present disclosure also provides a correction method of the sensing circuit for calculating the correction value of the integrating capacitor Cfb.
  • the method for calculating the correction value of the integrating capacitor Cfb includes: controlling the first switch S1, the third switch S3, and the fifth switch S5 to close, and the second switch S2, the second switch S2, and the second switch S2.
  • the fourth switch S4 and the sixth switch S6 are turned off, the first current signal is provided to the integrating capacitor Cfb through the second signal terminal Iref, and the third voltage signal V3 is provided to the non-inverting input terminal of the operational amplifier AMP through the first signal terminal Vref; then, The third output voltage signal of the output terminal of the operational amplifier AMP is obtained; finally, the correction value of the integrating capacitor Cfb is calculated according to the third voltage signal V3, the third output voltage signal and the capacitance of the integrating capacitor Cfb.
  • This method does not require an analog-to-digital converter ADC to digitize the voltage signal.
  • the present disclosure also provides a pixel driving module, which includes the aforementioned sensing circuit and pixel circuit.
  • the pixel circuit includes a driving unit, a light emitting unit 1, a data writing unit, a storage unit, and a sensing unit.
  • the control terminal of the driving unit and the second terminal of the data writing unit and the first terminal of the storage unit are connected to the fifth node N5, the first terminal is connected to the first voltage terminal ELVDD, and the second terminal is connected to the first terminal of the light emitting unit.
  • the terminal, the first terminal of the sensing unit and the second terminal of the storage unit are connected to the fourth node N4 for driving the light-emitting unit 1 to emit light.
  • the control terminal of the data writing unit is connected to the first gate line terminal GL1, and the first terminal is connected to the data line terminal DL for writing the data signal of the data line terminal DL to the control terminal of the driving unit through the adjustment of the memory cell.
  • the control terminal of the sensing unit is connected to the second gate line terminal GL2, and the second terminal is connected to the sensing line SL for inputting the signal of the fourth node N4 to the sensing line SL, so as to use the sensing circuit to perform the driving unit Sensing.
  • the second terminal of the light-emitting unit is connected to the second voltage terminal ELVSS.
  • the driving unit includes: a first transistor T1, the gate of which serves as the control terminal of the driving unit is connected to the fifth node N5, the first electrode of which serves as the first terminal of the driving unit is connected to the first voltage terminal ELVDD, and the second electrode The second end as the driving unit is connected to the fourth node N4.
  • the data writing unit includes a second transistor T2, the gate of which serves as the control terminal of the data writing unit is connected to the first gate line terminal GL1, and the first pole of which serves as the first terminal of the data writing unit is connected to the data line terminal DL.
  • the second end of the two poles as the data writing unit is connected to the fifth node N5.
  • the memory cell includes a storage capacitor Cst, the first terminal of which serves as the memory cell is connected to the fifth node N5, and the second pole of which serves as the second terminal of the light-emitting unit is connected to the fourth node N4.
  • the first pole of the light-emitting unit 1 is connected to the fourth node N4 as the first terminal of the light-emitting unit, and the second terminal of the light-emitting unit 1 is connected to the second voltage terminal ELVSS.
  • the sensing unit includes a third transistor T3, the gate of which serves as the control terminal of the sensing unit is connected to the second gate line terminal GL2, the first pole of which serves as the first terminal of the sensing unit is connected to the fourth node N4, and the second pole of which is connected to the fourth node N4.
  • the second end of the sensing unit is connected to the sensing line SL.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all N-type transistors; or, the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type transistors.
  • the present disclosure takes the above-mentioned transistors as N-type transistors as an example, so the on-signal is a high-level signal, and the off-signal is a low-level signal.
  • the first voltage terminal ELVDD is used to provide a working voltage
  • the second voltage terminal ELVSS is used to provide a reference voltage
  • the display device may include a plurality of sensing lines SL, one of the plurality of sensing lines SL may be connected to at least one column of sub-pixels, and at least one of the plurality of sensing lines SL may be connected to one sensor. Therefore, one sensing circuit can be connected to at least one column of sub-pixels, but the present disclosure is not limited to this.
  • the light-emitting unit 1 in this embodiment may be a current-driven light-emitting device including LED (Light Emitting Diode) or OLED (Organic Light Emitting Diode).
  • LED Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • the description is based on OLED as an example.
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 can be any controllable switching devices.
  • the pixel driving module of this embodiment can be applied to an organic light emitting diode display device, especially suitable for a larger size organic light emitting diode display device, for sensing transistors or light emitting devices in the pixel circuit of the organic light emitting diode display device, Therefore, the display performance of the organic light emitting diode display device is ensured.
  • the organic light emitting diode display device includes a plurality of pixel circuits distributed in an array to realize display.
  • the sensing circuit can have a one-to-one correspondence with the pixel circuit, or several rows or parts of the pixel circuit can correspond to one sensing circuit, which can be determined according to actual conditions.
  • a display device is provided. As shown in Figure 10, the display device is mainly composed of a display panel, a timing controller, a source driver, a gate driver, a memory, etc.
  • the display panel is connected to the source driver and the gate driver, and the timing controller is connected to the source driver,
  • the gate driver and the memory are connected, and the sensing circuit may be located in the source driver, and the pixel circuit may be located in the display panel.
  • the timing controller reads the data stored in the memory (RAM), and at the same time receives externally input data (RGB), timing control signals (Timing), and sensing data (SData) output by the source driver. After calculation, conversion, compensation and other processing procedures, the timing controller generates data (Data) and source control signals (SCS, Source Control Signal) after compensation calculations and outputs them to the source driver. The timing controller generates a gate control signal (GCS, Gate Control Signal) and outputs it to the gate driver.
  • GCS Gate Control Signal
  • the memory can store pixel compensation values of one or more pixel circuits, such as the threshold voltage Vth and mobility K of the first transistor T1 that controls the light-emitting unit 1 of the pixel circuit to emit light, and the light-emitting efficiency of the light-emitting unit.
  • the source driver receives the compensated data (Data) and the source number control signal (SCS) output by the timing controller, and the generated data signal (Vdata) is output to the display panel through the data line (DL).
  • the sensing circuit under the control of the source control signal (SCS), the sensing circuit is controlled to realize the correction function of the analog-to-digital converter ADC, operational amplifier AMP, and integrating capacitor Cfb of the sensing circuit, and realize the reset and reset of the sensing line SL. Charging function, etc.
  • the characteristic value of a certain row or a certain part of the pixel circuit is sensed through the sensing line SL, and the sensing data (SData) generated by the analog-to-digital converter ADC is output to the timing controller.
  • the gate driver receives the gate control signal (GCS), generates a scan signal corresponding to at least one scan line (GL1, GL2, GL3, etc.) and outputs it to the display panel.
  • GCS gate control signal
  • the organic light emitting diode display device may be any product or component with display function such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc.
  • the present disclosure also provides a method for sensing the threshold voltage of the above-mentioned pixel driving module. As shown in Figure 7a, the method includes steps S10 to S14.
  • step S10 that is, the first reset stage a1
  • a turn-on signal is input to the gate of the second transistor T1 and the gate of the third transistor T3 through the first gate line terminal GL1 and the second gate line terminal GL2, respectively, and controls the first gate line terminal GL1 and the second gate line terminal GL2.
  • the second switch S2 and the third switch S3 are closed and the first switch S1, the fourth switch S4, the fifth switch S5 and the sixth switch S6 are opened, and the first data is input to the first pole of the second transistor T2 through the data line terminal DL
  • the signal Vdata is used to write the signal of the first signal terminal Vref into the sensing line SL to reset the sensing line SL, and write the first data signal Vdata into the storage capacitor Cst.
  • the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are inputted with disconnection signals, and the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are turned off. Open; Input a conduction signal to the second switch S2 and the third switch S3, and the second switch S2 and the third switch S3 are closed.
  • the second transistor T2 and the third transistor T3 are turned on.
  • the first data signal Vdata is written into the storage capacitor Cst through the data line terminal DL
  • the constant voltage signal is written into the sensing line SL through the first signal terminal Vref.
  • this stage is equivalent to the sensing circuit resetting the sensing line SL, that is, the sensing circuit has a function of resetting the sensing line SL.
  • step S12 that is, the first charging stage a2
  • the first gate line terminal GL1 and the second gate line terminal GL2 respectively input turn-on signals to the gate of the second transistor T2 and the gate of the third transistor T3 to control the first
  • the switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are turned off to write the signal provided by the first voltage terminal ELVDD into the sensing line SL.
  • the first transistor T1 is turned on, and the signal from the first voltage terminal ELVDD causes the current to pass through the first transistor T1 and the third transistor T3 to the sensing line SL in turn, and make the sense The voltage on the measuring line SL continues to rise.
  • step S14 the first sensing stage a3, the fourth switch S4 and the sixth switch S6 are controlled to be closed, and the first switch S1, the second switch S2, the third switch S3, and the fifth switch S5 are opened.
  • the gate line terminal and the second gate line terminal input turn-on signals to the gate of the second transistor T2 and the gate of the third transistor T3, respectively, and the signal of the sensing line SL passes through the operational amplifier AMP and is output by the analog-to-digital converter ADC.
  • the voltage signal at the output terminal of the operational amplifier AMP is acquired to calculate the threshold voltage of the first transistor T1 according to the first data signal and the voltage signal at the output terminal of the operational amplifier AMP.
  • the present disclosure also provides a method for sensing the mobility of the aforementioned pixel driving module. As shown in Fig. 8a, the method includes steps S20 to S24.
  • step S20 that is, the second reset stage b1, through the first gate line terminal GL1 and the second gate line terminal GL2, respectively write turn-on signals to the gate of the second transistor T2 and the gate of the third transistor T3, and control
  • the second switch S2, the third switch S3 are closed and the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are opened, and the second data is input to the gate of the third transistor T3 through the data line terminal DL
  • the signal Vdata+Vth is used to write the signal of the first signal terminal Vref into the sensing line SL and the second data signal into the storage capacitor Cst.
  • the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are inputted with an off signal, and the first switch S1, the fourth switch S4, and the fifth switch S5, the sixth switch S6 is turned off.
  • a turn-on signal is input to the first gate line terminal GL1, the second gate line terminal GL2, the second switch S2, and the third switch S3, and the second transistor T2, the third transistor T3, the second switch S2, and the third switch S3 are turned on ,
  • the second data signal Vdata+Vth is written into the storage capacitor Cst through the data line terminal DL, and a constant voltage signal is written into the sensing line SL from the first signal terminal Vref.
  • this stage is equivalent to the sensing circuit resetting the sensing line SL, that is, the sensing circuit has a function of resetting the sensing line SL.
  • step S22 that is, the second charging stage b2
  • the conduction signal is input to the gate of the third transistor T3 through the second gate line terminal GL2, and the conduction signal is not written to the gate of the second transistor T2 through the first gate line terminal GL1.
  • an off signal is input to the first gate line terminal GL1, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6, and the second transistor T2 ,
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are turned off, which is equivalent to floating on the sensing line SL of the sensing circuit, that is, the sensing circuit It has the function of floating to the sensing line SL.
  • a turn-on signal is input to the second gate line terminal GL2, and the third transistor T3 is turned on.
  • the first transistor T1 is turned on, and the signal from the first voltage terminal ELVDD causes current to pass through the first transistor T1 and the third transistor T3 in turn and write to the sensing line SL, and sense The voltage on the measuring line SL continues to rise.
  • step S24 the second sensing stage b3, the first switch S1, the third switch S3, and the fourth switch S4 are controlled to be closed, and the second switch S2, the fifth switch S5, and the sixth switch S6 are opened.
  • the gate line terminal GL1 and the second gate line terminal GL2 input conduction signals to the gate of the second transistor T2 and the gate of the third transistor T3, and the signal of the sensing line SL passes through the operational amplifier AMP and is output by the analog-to-digital converter ADC .
  • the voltage signal at the output terminal of the operational amplifier AMP is acquired to calculate the mobility of the first transistor T1 according to the second data signal and the voltage signal at the output terminal of the operational amplifier AMP.
  • an off signal is input to the first gate line terminal GL1, the second gate line terminal GL2, the second switch S2, the fifth switch S5, and the sixth switch S6.
  • the three transistors T3, the second switch S2, the fifth switch S5, and the sixth switch S6 are turned off.
  • the first switch S1, the third switch S3, and the fourth switch S4 are turned on.
  • the voltage of the sensing line SL remains unchanged, and in turn
  • the fourth switch S4 and the storage capacitor Cfb reach the analog-to-digital converter ADC to output a corresponding voltage.
  • the corresponding voltage can reflect the current passing through the first transistor T1.
  • the voltage signal at the output terminal of the operational amplifier AMP is acquired to calculate the mobility K of the first transistor T1 according to the second data signal and the voltage signal at the output terminal of the operational amplifier AMP.
  • the present disclosure also provides a method for sensing the luminous efficiency of the light-emitting unit 1 of the above-mentioned pixel driving module. As shown in Figure 9a, the method includes steps S30 to S36.
  • step S30 the third reset stage c1, the second switch S2 and the third switch S3 are controlled to be closed, and the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are opened, passing the first gate line
  • the terminal GL1 inputs a turn-on signal to the gate of the second transistor T2, does not write a turn-on signal to the gate of the third transistor T3 through the second gate line terminal GL2, and sends a turn-on signal to the first transistor T2 through the data line terminal DL.
  • the third data signal Vdata+Vth is input to the first signal terminal Vref to write the signal of the first signal terminal Vref into the sensing line SL, and the third data signal Vdata+Vth is written into the storage capacitor Cst.
  • an off signal is input to the second gate line terminal GL2, the first switch S1, the fourth switch S4, the fifth switch S5, and the sixth switch S6, and the third transistor T3, the first switch S1, and the fourth switch S4 ,
  • the fifth switch S5 and the sixth switch S6 are turned off.
  • a turn-on signal is input to the first gate line terminal GL1, the second switch S2, and the third switch S3.
  • the second transistor T2, the second switch S2, and the third switch S3 are turned on, and the third data signal from the data line terminal DL is turned on.
  • Vdata+Vth is written into the storage capacitor Cst, and at the same time a constant voltage signal from the first signal terminal Vref is written into the sensing line SL.
  • this stage is equivalent to the sensing circuit resetting the sensing line SL, that is, the sensing circuit has a function of resetting the sensing line SL.
  • step S32 that is, the third charging stage c2, the gate line terminal GL1 and the second gate line terminal GL2 are not used to input turn-on signals to the gate of the second transistor T2 and the gate of the third transistor T3, respectively, to control the first gate line terminal GL1 and the second gate line terminal GL2.
  • a switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, and a sixth switch S6 are turned off to write the signal from the first voltage terminal ELVDD to the fourth node N4.
  • step S34 which is the stabilization phase c3, a turn-on signal is input to the gate of the second transistor T2 through the first gate line terminal GL1, and a turn-on signal is not written to the gate of the third transistor T3 through the second gate line terminal GL2 ,
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are controlled to be turned off, and the first switch is input to the first pole of the second transistor T2 through the data line terminal DL.
  • Four data signals to keep the voltage of the fourth node N4 stable.
  • an off signal is input to the second gate line terminal GL2, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6, and the third transistor T3 ,
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the sixth switch S6 are turned off.
  • a turn-on signal is input to the gate of the second transistor T2 through the first gate line terminal GL1, and the second transistor T2 is turned on.
  • the fourth data signal is input to the first electrode of the second transistor T2 through the data line terminal DL, and the fourth data signal has a voltage of 0V, so that the first transistor T1 is turned off and the voltage of the fourth node N4 remains unchanged.
  • step S36 which is the third sensing stage c4, write a turn-on signal to the gate of the third transistor T3 through the second gate line terminal GL2, and not input to the gate of the second transistor T2 through the first gate line terminal GL1
  • the turn-on signal controls the first switch S1, the third switch S3, and the fourth switch S4 to close and the second switch S2, the fifth switch S5 and the sixth switch S6 to open, and write the voltage of the fourth node N4 into the integrating capacitor Cfb .
  • the luminous efficiency of the light-emitting unit 1 is calculated.
  • an off signal is input to the first gate line terminal GL1, the second switch S2, the fifth switch S5, and the sixth switch S6, and the second transistor T2, the second switch S2, and the fifth switch S5, the sixth switch S6 is turned off.
  • An on signal is input to the second gate line terminal GL2, the first switch S1, the third switch S3, and the fourth switch S4.
  • the third transistor T3, the first switch S1, the third switch S3, and the fourth switch S4 are turned on.
  • the voltage of the four node N4 is written into the integrating capacitor Cfb through the fourth switch S4, and the luminous efficiency of the light emitting unit 1 is obtained according to the capacitance of the sensing integrating capacitor Cfb and the voltage of the fourth node.

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Abstract

一种感测电路及其校正方法、像素驱动模组及其感测方法、以及显示装置，感测电路包括：运算放大器(AMP)、积分电容器(Cfb)、第一开关(S1)、第二开关(S2)、第三开关(S3)、第四开关(S4)、第五开关(S5)和第六开关(S6)。

Description

感测电路及其校正方法、像素驱动模组及其感测方法、以及显示装置
相关申请的交叉引用
本申请要求于2020年6月4日在中国知识产权局提交的No.202010501623.2的中国专利申请的优先权，该中国专利申请的全部内容通过引用合并于此。
技术领域
本公开属于显示技术领域，具体涉及一种感测电路及其校正方法、像素驱动模组及其感测方法、以及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示装置由于具有广色域、广视角、薄型化、轻型化、低耗能、高对比度、可弯曲等优点，而被广泛引用，且其逐渐成为未来显示技术的发展方向。对于大尺寸有机发光二极管显示装置而言，由于其制备过程中导致的氧化物的工艺缺陷，使得形成的像素电路中的晶体管或者发光器件的特性不稳定。在相关技术中，一般采用外部感测的方式来补偿像素电路中的晶体管或者发光器件的老化，以保证有机发光二极管显示装置的正常显示。
发明内容
在一个方面，提供了一种感测电路，包括：运算放大器、积分电容器、第一开关、第二开关、第三开关、第四开关、第五开关和第六开关；其中，所述运算放大器的同相输入端通过所述第一开关与第一节点连接，其反相输入端与第二节点连接，其输出端与第三节点连接；所述积分电容器的第一极连接所述第二节点，其第二极连接所述第三节点；所述第一节点通过所述第二开关与感测线连接，所述第一节点通过所述第三开关与第一信号端连接；所述第二节点通过所述第四开关与所述感测线连接，所述第二节点通过所述第五开关与第二信号端连接；所述第三节点与所述感测电路的信号输出端连接；以及所述第二 节点通过所述第六开关与所述第三节点连接。
在一些实施例中，所述感测电路还包括：模数转换器，其第一端连接所述第三节点，第二端连接所述感测电路的信号输出端。
在一些实施例中，所述第一信号端提供恒定电压信号，所述第二信号端提供恒定电流信号。
在一个方面，提供了一种像素驱动模组，包括以上所述的感测电路以及像素电路，所述像素电路包括驱动单元、发光单元、数据写入单元、存储单元和感测单元，其中，所述驱动单元的控制端与所述数据写入单元的第二端和所述存储单元的第一端连接于第五节点，第一端与第一电压端连接，第二端与所述发光单元的第一端、所述感测单元的第一端和所述存储单元的第二端连接于第四节点；所述数据写入单元的控制端与第一栅线端连接，第一端与数据线端连接；所述发光单元的第二端与第二电压端连接；以及所述感测单元的控制端与第二栅线端连接，第二端与感测线连接。
在一些实施例中，所述驱动单元包括：第一晶体管，其栅极作为所述驱动单元的控制端连接所述第五节点，其第一极作为所述驱动单元的第一端连接所述第一电压端，其第二极作为所述驱动单元的第二端连接所述第四节点；所述数据写入单元包括：第二晶体管，其栅极作为所述数据写入单元的控制端连接所述第一栅线端，其第一极作为所述数据写入单元的第一端连接所述数据线端，其第二极作为所述数据写入单元的第二端连接所述第五节点；所述存储单元包括：存储电容器，其第一极作为所述存储单元的第一端连接所述第五节点，其第二极作为所述存储单元的第二端连接所述第四节点；所述发光单元的第一极作为所述发光单元的第一端连接所述第四节点，第二极作为所述发光单元的第二端连接所述第二电压端；以及所述感测单元包括：第三晶体管，其栅极作为所述感测单元的控制端连接所述第二栅线端，其第一极作为所述感测单元的第一端连接所述第四节点，其第二极作为所述感测单元的第二端连接所述感测线。
在一个方面，提供了一种显示装置，包括以上所述的像素驱动模组，所述显示装置还包括显示面板、时序控制器、源极驱动器、栅极驱动器和存储器，其中，所述显示面板与所述源极驱动器和所述栅极驱动器连接，所述时序控制器与所述源极驱动器、所述栅极驱动器和所述存储器连接，并且所述像素驱动模组中的感测电路位于所述源极驱动器中，所述像素驱动模组中的像素电路位于所述显示面板中，所述存储器存储有所述第一晶体管的阈值电压和迁移率以及所述发光单元的发光效率。
在一些实施例中，提供了一种对以上所述的感测电路的校正方法，包括：控制所述第二开关、所述第三开关、所述第四开关和所述第六开关闭合以及所述第一开关和所述第五开关断开，通过所述第一信号端向所述运算放大器的反相输入端和输出端提供第一电压信号；获取所述模数转换器的第二端的第一数字化输出电压信号；以及根据对所述第一电压信号数字化处理后的第一数字化电压信号和所述第一数字化输出电压信号，计算所述模数转换器的校正值。
在一些实施例中，所述校正方法还包括计算所述运算放大器的校正值，其中，计算所述运算放大器的校正值包括：控制所述第一开关、所述第三开关和所述第六开关闭合以及控制所述第二开关、所述第四开关和所述第五开关断开，通过所述第一信号端向所述运算放大器的同相输入端提供第二电压信号；获取所述模数转换器的第二端的第二数字化输出电压信号；以及根据对所述第二电压信号数字化处理后的第二数字化电压信号、所述第二数字化输出电压信号以及所述模数转换器的校正值，计算所述运算放大器的校正值。
在一些实施例中，所述校正方法还包括计算所述积分电容器的校正值，其中，计算所述积分电容器的校正值包括：控制所述第一开关、所述第三开关和所述第五开关闭合以及所述第二开关、所述第四开关和所述第六开关断开，通过所述第一信号端向所述运算放大器的同相输入端提供第三电压信号，通过第二信号端向所述积分电容器和所述运算放大器的反相输入端提供第一电流信号；获取所述模数转换器的第二端的第三数字化输出电压信号和第一端的第三 数字化输入电压信号；以及根据对所述第三电压信号数字化处理后的第三数字化电压信号、所述数字化第三输出电压信号、所述第三数字化输入电压信号以及所述积分电容器的电容，计算所述积分电容器的校正值。
在一个方面，提供了一种对以上所述的感测电路的校正方法，包括：控制第一开关、第三开关和第六开关闭合以及控制第二开关、第四开关和第五开关断开，通过第一信号端向运算放大器的同相输入端提供第二电压信号；获取所述运算放大器的输出端的第二输出电压信号；以及根据所述第二电压信号和所述第二输出电压信号，计算所述运算放大器的校正值。
在一个方面，提供了一种对以上所述的感测电路的校正方法，包括：控制第一开关、第三开关和第五开关闭合以及第二开关、第四开关和第六开关断开，通过第一信号端向运算放大器的同相输入端提供第三电压信号，通过第二信号端向积分电容器和所述运算放大器的反相输入端提供第一电流信号；获取所述运算放大器的输出端的第三输出电压信号；以及根据所述第三电压信号、所述第三输出电压信号以及所述积分电容器的电容，计算所述积分电容器的校正值。
在一个方面，提供了一种对以上所述的像素驱动模组的阈值电压的感测方法，包括：第一复位阶段，通过第一栅线端和第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，并控制第二开关和第三开关闭合以及第一开关、第四开关、第五开关和第六开关断开，通过数据线端向所述第二晶体管的第一极输入第一数据信号，以将第一信号端提供的信号写入感测线来对所述感测线进行复位，将所述第一数据信号写入所述存储电容器；第一充电阶段，通过所述第一栅线端和所述第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，控制所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开，以将第一电压端提供的信号写入所述感测线；以及第一感测阶段，控制所述第四开关和第六开关闭合以及所述第一开关、所述第二开关、所述第三开关和所述第五开关断开，不通过所述第一栅线端和所述第二栅线端分别向所述第二晶体管 的栅极和所述第三晶体管的栅极输入导通信号，并获取运算放大器的输出端电压信号，以根据所述第一数据信号和所述运算放大器的输出端电压信号，计算所述第一晶体管的阈值电压。
在一些实施例中，所述感测方法还包括将所述运算放大器的输出端电压信号输入至模数转换器，以将所述运算放大器的输出端电压信号转换为数字化电压信号，并根据对所述第一数据信号数字化处理后的第一数字化数据信号和所述运算放大器的输出端的数字化电压信号计算所述第一晶体管的阈值电压。
在一个方面，提供了一种对以上所述的像素驱动模组的迁移率的感测方法，包括：第二复位阶段，通过第一栅线端和第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，并控制第二开关和第三开关闭合以及第一开关、第四开关、第五开关和第六开关断开，通过数据线端向所述第二晶体管的第一极输入第二数据信号，以将第一信号端提供的信号写入感测线，将所述第二数据信号写入存储电容器；第二充电阶段，通过所述第二栅线端向所述第三晶体管的栅极输入导通信号，不通过所述第一栅线端向所述第二晶体管的栅极输入导通信号，并且控制所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开，以将第一电压端提供的信号写入所述感测线；以及第二感测阶段，控制所述第一开关、所述第三开关和所述第四开关闭合以及所述第二开关、所述第五开关和所述第六开关断开，不通过所述第一栅线端和所述第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，并获取所述运算放大器的输出端电压信号，以根据所述第二数据信号和所述运算放大器的输出端电压信号，计算所述第一晶体管的迁移率。
在一些实施例中，所述感测方法还包括将所述运算放大器的输出端电压信号输入至模数转换器，以将所述运算放大器的输出端电压信号转换为数字化电压信号，并根据对所述第二数据信号的数字化处理后的第二数字化数据信号和所述运算放大器的输出端的数字化电压信号计算所述第一晶体管的迁移率。
在一个方面，提供了一种对以上所述的像素驱动模组的发光单元发光效率的感测方法，包括：第三复位阶段，控制第二开关和第三开关闭合以及第一开关、第四开关、第五开关和第六开关断开，通过第一栅线端向所述第二晶体管的栅极输入导通信号，不通过第二栅线端向所述第三晶体管的栅极输入导通信号，通过数据线端向所述第二晶体管的第一极输入第三数据信号，以将第一信号端提供的信号写入感测线，将所述第三数据信号写入存储电容器；第三充电阶段，不通过所述第一栅线端和所述第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，控制所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开，以将第一电压端提供的信号写入第四节点；稳定阶段，通过所述第一栅线端向所述第二晶体管的栅极输入导通信号，不通过所述第二栅线端向所述第三晶体管的栅极输入导通信号，控制所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开，通过数据线端向所述第二晶体管的第一极输入第四数据信号，以保持所述第四节点的电压稳定；以及第三感测阶段，通过所述第二栅线端向所述第三晶体管的栅极输入导通信号，不通过所述第一栅线端向所述第二晶体管的栅极输入导通信号，控制所述第一开关、所述第三开关和所述第四开关闭合以及所述第二开关、所述第五开关和所述第六开关断开，将所述第四节点的电压写入积分电容器，并根据所述积分电容器的电容以及所述第四节点的电压，计算发光单元的发光效率。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开的实施例的一种感测电路的结构示意图；
图2为本公开的实施例的一种感测电路的校正方法的示意图；
图3为本公开的实施例的一种感测电路的校正方法的示意图；
图4为本公开的实施例的一种感测电路的校正方法的示意图；
图5为本公开的实施例的一种感测电路的复位阶段的示意图；
图6为本公开的实施例的一种像素驱动模组的结构示意图；
图7a为本公开的实施例的一种像素驱动模组的阈值电压的感测流程图；
图7b为本公开的实施例的一种像素驱动模组的阈值电压的感测示意图；
图7c为图7b的像素驱动模组的阈值电压的感测时序图；
图8a为本公开的实施例的一种像素驱动模组的迁移率的感测流程图；
图8b为本公开的实施例的一种像素驱动模组的迁移率的感测示意图；
图8c为图8b的像素驱动模组的迁移率的感测时序图；
图9a为本公开的实施例的一种像素驱动模组的发光效率的感测流程图；
图9b为本公开的实施例的一种像素驱动模组的发光效率的感测示意图；
图9c为图9b的像素驱动模组的发光效率的感测时序图；以及
图10为本公开的实施例的一种显示装置的结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
以下将参照附图更详细地描述本公开。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，在图中可能未示出某些公知的部分。
在下文中描述了本公开的许多特定的细节，例如部件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
对于超大尺寸有机发光二极管显示装置，因其感测线电阻和寄生电容较大，相关技术中的外部感测电路不能满足对其像素电路中的晶体管或者发光器件的感测，从而影响超大尺寸有机发光二极管显示装置的显示性能。
因此，根据本公开的一个方面，提供了一种感测电路。如1图所示，该感测电路包括：运算放大器AMP、积分电容器Cfb、第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6。
运算放大器AMP的同相输入端通过第一开关S1与第一节点N1连接，其反相输入端与第二节点N2连接，其输出端与第三节点N3连接。
积分电容器Cfb的第一极连接第二节点N2，其第二极连接第三节点N3。
第一节点N1通过第二开关S2与感测线SL连接，第一节点N1通过第三开关S3与第一信号端Vref连接。
第二节点N2通过第四开关S4与感测线SL连接，第二节点N2通过第五开关S5与第二信号端Iref连接。
第三节点N3与感测电路的信号输出端连接。
第二节点N2通过第六开关S6与第三节点N3连接。
通过控制，可以实现第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5和第六开关S6中的每一个的断开和闭合，从而可以实现感测线SL、运算放大器AMP和积分电容器Cfb之间的不同连接状态。进一步地，根据从第一信号端Vref和第二信号端Iref提供的信号、以及各个开关的闭合和断开的组合状态，可以实现对运算放大器AMP和积分电容器Cfb的校正。对运算放大器AMP和积分电容器Cfb的校正将在下文进行详细描述。
可选的，该感测电路还包括：模数转换器ADC，其第一端连接第三节点N3，第二端连接感测电路的信号输出端，用于将第三节点N3的信号进行模数转换。
可选的，通过第一信号端Vref提供恒定电压信号，通过第二信号端Iref提供恒定电流信号。
本实施例的感测电路能够应用于有机发光二极管显示装置，尤其适用于尺寸较大的有机发光二极管显示装置，可对有机发光二极管显示装置的像素电路中的晶体管或者发光器件的进行感测，从而保证有机发光二极管显示装置的显示性能。对有机发光二极管显示装置的像素电路中的晶体管或者发光器件的感测将在下文进行详细描述。
根据本公开的一个方面，还提供了一种感测电路的校正方法，用于对其中的模数转换器ADC进行校正。在上述感测电路包括模数转换器ADC的情况下，对模数转换器ADC的校正方法包括：控制第二开关S2、第三开关S3、第四开关S4和第六开关S6闭合以及第一开关S1和第五开关S5断开，通过第一信号端Vref向运算放大器AMP的反相输入端和输出端提供第一电压信号V1；然后获取模数转换器ADC的第二端(信号输出端)输出的数字化的第一数字化输出电压D1’。最后，根据对第一电压信号V1数字化处理后的第一数字化电压信号D1和第一输出电压信号D1’，计算模数转换器ADC的校正值C ADC。第一数字化电压信号D1通过对第一电压信号V1的理想化模数处理得到。
具体地，如图2所示，在校正模数转换器ADC时，保持第一开关S1和第五开关S5断开，保持第二开关S2、第三开关S3、第四开关S4和第六开关S6闭合，此时来自第一信号端Vref的第一电压信号V1依次经过第三开关S3、第二开关S2、第四开关S4和第六开关S6到达第三节点N3。第三节点N3处为第一电压信号V1，即模数转换器ADC的输入信号为第一电压信号V1。理想状态下，来自第一信号端Vref的第一电压信号V1经数模转换后为理想的第一数字化输出电压D1。但在实际情况下，由于模数转换器ADC内部各器件性能的影响，第一电压信号V1经模数转换器ADC后为第一数字化输出电压信号D1’，D1不同于D1’。因此，模数转换器ADC的校正值C ADC可计算为C ADC＝D1-D1’。
本公开还提供了一种感测电路的校正方法，用于对其中的运算放大器AMP进行校正。在上述感测电路包括模数转换器ADC的情况下，该运算放大器AMP的校正方法包括：控制第一开关S1、第三开关S3和第六开关S6闭合以及第二开关S2、第四开关S4和第五开关S5断开，通过第一信号端Vref向运算放大器AMP的同相输入端提供第二电压信号V2；然后获取模数转换器ADC的第二端的第二数字化输出电压D2’；最后，根据对第二电压信号V2数字化处理后的第二数字化电压信号D2、第二数字化输出电压信号D2’以及模数转换器ADC的校正值，计算运算放大器AMP的校正值C AMP。
具体地，如图3所示，保持第二开关S2、第四开关S4和第五开关S5断开 以及第一开关S1、第三开关S3和第六开关S6闭合，来自第一信号端Vref的第二电压信V2依次经过第三开关S3和第一开关S1到达运算放大器AMP的同相输入端。由于第六开关S6闭合，运算放大器AMP以电压跟随方式将第二输出电压输出至模数转换器ADC的第一端(输入端)。理想状态下，第一信号端Vref的第二电压信号V2对应第二数字化理想输出电压D2，运算放大器AMP以电压跟随方式输出第二输出电压，该第二输出电压经模数转换器ADC处理后得到第二数字化输出电压D2’。因此，运算放大器AMP的校正值可计算为C AMP＝D2+C ADC-D2’。
本公开还提供了一种感测电路的校正方法，用于计算积分电容器Cfb的校正值。在上述感测电路包括模数转换器ADC的情况下，计算积分电容器Cfb的校正值的方法包括：控制第一开关S1、第三开关S3和第五开关S5闭合以及第二开关S2、第四开关S4和第六开关S6断开，通过第二信号端Iref向积分电容器Cfb和运算放大器AMP的反相输入端提供第一电流信号，通过第一信号端Vref向运算放大器AMP的同相输入端提供第三电压信号V3；然后，获取模数转换器ADC的第二端的第三数字化输出电压信号d3’和第一端的第三数字化输入电压信号d3(即运算放大器AMP的输出的第三输出电压v3对应的数字化输出电压)；最后，根据对第三电压信号V3数字化处理后的第三数字化电压信号D3、第三数字化输出电压信号d3’、第三数字化输入电压信号d3以及积分电容器Cfb的电容，计算积分电容器Cfb的校正值。第三数字化输入电压信号d3通过对模数转换器的第一端的电压进行理想化模数转换得到。
具体地，如图4所示，保持第二开关S2、第四开关S4和第六开关S6断开以及第一开关S1、第三开关S3和第五开关S5闭合，通过第二信号端Iref将第一电流信号I1写入积分电容器Cfb。设定积分电容器Cfb的电容值为Cf。理想状态下，在固定时间T内，积分电容器Cfb处会有恒定电流流过，设定积分电容器Cfb两端的电压差为Vc。从第一信号端Vref将第三电压信号V3依次经过第三开关S3和第一开关S1提供给运算放大器AMP的同相输入端，从第二信号端Iref将第一电流信号I1通过第五开关S5提供给积分电容器Cfb。运算放大器 AMP的输出端输出第三输出电压v3至模数转换器ADC，模数转换器ADC输出数字化的第三输出电压d3’，理想状态下第三输出电压v3对应第三理想输出电压d3。理想状态下，来自第一信号端Vref的第三电压信号V3对应第三理想输出电压D3，第三电压信号V3经模数转换器ADC输出数字化的第三输出电压D3’。因此，积分电容器Cfb的校正值可计算为C Cfb＝Cf*(D3-d3)/(D3-d3’)。
由上可知，在电流感测模式下，如果有电流I2在固定时间T’通过感测线SL流经至感测电路的积分电容器Cfb处，根据模数转换器ADC校正值、运算放大器AMP校正值和积分电容器Cfb校正值，最终模数转换器ADC的输出的值为V ADC＝(I2×T’)/C Cfb+C AMP+C ADC。
本公开还提供了一种感测电路的校正方法，用于对其中的运算放大器AMP进行校正。在上述感测电路不包括模数转换器ADC的情况下，该运算放大器AMP的校正方法包括：控制第一开关S1、第三开关S3和第六开关S6闭合以及第二开关S2、第四开关S4和第五开关S5断开，通过第一信号端Vref向运算放大器AMP的同相输入端提供第二电压信号V2；然后获取运算放大器AMP的输出端的第二输出电压；最后，根据第二电压信号和第二输出电压信号，计算运算放大器AMP的校正值C AMP。该方法无需模数转换器ADC对电压信号进行数字化处理。
本公开还提供了一种感测电路的校正方法，用于计算积分电容器Cfb的校正值。在上述感测电路不包括模数转换器ADC的情况下，计算积分电容器Cfb的校正值的方法包括：控制第一开关S1、第三开关S3和第五开关S5闭合以及第二开关S2、第四开关S4和第六开关S6断开，通过第二信号端Iref向积分电容器Cfb提供第一电流信号，通过第一信号端Vref向运算放大器AMP的同相输入端提供第三电压信号V3；然后，获取运算放大器AMP的输出端的第三输出电压信号；最后，根据第三电压信号V3以及第三输出电压信号以及积分电容器Cfb的电容，计算积分电容器Cfb的校正值。该方法无需模数转换器ADC对电压信号进行数字化处理。
如图6至图10所示，本公开还提供了一种像素驱动模组，该像素驱动模组 包括：上述的感测电路以及像素电路。
该像素电路包括驱动单元、发光单元1、数据写入单元、存储单元和感测单元。其中，驱动单元的控制端与数据写入单元的第二端和存储单元的第一端连接于第五节点N5，第一端与第一电压端ELVDD连接，第二端与发光单元的第一端、感测单元的第一端和存储单元的第二端连接于第四节点N4，用于驱动发光单元1进行发光。数据写入单元的控制端与第一栅线端GL1连接，第一端与数据线端DL连接，用于通过存储单元的调节向驱动单元的控制端写入数据线端DL的数据信号。感测单元的控制端与第二栅线端GL2连接，第二端与感测线SL连接，用于将第四节点N4的信号输入至感测线SL，以利用感测电路对驱动单元进行感测。发光单元的第二端与第二电压端ELVSS连接。
可选的，驱动单元包括：第一晶体管T1，其栅极作为驱动单元的控制端连接第五节点N5，其第一极作为驱动单元的第一端连接第一电压端ELVDD，其第二极作为驱动单元的第二端连接第四节点N4。
数据写入单元包括第二晶体管T2，其栅极作为数据写入单元的控制端连接第一栅线端GL1，其第一极作为数据写入单元的第一端连接数据线端DL，其第二极作为数据写入单元的第二端连接第五节点N5。
存储单元包括存储电容器Cst，其第一极作为存储单元的第一端连接第五节点N5，其第二极作为发光单元的第二端连接第四节点N4。
发光单元1的第一极作为发光单元的第一端连接第四节点N4，第二极作为发光单元的第二端连接第二电压端ELVSS。
感测单元包括：第三晶体管T3，其栅极作为感测单元的控制端连接第二栅线端GL2，其第一极作为感测单元的第一端连接第四节点N4，其第二极作为感测单元的第二端连接感测线SL。
可选的，第一晶体管T1、第二晶体管T2和第三晶体管T3均为N型晶体管；或者，第一晶体管T1、第二晶体管T2和第三晶体管T3均为P型晶体管。本公开以上述晶体管均是N型晶体管为例进行说明，故其中导通信号为高电平信号，断开信号为低电平信号。
在本实施例中，第一电压端ELVDD用于提供工作电压，第二电压端ELVSS用于提供参考电压。
在本公开中，可选地，显示装置可包括多条感测线SL，多条感测线SL中的一条可连接至少一列子像素，多条感测线SL中的至少一条可连接一个感测电路，从而可以实现一个感测电路连接至少一列子像素，但本公开不限于此。
需要说明的是，本实施例中的发光单元1可以是包括LED(Light Emitting Diode，发光二极管)或OLED(Organic Light Emitting Diode，有机发光二极管)在内的电流驱动的发光器件，在本实施例中是以OLED为例进行的说明。第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5和第六开关S6可为任意可控开关器件。
本实施例的像素驱动模组能够应用于有机发光二极管显示装置，尤其适用于尺寸较大的有机发光二极管显示装置，对有机发光二极管显示装置的像素电路中的晶体管或者发光器件的进行感测，从而保证有机发光二极管显示装置的显示性能。
需要说明的是，有机发光二极管显示装置中包括阵列分布的多个像素电路，以实现显示。而感测电路可以与像素电路一一对应，也可以是几行或者部分的像素电路对应一个感测电路，可以根据实际情况来确定。
根据本公开的一个方面，提供了一种显示装置。如图10所示，该显示装置主要由显示面板、时序控制器、源极驱动器、栅极驱动器、存储器等组成，显示面板与源极驱动器和栅极驱动器连接，时序控制器与源极驱动器、栅极驱动器和存储器连接，并且感测电路可位于源极驱动器中，像素电路可位于显示面板中。
时序控制器读取存储器(RAM)中存储的数据，同时接收外部输入的数据(RGB)、时序控制信号(Timing)、源极驱动器输出的感测数据(SData)。经过计算、转换、补偿等处理过程，时序控制器产生经过补偿运算后的数据(Data)和源极控制信号(SCS，Source Control Signal)输出给源极驱动器。时序控制器产生栅极控制信号(GCS，Gate Control Signal)输出给栅极驱动器。
存储器可存储一个或者多个像素电路的像素补偿值，如控制像素电路的发光单元1发光的第一晶体管T1的阈值电压Vth和迁移率K以及发光单元的发光效率等。
源极驱动器接收时序控制器输出的经过补偿计算后的数据(Data)和源极号控制信号(SCS)，产生的数据信号(Vdata)通过数据线(DL)输出给显示面板。同时在源极控制信号(SCS)的控制下，控制感测电路，实现感测电路的模数转换器ADC、运算放大器AMP、积分电容器Cfb的校正功能、实现对感测线SL的重置和充电功能等。并通过感测线SL感测某行或某部分像素电路的特征值，经过模数转换器ADC产生的感测数据(SData)输出给时序控制器。
栅极驱动器接收栅极控制信号(GCS)，产生对应至少一条扫描线(GL1，GL2，GL3等)的扫描信号并输出给显示面板。
具体的，该有机发光二极管显示装置可为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
如图7a、图7b和图7c所示，本公开还提供一种对上述像素驱动模组的阈值电压的感测方法。如图7a所示，该方法包括步骤S10～S14。
在步骤S10，即第一复位阶段a1，通过第一栅线端GL1和第二栅线端GL2分别向第二晶体管T1的栅极和第三晶体管T3的栅极输入导通信号，并控制第二开关S2和第三开关S3闭合以及第一开关S1、第四开关S4、第五开关S5和第六开关S6断开，通过数据线端DL向第二晶体管T2的第一极输入第一数据信号Vdata，以将第一信号端Vref的信号写入感测线SL来对感测线SL进行复位，将第一数据信号Vdata写入存储电容器Cst。
参考图5，向第一开关S1、第四开关S4、第五开关S5、第六开关S6输入断开信号，则第一开关S1、第四开关S4、第五开关S5、第六开关S6断开；向第二开关S2、第三开关S3输入导通信号，则第二开关S2、第三开关S3闭合。同时，向第一栅线端GL1、第二栅线端GL2输入导通信号，则第二晶体管T2、第三晶体管T3导通。在这种情况下，通过数据线端DL将第一数据信号Vdata 写入存储电容器Cst，同时通过第一信号端Vref将恒定电压信号写入感测线SL。需要说明的是，如图5所示，该阶段相当于感测电路对感测线SL进行复位，即感测电路具有对感测线SL复位的功能。
在步骤S12，即第一充电阶段a2，通过第一栅线端GL1和第二栅线端GL2分别向第二晶体管T2的栅极和第三晶体管T3的栅极输入导通信号，控制第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5和第六开关S6断开，以将第一电压端ELVDD提供的信号写入感测线SL。
参考图6，也就是说，向第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5和第六开关S6输入断开信号，则第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6断开，相当于对于感测电路感测线SL浮接，即感测电路具有对感测线SL浮接(Floating)的功能。向第一栅线端GL1、第二栅线端GL2输入导通信号，第二晶体管T2、第三晶体管T3导通。同时由于上一阶段的存储电容器Cst的作用，第一晶体管T1导通，来自第一电压端ELVDD的信号使得有电流依次经过第一晶体管T1、第三晶体管T3到达感测线SL，并且使得感测线SL上的电压不断升高。
在步骤S14，即第一感测阶段a3，控制第四开关S4、第六开关S6闭合以及第一开关S1、第二开关S2、第三开关S3、第五开关S5断开，不通过第一栅线端和第二栅线端分别向第二晶体管T2的栅极和第三晶体管T3的栅极输入导通信号，感测线SL的信号经过运算放大器AMP并由模数转换器ADC输出。获取运算放大器AMP的输出端的电压信号，以根据第一数据信号和运算放大器AMP的输出端的电压信号，计算第一晶体管T1的阈值电压。
如图7b和图7c所示，也就是说，向第一栅线端GL1、第二栅线端GL2、第一开关S1、第二开关S2、第三开关S3、第五开关S5输入断开信号，第二晶体管T2、第三晶体管T3、第一开关S1、第二开关S2、第三开关S3、第五开关S5断开。向第四开关S4、第六开关S6输入导通信号，第四开关S4、第六开关S6导通。此时感测线SL的电压不变，并且经过第四开关S4和第六开关S6到达第三节点N3，N3处的信号为Vdata-Vth。复位阶段中数据线端DL的第一数 据信号Vdata与该输出信号Vdata-Vth的差为第一晶体管T1的阈值电压Vth。
如图8a、图8b和8c所示，本公开还提供一种对上述像素驱动模组的迁移率的感测方法。如图8a所示，该方法包括步骤S20～S24。
在步骤S20，即第二复位阶段b1，通过第一栅线端GL1、第二栅线端GL2分别向第二晶体管T2的栅极和第三晶体管T3的栅极写入导通信号，并控制第二开关S2、第三开关S3闭合以及第一开关S1、第四开关S4、第五开关S5、第六开关S6断开，通过数据线端DL向第三晶体管T3的栅极输入第二数据信号Vdata+Vth，以将第一信号端Vref的信号写入感测线SL，将第二数据信号写入存储电容器Cst。
如图8b和8c所示，也就是说，向第一开关S1、第四开关S4、第五开关S5、第六开关S6输入断开信号，第一开关S1、第四开关S4、第五开关S5、第六开关S6断开。向第一栅线端GL1、第二栅线端GL2、第二开关S2、第三开关S3输入导通信号，第二晶体管T2、第三晶体管T3、第二开关S2、第三开关S3导通，通过数据线端DL将第二数据信号Vdata+Vth写入存储电容器Cst，同时从第一信号端Vref将恒定电压信号写入感测线SL。
需要说明的是，如图5所示，该阶段相当于感测电路对感测线SL进行复位，即感测电路具有对感测线SL复位的功能。
在步骤S22，即第二充电阶段b2，通过第二栅线端GL2向第三晶体管T3的栅极输入导通信号，不通过第一栅线端GL1向第二晶体管T2的栅极写入导通信号，控制第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6断开，以将第一电压端ELVDD的信号写入感测线SL。
也就是说，向第一栅线端GL1、第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6输入断开信号，第二晶体管T2，第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6断开，相当于对于感测电路感测线SL浮接，即感测电路具有对感测线SL浮接(Floating)的功能。同时向第二栅线端GL2输入导通信号，第三晶体管T3导通。同时由于上一阶段的存储电容器Cst的作用第一晶体管T1导通，来自第一 电压端ELVDD的信号使得有电流依次经过第一晶体管T1、第三晶体管T3并写入感测线SL，并且感测线SL上的电压不断升高。
在步骤S24，即第二感测阶段b3，控制第一开关S1、第三开关S3、第四开关S4闭合以及第二开关S2、第五开关S5、第六开关S6断开，不通过第一栅线端GL1、第二栅线端GL2向第二晶体管T2的栅极和第三晶体管T3的栅极输入导通信号，感测线SL的信号经过运算放大器AMP并由模数转换器ADC输出。获取运算放大器AMP的输出端的电压信号，以根据第二数据信号和运算放大器AMP的输出端的电压信号，计算第一晶体管T1的迁移率。
如图8c所示，也就是说，向第一栅线端GL1、第二栅线端GL2、第二开关S2、第五开关S5、第六开关S6输入断开信号，第二晶体管T2、第三晶体管T3、第二开关S2、第五开关S5、第六开关S6断开。向第一开关S1、第三开关S3、第四开关S4输入导通信号，第一开关S1、第三开关S3、第四开关S4导通，此时感测线SL的电压不变，并且依次经过第四开关S4和存储电容器Cfb到达模数转换器ADC以输出对应电压，该对应电压大小能够反应经过第一晶体管T1的电流的大小。获取运算放大器AMP的输出端的电压信号，以根据第二数据信号和运算放大器AMP的输出端的电压信号，计算第一晶体管T1迁移率K。
如图9a、图9b和图9c所示，本公开还提供一种对上述像素驱动模组的发光单元1发光效率的感测方法。如图9a所示，该方法包括步骤S30～S36。
在步骤S30，即第三复位阶段c1，控制第二开关S2、第三开关S3闭合以及第一开关S1、第四开关S4、第五开关S5、第六开关S6断开，通过第一栅线端GL1向第二晶体管T2的栅极输入导通信号，不通过第二栅线端GL2向第三晶体管T3的栅极写入导通信号，通过数据线端DL向第二晶体管T2的第一极输入第三数据信号Vdata+Vth，以将第一信号端Vref的信号写入感测线SL，将第三数据信号Vdata+Vth写入存储电容器Cst。
也就是说，向第二栅线端GL2、第一开关S1、第四开关S4、第五开关S5、第六开关S6输入断开信号，第三晶体管T3、第一开关S1、第四开关S4、第五开关S5、第六开关S6断开。向第一栅线端GL1、第二开关S2、第三开关S3 输入导通信号，第二晶体管T2、第二开关S2、第三开关S3导通，将来自数据线端DL的第三数据信号Vdata+Vth写入存储电容器Cst，同时将来自第一信号端Vref的恒定电压信号写入感测线SL。
需要说明的是，如图5所示，该阶段相当于感测电路对感测线SL进行复位，即感测电路具有对感测线SL复位的功能。
在步骤S32，即第三充电阶段c2，不通过第一栅线端GL1、第二栅线端GL2分别向第二晶体管T2的栅极和第三晶体管T3的栅极输入导通信号，控制第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6断开，以将来自第一电压端ELVDD的信号写入第四节点N4。
如图9b和9c所示，也就是说，向第一栅线端GL1、第二栅线端GL2、第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6输入断开信号，第二晶体管T2、第三晶体管T3、第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6断开。同时由于上一阶段的存储电容器Cst的作用第一晶体管T1导通，来自第一电压端ELVDD的信号使得有电流经过第一晶体管T1，使得第四节点N4的电压不断升高。
在步骤S34，即稳定阶段c3，通过第一栅线端GL1向第二晶体管T2的栅极输入导通信号，不通过第二栅线端GL2向第三晶体T3的栅极写入导通信号，控制第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6断开，通过数据线端DL向第二晶体管T2的第一极输入第四数据信号，以保持第四节点N4的电压稳定。
也就是说，向第二栅线端GL2、第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6输入断开信号，第三晶体管T3、第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6断开。通过第一栅线端GL1向第二晶体管T2的栅极输入导通信号，第二晶体管T2导通。通过数据线端DL向第二晶体管T2的第一极输入第四数据信号，且第四数据信号为0V电压，以使第一晶体管T1关断，第四节点N4的电压保持不变。
在步骤S36，即第三感测阶段c4，通过第二栅线端GL2向第三晶体管T3的栅极写入导通信号，不通过第一栅线端GL1向第二晶体管T2的栅极输入导通信号，控制第一开关S1、第三开关S3、第四开关S4闭合以及第二开关S2、第五开关S5、第六开关S6断开，将第四节点N4的电压写入积分电容器Cfb。根据积分电容器的电容以及第四节点的电压，计算发光单元1的发光效率。
如图9b所示，也就是说，向第一栅线端GL1、第二开关S2、第五开关S5、第六开关S6输入断开信号，第二晶体管T2、第二开关S2、第五开关S5、第六开关S6断开。向第二栅线端GL2、第一开关S1、第三开关S3、第四开关S4输入导通信号，第三晶体管T3、第一开关S1、第三开关S3、第四开关S4导通，第四节点N4的电压经过第四开关S4写入积分电容器Cfb，并根据感测积分电容器Cfb的电容和第四节点的电压而得到发光单元1的发光效率。
应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本公开的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该公开仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本公开的原理和实际应用，从而使所属技术领域技术人员能很好地利用本公开以及在本公开基础上的修改使用。本公开仅受权利要求书及其全部范围和等效物的限制。

Claims (16)

  1. 一种感测电路，包括：运算放大器、积分电容器、第一开关、第二开关、第三开关、第四开关、第五开关和第六开关；其中，
    所述运算放大器的同相输入端通过所述第一开关与第一节点连接，其反相输入端与第二节点连接，其输出端与第三节点连接；
    所述积分电容器的第一极连接所述第二节点，其第二极连接所述第三节点；
    所述第一节点通过所述第二开关与感测线连接，所述第一节点通过所述第三开关与第一信号端连接；
    所述第二节点通过所述第四开关与所述感测线连接，所述第二节点通过所述第五开关与第二信号端连接；
    所述第三节点与所述感测电路的信号输出端连接；以及
    所述第二节点通过所述第六开关与所述第三节点连接。
  2. 根据权利要求1所述的感测电路，还包括：模数转换器，其第一端连接所述第三节点，第二端连接所述感测电路的信号输出端。
  3. 根据权利要求1或2中任一项所述的感测电路，其中，所述第一信号端提供恒定电压信号，所述第二信号端提供恒定电流信号。
  4. 一种像素驱动模组，包括权利要求1-3中任一项所述的感测电路以及像素电路，所述像素电路包括驱动单元、发光单元、数据写入单元、存储单元和感测单元，其中，
    所述驱动单元的控制端与所述数据写入单元的第二端和所述存储单元的第一端连接于第五节点，第一端与第一电压端连接，第二端与所述发光单元的第一端、所述感测单元的第一端和所述存储单元的第二端连接于第四节点；
    所述数据写入单元的控制端与第一栅线端连接，第一端与数据线端连接；
    所述发光单元的第二端与第二电压端连接；以及
    所述感测单元的控制端与第二栅线端连接，第二端与感测线连接。
  5. 根据权利要求4所述的像素驱动模组，其中，
    所述驱动单元包括：第一晶体管，其栅极作为所述驱动单元的控制端连接所述第五节点，其第一极作为所述驱动单元的第一端连接所述第一电压端，其第二极作为所述驱动单元的第二端连接所述第四节点；
    所述数据写入单元包括：第二晶体管，其栅极作为所述数据写入单元的控制端连接所述第一栅线端，其第一极作为所述数据写入单元的第一端连接所述数据线端，其第二极作为所述数据写入单元的第二端连接所述第五节点；
    所述存储单元包括：存储电容器，其第一极作为所述存储单元的第一端连接所述第五节点，其第二极作为所述存储单元的第二端连接所述第四节点；
    所述发光单元的第一极作为所述发光单元的第一端连接所述第四节点，第二极作为所述发光单元的第二端连接所述第二电压端；以及
    所述感测单元包括：第三晶体管，其栅极作为所述感测单元的控制端连接所述第二栅线端，其第一极作为所述感测单元的第一端连接所述第四节点，其第二极作为所述感测单元的第二端连接所述感测线。
  6. 一种显示装置，包括权利要求5所述的像素驱动模组，其中，所述显示装置还包括显示面板、时序控制器、源极驱动器、栅极驱动器和存储器，其中，所述显示面板与所述源极驱动器和所述栅极驱动器连接，所述时序控制器与所述源极驱动器、所述栅极驱动器和所述存储器连接，并且所述像素驱动模组中的感测电路位于所述源极驱动器中，所述像素驱动模组中的像素电路位于所述显示面板中，所述存储器存储有所述第一晶体管的阈值电压和迁移率以及所述发光单元的发光效率。
  7. 一种对权利要求2或3所述的感测电路的校正方法，包括：
    控制所述第二开关、所述第三开关、所述第四开关和所述第六开关闭合以及所述第一开关和所述第五开关断开，通过所述第一信号端向所述运算放大器的反相输入端和输出端提供第一电压信号；
    获取所述模数转换器的第二端的第一数字化输出电压信号；以及
    根据对所述第一电压信号数字化处理后的第一数字化电压信号和所述第一数字化输出电压信号，计算所述模数转换器的校正值。
  8. 根据权利要求7所述的校正方法，还包括计算所述运算放大器的校正值，其中，计算所述运算放大器的校正值包括：
    控制所述第一开关、所述第三开关和所述第六开关闭合以及控制所述第二开关、所述第四开关和所述第五开关断开，通过所述第一信号端向所述运算放大器的同相输入端提供第二电压信号；
    获取所述模数转换器的第二端的第二数字化输出电压信号；以及
    根据对所述第二电压信号数字化处理后的第二数字化电压信号、所述第二数字化输出电压信号以及所述模数转换器的校正值，计算所述运算放大器的校正值。
  9. 根据权利要求7或8所述的校正方法，还包括计算所述积分电容器的校正值，其中，计算所述积分电容器的校正值包括：
    控制所述第一开关、所述第三开关和所述第五开关闭合以及所述第二开关、所述第四开关和所述第六开关断开，通过所述第一信号端向所述运算放大器的同相输入端提供第三电压信号，通过第二信号端向所述积分电容器和所述运算放大器的反相输入端提供第一电流信号；
    获取所述模数转换器的第二端的第三数字化输出电压信号和第一端的第三数字化输入电压信号；以及
    根据对所述第三电压信号数字化处理后的第三数字化电压信号、所述数字化第三输出电压信号、所述第三数字化输入电压信号以及所述积分电容器的电 容，计算所述积分电容器的校正值。
  10. 一种对权利要求1-3中任一项所述的感测电路的校正方法，包括：
    控制第一开关、第三开关和第六开关闭合以及控制第二开关、第四开关和第五开关断开，通过第一信号端向运算放大器的同相输入端提供第二电压信号；
    获取所述运算放大器的输出端的第二输出电压信号；以及
    根据所述第二电压信号和所述第二输出电压信号，计算所述运算放大器的校正值。
  11. 一种对权利要求1-3中任一项所述的感测电路的校正方法，包括：
    控制第一开关、第三开关和第五开关闭合以及第二开关、第四开关和第六开关断开，通过第一信号端向运算放大器的同相输入端提供第三电压信号，通过第二信号端向积分电容器和所述运算放大器的反相输入端提供第一电流信号；
    获取所述运算放大器的输出端的第三输出电压信号；以及
    根据所述第三电压信号、所述第三输出电压信号以及所述积分电容器的电容，计算所述积分电容器的校正值。
  12. 一种对权利要求5所述的像素驱动模组的阈值电压的感测方法，包括：
    第一复位阶段，通过第一栅线端和第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，并控制第二开关和第三开关闭合以及第一开关、第四开关、第五开关和第六开关断开，通过数据线端向所述第二晶体管的第一极输入第一数据信号，以将第一信号端提供的信号写入感测线来对所述感测线进行复位，将所述第一数据信号写入所述存储电容器；
    第一充电阶段，通过所述第一栅线端和所述第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，控制所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开， 以将第一电压端提供的信号写入所述感测线；以及
    第一感测阶段，控制所述第四开关和第六开关闭合以及所述第一开关、所述第二开关、所述第三开关和所述第五开关断开，不通过所述第一栅线端和所述第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，并获取运算放大器的输出端电压信号，以根据所述第一数据信号和所述运算放大器的输出端电压信号，计算所述第一晶体管的阈值电压。
  13. 根据权利要求12所述的感测方法，还包括将所述运算放大器的输出端电压信号输入至模数转换器，以将所述运算放大器的输出端电压信号转换为数字化电压信号，并根据对所述第一数据信号数字化处理后的第一数字化数据信号和所述运算放大器的输出端的数字化电压信号计算所述第一晶体管的阈值电压。
  14. 一种对权利要求5所述的像素驱动模组的迁移率的感测方法，包括：
    第二复位阶段，通过第一栅线端和第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，并控制第二开关和第三开关闭合以及第一开关、第四开关、第五开关和第六开关断开，通过数据线端向所述第二晶体管的第一极输入第二数据信号，以将第一信号端提供的信号写入感测线，将所述第二数据信号写入存储电容器；
    第二充电阶段，通过所述第二栅线端向所述第三晶体管的栅极输入导通信号，不通过所述第一栅线端向所述第二晶体管的栅极输入导通信号，并且控制所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开，以将第一电压端提供的信号写入所述感测线；以及
    第二感测阶段，控制所述第一开关、所述第三开关和所述第四开关闭合以及所述第二开关、所述第五开关和所述第六开关断开，不通过所述第一栅线端和所述第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，并获取所述运算放大器的输出端电压信号，以根据所述第二数据信 号和所述运算放大器的输出端电压信号，计算所述第一晶体管的迁移率。
  15. 根据权利要求14所述的感测方法，还包括将所述运算放大器的输出端电压信号输入至模数转换器，以将所述运算放大器的输出端电压信号转换为数字化电压信号，并根据对所述第二数据信号的数字化处理后的第二数字化数据信号和所述运算放大器的输出端的数字化电压信号计算所述第一晶体管的迁移率。
  16. 一种对权利要求5所述的像素驱动模组的发光单元发光效率的感测方法，包括：
    第三复位阶段，控制第二开关和第三开关闭合以及第一开关、第四开关、第五开关和第六开关断开，通过第一栅线端向所述第二晶体管的栅极输入导通信号，不通过第二栅线端向所述第三晶体管的栅极输入导通信号，通过数据线端向所述第二晶体管的第一极输入第三数据信号，以将第一信号端提供的信号写入感测线，将所述第三数据信号写入存储电容器；
    第三充电阶段，不通过所述第一栅线端和所述第二栅线端分别向所述第二晶体管的栅极和所述第三晶体管的栅极输入导通信号，控制所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开，以将第一电压端提供的信号写入第四节点；
    稳定阶段，通过所述第一栅线端向所述第二晶体管的栅极输入导通信号，不通过所述第二栅线端向所述第三晶体管的栅极输入导通信号，控制所述第一开关、所述第二开关、所述第三开关、所述第四开关、所述第五开关和所述第六开关断开，通过数据线端向所述第二晶体管的第一极输入第四数据信号，以保持所述第四节点的电压稳定；以及
    第三感测阶段，通过所述第二栅线端向所述第三晶体管的栅极输入导通信号，不通过所述第一栅线端向所述第二晶体管的栅极输入导通信号，控制所述第一开关、所述第三开关和所述第四开关闭合以及所述第二开关、所述第五开 关和所述第六开关断开，将所述第四节点的电压写入积分电容器，并根据所述积分电容器的电容以及所述第四节点的电压，计算发光单元的发光效率。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554220B (zh) 2020-06-04 2024-05-31 京东方科技集团股份有限公司 感测电路及其校正方法、像素驱动模组及其感测方法
WO2022267055A1 (zh) * 2021-06-25 2022-12-29 京东方科技集团股份有限公司 一种电流检测装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105741782A (zh) * 2014-12-26 2016-07-06 乐金显示有限公司 感测电路及具有该感测电路的有机发光二极管显示装置
US20180005559A1 (en) * 2011-05-20 2018-01-04 Ignis Innovation Inc. System and methods for extraction of threshold and mobility parameters in amoled displays
CN108205391A (zh) * 2016-12-20 2018-06-26 乐金显示有限公司 触摸电路、触摸感测装置和触摸感测方法
CN109935182A (zh) * 2018-07-27 2019-06-25 京东方科技集团股份有限公司 像素电流检测电路、方法、显示装置
CN110164374A (zh) * 2019-06-14 2019-08-23 京东方科技集团股份有限公司 一种像素补偿电路、显示装置以及像素补偿电路的驱动方法
CN111028783A (zh) * 2018-10-04 2020-04-17 乐金显示有限公司 像素感测装置、有机发光显示装置及其像素补偿方法
CN111554220A (zh) * 2020-06-04 2020-08-18 京东方科技集团股份有限公司 感测电路及其校正方法、像素驱动模组及其感测方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110007102A1 (en) * 2009-07-10 2011-01-13 Casio Computer Co., Ltd. Pixel drive apparatus, light-emitting apparatus and drive control method for light-emitting apparatus
US9236011B2 (en) * 2011-08-30 2016-01-12 Lg Display Co., Ltd. Organic light emitting diode display device for pixel current sensing in the sensing mode and pixel current sensing method thereof
KR102128082B1 (ko) * 2013-07-24 2020-06-30 삼성디스플레이 주식회사 유기전계발광 표시장치 및 그의 구동방법
KR102083458B1 (ko) * 2013-12-26 2020-03-02 엘지디스플레이 주식회사 유기발광 표시장치
US9721502B2 (en) * 2014-04-14 2017-08-01 Apple Inc. Organic light-emitting diode display with compensation for transistor variations
KR101549343B1 (ko) * 2014-06-27 2015-09-02 엘지디스플레이 주식회사 구동소자의 전기적 특성을 센싱할 수 있는 유기발광 표시장치
CA2900170A1 (en) * 2015-08-07 2017-02-07 Gholamreza Chaji Calibration of pixel based on improved reference values
CN105280140B (zh) * 2015-11-24 2018-02-16 深圳市华星光电技术有限公司 感测电路与相应的oled显示设备
US10223965B2 (en) * 2016-03-02 2019-03-05 Apple Inc. System and method for data sensing for compensation in an electronic display
KR102609508B1 (ko) * 2016-11-11 2023-12-04 엘지디스플레이 주식회사 외부 보상용 드라이버 집적회로와 그를 포함한 표시장치
KR102652882B1 (ko) * 2016-11-23 2024-03-29 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그의 구동 방법
KR102642577B1 (ko) * 2016-12-12 2024-02-29 엘지디스플레이 주식회사 외부 보상용 드라이버 집적회로와 그를 포함한 표시장치, 및 표시장치의 데이터 보정방법
KR102350396B1 (ko) * 2017-07-27 2022-01-14 엘지디스플레이 주식회사 유기발광 표시장치와 그의 열화 센싱 방법
CN206946907U (zh) * 2017-11-07 2018-01-30 深圳市华星光电半导体显示技术有限公司 一种有机发光显示设备
CN108399889B (zh) * 2018-05-29 2020-04-07 深圳市华星光电技术有限公司 Oled像素驱动电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180005559A1 (en) * 2011-05-20 2018-01-04 Ignis Innovation Inc. System and methods for extraction of threshold and mobility parameters in amoled displays
CN105741782A (zh) * 2014-12-26 2016-07-06 乐金显示有限公司 感测电路及具有该感测电路的有机发光二极管显示装置
CN108205391A (zh) * 2016-12-20 2018-06-26 乐金显示有限公司 触摸电路、触摸感测装置和触摸感测方法
CN109935182A (zh) * 2018-07-27 2019-06-25 京东方科技集团股份有限公司 像素电流检测电路、方法、显示装置
CN111028783A (zh) * 2018-10-04 2020-04-17 乐金显示有限公司 像素感测装置、有机发光显示装置及其像素补偿方法
CN110164374A (zh) * 2019-06-14 2019-08-23 京东方科技集团股份有限公司 一种像素补偿电路、显示装置以及像素补偿电路的驱动方法
CN111554220A (zh) * 2020-06-04 2020-08-18 京东方科技集团股份有限公司 感测电路及其校正方法、像素驱动模组及其感测方法

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