WO2021249264A1 - 像素补偿装置及像素补偿方法、显示装置 - Google Patents

像素补偿装置及像素补偿方法、显示装置 Download PDF

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Publication number
WO2021249264A1
WO2021249264A1 PCT/CN2021/097978 CN2021097978W WO2021249264A1 WO 2021249264 A1 WO2021249264 A1 WO 2021249264A1 CN 2021097978 W CN2021097978 W CN 2021097978W WO 2021249264 A1 WO2021249264 A1 WO 2021249264A1
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Prior art keywords
circuit
voltage
sensing
sub
current
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PCT/CN2021/097978
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English (en)
French (fr)
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王糖祥
杨飞
王雨
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京东方科技集团股份有限公司
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Priority to US17/790,085 priority Critical patent/US11694624B2/en
Publication of WO2021249264A1 publication Critical patent/WO2021249264A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the display field, for example, to a pixel compensation device, a pixel compensation method, and a display device.
  • AMOLED Active-matrix organic light emitting diode
  • a pixel compensation device in one aspect, includes a controller and an external compensation circuit connected to the controller.
  • the external compensation circuit is located outside the pixel and connected to at least one pixel driving circuit; the pixel driving circuit includes a driving sub-circuit; one light-emitting driving cycle of the pixel driving circuit includes an initialization phase, a pre-storage phase, and a data compensation writing phase ;
  • the external compensation circuit includes a first input circuit, a second input circuit and a sensing circuit.
  • the first input circuit is respectively connected to the first end of the driving sub-circuit and the sensing circuit, and is configured to transmit a first voltage to the first end of the driving sub-circuit during the initialization phase, and The pre-storage stage is vacant; and the threshold compensation voltage is transmitted to the first terminal of the driving sub-circuit in the data compensation writing stage.
  • the second input circuit is connected to the control terminal of the driving sub-circuit, and is configured to transmit a second voltage to the control terminal of the driving sub-circuit during the initialization phase and the pre-storage phase, so that the driving The voltage of the first terminal of the sub-circuit is compensated by the first voltage to the threshold compensation voltage in the pre-storage stage.
  • the first terminal of the driving sub-circuit is connected to the light emitting device, the first voltage and the threshold compensation voltage are both less than the turn-on voltage of the light emitting device; the threshold compensation voltage is equal to the second voltage and the The difference between the threshold voltage of the driving sub-circuit.
  • the sensing circuit is also connected to the first end of the driving sub-circuit, and is configured to sense the threshold compensation voltage during the data compensation writing stage, and transmit the threshold compensation voltage to the first Input circuit.
  • the controller is also connected to the control terminal of the driving sub-circuit, and is configured to transmit a data voltage to the control terminal of the driving sub-circuit during the data compensation writing phase.
  • the data voltage is a modified voltage of the actual characteristic value of the driving sub-circuit determined by the controller according to the previous light-emitting driving period.
  • the sensing circuit is further connected to the controller, and the sensing circuit is further configured to sense the first current transmitted by the first terminal of the driving sub-circuit in the initialization phase, And transmitting the first current to the controller; and transmitting the sensed threshold compensation voltage to the controller in the data compensation writing stage.
  • the controller is further configured to: determine the actual characteristic value of the driving sub-circuit according to the first current and the threshold compensation voltage, and correct according to the actual characteristic value to be in the next data compensation writing stage. The voltage of the transmitted data.
  • the light-emitting driving cycle further includes an aging sensing phase.
  • the second input circuit is further configured to: transmit a third voltage to the control terminal of the driving sub-circuit during the aging sensing phase to control the driving sub-circuit to turn off.
  • the sensing circuit is further configured to sense the second current transmitted from the light-emitting device to the first end of the driving sub-circuit during the aging sensing stage.
  • the controller is further configured to determine the aging information of the light emitting device according to the second current, and correct the data voltage to be transmitted in the next data compensation writing stage according to the aging information.
  • the sensing circuit includes a voltage sensing sub-circuit, and the voltage sensing sub-circuit is respectively connected to the first end of the driving sub-circuit and the first input circuit; the voltage sensing The sub-circuit is configured to sense the threshold compensation voltage in the data compensation writing stage, and transmit the threshold compensation voltage to the first input circuit.
  • the voltage sensing sub-circuit is further connected to the controller; the voltage sensing sub-circuit is further configured to: in the data compensation writing stage, the sensed threshold compensation voltage Transfer to the controller.
  • the light-emitting driving period further includes a first calibration phase.
  • the first input circuit is further configured to transmit the first voltage to the voltage sensing sub-circuit in the first calibration stage, so that the voltage sensing sub-circuit outputs a fourth voltage to the control Device.
  • the controller is further configured to: modify the sensing voltage signal transmitted by the voltage sensing sub-circuit to the controller according to the difference between the fourth voltage and the first voltage; the sensing voltage signal Including the threshold compensation voltage.
  • the voltage sensing sub-circuit includes the first operational amplifier, a fourth switch, and a fifth switch.
  • the non-inverting input terminal of the first operational amplifier is also connected to the first terminal of the driving sub-circuit through the fourth switch; the inverting input terminal of the first operational amplifier is also connected to the first terminal of the driving sub-circuit through the fifth switch.
  • the output terminal of the first operational amplifier is connected.
  • the sensing circuit includes a current sensing sub-circuit, the current sensing sub-circuit is respectively connected to the first end of the driving sub-circuit and the controller; the current sensing sub-circuit It is configured to: sense a first current in the initialization phase, and transmit the first current to the controller; and/or, sense the second current in the aging sensing phase, and transfer the first current to Two currents are transmitted to the controller.
  • the light-emitting driving period further includes a second calibration phase.
  • the current sensing sub-circuit is also connected with a reference current source.
  • the reference current source is configured to transmit a reference current to the current sensing sub-circuit in the second calibration stage, so that the current sensing sub-circuit outputs a third current.
  • the controller is further configured to: according to the difference between the third current and the reference current, correct the sensing current signal transmitted by the current sensing sub-circuit to the controller; the sensing current signal includes The first current and/or the second current.
  • the current sensing sub-circuit includes a first operational amplifier, an integrating capacitor, a first switch, and a second switch; wherein, the non-inverting input terminal of the first operational amplifier communicates with a reference through the second switch.
  • the voltage terminal is connected; the inverting input terminal of the first operational amplifier is connected to the first terminal of the driving sub-circuit through the first switch; the inverting input terminal of the first operational amplifier is also connected to the integrating capacitor
  • the first pole is connected; the output terminal of the first operational amplifier is connected to the second pole of the integrating capacitor and the controller respectively.
  • the second input circuit includes a multiplexer.
  • the multiplexer includes a first input terminal, a second input terminal, and an output terminal.
  • the first input terminal is connected to the second voltage terminal and is configured to receive the second voltage transmitted by the second voltage terminal.
  • the second input terminal is connected to the controller and is configured to receive the data voltage transmitted by the controller.
  • the output terminal of the multiplexer is connected to the control terminal of the driving sub-circuit, and is configured to transmit the second voltage to the driving sub-circuit during the initialization phase and the pre-storage phase. Control terminal; in the data compensation writing stage, the data voltage is transmitted to the control terminal of the driving sub-circuit.
  • the second input circuit when the light-emitting driving cycle further includes an aging sensing phase, further includes a third input terminal.
  • the third input terminal is connected to the third voltage terminal and is configured to receive the third voltage transmitted by the third voltage terminal.
  • the output terminal of the multiplexer is further configured to transmit the third voltage to the control terminal of the driving sub-circuit during the aging sensing stage.
  • the second input circuit further includes a third operational amplifier.
  • the non-inverting input terminal of the third operational amplifier is connected with the output terminal of the multiplexer; the output terminal of the third operational amplifier is connected with the control terminal of the driving sub-circuit; The inverting input terminal is connected to the output terminal of the third operational amplifier.
  • the first input circuit includes a second operational amplifier, a sixth switch, and a seventh switch.
  • the non-inverting input terminal of the second operational amplifier is connected to the sensing circuit through the sixth switch; the non-inverting input terminal of the second operational amplifier is also connected to the first voltage terminal through the seventh switch;
  • the inverting input terminal of the second operational amplifier is connected with the output terminal of the second operational amplifier; the output terminal of the second operational amplifier is also connected with the first terminal of the driving sub-circuit.
  • the external compensation circuit further includes a storage circuit disposed between the sensing circuit and the controller; the storage circuit is configured to store the output of the sensing circuit A sensing signal; and, transmitting the sensing signal to the controller in response to an output control signal; wherein the sensing signal includes at least the threshold compensation voltage.
  • the storage circuit includes a storage capacitor, an eighth switch, and a ninth switch.
  • the sensing circuit is connected to the first pole of the storage capacitor through the eighth switch.
  • the controller is connected to the first pole of the storage capacitor through the ninth switch.
  • the second pole of the storage capacitor is grounded.
  • the driving sub-circuit includes a driving transistor; wherein, the first terminal of the driving transistor is the first terminal of the driving sub-circuit; the control terminal of the driving transistor is the control terminal of the driving sub-circuit .
  • a pixel compensation method is provided.
  • the pixel compensation method is applied to the pixel compensation device described in any one of the above embodiments, and the pixel compensation method includes a plurality of light-emitting driving cycles, and one light-emitting driving cycle includes an initialization phase, a pre-storage phase, and a data compensation writing phase .
  • the initialization phase the first input circuit transmits the first voltage to the first terminal of the driving sub-circuit; the second input circuit transmits the second voltage to the control terminal of the transistor ,
  • the driving sub-circuit is turned on.
  • the first input circuit is empty; the second input circuit maintains the voltage of the control terminal of the driver sub-circuit at the second voltage, so that the first terminal of the driver sub-circuit The voltage is compensated from the first voltage to the threshold compensation voltage.
  • the controller transmits the data voltage to the control terminal of the driving sub-circuit; the sensing circuit senses the threshold compensation voltage and transmits it to the first Input circuit; the first input circuit feeds the threshold compensation voltage back to the first end of the driving sub-circuit.
  • the data voltage is a modified voltage of the actual characteristic value of the driving sub-circuit determined by the controller according to the previous light-emitting driving period.
  • the driving sub-circuit in the initialization phase: the driving sub-circuit is turned on to output a first current; the sensing circuit senses the first current and transmits it to the controller.
  • the sensing circuit In the data compensation writing stage: the sensing circuit transmits the sensed threshold compensation voltage to the controller; the controller determines the threshold compensation voltage according to the first current and the threshold compensation voltage The actual characteristic value of the sub-circuit is driven, and the data voltage to be transmitted in the next data compensation writing stage is corrected according to the actual characteristic value.
  • the light-emitting driving cycle further includes an aging sensing phase.
  • the pixel compensation method further includes: in the aging sensing phase, the second input circuit transmits a third voltage to the control terminal of the driving sub-circuit to control the driving sub-circuit to turn off; the sensing circuit Sensing the second current transmitted from the light-emitting device to the first end of the driving sub-circuit; the controller determines the aging information of the light-emitting device according to the second current, and corrects the aging information to be transmitted according to the aging information The data voltage.
  • the controller is connected to a plurality of the external compensation circuits; the external compensation circuit is connected to a plurality of the pixel driving circuits.
  • different sensing circuits have the same duration of sensing the first current; and/or, in different external compensation circuits and/or the same Different sensing circuits in one external compensation circuit have the same duration for sensing the second current.
  • the sensing circuit includes the voltage sensing sub-circuit.
  • the light-emitting driving cycle also includes a first calibration phase.
  • the pixel compensation method further includes: in the first calibration stage, the first input circuit transmits the first voltage to the voltage sensing sub-circuit, so that the voltage sensing sub-circuit outputs a fourth The voltage is sent to the controller; the controller corrects the sensing voltage signal transmitted by the voltage sensing sub-circuit to the controller according to the difference between the fourth voltage and the first voltage.
  • the sensing circuit includes the current sensing sub-circuit.
  • the light-emitting driving cycle also includes a second calibration phase.
  • the pixel compensation method further includes: in the second calibration stage, a reference current source transmits a reference current to the current sensing sub-circuit, so that the current sensing sub-circuit outputs a third current; the controller According to the difference between the third current and the reference current, correct the sensing current signal transmitted by the current sensing sub-circuit to the controller.
  • a display device including the pixel compensation device described in any of the above embodiments.
  • FIG. 1 is a structural diagram of a display device provided by some embodiments of the present disclosure
  • FIG. 2 is a structural diagram of another display device provided by some embodiments of the present disclosure.
  • FIG. 3 is a structural diagram of a pixel driving circuit provided by some embodiments of the present disclosure.
  • FIG. 4 is a structural diagram of a pixel compensation device provided by some embodiments of the present disclosure.
  • FIG. 5 is a structural diagram of another pixel compensation device provided by some embodiments of the present disclosure.
  • FIG. 6 is a structural diagram of still another pixel compensation device provided by some embodiments of the present disclosure.
  • FIG. 7 is a flowchart of a pixel compensation method provided by some embodiments of the present disclosure.
  • FIG. 8 is a flowchart of another pixel compensation method provided by some embodiments of the present disclosure.
  • FIG. 9 is a flowchart of still another pixel compensation method provided by some embodiments of the present disclosure.
  • FIG. 10 is a flowchart of another pixel compensation method provided by some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of still another pixel compensation device provided by some embodiments of the present disclosure.
  • FIG. 12 is a structural diagram of yet another pixel compensation device provided by some embodiments of the present disclosure.
  • FIG. 13 is a structural diagram of another pixel compensation device provided by some embodiments of the present disclosure.
  • FIG. 14 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the first sub-stage of the initialization stage;
  • 15 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the second sub-stage of the initialization stage;
  • 16 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the pre-storage stage;
  • 17 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the first sub-stage of the data compensation writing stage;
  • FIG. 18 is a schematic diagram of the signal transmission direction in the second sub-stage of the data compensation writing stage of the pixel compensation device shown in FIG. 13;
  • 19 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the first sub-stage of the aging sensing stage;
  • 20 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the second sub-stage of the aging sensing stage;
  • 21 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the first sub-stage of the first calibration stage;
  • FIG. 22 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the second sub-stage of the first calibration stage;
  • FIG. 23 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the first sub-stage of the second calibration stage;
  • 24 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 in the second sub-stage of the second calibration stage;
  • 25 is a schematic diagram of the signal transmission direction of the pixel compensation device shown in FIG. 13 during the calibration phase of the analog-to-digital converter.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features.
  • plural means two or more.
  • connection and its extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • equal includes the stated situation and the situation similar to the stated situation, and the range of the similar situation is within the acceptable deviation range, wherein the acceptable deviation range is as defined by the art
  • the acceptable deviation range is as defined by the art
  • a person of ordinary skill considers the measurement in question and the error associated with the measurement of a specific quantity (ie, the limitations of the measurement system) to determine it.
  • “equal” includes absolute equality and approximately equal, wherein the difference between the two within the acceptable deviation range of approximately equal, for example, which may be equal, is less than or equal to 5% of either one.
  • the pixels in the AMOLED display substrate include a light-emitting device, that is, an OLED, and a pixel circuit connected to the OLED.
  • the output current of the driver thin film transistor (Driver Thin Film Transistor, DTFT for short) in the pixel circuit is used to drive the corresponding OLED to emit light, which directly determines the luminous brightness of the OLED.
  • the output current I ds of the driving transistor satisfies the following formula:
  • ⁇ is the electron mobility of the drive transistor
  • Cox is the capacitance per unit area of the gate oxide layer of the drive transistor
  • It is the ratio of the channel width to the channel length of the driving transistor
  • V gs is the gate-source voltage of the driving transistor
  • V th is the threshold voltage of the driving transistor
  • K is called the characteristic value of the driving transistor.
  • K is related to the electron mobility of the driving transistor.
  • the threshold voltage and the electron mobility of the driving transistor in each pixel circuit may be different. Moreover, as the use time increases, the threshold voltage and electron mobility of each driving transistor are prone to drift. Therefore, the driving capability of each driving transistor (that is, the capability of outputting current under the same light-emitting driving voltage) will be different, which leads to problems such as uneven display of the AMOLED display substrate.
  • the AMOLED display device can compensate the pixels in two ways: internal compensation and external compensation, so as to solve the problem of uneven display of the AMOLED display substrate.
  • the internal compensation is to construct a compensation sub-circuit inside the pixel to compensate the pixel.
  • This compensation method easily causes the aperture ratio of the pixel to decrease, and the driving speed of the AMOLED display substrate decreases.
  • External compensation is to sense related electrical signals, such as voltage or current, in the pixel through a circuit or device outside the pixel, and adjust the related input signal of the corresponding pixel, such as data voltage, according to the electrical signal, to achieve compensation for the pixel.
  • This compensation method has fast driving speed and good compensation effect.
  • the display device 3 generally includes a display substrate 1 and a pixel compensation device 2.
  • the above-mentioned display device 3 includes many types, for example, it can be an organic light-emitting diode (Organic Light-Emitting Diode, OLED for short) display device (including AMOLED display device), quantum dot light-emitting diode (Quantum Dot Light Emitting) Diodes, QLED for short) display devices or Light Emitting Diodes (LED for short) display devices, etc.
  • the above-mentioned display device 3 also includes a variety of product forms, for example, it can be any product or component with a display function such as electronic paper, television, monitor, notebook computer, tablet computer, digital photo frame, mobile phone, navigator, etc.
  • the above-mentioned display substrate 1 has a display area AA and a non-display area BB located on at least one side of the display area AA.
  • a plurality of sub-pixels PX are provided in the display area AA, and the plurality of sub-pixels PX may include, for example, a plurality of red sub-pixels, a plurality of green sub-pixels, and a plurality of blue sub-pixels.
  • the plurality of sub-pixels PX are distributed in an array in the display area AA, and every three sub-pixels PX may constitute one pixel.
  • each sub-pixel PX includes a light-emitting device and a pixel driving circuit 101 connected to the light-emitting device.
  • the pixel driving circuit 101 is configured to drive the corresponding light emitting device to emit light.
  • the above-mentioned display substrate may be an OLED display substrate (including an AMOLED display substrate), a QLED display substrate, or an LED display substrate.
  • the type of the light-emitting device is matched with the type of the corresponding display substrate 1.
  • the light-emitting device corresponding to the OLED display substrate is an OLED.
  • the light-emitting device corresponding to the QLED display substrate is a QLED.
  • the light-emitting device corresponding to the LED display substrate is an LED.
  • the function of the pixel driving circuit 101 is as described above, and examples of its structure include, but are not limited to, "2T1C", “3T1C”, “6T1C”, “6T2C”, “7T1C”, “7T2C” or “8T1C” and so on.
  • T means a transistor
  • the number in front of “T” means the number of transistors
  • C means a capacitor
  • the number in front of “C” means the number of capacitors.
  • “3T1C” means 3 transistors and 1 capacitor.
  • the “3T1C” pixel driving circuit 101 includes a first transistor T1, a second transistor T2, a driving transistor DT, and a first capacitor C0.
  • the control electrode of the first transistor T1 is connected to the first scan signal line G1
  • the first electrode of the first transistor T1 is connected to the control electrode of the driving transistor DT and the first electrode of the first capacitor C0 respectively
  • the first electrode of the first transistor T1 The second pole is connected to node P.
  • the first electrode of the driving transistor DT is connected to the second electrode of the first capacitor C0, the first electrode of the light emitting device PD, and the first electrode of the second transistor T2, respectively, and the second electrode of the driving transistor DT is connected to the first power supply voltage terminal VDD. connect.
  • the control electrode of the second transistor T2 is connected to the second scanning signal line G2, and the second electrode of the second transistor T2 is connected to the node Q.
  • the second pole of the light emitting device PD is connected to the second power supply voltage terminal VSS.
  • the node P is a node where the component that supplies voltage to the control electrode of the driving transistor DT is connected to the pixel driving circuit 101.
  • the node Q may be a node where a component that senses signals (including current or voltage, etc.) related to the driving transistor DT or the light-emitting device PD is connected to the pixel driving circuit 101, and/or a component that supplies voltage to the first electrode of the driving transistor DT and The connection node of the pixel drive circuit 101.
  • the node P and the node Q do not represent actual components, but represent the junction of related electrical connections in the circuit diagram, that is, these nodes are defined by the circuit diagram.
  • the light emitting device PD is an OLED.
  • the first electrode of the light emitting device PD is the anode of the OLED, and the second electrode of the light emitting device PD is the cathode of the OLED.
  • the first power supply voltage terminal VDD provides a high level
  • the second power supply voltage terminal VSS provides a low level.
  • the second power supply voltage terminal VSS is grounded.
  • transistors involved in some embodiments of the present disclosure may be N-type thin film transistors, or P-type thin film transistors, or may also be other devices with the same characteristics.
  • an N-type thin film transistor is taken as an example for description.
  • the control electrode of each transistor used in the pixel driving circuit 101 is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor.
  • the source and drain of the transistor can be symmetrical in structure, the source and drain of the transistor can be structurally indistinguishable, that is, the first and second electrodes of the transistor There can be no difference in structure.
  • the control electrode of each thin film transistor is a gate electrode, a first electrode is a source electrode, and a second electrode is a drain electrode.
  • the aforementioned pixel compensation device 2 is connected to each sub-pixel PX in the display substrate 1, respectively.
  • the pixel compensation device 2 provided by some embodiments of the present disclosure includes a controller 21 and an external compensation circuit 22 connected to the controller 21.
  • the external compensation circuit 22 may be independently provided, or may be integrated in the non-display area BB of the display substrate 1.
  • the controller 21 is an electronic device or device with functions such as signal transmission, data storage, and processing, such as a screen driver board (TCON).
  • the number of external compensation circuits 22 connected to the controller 21 may be one or more, which is specifically selected and determined according to actual needs, which is not limited in some embodiments of the present disclosure. Exemplarily, as shown in FIG. 2, the number of external compensation circuits 22 connected to the controller 21 is multiple.
  • the above-mentioned external compensation circuit 22 is located outside the sub-pixel PX (that is, located in the non-display area BB), and is connected to the pixel driving circuit 101 in at least one sub-pixel PX.
  • the number of pixel driving circuits 101 connected to one external compensation circuit 22 may be one or more, which may be selected and determined according to actual needs.
  • the number of pixel driving circuits 101 connected to one external compensation circuit 22 is multiple.
  • the corresponding relationship between each external compensation circuit 22 and each pixel driving circuit 101 in the display substrate 1 can be selected and determined according to actual needs, as long as the respective functions can be successfully implemented.
  • a plurality of sub-pixels PX in the display substrate 1 are displayed in a row-by-row driving manner, and an external compensation circuit 22 and a corresponding pixel driving circuit 101 of multiple columns (for example, two columns) of sub-pixels PX are displayed. They are connected separately, and the pixel driving circuits 101 corresponding to any two external compensation circuits 22 do not overlap each other.
  • multiple external compensation circuits 22 can simultaneously sense and compensate the sub-pixels PX on different columns in the same row, and the pixel compensation device 2 can realize all sub-pixels in the display substrate 1 by providing fewer external compensation circuits 22 The compensation of PX can effectively improve the efficiency of compensation.
  • the pixel driving circuit 101 includes a driving sub-circuit DS.
  • the first end of the driving sub-circuit DS is connected to the light emitting device PD.
  • a light-emitting driving cycle of the pixel driving circuit includes an initialization phase, a pre-storage phase, and a data compensation writing phase.
  • the external compensation circuit 22 includes a first input circuit 221, a second input circuit 222, and a sensing circuit 223.
  • the first input circuit 221 is connected to the first end of the driving sub-circuit DS and the sensing circuit 223 respectively.
  • the second input circuit 222 is connected to the control terminal of the driving sub-circuit DS.
  • the sensing circuit 223 is also connected to the first end of the controller 21 and the driving sub-circuit DS.
  • the controller 21 is also connected to the control terminal of the driving sub-circuit DS.
  • the driving sub-circuit DS includes a driving transistor DT.
  • the first terminal of the driving transistor DT drives the first terminal of the sub-circuit DS;
  • the control terminal of the driving transistor DT is the control terminal of the driving sub-circuit DS;
  • the second terminal of the driving transistor DT Drive the second end of the sub-circuit DS.
  • the structure of the pixel driving circuit 101 is a "3T1C" structure.
  • the first input circuit 221 and the sensing circuit 223 are respectively connected to the first pole of the driving transistor DT through the second transistor T2.
  • the second input circuit 222 and the controller 21 are respectively connected to the control electrode of the driving transistor DT through the first transistor T1.
  • controller 21 is connected to the control electrode of the driving transistor DT through the first transistor T1”, for example, may be the controller 21 as shown in FIG. 5 directly through the control electrode of the first transistor T1 and the driving transistor DT. connect.
  • controller 21 as shown in FIG. 6 may be connected to the control electrode of the driving transistor DT through the second input circuit 222 and the first transistor T1 in sequence.
  • the first input circuit 221 is configured to transmit the first voltage V1 to the first pole of the driving transistor DT during the initialization phase, to be left empty in the pre-storage phase, and to transmit threshold compensation to the first pole of the driving transistor DT during the data compensation writing phase.
  • the voltage is ⁇ V.
  • the second input circuit 222 is configured to transmit the second voltage V2 to the control electrode of the driving transistor DT during the initialization phase and the pre-storage phase, so that the voltage of the first electrode of the driving transistor DT is compensated by the first voltage V1 during the pre-storage phase. Threshold compensation voltage ⁇ V.
  • both the first voltage V1 and the threshold compensation voltage ⁇ V are less than the turn-on voltage of the light emitting device PD.
  • the sensing circuit 223 is configured to sense the threshold compensation voltage ⁇ V in the data compensation writing stage, and transmit the threshold compensation voltage ⁇ V to the first input circuit 221.
  • the controller 21 is configured to transmit a data voltage to the control electrode of the driving transistor DT during the data compensation writing phase.
  • the above-mentioned data voltage is a voltage after correction of the actual characteristic value of the driving sub-circuit DS determined by the controller 21 according to the last light-emitting driving period.
  • the sensing circuit 223 is further connected to the controller 21, and the sensing circuit 223 is further configured to sense the first current I 2-1 transmitted by the first end of the driving transistor DT during the initialization phase, and to combine the first current I 2-1 is transmitted to the controller 21; and, in the data compensation writing phase, the sensed threshold compensation voltage ⁇ V is transmitted to the controller 21.
  • the controller 21 is further configured to determine the actual characteristic value of the driving transistor DT according to the first current I 2-1 and the threshold compensation voltage ⁇ V, and to correct the data voltage to be transmitted in the next data compensation writing stage according to the actual characteristic value.
  • the pixel compensation device 2 in some embodiments of the present disclosure uses the pixel compensation method described below to compensate each sub-pixel PX in the display substrate 1. Please refer to FIG. 7, the pixel compensation method includes S100-S300.
  • the first input circuit 221 transmits the first voltage V1 to the first electrode of the driving transistor DT; the second input circuit 222 transmits the second voltage to the control electrode of the driving transistor DT, and the driving transistor DT is turned on.
  • the first transistor T1 is turned on in response to the first gate scanning signal; the second transistor T2 is turned on in response to the second gate scanning signal; the first input circuit 221 passes through the The second transistor T2 transmits the first voltage V1 to the first electrode of the driving transistor DT and the second electrode of the first capacitor C0; the second input circuit 222 transmits the second voltage V2 to the driving transistor DT through the first transistor T1 Control pole and the first pole of the first capacitor C0.
  • the driving transistor DT is turned on, the first capacitor C0 is charged, the voltage of the first electrode is equal to the second voltage V2, and the voltage of the second electrode is equal to the first voltage V1.
  • the first input circuit 221 is empty; the second input circuit 222 maintains the control electrode voltage of the driving transistor DT at the second voltage V2, so that the first electrode voltage of the driving transistor DT is compensated by the first voltage V1 To the threshold compensation voltage ⁇ V.
  • the vacancy of the first input circuit 221 means that the first input circuit 221 is disconnected from the relevant voltage terminal and does not transmit the first voltage V1 or other signals to the driving transistor DT.
  • the first transistor T1 is turned on in response to the first gate scan signal; the second transistor T2 is turned on in response to the second gate scan signal; the first input circuit 221 Empty; the second input circuit 222 continuously transmits the second voltage V2 to the control electrode of the driving transistor DT through the first transistor T1, and the second voltage controls the driving transistor DT to turn on; the first power supply voltage terminal VDD will drive the second voltage of the transistor DT
  • the voltage of one pole is pulled up until the driving transistor DT reaches the critical state of on and off; the voltage of the first pole of the driving transistor DT is stable at the threshold compensation voltage ⁇ V (that is, the difference between the second voltage and the threshold voltage of the driving transistor DT) ,
  • the threshold compensation voltage ⁇ V is simultaneously written into the second pole of the first capacitor C0.
  • the controller 21 transmits the data voltage to the control electrode of the driving transistor DT; the sensing circuit 223 senses the threshold compensation voltage ⁇ V and transmits it to the first input circuit 221; the first input circuit 221 The threshold compensation voltage ⁇ V is fed back to the first pole of the driving transistor DT.
  • the data voltage may be a modified voltage of the actual characteristic value of the driving transistor DT determined by the controller 21 according to the last light-emitting driving period.
  • the first transistor T1 is turned on in response to the first gate scan signal; the second transistor T2 is turned on in response to the second gate scan signal; the controller 21
  • the data voltage is transmitted to the first pole of the driving transistor DT and the first pole of the first capacitor C0 through the second transistor T2; the sensing circuit 223 senses the threshold compensation voltage ⁇ V through the first transistor T1 and transmits it to The first input circuit 221; the first input circuit 221 feeds the threshold compensation voltage ⁇ V back to the first pole of the driving transistor DT.
  • the first electrode voltage of the driving transistor DT is maintained at the threshold compensation voltage ⁇ V.
  • the output current of the driving transistor DT that is, the light-emitting current I of the light- emitting device PD
  • the light-emitting current I of the light- emitting device PD has nothing to do with the threshold voltage of the driving transistor DT. That is, the pixel compensation device 2 of some of the above embodiments realizes compensation for the threshold voltage Vth of the driving transistor DT.
  • the pixel compensation method is based on S100-S300 in the foregoing embodiments, replacing S100 with S100', and S300 with S300'.
  • the first input circuit 221 transmits the first voltage V1 to the first electrode of the driving transistor DT; the second input circuit 222 transmits the second voltage to the control electrode of the driving transistor DT, and the driving transistor DT is turned on , And output the first current I 2-1 ; the sensing circuit 223 senses the first current I 2-1 and transmits it to the controller 21.
  • the first transistor T1 is turned on in response to the first gate scanning signal; the second transistor T2 is turned on in response to the second gate scanning signal; the first input circuit 221 passes through the The second transistor T2 transmits the first voltage V1 to the first electrode of the driving transistor DT and the second electrode of the first capacitor C0; the second input circuit 222 transmits the second voltage V2 to the driving transistor DT through the first transistor T1
  • the control electrode and the first electrode of the first capacitor C0 in this way, the driving transistor DT is turned on, and output the first current I 2-1 ; the first capacitor C0 is charged, the voltage of the first electrode is equal to the second voltage V2, The pole voltage is equal to the first voltage V1; the sensing circuit 223 senses the first current I 2-1 through the second transistor T2, and transmits it to the controller 21.
  • the absolute value of the gate-source voltage Vgs of the driving transistor DT is greater than the absolute value of the threshold voltage of the driving transistor DT, so that the driving transistor DT meets the conduction condition and can output the first current I 2-1 .
  • the controller 21 transmits the data voltage to the control electrode of the driving transistor DT; the sensing circuit 223 senses the threshold compensation voltage ⁇ V, and transmits it to the controller 21 and the first input circuit 221 respectively
  • the first input circuit 221 feeds the threshold compensation voltage ⁇ V back to the first pole of the driving transistor DT; the controller 221 determines the actual characteristic value of the driving transistor according to the first current I 1-2 and the threshold compensation voltage ⁇ V, and according to the actual characteristics The value is corrected for the next data to compensate for the voltage of the data to be transmitted in the write phase.
  • the data voltage may be a modified voltage of the actual characteristic value of the driving transistor DT determined by the controller 21 according to the last light-emitting driving period.
  • the first transistor T1 is turned on in response to the first gate scan signal; the second transistor T2 is turned on in response to the second gate scan signal; the controller 21
  • the data voltage is transmitted to the first pole of the driving transistor DT and the first pole of the first capacitor C0 through the second transistor T2; the sensing circuit 223 senses the threshold compensation voltage ⁇ V through the first transistor T1, and transmits them respectively To the first input circuit 221 and the controller 21; the first input circuit 221 feeds the threshold compensation voltage ⁇ V back to the first pole of the driving transistor DT.
  • the first electrode voltage of the driving transistor DT is maintained at the threshold compensation voltage ⁇ V.
  • the controller 21 can also determine the actual characteristic value K of the driving transistor DT according to the received first current I 2-1 and the threshold compensation voltage ⁇ V, and according to the actual characteristic value K corrects the data voltage V data to be transmitted in the next data compensation writing phase.
  • specific values of the first voltage V1, the second voltage V2, and the original characteristic value K0 of the driving transistor DT are pre-stored in the controller 21.
  • the specific value of the threshold voltage Vth of the driving transistor DT can be determined.
  • the data voltage to be transmitted in the next data compensation writing stage can be corrected through a related formula or corresponding relationship.
  • the controller 21 is connected to a plurality of external compensation circuits 22.
  • the external compensation circuit 22 is connected to a plurality of pixel driving circuits 101.
  • different external compensation circuits 22 and/or different sensing circuits 223 in the same external compensation circuit 22 have the same duration for sensing the first current I 2-1.
  • all the sensing circuits 223 in the pixel compensation device 2 sense the first current I 2-1 for a time period that is uniformly set to the same fixed value. In this way, it is beneficial to reduce the sensing deviation caused by the difference of the sensing circuit 223, and to improve the overall sensing signal, that is, to improve the accuracy of the sensed first current I 2-1 , thereby effectively ensuring the characteristic value compensation of the driving transistor DT. Accuracy.
  • the pixel compensation device 2 in some of the above embodiments can cause the pixel driving circuit 101 to generate a corresponding threshold compensation voltage ⁇ V according to the second voltage V2 provided by the second input circuit 222 in one light-emitting driving cycle, and to set the threshold value
  • the compensation voltage ⁇ V is fed back to the first pole of the driving transistor DT in real time through the sensing circuit 223 and the first input circuit 221, thereby realizing compensation for the threshold voltage of the driving transistor DT.
  • the above-mentioned threshold compensation voltage can also be transmitted to the controller 21 through the sensing circuit 223.
  • the sensing circuit 223 can also sense the first current I 1-2 output by the driving transistor DT during the initialization phase, and transmit it to the controller 21.
  • the first current I 1-2 is the output current when the control electrode voltage of the driving transistor DT is the second voltage V2 and the first electrode voltage is the first voltage V1.
  • the controller 21 can determine the actual characteristic value of the driving transistor DT according to the first current I 1-2 and the above-mentioned threshold compensation voltage ⁇ V, so that in the next data compensation writing stage, the data voltage to be written is performed according to the actual characteristic value. Correction to achieve compensation for the characteristic value of the drive transistor DT. That is, the pixel compensation device 2 in some of the above embodiments can compensate the pixel driving circuit 101 in terms of the threshold voltage and the characteristic value of the driving transistor DT, which effectively improves the accuracy of compensation and ensures that the display effect of the display device 3 is uniform.
  • the sensing circuit 223 is connected to the first electrode of the driving transistor DT and the light emitting device PD, respectively. Therefore, the sensing circuit 223 can be configured to sense signals related to the driving transistor DT (for example, the first current I 1-2 or the threshold compensation voltage ⁇ V, etc.), and can also be configured to sense signals related to the light emitting device PD. , For example, sensing the discharge current of the light emitting device PD, etc.
  • the light-emitting driving cycle further includes an aging sensing phase.
  • the second input circuit 222 is also configured to transmit a third voltage to the control electrode of the driving transistor DT during the aging sensing phase, and control the driving transistor DT to turn off.
  • the sensing circuit 223 is further configured to sense the second current transmitted from the light emitting device PD to the first pole of the driving transistor DT in the aging sensing stage.
  • the controller 21 is further configured to determine the aging information of the light emitting device PD according to the second current, and to correct the data voltage to be transmitted in the next data compensation writing stage according to the aging information.
  • the pixel compensation method adopted by the pixel compensation device 2 in some embodiments of the present disclosure includes S100-S300 or S100', S200, S300' and S400.
  • the second input circuit 222 transmits the third voltage to the control electrode of the driving transistor DT, and controls the driving transistor DT to turn off;
  • the sensing circuit 223 senses the light emitting device PD transmitted to the first electrode of the driving transistor DT The second current;
  • the controller 21 determines the aging information of the light-emitting device PD according to the second current, and corrects the data voltage to be transmitted according to the aging information.
  • the aging sensing phase is immediately after the light emitting phase, and the driving transistor DT does not output any signal to the light emitting device PD.
  • the light-emitting device PD relies on the residual charge after emitting light to discharge itself, and the resulting discharge current is the above-mentioned second current, and the second current is related to the degree of aging of the light-emitting device PD.
  • the third voltage is configured to turn off the driving transistor DT. It can be a low level or a high level, which is specifically determined according to the type of the driving transistor DT.
  • the driving transistor DT is a P-type transistor, and the third voltage is a high level.
  • the driving transistor DT is an N-type transistor, and the third voltage is a low level.
  • the first transistor T1 is turned on in response to the first gate scan signal; the second transistor T2 is turned on in response to the second gate scan signal; the second input circuit 222
  • the third voltage is transmitted to the control electrode of the driving transistor DT through the first transistor T1, and the driving transistor DT is controlled to be turned off;
  • the sensing circuit 223 senses the second current through the second transistor T2 and transmits it to the controller 21;
  • the controller 21 can determine the aging information of the light emitting device PD according to the second current to correct the data voltage to be transmitted.
  • the pixel compensation circuit provided by some of the above embodiments can also perform aging compensation for the light-emitting device PD when the threshold voltage and the characteristic value of the driving transistor DT are compensated. Therefore, the effect of pixel compensation is further improved, and the display effect of the display device 3 is ensured to be uniform.
  • the relevant voltage of the light-emitting device PD (such as the anode voltage of an OLED) has no clear and firm relationship with its luminous efficiency, the relevant technology can only obtain a rough fitting relationship curve through a large number of test experiments.
  • the combined relationship curve has no reusability for different display substrates 1.
  • the relevant current (including the light-emitting current or the discharge current) of the light-emitting device PD is linearly related to the light-emitting efficiency, and the relationship between the two is more direct and accurate. In this way, the corresponding relationship between the two can be determined through less test experiments.
  • the pixel compensation device 2 in some embodiments of the present disclosure detects the light-emitting device PD.
  • the discharge current is used for aging compensation, and a more accurate aging compensation effect can be obtained through a more simplified method.
  • the aging sensing of the light emitting device PD may be performed once every certain time interval.
  • the specific time interval can be selected and determined according to the actual situation.
  • the aging test is performed on the light emitting device PD every three days.
  • the aging sensing phase in the specific light-emitting driving cycle is set as the effective phase.
  • the pixel compensation device 2 performs aging sensing and compensation functions.
  • the aging sensing phase in other light-emitting driving cycles is set as an invalid phase.
  • the pixel compensation device 2 does not perform the function of aging sensing and compensation, but skips this stage to perform the function of the next corresponding stage.
  • the controller 21 is connected to a plurality of external compensation circuits 22.
  • the external compensation circuit 22 is connected to a plurality of pixel driving circuits 101.
  • different external compensation circuits 22 and/or different sensing circuits 223 in the same external compensation circuit 22 have the same duration for sensing the second current.
  • the duration of sensing the second current by all the sensing circuits 223 in the pixel compensation device 2 is uniformly set to the same fixed value. In this way, it is beneficial to reduce the sensing deviation caused by the difference of the sensing circuit 223, and to improve the overall sensing signal, that is, to improve the accuracy of the second current sensed, thereby effectively ensuring the accuracy of the aging compensation of the light emitting device PD.
  • sensing circuit 223 is as described above, and its specific structure can be selected and determined according to actual needs, which is not limited in some embodiments of the present disclosure.
  • the sensing circuit 223 includes a voltage sensing sub-circuit 2232.
  • the voltage sensing sub-circuit 2232 is connected to the first pole of the driving transistor DT and the first input circuit 221 respectively. It is configured to sense the threshold compensation voltage during the data compensation writing stage, and transmit it to the first input circuit 221.
  • the voltage sensing sub-circuit 2232 is also connected to the controller 21.
  • the voltage sensing sub-circuit is further configured to sense the threshold compensation voltage ⁇ V during the data compensation writing phase, and transmit the threshold compensation voltage ⁇ V to the controller 21.
  • the voltage sensing sub-circuit 2232 includes a first operational amplifier A1, a fourth switch S4, and a fifth switch S5.
  • the non-inverting input terminal of the first operational amplifier A1 is also connected to the first pole of the driving transistor DT through the fourth switch S4.
  • the inverting input terminal of the first operational amplifier A1 is also connected to the output terminal of the first operational amplifier A1 through the fifth switch S5.
  • the sensing circuit further includes a current sensing sub-circuit 2231.
  • the current sensing sub-circuit 2231 is connected to the first pole of the driving transistor DT and the controller 21 respectively. It is configured to sense the first current I 1-2 in the initialization phase, and transmit the first current I 1-2 to the controller 21; and/or, sense the second current in the aging sensing phase, and transfer the second current Transmitted to the controller 21.
  • the current sensing sub-circuit 2231 includes a first operational amplifier A1, an integrating capacitor C1, a first switch S1, and a second switch S2.
  • the non-inverting input terminal of the first operational amplifier A1 is connected to the reference voltage terminal Uref through the second switch S2.
  • the inverting input terminal of the first operational amplifier A1 is connected to the first pole of the driving transistor DT through the first switch S1.
  • the inverting input terminal of the first operational amplifier A1 is also connected to the first pole of the integrating capacitor C1.
  • the output terminal of the first operational amplifier A1 is connected to the second pole of the integrating capacitor C1 and the controller 21 respectively.
  • the current sensing sub-circuit 2231 may further include a third switch S3, and the third switch S3 is respectively connected to the inverting input terminal of the first operational amplifier A1 and the reference current source IS.
  • the reference current source IS may also be connected to a related voltage terminal (not shown in the figure) to ensure its normal working state.
  • the voltage sensing sub-circuit 2232 and the current sensing sub-circuit 2231 may share the first operational amplifier A1.
  • the sensing circuit 223 (including the voltage sensing sub-circuit 2232 and the current sensing sub-circuit 2231) needs to be calibrated regularly to ensure that it has good sensing precision.
  • the first input circuit 221 is connected to the voltage sensing sub-circuit 2232. With this design, the first input circuit 221 can be configured to provide a voltage input signal to the sensing circuit 223 to assist it in achieving calibration.
  • the light-emitting driving cycle further includes a first calibration phase.
  • the first input circuit 221 is further configured to transmit the first voltage to the voltage sensing sub-circuit 2232 in the first calibration stage, so that the voltage sensing sub-circuit 2232 outputs the fourth voltage to the controller 21.
  • the controller 21 is further configured to: according to the difference between the fourth voltage and the first voltage, correct the sensed voltage signal transmitted from the voltage sensing sub-circuit 2232 to the controller 21.
  • the sensing voltage signal includes a threshold compensation voltage.
  • the pixel compensation method adopted by the pixel compensation device 2 in some embodiments of the present disclosure further includes S500.
  • the first input circuit 221 transmits the first voltage to the voltage sensing sub-circuit 2232, so that the voltage sensing sub-circuit 2232 outputs the fourth voltage to the controller 21; the controller 21 according to the fourth voltage The difference with the first voltage is used to correct the voltage sensing signal transmitted from the voltage sensing sub-circuit 2232 to the controller 21.
  • the pixel compensation device 2 in some of the above embodiments multiplexes the first input circuit 221 to provide the input signal required for calibration to the voltage sensing sub-circuit 2232.
  • the pixel compensation device 2 in some embodiments of the present disclosure can simplify the corresponding external voltage terminals and corresponding The signal line saves corresponding space, thereby facilitating the narrow bezel design of the display device 3.
  • the light-emitting driving cycle further includes a second calibration phase.
  • the current sensing sub-circuit 2231 is also connected to the reference current source IS.
  • the reference current source IS is configured to transmit the reference current to the current sensing sub-circuit 2231 in the second calibration stage, so that the current sensing sub-circuit 2231 outputs the third current.
  • the controller 21 is further configured to correct the sensed current signal transmitted by the current sensing sub-circuit 2231 to the controller 21 according to the difference between the third current and the reference current. Wherein, the sensed current signal includes the first current and/or the second current.
  • the pixel compensation method in some embodiments of the present disclosure further includes S600.
  • the reference current source IS transmits the reference current to the current sensing sub-circuit 2231, so that the current sensing sub-circuit 2231 outputs the third current; the controller 21 according to the difference between the third current and the reference current , The current sensing sub-circuit 2231 transmits the sensing current signal to the controller 21 to be corrected.
  • the voltage sensing sub-circuit 2232 and the current sensing sub-circuit 2231 are out of adjustment (that is, the precision becomes poor), the process is usually relatively slow. Therefore, the voltage sensing sub-circuit 2232 and/or the current sensing sub-circuit The calibration of 2231 can be carried out at regular intervals. The specific time interval can be selected and determined according to the actual situation. Exemplarily, the voltage sensing sub-circuit 2232 and the current sensing sub-circuit 2231 are calibrated once every three days. Exemplarily, the first calibration phase or the second calibration phase in the specific light-emitting driving period is set as the effective phase.
  • the pixel compensation device 2 performs a calibration function for the voltage sensing sub-circuit 2232 or a calibration function for the current sensing sub-circuit 2231.
  • the first calibration phase or the second calibration phase in other light-emitting driving cycles is set as an invalid phase.
  • the pixel compensation device 2 does not perform the calibration function for the voltage sensing sub-circuit 2232 or the calibration function for the current sensing sub-circuit 2231.
  • the first calibration phase or the second calibration phase may also be set within the standby time period of the display device 3.
  • the standby time period refers to a time period during which the display device 3 displays a black screen.
  • the external compensation circuit 22 when the external compensation circuit 22 and the pixel driving circuits 101 in the plurality of sub-pixels PX are respectively connected (for example, two), the external compensation circuit 22 further includes a storage circuit 224.
  • the storage circuit 224 is disposed between the sensing circuit 223 and the controller 21, and is configured to store the sensing signal output by the sensing circuit 223; and transmit the sensing signal to the controller 21 in response to the output control signal.
  • the sensing signal is at least a threshold compensation voltage.
  • the sensing signal may further include at least one of the first current, the second current, the third current, and the fourth voltage.
  • the pixel compensation circuit utilizes the temporary data storage function of the storage circuit 224 to stagger the data processing time period of the controller 21 and the signal sensing time period of the sensing circuit 223, and to detect the signal when needed. Output to the controller 21.
  • the controller 21 can have more sufficient time to process relevant data, and the operating pressure of the controller 21 and even the display device 3 can be effectively reduced while ensuring the sensing efficiency of the sensing circuit 223.
  • the sensing circuit 223 senses the first current and temporarily stores it in the storage circuit 224.
  • the storage circuit 224 transmits the above-mentioned first current to the controller 21 in response to the corresponding output control signal.
  • the sensing circuit 223 senses the threshold compensation voltage and temporarily stores it in the storage circuit 224.
  • the storage circuit 224 transmits the above-mentioned threshold compensation voltage to the controller 21 in response to the corresponding output control signal.
  • the sensing circuit 223 senses the second current and temporarily stores it in the storage circuit 224.
  • the storage circuit 224 transmits the aforementioned second current to the controller 21 in response to the corresponding output control signal.
  • the voltage sensing sub-circuit 2232 outputs the fourth voltage and temporarily stores it in the storage circuit 224.
  • the storage circuit 224 transmits the aforementioned fourth voltage to the controller 21 in response to the corresponding output control signal.
  • the current sensing sub-circuit 2231 senses the third current and temporarily stores it in the storage circuit 224.
  • the storage circuit 224 transmits the aforementioned third current to the controller 21 in response to the corresponding output control signal.
  • the function of the storage circuit 224 is as described above, and its specific structure can be selected and determined according to actual needs, which is not limited in some embodiments of the present disclosure.
  • the storage circuit 224 includes a storage capacitor C2, an eighth switch S8, and a ninth switch S9.
  • the sensing circuit 223 is connected to the first pole of the storage capacitor C2 through the eighth switch S8.
  • the controller 21 is connected to the first pole of the storage capacitor C2 through the ninth switch S9. The second pole of the storage capacitor C2 is grounded.
  • the function of the first input circuit 221 is as described above, and its specific structure can be selected and determined according to actual needs, which is not limited in some embodiments of the present disclosure.
  • the first input circuit 221 includes a second operational amplifier A2, a sixth switch S6, and a seventh switch S7.
  • the non-inverting input terminal of the second operational amplifier A2 is connected to the sensing circuit 223 through the sixth switch S6.
  • the non-inverting input terminal of the second operational amplifier A2 is also connected to the first voltage terminal U1 through the seventh switch S7.
  • the inverting input terminal of the second operational amplifier A2 is connected to its output terminal.
  • the output terminal of the second operational amplifier A2 is also connected to the first pole of the driving transistor DT.
  • the function of the second input circuit 222 is as described above, and its specific structure can be selected and determined according to actual needs, which is not limited in some embodiments of the present disclosure.
  • the second input circuit 222 includes a multiplexer MUX.
  • the multiplexer MUX includes a first input terminal, a second input terminal, and an output terminal.
  • the first input terminal is connected to the second voltage terminal U2 and is configured to receive the second voltage transmitted by the second voltage terminal U2.
  • the second input terminal is connected to the controller 21 and is configured to receive the data voltage transmitted by the controller 21.
  • the output terminal is connected to the control electrode of the driving transistor DT, and is configured to transmit the second voltage to the control electrode of the driving transistor DT during the initialization phase and the pre-storage phase; and during the data compensation writing phase, the data voltage is transmitted to the driving transistor DT The control pole.
  • the second input circuit 222 further includes a third input terminal.
  • the third input terminal is connected to the third voltage terminal U3 and is configured to receive the third voltage transmitted by the third voltage terminal U3.
  • the output terminal of the multiplexer MUX is also configured to transmit the third voltage to the control electrode of the driving transistor in the aging sensing phase.
  • the multiplexer MUX can respond to the corresponding control signal to realize the time-sharing transmission of different data.
  • the multiplexer MUX is also connected to the first control signal line H1 and the second control signal line H2, respectively.
  • the data transmission function of the multiplexer MUX is jointly controlled by the first control signal and the second control signal. For example, when the first control signal and the second control signal are both at a low level, the multiplexer MUX outputs the second voltage. When the first control signal is at a low level and the second control signal is at a high level, the multiplexer MUX outputs the data voltage. When the first control signal and the second control signal are both high, the multiplexer MUX outputs the third voltage.
  • the controller 21 transmits the data voltage to the pixel driving circuit 101 through the multiplexer MUX, that is, the multiplexer MUX time-division multiplexes the second input circuit 222 or the transmission of the data voltage. Signal line.
  • the multiplexer MUX time-division multiplexes the second input circuit 222 or the transmission of the data voltage. Signal line.
  • the second input circuit 222 further includes a third operational amplifier A3.
  • the non-inverting input terminal of the third operational amplifier A3 is connected to the output terminal of the multiplexer MUX.
  • the output terminal of the third operational amplifier A3 is connected to the control electrode of the driving transistor DT.
  • the inverting input terminal of the third operational amplifier A3 is connected to its output terminal.
  • the third operational amplifier A3 is used as a voltage follower in the second input circuit 222.
  • the pixel compensation device 2 can increase the signal driving force of the second input circuit 222 by providing the voltage follower in the second input circuit 222, that is, reduce the loss of the data voltage during the transmission process. This effectively guarantees the accuracy of the data voltage received by the pixel driving circuit 101 and even the display effect of the display device 3.
  • the pixel compensation device 2 may further include an analog-to-digital converter ADC and/or a digital-to-analog converter DAC.
  • the analog-to-digital converter ADC is provided between the sensing circuit 223 and the controller 21, and is configured to output the analog signal (such as the first current, the second current, the third current, the threshold compensation voltage or the fourth voltage) output by the external compensation circuit 22 ) Is converted into a digital signal and transmitted to the controller 21.
  • the digital-to-analog converter DAC is disposed between the controller 21 and the pixel driving circuit 101 and is configured to convert a digital signal (for example, a data voltage) output by the controller 21 into an analog signal, and transmit it to the pixel driving circuit 101.
  • the pixel compensation device 2 shown in FIG. 13 is taken as an example below for detailed description.
  • the second transistor T2 in the pixel driving circuit 101 is connected to the first switch S1 and the fourth switch S4 in the sensing circuit 223, respectively.
  • the sensing circuit 223 is respectively connected to the eighth switch S8 in the storage circuit 224 and the sixth switch S6 in the first input circuit 221 through the output terminal of the first operational amplifier A1.
  • the storage circuit 224 is connected to the input terminal of the analog-to-digital converter ADC through the ninth switch S9.
  • the output terminal of the analog-to-digital converter ADC is connected to the controller 21.
  • the controller 21 is also connected to the input terminal of the digital-to-analog converter DAC.
  • the output terminal of the digital-to-analog converter DAC is connected to the second input circuit 222 through the first input terminal of the multiplexer MUX.
  • the second input circuit 222 is connected to the second pole of the first transistor T1 in the pixel circuit through the output terminal of the third operational amplifier A3.
  • the method for the pixel compensation device 2 shown in FIG. 13 to compensate the pixel drive circuit 101 is as follows.
  • the first gate scan signal controls the first transistor T1 to turn on; the second gate scan signal controls the second transistor T2 On; the sixth switch S6 is off; the seventh switch S7 is closed; the multiplexer MUX responds to the first control signal and the second control signal to output the second voltage at the first input; the second operational amplifier A2 turns the A voltage is transmitted to the first electrode of the driving transistor DT through the second transistor T2; the multiplexer MUX transmits the second voltage to the control electrode of the driving transistor DT through the third operational amplifier A3 and the first transistor T1; the driving transistor DT Output the first current.
  • the first switch S1, the second switch S2, and the eighth switch S8 are closed; the third switch S3, the fourth switch S4, and the fifth switch S5
  • the ninth switch S9 is disconnected; the first current is transmitted to the inverting input terminal of the first operational amplifier A1 through the second transistor T2 and the first switch S1; the reference voltage is transmitted to the non-inverting input terminal of the first operational amplifier A1 through the second switch S2
  • the first signal includes the voltage signal and/or the first current signal; the first signal passes through the first
  • the eight switch S8 is transmitted to the first pole of the storage capacitor C2; the storage capacitor C2 is charged to store the first signal.
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, and the eighth switch S8 are turned off; the ninth switch S9 Closed; the storage capacitor C2 is discharged, and the first signal is transmitted to the controller 21 through the ninth switch S9 and the analog-to-digital converter ADC.
  • the first gate scan signal controls the first transistor T1 to turn on; the second gate scan signal controls the second transistor T2 to turn on; the first switch S1, the second switch S2, and the third switch
  • the switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8, and the ninth switch S9 are all off; the multiplexer MUX responds to the first control signal and the first control signal.
  • Two control signals output the second voltage of the first input terminal; the second voltage is continuously transmitted to the control electrode of the driving transistor DT through the third operational amplifier A3 and the first transistor T1; the input terminal of the second operational amplifier A2 is empty; the driving transistor DT
  • the voltage of the first pole of is compensated by the first voltage to the threshold compensation voltage; the threshold compensation voltage is written into the second pole of the first capacitor C0.
  • the first gate scan signal controls the first transistor T1 to turn on; the second gate scan signal controls the second The second transistor T2 is turned on; the first switch S1, the second switch S2, the third switch S3, and the seventh switch S7 are turned off; the fourth switch S4, the fifth switch S5, and the sixth switch S6 are closed; the multiplexer MUX In response to the first control signal and the second control signal, the data voltage of the first input terminal is output.
  • the controller 21 transmits the data voltage to the first input terminal of the multiplexer MUX through the digital-to-analog converter DAC; the multiplexer MUX transmits the data voltage to the driving transistor DT through the third operational amplifier A3 and the first transistor T1
  • the threshold compensation voltage is transmitted to the non-inverting input terminal of the first operational amplifier A1 through the second transistor T2 and the fourth switch S4, and then through the output terminal of the voltage follower composed of the first operational amplifier A1 and the fifth switch S5 Output; afterwards, it is fed back to the first pole of the driving transistor DT through the sixth switch S6, the second operational amplifier A2, and the second transistor T2.
  • the eighth switch S8 is closed; the ninth switch S9 is open; the voltage formed by the first operational amplifier A1 and the fifth switch S5
  • the threshold compensation voltage output by the output terminal of the follower is also transmitted to the first pole of the storage capacitor C2 through the eighth switch S8; the storage capacitor C2 is charged to store the threshold compensation voltage.
  • the eighth switch S8 is open; the ninth switch S9 is closed; the storage capacitor C2 is discharged, and the threshold compensation voltage is passed through the ninth switch S9 and the analog-to-digital converter ADC It is transmitted to the controller 21; the controller 21 determines the actual characteristic value of the driving transistor DT according to the first signal and the threshold compensation voltage.
  • the first gate scan signal controls the first transistor T1 to turn on; the second gate scan signal controls the second The transistor T2 is turned on; the multiplexer MUX responds to the first control signal and the second control signal to output the third voltage at the third input terminal to control the driving transistor DT to turn off; the third switch S3, the fourth switch S4, and the The fifth switch S5, the sixth switch S6 and the seventh switch S7 are turned off; the multiplexer MUX transmits the third voltage to the control electrode of the driving transistor DT through the third operational amplifier A3 and the first transistor T1 to control the driving transistor DT Turn off; the light emitting device PD discharges and outputs a second current.
  • the first switch S1, the second switch S2, and the eighth switch S8 are closed; the ninth switch S9 is open; the second current passes through the The two transistors T2 and the first switch S1 are transmitted to the inverting input terminal of the first operational amplifier A1; the reference voltage is transmitted to the non-inverting input terminal of the first operational amplifier A1 through the second switch S2; by the integrating capacitor C1 and the first operational amplifier A1
  • the composed integrator outputs a second signal according to the second current and the reference voltage; the second signal includes a voltage signal and/or a second current signal; the second signal is transmitted to the first pole of the storage capacitor C2 through the eighth switch S8 ;
  • the storage capacitor C2 is charged to store the second signal.
  • the first switch S1, the second switch S2, and the eighth switch S8 are opened; the ninth switch S9 is closed; the second signal stored in the storage capacitor C2 passes The ninth switch S9 and the analog-to-digital converter ADC are transmitted to the controller 21; the controller 21 determines the aging information of the light-emitting device PD according to the second signal.
  • the first gate scan signal controls the first transistor T1 to turn off; the second gate scan signal controls the second transistor T2 to turn off; the fourth switch S4, The fifth switch S5, the seventh switch S7, and the eighth switch S8 are closed; the first switch S1, the second switch S2, the third switch S3, the sixth switch S6, and the ninth switch S9 are opened; the first voltage passes through the second calculation
  • the amplifier A2 and the fourth switch S4 are transmitted to the non-inverting input terminal of the first operational amplifier A1; the voltage follower composed of the first operational amplifier A1 and the fifth switch S5 outputs the fourth voltage; the fourth voltage is transmitted to the eighth switch S8
  • the first pole of the storage capacitor C2; the storage capacitor C2 is charged to store the fourth voltage.
  • the first gate scan signal controls the first transistor T1 to turn off; the second gate scan signal controls the second transistor T2 to turn off; the first switch S1, the second The second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are opened; the ninth switch S9 is closed; the storage capacitor C2 is discharged, and the fourth switch
  • the voltage is transmitted to the controller 21 through the ninth switch S9 and the analog-to-digital converter ADC; the controller 21 corrects the voltage sensing signal transmitted to the controller 21 by the voltage sensing sub-circuit 2232 according to the difference between the fourth voltage and the first voltage .
  • the first gate scan signal controls the first transistor T1 to turn off; the second gate scan signal controls the second transistor T2 to turn off; the second switch S2, The third switch S3 and the eighth switch S8 are closed; the first switch S1, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the ninth switch S9 are open.
  • the reference voltage is transmitted to the non-inverting input terminal of the first operational amplifier A1 through the second switch S2; the reference current is transmitted to the inverting input terminal of the first operational amplifier A1 through the third switch S3, which is composed of the first operational amplifier A1 and the integrating capacitor C1
  • the integrator outputs a third signal; the third signal includes a voltage signal and/or a third current signal; the third signal is transmitted to the first pole of the storage capacitor C2 through the eighth switch S8; the storage capacitor C2 is charged to store the third signal.
  • the first gate scan signal controls the first transistor T1 to turn off; the second gate scan signal controls the second transistor T2 to turn off;
  • the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are opened;
  • the ninth switch S9 is closed;
  • the storage capacitor C2 is discharged, and the third
  • the current signal is transmitted to the controller 21 through the ninth switch S9 and the analog-to-digital converter ADC; the controller 21 corrects the current sensing signal transmitted to the controller 21 by the current sensing sub-circuit 2231 according to the difference between the third current and the reference current .
  • the first operational amplifier A1 and the integrating capacitor C1 are used to form an integrator to sense and output current signals (including the first current signal and the second current signal). ; By connecting the inverting input terminal of the first operational amplifier A1 to its output terminal, it is used as a voltage follower to sense and output a voltage signal (including a threshold compensation voltage). That is, the pixel compensation device 2 in some embodiments of the present disclosure performs two functions of voltage sensing and current sensing by multiplexing the first operational amplifier A1. In this way, the circuit structure of the pixel compensation device 2 can be simplified, and the space occupied by the corresponding electronic devices can be saved, so that the narrow frame design of the display device 3 can be realized.
  • the first voltage terminal U1 can also be used to calibrate the analog-to-digital converter ADC.
  • the first gate scan signal controls the first transistor T1 to turn off; the second gate scan signal controls the second transistor T2 to turn off; the first switch S1 , The second switch S2, the third switch S3, and the sixth switch S6 are open; the fourth switch S4, the fifth switch S5, the seventh switch S7, the eighth switch S8, and the ninth switch S9 are closed; the first voltage passes through the second The operational amplifier A2 and the fourth switch S4 are transmitted to the non-inverting input terminal of the first operational amplifier A1; the voltage follower composed of the first operational amplifier A1 and the fifth switch S5 outputs the first voltage; the first voltage passes through the eighth switch S8 and The ninth switch S9 is transmitted to the analog-to-digital converter ADC; the analog-to-digital converter ADC outputs the fifth
  • the controller 21 can correct the sensing signal (including the sensing current signal and the sensing voltage signal) transmitted by the sensing circuit 223 to the controller 21 according to the difference between the fifth voltage and the first voltage to further ensure the sensing.
  • the accuracy of the measurement signal makes the compensation of the sub-pixel PX by the pixel compensation device 2 more accurate.
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 or the ninth switch S9 can be any electronic device that can be opened and closed through a control signal.
  • the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, the eighth switch S8, or the ninth switch S9 are switches.
  • Type transistor The switching transistor includes a P-type transistor or an N-type transistor, which is controlled to be turned on or off by a corresponding control signal applied to its control electrode.
  • the control signal is provided by the controller 21 (for example, TCON).
  • the beneficial effects that can be achieved by the display device 3 or the pixel compensation method in some embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the pixel compensation device 2 in some of the above embodiments, and will not be repeated here.

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Abstract

一种像素补偿装置，包括控制器以及与控制器连接的外部补偿电路；所述外部补偿电路位于像素外且与至少一个像素驱动电路连接，所述像素驱动电路包括驱动子电路，所述驱动子电路的第一端与发光器件连接；所述外部补偿电路包括第一输入电路、第二输入电路和感测电路；所述第一输入电路与所述驱动子电路的第一端、所述感测电路分别连接；所述第二输入电路与所述驱动子电路的控制端连接；所述感测电路还与所述驱动子电路的第一端连接；所述控制器还与所述驱动子电路的控制端连接。

Description

像素补偿装置及像素补偿方法、显示装置
本申请要求于2020年06月11日提交中国专利局、申请号为202010527799.5的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示领域，例如涉及一种像素补偿装置及像素补偿方法、显示装置。
背景技术
有源矩阵有机发光二极管(Active-matrix organic light emitting diode，AMOLED)显示技术具有超轻薄、高色域、高对比度、宽视角、快速响应等诸多优点，在行业内受到广泛应用。
发明内容
一方面，提供一种像素补偿装置。所述像素补偿装置包括控制器以及与所述控制器连接的外部补偿电路。所述外部补偿电路位于像素外且与至少一个像素驱动电路连接；所述像素驱动电路包括驱动子电路；所述像素驱动电路的一个发光驱动周期包括初始化阶段、预存储阶段以及数据补偿写入阶段；所述外部补偿电路包括第一输入电路、第二输入电路和感测电路。所述第一输入电路与所述驱动子电路的第一端、所述感测电路分别连接，配置为：在所述初始化阶段向所述驱动子电路的第一端传输第一电压，在所述预存储阶段空置；以及，在数据补偿写入阶段向所述驱动子电路的第一端传输阈值补偿电压。所述第二输入电路与所述驱动子电路的控制端连接，配置为：在所述初始化阶段和所述预存储阶段向所述驱动子电路的控制端传输第二电压，以使所述驱动子电路的第一端的电压在所述预存储阶段由所述第一电压补偿至所述阈值补偿电压。其中，所述驱动子电路的第一端与发光器件连接，所述第一电压和所述阈值补偿电压均小于所述发光器件的开启电压；所述阈值补偿电压等于所述第二电压与所述驱动子电路的阈值电压之差。所述感测电路还与所述驱动子电路的第一端连接，配置为：在所述数据补偿写入阶段感测所述阈值补偿电压，并将所述阈值补偿电压传输至所述第一输入电路。所述控制器还与所述驱动子电路的控制端连接，配置为：在所述数据补偿写入阶段向所述驱动子电路的控制端传输数据电压。
在一些实施例中，所述数据电压为所述控制器根据上一个所述发光驱动周期确定的所述驱动子电路的实际特征值修正后的电压。
在一些实施例中，所述感测电路还与所述控制器连接，所述感测电路还配置为：在所述初始化阶段感测所述驱动子电路的第一端传输的第一电流，并将所述第一电流传输至所述控制器；以及，在所述数据补偿写入阶段将感测到的所述阈值补偿电压传输至所述控制器。所述控制器还配置为：根据所述第一电流和所述阈值补偿电压确定所述驱动子电路的实际特征值，并根据所述实际特征值修正下一个所述数据补偿写入阶段中待传输的数据电压。
在一些实施例中，所述发光驱动周期还包括老化感测阶段。所述第二输入电路还配置为：在所述老化感测阶段向所述驱动子电路的控制端传输第三电压，控制所述驱动子电路关断。所述感测电路还配置为：在所述老化感测阶段感测所述发光器件传输至所述驱动子电路的第一端的第二电流。所述控制器还配置为：根据所述第二电流确定所述发光器件的老化信息，并根据所述老化信息修正下一个所述数据补偿写入阶段待传输的数据电压。
在一些实施例中，所述感测电路包括电压感测子电路，所述电压感测子电路与所述驱动子电路的第一端以及所述第一输入电路分别连接；所述电压感测子电路配置为：在所述数据补偿写入阶段感测所述阈值补偿电压，并将所述阈值补偿电压传输至所述第一输入电路。
在一些实施例中，所述电压感测子电路还与所述控制器连接；所述电压感测子电路还配置为：在所述数据补偿写入阶段将感测到的所述阈值补偿电压传输至所述控制器。
在一些实施例中，所述发光驱动周期还包括第一校准阶段。所述第一输入电路还配置为：在所述第一校准阶段将所述第一电压传输至所述电压感测子电路，以使所述电压感测子电路输出第四电压至所述控制器。所述控制器还配置为：根据所述第四电压与所述第一电压的差值，修正所述电压感测子电路传输至所述控制器的感测电压信号；所述感测电压信号包括所述阈值补偿电压。
在一些实施例中，所述电压感测子电路包括所述第一运算放大器、第四开关以及第五开关。所述第一运算放大器的同相输入端还通过所述第四开关与所述驱动子电路的第一端连接；所述第一运算放大器的反相输入端还通过所述第五开关与所述第一运算放大器的输出端连接。
在一些实施例中，所述感测电路包括电流感测子电路，所述电流感测子电路与所述驱动子电路的第一端以及所述控制器分别连接；所述电流感测子电路配置为：在所述初始化阶段感测第一电流，将所述第一电流传输至所述控制器；和/或，在所述老化感测阶段感测所述第二电流，将所述第二电流传 输至所述控制器。
在一些实施例中，所述发光驱动周期还包括第二校准阶段。所述电流感测子电路还与基准电流源连接。所述基准电流源配置为：在所述第二校准阶段将基准电流传输至所述电流感测子电路，以使所述电流感测子电路输出第三电流。所述控制器还配置为：根据所述第三电流与所述基准电流的差值，修正所述电流感测子电路传输至所述控制器的感测电流信号；所述感测电流信号包括所述第一电流和/或所述第二电流。
在一些实施例中，所述电流感测子电路包括第一运算放大器、积分电容、第一开关以及第二开关；其中，所述第一运算放大器的同相输入端通过所述第二开关与基准电压端连接；所述第一运算放大器的反相输入端通过所述第一开关与所述驱动子电路的第一端连接；所述第一运算放大器的反相输入端还与所述积分电容的第一极连接；所述第一运算放大器的输出端与所述积分电容的第二极、所述控制器分别连接。
在一些实施例中，所述第二输入电路包括多路复用器。所述多路复用器包括第一输入端、第二输入端以及输出端。所述第一输入端与第二电压端连接，配置为：接收所述第二电压端传输的所述第二电压。所述第二输入端与控制器连接，配置为：接收所述控制器传输的所述数据电压。所述多路复用器的输出端与所述驱动子电路的控制端连接，配置为：在所述初始化阶段和所述预存储阶段，将所述第二电压传输至所述驱动子电路的控制端；在所述数据补偿写入阶段，将所述数据电压传输至所述驱动子电路的控制端。
在一些实施例中，在所述发光驱动周期还包括老化感测阶段时，所述第二输入电路还包括第三输入端。所述第三输入端与第三电压端连接，配置为：接收所述第三电压端传输的第三电压。所述多路复用器的输出端还配置为：在所述老化感测阶段，将所述第三电压传输至所述驱动子电路的控制端。
在一些实施例中，所述第二输入电路还包括第三运算放大器。所述第三运算放大器的同相输入端与所述多路复用器的输出端连接；所述第三运算放大器的输出端与所述驱动子电路的控制端连接；所述第三运算放大器的反相输入端与所述第三运算放大器的输出端连接。
在一些实施例中，所述第一输入电路包括第二运算放大器、第六开关以及第七开关。所述第二运算放大器的同相输入端通过所述第六开关与所述感测电路连接；所述第二运算放大器的同相输入端还通过所述第七开关与第一电压端连接；所述第二运算放大器的反相输入端与所述第二运算放大器的输出端连接；所述第二运算放大器的输出端还与所述驱动子电路的第一端连接。
在一些实施例中，所述外部补偿电路还包括存储电路，所述存储电路设置于所述感测电路与所述控制器之间；所述存储电路配置为：存储所述感测电路输出的感测信号；以及，响应于输出控制信号将所述感测信号传输至所述控制器；其中，所述感测信号至少包括所述阈值补偿电压。
在一些实施例中，所述存储电路包括存储电容、第八开关以及第九开关。所述感测电路通过所述第八开关与所述存储电容的第一极连接。所述控制器通过所述第九开关与所述存储电容的第一极连接。所述存储电容的第二极接地。
在一些实施例中，所述驱动子电路包括驱动晶体管；其中，所述驱动晶体管的第一极为所述驱动子电路的第一端；所述驱动晶体管的控制极为所述驱动子电路的控制端。
另一方面，提供一种像素补偿方法。所述像素补偿方法应用于上述任一实施例所述的像素补偿装置，所述像素补偿方法包括多个发光驱动周期，一个所述发光驱动周期包括初始化阶段、预存储阶段和数据补偿写入阶段。在所述初始化阶段：所述第一输入电路将所述第一电压传输至所述驱动子电路的第一端；所述第二输入电路将所述第二电压传输至所述晶体管的控制端，所述驱动子电路导通。在所述预存储阶段：所述第一输入电路空置；所述第二输入电路将所述驱动子电路的控制端电压维持在所述第二电压，以使所述驱动子电路的第一端电压由所述第一电压补偿至所述阈值补偿电压。在所述数据补偿写入阶段：所述控制器向所述驱动子电路的控制端传输所述数据电压；所述感测电路感测所述阈值补偿电压，并将其传输至所述第一输入电路；所述第一输入电路将所述阈值补偿电压馈回至所述驱动子电路的第一端。
在一些实施例中，所述数据电压为所述控制器根据上一个所述发光驱动周期确定的所述驱动子电路的实际特征值修正后的电压。
在一些实施例中，在所述初始化阶段：所述驱动子电路导通，输出第一电流；所述感测电路感测所述第一电流，并将其传输至所述控制器。在所述数据补偿写入阶段：所述感测电路将感测到的所述阈值补偿电压传输至所述控制器；所述控制器根据所述第一电流和所述阈值补偿电压确定所述驱动子电路的实际特征值，并根据所述实际特征值修正下一个所述数据补偿写入阶段中待传输的数据电压。
在一些实施例中，所述发光驱动周期还包括老化感测阶段。所述像素补偿方法还包括：在所述老化感测阶段，所述第二输入电路向所述驱动子电路的控制端传输第三电压，控制所述驱动子电路关断；所述感测电路感测所述 发光器件传输至所述驱动子电路的第一端的第二电流；所述控制器根据所述第二电流确定所述发光器件的老化信息，并根据所述老化信息修正待传输的所述数据电压。
在一些实施例中，所述控制器与多个所述外部补偿电路连接；所述外部补偿电路与多个所述像素驱动电路连接。不同的所述外部补偿电路中和/或同一个所述外部补偿电路中不同所述感测电路感测第一电流的时长相同；和/或，不同的所述外部补偿电路中和/或同一个所述外部补偿电路中不同所述感测电路感测所述第二电流的时长相同。
在一些实施例中，所述感测电路包括所述电压感测子电路。所述发光驱动周期还包括第一校准阶段。所述像素补偿方法还包括：在所述第一校准阶段，所述第一输入电路将所述第一电压传输至所述电压感测子电路，以使所述电压感测子电路输出第四电压至所述控制器；所述控制器根据所述第四电压与所述第一电压的差值，修正所述电压感测子电路传输至所述控制器的感测电压信号。
在一些实施例中，所述感测电路包括所述电流感测子电路。所述发光驱动周期还包括第二校准阶段。所述像素补偿方法还包括：在所述第二校准阶段，基准电流源将基准电流传输至所述电流感测子电路，以使所述电流感测子电路输出第三电流；所述控制器根据所述第三电流与所述基准电流的差值，修正所述电流感测子电路传输至所述控制器的感测电流信号。
再一方面，提供一种显示装置，包括上述任一实施例所述的像素补偿装置。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开一些实施例提供的一种显示装置的结构图；
图2为本公开一些实施例提供的另一种显示装置的结构图；
图3为本公开一些实施例提供的一种像素驱动电路的结构图；
图4为本公开一些实施例提供的一种像素补偿装置的结构图；
图5为本公开一些实施例提供的另一种像素补偿装置的结构图；
图6为本公开一些实施例提供再一种像素补偿装置的结构图；
图7为本公开一些实施例提供的一种像素补偿方法的流程图；
图8为本公开一些实施例提供的另一种像素补偿方法的流程图；
图9为本公开一些实施例提供的再一种像素补偿方法的流程图；
图10为本公开一些实施例提供的又一种像素补偿方法的流程图；
图11为本公开一些实施例提供的再一种像素补偿装置的结构图；
图12为本公开一些实施例提供的又一种像素补偿装置的结构图；
图13为本公开一些实施例提供的又一种像素补偿装置的结构图；
图14为图13所示的像素补偿装置在初始化阶段的第一个子阶段的信号传输方向的示意图；
图15为图13所示的像素补偿装置在初始化阶段的第二个子阶段的信号传输方向的示意图；
图16为图13所示的像素补偿装置在预存储阶段的信号传输方向的示意图；
图17为图13所示的像素补偿装置在数据补偿写入阶段的第一个子阶段的信号传输方向的示意图；
图18为图13所示的像素补偿装置在数据补偿写入阶段的第二个子阶段的信号传输方向的示意图；
图19为图13所示的像素补偿装置在老化感测阶段的第一个子阶段的信号传输方向的示意图；
图20为图13所示的像素补偿装置在老化感测阶段的第二个子阶段的信号传输方向的示意图；
图21为图13所示的像素补偿装置在第一校准阶段的第一个子阶段的信号传输方向的示意图；
图22为图13所示的像素补偿装置在第一校准阶段的第二个子阶段的信号传输方向的示意图；
图23为图13所示的像素补偿装置在第二校准阶段的第一个子阶段的信号传输方向的示意图；
图24为图13所示的像素补偿装置在第二校准阶段的第二个子阶段的信号传输方向的示意图；
图25为图13所示的像素补偿装置在模数转换器校准阶段的信号传输方向的示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“配置为”的使用意味着开放和包容性的语言，其不排除适用于或配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量 的测量相关的误差(即，测量系统的局限性)所确定。例如，“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
AMOLED显示基板中的像素包括发光器件，即OLED，以及与OLED连接的像素电路。像素电路中的驱动晶体管(Driver Thin Film Transistor，简称DTFT)的输出电流用于驱动对应OLED发光，直接决定该OLED的发光亮度。驱动晶体管的输出电流I ds满足如下公式：
Figure PCTCN2021097978-appb-000001
Figure PCTCN2021097978-appb-000002
其中，μ为驱动晶体管的电子迁移率，C ox为驱动晶体管的栅氧化层单位面积电容，
Figure PCTCN2021097978-appb-000003
为驱动晶体管的沟道宽和沟道长之比，V gs为驱动晶体管的栅源极电压，V th为驱动晶体管的阈值电压，K称为驱动晶体管的特征值。K与驱动晶体管的电子迁移率有关。
由于工艺制程的差异，每个像素电路中的驱动晶体管的阈值电压和其电子迁移率等参数可能存在不同。并且，随着使用时间的增加，各驱动晶体管的阈值电压和电子迁移率等参数容易发生漂移。因此，各驱动晶体管的驱动能力(即在相同的发光驱动电压下输出电流的能力)会有所不同，导致AMOLED显示基板出现显示不均等问题。
在相关技术中，AMOLED显示装置可以通过内部补偿和外部补偿两种方式对像素进行补偿，以解决AMOLED显示基板出现显示不均等不良问题。其中，内部补偿即在像素内部构建补偿子电路，以对像素进行补偿。该补偿方式容易导致像素的开口率减小，AMOLED显示基板的驱动速度降低。外部补偿即通过像素外的电路或装置感测像素内的相关电信号，例如电压或电流等，并根据该电信号调节对应像素的相关输入信号，例如数据电压等，以实现对像素的补偿。该补偿方式驱动速度快、补偿效果好。
基于此，请参阅图1，本公开一些实施例提供了一种显示装置3。该显示装置3通常包括显示基板1以及像素补偿装置2。
需要说明的是，上述显示装置3的类型包括多种，例如，可以为有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示装置(包括AMOLED显示装置)、量子点发光二极管(Quantum Dot Light Emitting Diodes，简称QLED)显示装置或发光二极管(Light Emitting Diodes，简称LED)显示装置 等。上述显示装置3的产品形式也包括多种，例如，可以为电子纸、电视机、显示器、笔记本电脑、平板电脑、数码相框、手机、导航仪等任何具有显示功能的产品或部件。
上述显示基板1具有显示区AA和位于显示区AA的至少一侧的非显示区BB。显示区AA内设置有多个子像素PX，多个子像素PX例如可以包括多个红色子像素、多个绿色子像素和多个蓝色子像素。示例性的，所述多个子像素PX呈阵列分布于显示区AA，每三个子像素PX可以构成一个像素。其中，每个子像素PX包括发光器件以及与该发光器件连接的像素驱动电路101。像素驱动电路101配置为驱动对应的发光器件发光。
需要说明的是，上述显示基板1的类型可以有多种，例如，可以为OLED显示基板(包括AMOLED显示基板)、QLED显示基板或LED显示基板等。
上述发光器件的类型可以有多种，发光器件的类型与所对应的显示基板1的类型匹配设置。例如，OLED显示基板对应的发光器件为OLED。又例如，QLED显示基板对应的发光器件为QLED。再例如，LED显示基板对应的发光器件为LED。
像素驱动电路101的功能如上所述，其结构的例子包括，但不限于“2T1C”、“3T1C”、“6T1C”、“6T2C”、“7T1C”、“7T2C”或“8T1C”等。其中，“T”表示为晶体管，位于“T”前面的数字表示为晶体管的个数，“C”表示为电容器，位于“C”前面的数字表示为电容器的个数。例如，“3T1C”表示3个晶体管和1个电容器。
示例性的，“3T1C”的结构如图3所示。该“3T1C”像素驱动电路101包括第一晶体管T1、第二晶体管T2、驱动晶体管DT以及第一电容C0。其中，第一晶体管T1的控制极与第一扫描信号线G1连接，第一晶体管T1的第一极与驱动晶体管DT的控制极和第一电容C0的第一极分别连接，第一晶体管T1的第二极与节点P连接。驱动晶体管DT的第一极与第一电容C0的第二极、发光器件PD的第一极和第二晶体管T2的第一极分别连接，驱动晶体管DT的第二极与第一电源电压端VDD连接。第二晶体管T2的控制极与第二扫描信号线G2连接，第二晶体管T2的第二极与节点Q连接。发光器件PD的第二极与第二电源电压端VSS连接。其中，节点P为向驱动晶体管DT的控制极提供电压的部件与该像素驱动电路101连接的节点。节点Q可以为感测驱动晶体管DT或发光器件PD相关信号(包括电流或电压等)的部件与该像素驱动电路101连接的节点，和/或向驱动晶体管DT的第一极提供电压的部件与该像素驱动电路101的连接的节点。
需要说明的是，在本公开一些实施例提供的电路中，节点P和节点Q并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
示例性的，发光器件PD为OLED。发光器件PD的第一极为OLED的阳极，发光器件PD的第二极为OLED的阴极。在此基础上，容易理解的是，第一电源电压端VDD提供高电平，第二电源电压端VSS提供低电平。示例性的，第二电源电压端VSS接地。
需要说明的是，本公开一些实施例中涉及的各晶体管可以为N型薄膜晶体管，也可以为P型薄膜晶体管，或者还可以为其他特性相同的器件。
本公开的各实施例中均以N型薄膜晶体管为例进行说明。
在一些示例中，像素驱动电路101所采用的各晶体管的控制极为晶体管的栅极，第一极为晶体管的源极和漏极中的一者，第二极为晶体管的源极和漏极中的另一者。需要说明的是，由于晶体管的源极、漏极在结构上可以是对称的，所以晶体管的源极、漏极在结构上可以是没有区别的，也就是说，晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，上述各晶体管为N型薄膜晶体管的情况下，各薄膜晶体管的控制极为栅极，第一极为源极，第二极为漏极。
上述像素补偿装置2与显示基板1内的各子像素PX分别连接。
请参阅图2，本公开一些实施例提供的像素补偿装置2包括：控制器21以及与控制器21连接的外部补偿电路22。示例性的，外部补偿电路22可以独立设置，也可以集成于显示基板1的非显示区BB。
需要说明的是，控制器21为具有信号传输、数据存储和处理等功能的电子装置或器件，例如屏驱动板(TCON)等。与控制器21连接的外部补偿电路22的数目可以为一个或者多个，具体根据实际需要选择确定，本公开一些实施例对此不做限定。示例性的，如图2所示，与控制器21连接的外部补偿电路22的数目为多个。
在一些示例中，上述外部补偿电路22位于子像素PX外(即位于非显示区BB)，且与至少一个子像素PX内的像素驱动电路101连接。
需要说明地是，与一个外部补偿电路22连接的像素驱动电路101的数目可以为一个或多个，具体可以根据实际需要选择确定。
在一些示例中，与一个外部补偿电路22连接的像素驱动电路101的数目为多个。此时，每个外部补偿电路22与显示基板1中各个像素驱动电路101的对应关系，可以根据实际需要选择确定，只要能够顺利实现各自功能均可。 示例性的，如图2所示，显示基板1中的多个子像素PX采用逐行驱动的方式进行显示，一个外部补偿电路22与多列(例如两列)子像素PX的对应像素驱动电路101分别连接，且任意两个外部补偿电路22对应的像素驱动电路101互不重叠。这样设计，多个外部补偿电路22可以同时对同一行的不同列上的子像素PX进行感测以及补偿，像素补偿装置2可以通过设置较少的外部补偿电路22实现显示基板1中所有子像素PX的补偿，有效提高补偿效率。
在一些示例中，像素驱动电路101包括驱动子电路DS。驱动子电路DS的第一端与发光器件PD连接。像素驱动电路的一个发光驱动周期包括初始化阶段、预存储阶段以及数据补偿写入阶段。
请参阅图4和图5，外部补偿电路22包括第一输入电路221、第二输入电路222和感测电路223。第一输入电路221与驱动子电路DS的第一端、感测电路223分别连接。第二输入电路222与驱动子电路DS的控制端连接。感测电路223还与控制器21、驱动子电路DS的第一端连接。控制器21还与驱动子电路DS的控制端连接。
示例性的，驱动子电路DS包括驱动晶体管DT，驱动晶体管DT的第一极为驱动子电路DS的第一端；驱动晶体管DT的控制极为驱动子电路DS的控制端；驱动晶体管DT的第二极为驱动子电路DS的第二端。
示例性的，请参阅图5或图6，像素驱动电路101的结构为“3T1C”结构。第一输入电路221和感测电路223分别通过第二晶体管T2，与驱动晶体管DT的第一极连接。第二输入电路222和控制器21分别通过第一晶体管T1，与驱动晶体管DT的控制极连接。
需要说明的是，上述“控制器21通过第一晶体管T1与驱动晶体管DT的控制极连接”例如，可以是如图5所示的控制器21直接通过第一晶体管T1与驱动晶体管DT的控制极连接。
或者，还可以是如图6所示的控制器21依次通过第二输入电路222和第一晶体管T1与驱动晶体管DT的控制极连接。
第一输入电路221配置为：在初始化阶段向驱动晶体管DT的第一极传输第一电压V1，在预存储阶段空置，以及，在数据补偿写入阶段向驱动晶体管DT的第一极传输阈值补偿电压ΔV。第二输入电路222配置为：在初始化阶段和预存储阶段向驱动晶体管DT的控制极传输第二电压V2，以使驱动晶体管DT的第一极的电压在预存储阶段由第一电压V1补偿至阈值补偿电压ΔV。
其中，第一电压V1和阈值补偿电压ΔV均小于发光器件PD的开启电压。以保证发光器件PD在初始化阶段、预存储阶段和数据补偿写入阶段均不发 光。阈值补偿电压ΔV等于第二电压V2与驱动晶体管DT的阈值电压Vth之差，即ΔV＝V2-Vth。
感测电路223配置为：在数据补偿写入阶段感测阈值补偿电压ΔV，并将阈值补偿电压ΔV传输至第一输入电路221。
控制器21配置为：在数据补偿写入阶段向驱动晶体管DT的控制极传输数据电压。
示例性的，上述数据电压为控制器21根据上一个发光驱动周期确定的驱动子电路DS的实际特征值修正后的电压。
示例性的，感测电路223还与控制器21连接，感测电路223还配置为：在初始化阶段感测驱动晶体管DT的第一端传输的第一电流I 2-1，并将第一电流I 2-1传输至控制器21；以及，在数据补偿写入阶段将感测到的阈值补偿电压ΔV传输至控制器21。控制器21还配置为：根据第一电流I 2-1和阈值补偿电压ΔV确定驱动晶体管DT的实际特征值，并根据实际特征值修正下一个数据补偿写入阶段中待传输的数据电压。
本公开一些实施例中的像素补偿装置2采用如下所述的像素补偿方法，对显示基板1中的各子像素PX进行补偿。请参阅图7，该像素补偿方法包括S100～S300。
S100、在初始化阶段：第一输入电路221将第一电压V1传输至驱动晶体管DT的第一极；第二输入电路222将第二电压传输至驱动晶体管DT的控制极，驱动晶体管DT导通。
示例性的，请参阅图5，在初始化阶段：第一晶体管T1响应于第一栅极扫描信号导通；第二晶体管T2响应于第二栅极扫描信号导通；第一输入电路221通过第二晶体管T2，将第一电压V1传输至驱动晶体管DT的第一极和第一电容C0的第二极；第二输入电路222通过第一晶体管T1，将第二电压V2传输至驱动晶体管DT的控制极和第一电容C0的第一极。这样，驱动晶体管DT导通，第一电容C0充电，其第一极电压与第二电压V2相等，其第二极电压与第一电压V1相等。
此时，驱动晶体管DT的栅源电压Vgs等于第二电压V2与第一电压V1之差，即Vgs＝V2-V1。并且，驱动晶体管DT的栅源电压Vgs的绝对值大于驱动晶体管DT的阈值电压的绝对值，以使驱动晶体管满足导通条件。
S200、在预存储阶段：第一输入电路221空置；第二输入电路222将驱动晶体管DT的控制极电压维持在第二电压V2，以使驱动晶体管DT的第一极电压由第一电压V1补偿至阈值补偿电压ΔV。
此处，第一输入电路221空置是指第一输入电路221断开与相关电压端的连接，不向驱动晶体管DT传输第一电压V1或其他信号。
示例性的，请继续参阅图5，在预存储阶段：第一晶体管T1响应于第一栅极扫描信号导通；第二晶体管T2响应于第二栅极扫描信号导通；第一输入电路221空置；第二输入电路222通过第一晶体管T1，持续传输第二电压V2至驱动晶体管DT的控制极，该第二电压控制驱动晶体管DT导通；第一电源电压端VDD将驱动晶体管DT的第一极的电压拉高，直至驱动晶体管DT达到导通和关断的临界状态；驱动晶体管DT的第一极电压稳定于阈值补偿电压ΔV(即第二电压与驱动晶体管DT的阈值电压之差)，该阈值补偿电压ΔV同时写入第一电容C0的第二极。
S300、在数据补偿写入阶段：控制器21向驱动晶体管DT的控制极传输数据电压；感测电路223感测阈值补偿电压ΔV，并将其传输至第一输入电路221；第一输入电路221将阈值补偿电压ΔV馈回至驱动晶体管DT的第一极。
示例性的，数据电压可以为控制器21根据上一个发光驱动周期确定的驱动晶体管DT的实际特征值修正后的电压。
示例性的，请继续参阅图5，在数据补偿写入阶段：第一晶体管T1响应于第一栅极扫描信号导通；第二晶体管T2响应于第二栅极扫描信号导通；控制器21通过第二晶体管T2，将数据电压传输至驱动晶体管DT的第一极和第一电容C0的第一极；感测电路223通过第一晶体管T1，感测阈值补偿电压ΔV，并将其传输至第一输入电路221；第一输入电路221将阈值补偿电压ΔV馈回至驱动晶体管DT的第一极。这样，驱动晶体管DT的第一极电压维持在阈值补偿电压ΔV。此时，驱动晶体管DT的栅源电压Vgs＝Vdata-V2+Vth；其中，Vdata代表数据电压。
如此，在发光阶段，驱动晶体管DT的输出电流，也即发光器件PD的发光电流I 发光＝K(Vgs-Vth) 2＝K(Vdata-V2) 2。可见，发光器件PD的发光电流I 发光与驱动晶体管DT的阈值电压无关。也即，上述一些实施例的像素补偿装置2实现了对驱动晶体管DT的阈值电压Vth的补偿。
在另一些实施例中，请参阅图8，像素补偿方法在上述实施例的S100～S300的基础上，将S100替换为S100’，将S300替换为S300’。
S100’、在初始化阶段：第一输入电路221将第一电压V1传输至驱动晶体管DT的第一极；第二输入电路222将第二电压传输至驱动晶体管DT的控制极，驱动晶体管DT导通，并输出第一电流I 2-1；感测电路223感测第一电流I 2-1，并将其传输至控制器21。
示例性的，请参阅图5，在初始化阶段：第一晶体管T1响应于第一栅极扫描信号导通；第二晶体管T2响应于第二栅极扫描信号导通；第一输入电路221通过第二晶体管T2，将第一电压V1传输至驱动晶体管DT的第一极和第一电容C0的第二极；第二输入电路222通过第一晶体管T1，将第二电压V2传输至驱动晶体管DT的控制极和第一电容C0的第一极，这样，驱动晶体管DT导通，输出第一电流I 2-1；第一电容C0充电，其第一极电压与第二电压V2相等，其第二极电压与第一电压V1相等；感测电路223通过第二晶体管T2感测第一电流I 2-1，并将其传输至控制器21。
此时，驱动晶体管DT的栅源电压Vgs等于第二电压V2与第一电压V1之差，即Vgs＝V2-V1。并且，驱动晶体管DT的栅源电压Vgs的绝对值大于驱动晶体管DT的阈值电压的绝对值，以使驱动晶体管DT满足导通条件，能够输出第一电流I 2-1。
容易理解的是，第一电流I 2-1与驱动晶体管DT的栅源电压Vgs满足公式：I 1-2＝K(Vgs-V2) 2。因此，I 1-2＝K(V2-V1-Vth) 2；其中，I 1-2代表第一电流，K代表驱动晶体管DT的实际特征值。如此，根据该第一电流I 1-2、第一电压V1、第二电压V2、以及后续确定的驱动晶体管DT的阈值电压ΔV，便可以确定驱动晶体管DT的实际特征值。
S300’、在数据补偿写入阶段：控制器21向驱动晶体管DT的控制极传输数据电压；感测电路223感测阈值补偿电压ΔV，并分别将其传输至控制器21和第一输入电路221；第一输入电路221将阈值补偿电压ΔV馈回至驱动晶体管DT的第一极；控制器221根据第一电流I 1-2和阈值补偿电压ΔV确定驱动晶体管的实际特征值，并根据实际特征值修正下一个数据补偿写入阶段中待传输的数据电压。
示例性的，数据电压可以为控制器21根据上一个发光驱动周期确定的驱动晶体管DT的实际特征值修正后的电压。
示例性的，请继续参阅图5，在数据补偿写入阶段：第一晶体管T1响应于第一栅极扫描信号导通；第二晶体管T2响应于第二栅极扫描信号导通；控制器21通过第二晶体管T2，将数据电压传输至驱动晶体管DT的第一极和第一电容C0的第一极；感测电路223通过第一晶体管T1，感测阈值补偿电压ΔV，并将其分别传输至第一输入电路221和控制器21；第一输入电路221将阈值补偿电压ΔV馈回至驱动晶体管DT的第一极。这样，驱动晶体管DT的第一极电压维持在阈值补偿电压ΔV。此时，驱动晶体管DT的栅源电压Vgs＝Vdata-V2+Vth；其中，Vdata代表数据电压。
这样设计，除了能够实现阈值电压Vth的补偿以外；控制器21还能根据接收到的第一电流I 2-1和阈值补偿电压ΔV，确定驱动晶体管DT的实际特征值K，并根据实际特征值K修正下一个数据补偿写入阶段中待传输的数据电压V data。
示例性的，控制器21中预存储有第一电压V1、第二电压V2和驱动晶体管DT的原始特征值K0的具体数值。这样，首先根据接收到的阈值补偿电压ΔV(也即V2-Vth)，便能确定驱动晶体管DT的阈值电压Vth的具体数值。然后，结合接收到的第一电流I 1-2，通过公式I 1-2＝K(V2-V1-Vth) 2,便可以确定驱动晶体管DT的实际特征值。进而，根据驱动晶体管DT的实际特征值K与其原始特征值K0的差值，通过相关公式或对应关系，便能够修正下一个数据补偿写入阶段中待传输的数据电压。
在一些示例中，请参阅图2，控制器21与多个外部补偿电路22连接。外部补偿电路22与多个像素驱动电路101连接。示例性的，不同的外部补偿电路22中和/或同一个外部补偿电路22中的不同感测电路223感测第一电流I 2-1的时长相同。
也即，像素补偿装置2中的所有感测电路223感测第一电流I 2-1的时长统一设置为同一固定值。如此，利于降低因感测电路223不同带来的感测偏差，提高整体感测信号，即提高感测到的第一电流I 2-1的准确性，进而有效保证驱动晶体管DT的特征值补偿的准确性。
可见，上述一些实施例中的像素补偿装置2能够在一个发光驱动周期内，使像素驱动电路101根据第二输入电路222提供的第二电压V2，生成对应的阈值补偿电压ΔV，并将该阈值补偿电压ΔV通过感测电路223和第一输入电路221实时馈回至驱动晶体管DT的第一极，从而实现对驱动晶体管DT的阈值电压的补偿。同时，上述阈值补偿电压还可以通过感测电路223传输至控制器21。而感测电路223还能够在初始化阶段，感测驱动晶体管DT输出的第一电流I 1-2，并将其传输至控制器21。该第一电流I 1-2为驱动晶体管DT控制极电压为第二电压V2、第一极电压为第一电压V1的情况下的输出电流。控制器21根据该第一电流I 1-2和上述阈值补偿电压ΔV，能够确定驱动晶体管DT的实际特征值，以在下一个数据补偿写入阶段，根据该实际特征值对待写入的数据电压进行修正，实现对驱动晶体管DT特征值的补偿。也即，上述一些实施例中的像素补偿装置2能够对像素驱动电路101进行驱动晶体管DT的阈值电压和特征值两方面的补偿，有效提高补偿的准确度，保证显示装置3的显示效果均一。
需要说明的是，在本公开一些实施例提供的像素补偿装置2中，感测电 路223与驱动晶体管DT的第一极、发光器件PD分别连接。因此，感测电路223除能够配置为感测与驱动晶体管DT有关的信号(例如第一电流I 1-2或阈值补偿电压ΔV等)以外，还能够配置为与感测发光器件PD相关的信号，例如感测发光器件PD的放电电流等。
在一些实施例中，发光驱动周期还包括老化感测阶段。第二输入电路222还配置为：在老化感测阶段向驱动晶体管DT的控制极传输第三电压，控制驱动晶体管DT关断。感测电路223还配置为：在老化感测阶段感测发光器件PD传输至驱动晶体管DT的第一极的第二电流。控制器21还配置为：根据第二电流确定发光器件PD的老化信息，并根据老化信息修正下一个数据补偿写入阶段待传输的数据电压。
相应地，请参阅图9或图10，本公开一些实施例中的像素补偿装置2采用的像素补偿方法在包括S100～S300或S100’、S200、S300’的基础上，还包括S400。
S400、在老化感测阶段：第二输入电路222向驱动晶体管DT的控制极传输第三电压，控制驱动晶体管DT关断；感测电路223感测发光器件PD传输至驱动晶体管DT的第一极的第二电流；控制器21根据第二电流确定发光器件PD的老化信息，并根据老化信息修正待传输的数据电压。
此处，老化感测阶段紧邻于发光阶段之后，驱动晶体管DT不向发光器件PD输出任何信号。发光器件PD依靠发光后的残余电荷进行自身放电，由此产生的放电电流即上述第二电流，该第二电流与发光器件PD的老化程度相关。
需要说明的是，第三电压配置为关断驱动晶体管DT。其可以为低电平或高电平，具体根据驱动晶体管DT的类型确定。例如，驱动晶体管DT为P型晶体管，第三电压为高电平。又例如，驱动晶体管DT为N型晶体管，第三电压为低电平。
示例性的，请参阅图5，在老化感测阶段：第一晶体管T1响应于第一栅极扫描信号导通；第二晶体管T2响应于第二栅极扫描信号导通；第二输入电路222通过第一晶体管T1向驱动晶体管DT的控制极传输第三电压，控制驱动晶体管DT关断；感测电路223通过第二晶体管T2感测第二电流，并将其传输至控制器21；如此，控制器21便能够根据第二电流确定发光器件PD的老化信息，以修正待传输的数据电压。
由此可见，上述一些实施例提供的像素补偿电路在对驱动晶体管DT的阈值电压和特征值进行补偿的情况下，还能够对发光器件PD进行老化补偿。从 而，进一步提高像素补偿的效果，保证显示装置3的显示效果均一。
需要说明的是，由于发光器件PD的相关电压(例如OLED的阳极电压)与其发光效率没有明确且牢固的关系，相关技术中只能通过大量的测试实验获取大致的拟合关系曲线，但是该拟合关系曲线对于不同的显示基板1没有复用性。而发光器件PD的相关电流(包括发光电流或放电电流)与其发光效率之间呈线性相关，二者之间的关系更为直接、更为准确。这样，通过较少的测试实验便可确定二者的对应关系。因此，与相关技术中通过感测发光器件PD的相关电压(例如OLED的阳极电压)对其进行老化补偿的方式相比，本公开一些实施例中的像素补偿装置2通过感测发光器件PD的放电电流对其进行老化补偿，还能够通过更加简化的方式，获得更为准确的老化补偿效果。
可以理解的是，由于发光器件PD的老化过程通常比较缓慢，因此，对发光器件PD的老化感测可以每隔一定的时间间隔进行一次。具体的时间间隔可以根据实际情况选择确定。示例性的，每隔三天对发光器件PD进行一次老化检测。示例性的，特定发光驱动周期内的老化感测阶段设定为有效阶段。此时，像素补偿装置2执行老化感测及补偿功能。其他发光驱动周期内的老化感测阶段设定为无效阶段。此时，像素补偿装置2不执行老化感测及补偿功能，而是跳过该阶段执行下一对应阶段的功能。
在一些示例中，请参阅图2，控制器21与多个外部补偿电路22连接。外部补偿电路22与多个像素驱动电路101连接。示例性的，不同的外部补偿电路22中和/或同一个外部补偿电路22中不同感测电路223感测第二电流的时长相同。
也即，像素补偿装置2中的所有感测电路223感测第二电流的时长统一设置为同一固定值。如此，利于降低因感测电路223不同带来的感测偏差，提高整体感测信号，即提高感测到的第二电流的准确性，进而有效保证发光器件PD老化补偿的准确性。
需要说明的是，感测电路223的功能如上所述，其具体结构可以根据实际需要选择确定，本公开一些实施例对此不做限定。
在一些实施例中，请参阅图11，感测电路223包括电压感测子电路2232。电压感测子电路2232与驱动晶体管DT的第一极、第一输入电路221分别连接。其配置为：在数据补偿写入阶段感测阈值补偿电压，并将其传输第一输入电路221。
在一些示例中，请继续参阅图11，电压感测子电路2232还与控制器21连接。电压感测子电路还配置为：在数据补偿写入阶段感测阈值补偿电压ΔV， 并将阈值补偿电压ΔV传输至控制器21。
需要说明的是，上述电压感测子电路2232的结构可以有多种。
示例性的，请继续参阅图13，电压感测子电路2232包括第一运算放大器A1、第四开关S4以及第五开关S5。其中，第一运算放大器A1的同相输入端还通过第四开关S4与驱动晶体管DT的第一极连接。第一运算放大器A1的反相输入端还通过第五开关S5与第一运算放大器A1的输出端连接。
在一些示例中，感测电路还包括电流感测子电路2231。电流感测子电路2231与驱动晶体管DT的第一极以及控制器21分别连接。其配置为：在初始化阶段感测第一电流I 1-2，将第一电流传输I 1-2至控制器21；和/或，在老化感测阶段感测第二电流，将第二电流传输至控制器21。
需要说明的是，上述电流感测子电路2231的结构可以有多种。
在一些示例中，请参阅图13，电流感测子电路2231包括第一运算放大器A1、积分电容C1、第一开关S1、第二开关S2。其中，第一运算放大器A1的同相输入端通过第二开关S2与基准电压端Uref连接。第一运算放大器A1的反相输入端通过第一开关S1与驱动晶体管DT的第一极连接。第一运算放大器A1的反相输入端还与积分电容C1的第一极连接。第一运算放大器A1的输出端与积分电容C1的第二极、控制器21分别连接。
示例性的，请继续参阅图13，电流感测子电路2231还可以包括第三开关S3，第三开关S3与第一运算放大器A1的反相输入端、基准电流源IS分别连接。
示例性的，基准电流源IS还可以与相关电压端连接(图中未示出)，以保证其的正常工作状态。
需要说明的是，上述一些实施例中，电压感测子电路2232和电流感测子电路2231可以共用第一运算放大器A1。
容易理解的是，为了保证感测信号的准确性，感测电路223(包括电压感测子电路2232和电流感测子电路2231)需要通过定期校准，使自身具备良好的感测精密度。在本公开一些实施例的像素补偿装置2中，第一输入电路221与电压感测子电路2232连接。这样设计，第一输入电路221可以配置为向感测电路223提供电压输入信号，以辅助其实现校准。
在一些实施例中，发光驱动周期还包括第一校准阶段。第一输入电路221还配置为：在第一校准阶段将第一电压传输至电压感测子电路2232，使电压感测子电路2232输出第四电压至控制器21。控制器21还配置为：根据第四电压与第一电压的差值，修正电压感测子电路2232传输至控制器21的感测 电压信号。其中，感测电压信号包括阈值补偿电压。
相应地，请继续参阅图9或图10，本公开一些实施例中的像素补偿装置2采用的像素补偿方法还包括S500。
S500、在第一校准阶段：第一输入电路221将第一电压传输至电压感测子电路2232，以使电压感测子电路2232输出第四电压至控制器21；控制器21根据第四电压与第一电压的差值，修正电压感测子电路2232传输至控制器21的感测电压信号。
可见，上述一些实施例中的像素补偿装置2通过复用第一输入电路221，向电压感测子电路2232提供校准所需的输入信号。与相关技术中通过引入其他外部电压端，向电压感测子电路2232提供校准所需的输入信号相比，本公开一些实施例中的像素补偿装置2能够精简掉对应的外部电压端及相应的信号线，节省对应空间，从而利于显示装置3的窄边框设计。
在一些实施例中，发光驱动周期还包括第二校准阶段。电流感测子电路2231还与基准电流源IS连接。基准电流源IS配置为：在第二校准阶段将基准电流传输至电流感测子电路2231，使电流感测子电路2231输出第三电流。控制器21还配置为：根据第三电流与基准电流的差值，修正电流感测子电路2231传输至控制器21的感测电流信号。其中，感测电流信号包括第一电流和/或第二电流。
相应地，请继续参阅图9或图10，本公开一些实施例中的像素补偿方法还包括S600。
S600，在第二校准阶段：基准电流源IS将基准电流传输至电流感测子电路2231，以使电流感测子电路2231输出第三电流；控制器21根据第三电流与基准电流的差值，修正电流感测子电路2231传输至控制器21的感测电流信号。
需要说明的是，由于电压感测子电路2232和电流感测子电路2231失调(即精密度变差)的过程通常比较缓慢，因此，对电压感测子电路2232和/或电流感测子电路2231的校准可以隔一定的时间间隔进行一次。具体的时间间隔可以根据实际情况选择确定。示例性的，每隔三天对电压感测子电路2232和电流感测子电路2231进行一次校准。示例性的，特定发光驱动周期内的第一校准阶段或第二校准阶段设定为有效阶段。此时，像素补偿装置2执行对电压感测子电路2232的校准功能或对电流感测子电路2231的校准功能。其他发光驱动周期内的第一校准阶段或第二校准阶段设定为无效阶段。此时，像素补偿装置2不执行对电压感测子电路2232的校准功能或对电流感测子电 路2231的校准功能。
在一些示例中，第一校准阶段或第二校准阶段还可以设定在显示装置3的待机时间段内。此处，所述待机时间段是指显示装置3显示黑画面的时间段。如此，可以在不影响显示装置3正常显示的情况下，完成对电压感测子电路2232和电流感测子电路2231的校准，保证显示过程的稳定性。
需要说明的是，请参阅图12，在外部补偿电路22与多个子像素PX内的像素驱动电路101分别连接(例如为两个)的情况下，外部补偿电路22还包括存储电路224。存储电路224设置于感测电路223与控制器21之间，配置为：存储感测电路223输出的感测信号；以及，响应于输出控制信号将感测信号传输至控制器21。其中，感测信号至少阈值补偿电压。
在一些示例中，感测信号还可以包括第一电流、第二电流、第三电流和第四电压中的至少一种。
容易理解的是，像素补偿电路利用存储电路224的暂存数据功能，可以将控制器21的数据处理时间段与感测电路223的信号感测时间段错开设置，在需要的时候将感测信号输出至控制器21。这样，可以使控制器21有更加充足的时间进行相关数据的处理，能够在保证感测电路223感测效率的情况下，有效降低控制器21、乃至显示装置3的运行压力。
示例性的，在初始化阶段的第一个子阶段，感测电路223感测第一电流，并将其暂存于存储电路224。在初始化阶段的第二个子阶段，存储电路224响应于对应输出控制信号，将上述第一电流传输至控制器21。
示例性的，在数据补偿写入阶段的第一个子阶段，感测电路223感测阈值补偿电压，并将其暂存于存储电路224。在数据补偿写入阶段的第二个子阶段，存储电路224响应于对应输出控制信号，将上述阈值补偿电压传输控制器21。
示例性的，在老化感测阶段的第一个子阶段，感测电路223感测第二电流，并将其暂存于存储电路224。在老化感测阶段的第二个子阶段，存储电路224响应于对应输出控制信号，将上述第二电流传输控制器21。
示例性的，在第一校准阶段的第一个子阶段，电压感测子电路2232输出第四电压，并将其暂存于存储电路224。在第一校准阶段的第二个子阶段，存储电路224响应于对应输出控制信号，将上述第四电压传输控制器21。
示例性的，在第二校准阶段的第一个子阶段，电流感测子电路2231感测第三电流，并将其暂存于存储电路224。在第二校准阶段的第二个子阶段，存储电路224响应于对应输出控制信号，将上述第三电流传输控制器21。
需要说明的是，存储电路224的功能如上所述，其具体结构可以根据实际需要选择确定，本公开一些实施例对此不做限定。
在一些实施例中，请继续参阅图13，存储电路224包括存储电容C2、第八开关S8以及第九开关S9。其中，感测电路223通过第八开关S8与存储电容C2的第一极连接。控制器21通过第九开关S9与存储电容C2的第一极连接。存储电容C2的第二极接地。
需要说明的是，第一输入电路221的功能如上所述，其具体结构可以根据实际需要选择确定，本公开一些实施例对此不做限定。
在一些实施例中，请继续参阅图13，第一输入电路221包括第二运算放大器A2、第六开关S6以及第七开关S7。其中，第二运算放大器A2的同相输入端通过第六开关S6与感测电路223连接。第二运算放大器A2的同相输入端还通过第七开关S7与第一电压端U1连接。第二运算放大器A2的反相输入端与其输出端连接。第二运算放大器A2的输出端还与驱动晶体管DT的第一极连接。
需要说明的是，第二输入电路222的功能如上所述，其具体结构可以根据实际需要选择确定，本公开一些实施例对此不做限定。
在一些实施例中，请继续参阅图13，第二输入电路222包括多路复用器MUX。多路复用器MUX包括第一输入端、第二输入端以及输出端。其中，第一输入端与第二电压端U2连接，配置为接收第二电压端U2传输的第二电压。第二输入端与控制器21连接，配置为接收控制器21传输的数据电压。
输出端与驱动晶体管DT的控制极连接，配置为：在初始化阶段和预存储阶段，将第二电压传输至驱动晶体管DT的控制极；在数据补偿写入阶段，将数据电压传输至驱动晶体管DT的控制极。
在一些示例中，请继续参阅图13，在发光驱动周期还老化感测阶段时，第二输入电路222还包括第三输入端。第三输入端与第三电压端U3连接，配置为接收第三电压端U3传输的第三电压。
多路复用器MUX的输出端还配置为：在老化感测阶段，将第三电压传输至驱动晶体管的控制极。
容易理解的是，多路复用器MUX能够响应于对应的控制信号，实现不同数据的分时传输。示例性的，请参阅图13，多路复用器MUX还与第一控制信号线H1和第二控制信号线H2分别连接。该多路复用器MUX的数据传输功能由第一控制信号和第二控制信号联合控制。例如，第一控制信号和第二控制信号均为低电平时，多路复用器MUX输出第二电压。第一控制信号为低 电平，且第二控制信号为高电平时，多路复用器MUX输出数据电压。第一控制信号和第二控制信号均为高电平时，多路复用器MUX输出第三电压。
由上可见，上述一些示例中控制器21通过多路复用器MUX将数据电压传输至像素驱动电路101，即多路复用器MUX分时复用为第二输入电路222或数据电压的传输信号线。如此，能够简化像素补偿装置2的结构，节省对应信号线的占用空间，利于实现显示装置3的窄边框设计。
在一些示例中，请继续参阅图13，第二输入电路222还包括第三运算放大器A3。第三运算放大器A3的同相输入端与多路复用器MUX的输出端连接。第三运算放大器A3的输出端与驱动晶体管DT的控制极连接。第三运算放大器A3的反相输入端与其输出端连接。
容易理解的是，第三运算放大器A3在第二输入电路222中作为电压跟随器使用。如此，像素补偿装置2通过在第二输入电路222中设置该电压跟随器，能够提高第二输入电路222的信号驱动力，也即降低数据电压在传输过程中的损耗。以有效保证像素驱动电路101接收到的数据电压的准确性，乃至显示装置3的显示效果。
在一些示例中，请继续参阅图13，像素补偿装置2还可以包括模数转换器ADC和/或数模转换器DAC。模数转换器ADC设置于感测电路223与控制器21之间，配置为将外部补偿电路22输出的模拟信号(例如第一电流、第二电流、第三电流、阈值补偿电压或第四电压)转换为数字信号，并传输至控制器21。数模转换器DAC设置于控制器21与像素驱动电路101之间，配置为将控制器21输出的数字信号(例如数据电压)转换为模拟信号，并传输至像素驱动电路101。
为了更加清楚地说明本公开一些实施例中的像素补偿装置2及像素补偿方法，下面以图13所示的像素补偿装置2为例，进行详细描述。
需要说明的是，图13所示的像素驱动电路101、感测电路223、第一输入电路221、第二输入电路222以及存储电路224的内部结构在前述一些实施例中已进行了详细说明，此处不再赘述。以下仅对上述像素补偿装置2的各组成部分之间、以及其与像素驱动电路101之间的连接关系进行说明。
如图13所示，像素驱动电路101中的第二晶体管T2与感测电路223中的第一开关S1、第四开关S4分别连接。感测电路223通过第一运算放大器A1的输出端与存储电路224中的第八开关S8、第一输入电路221中的第六开关S6分别连接。存储电路224通过第九开关S9与模数转换器ADC的输入端连接。模数转换器ADC的输出端与控制器21连接。控制器21还与数模转换 器DAC的输入端连接。数模转换器DAC的输出端通过多路复用器MUX的第一输入端与第二输入电路222连接。第二输入电路222通过第三运算放大器A3的输出端与像素电路中的第一晶体管T1的第二极连接。
图13所示的像素补偿装置2对像素驱动电路101进行补偿的方法如下所述。
在初始化阶段(包括第一个子阶段和第二个子阶段)：请参阅图14和图15，第一栅极扫描信号控制第一晶体管T1导通；第二栅极扫描信号控制第二晶体管T2导通；第六开关S6断开；第七开关S7闭合；多路复用器MUX响应于第一控制信号和第二控制信号，输出第一输入端的第二电压；第二运算放大器A2将第一电压通过第二晶体管T2传输至驱动晶体管DT的第一极；多路复用器MUX将第二电压通过第三运算放大器A3、第一晶体管T1传输至驱动晶体管DT的控制极；驱动晶体管DT输出第一电流。
在此基础上，在初始化阶段的第一个子阶段：请参阅图14，第一开关S1、第二开关S2和第八开关S8闭合；第三开关S3、第四开关S4、第五开关S5和第九开关S9断开；第一电流通过第二晶体管T2、第一开关S1传输至第一运算放大器A1的反相输入端；基准电压通过第二开关S2传输至第一运算放大器A1的同相输入端；由积分电容C1和第三运算放大器A3组成的积分器，根据第一电流和基准电压，输出第一信号；第一信号包括电压信号和/或第一电流信号；第一信号通过第八开关S8，传输至存储电容C2的第一极；存储电容C2充电，存储第一信号。
在初始化阶段的第二个子阶段：请参阅图15，第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5和第八开关S8断开；第九开关S9闭合；存储电容C2放电，将第一信号通过第九开关S9、模数转换器ADC传输至控制器21。
在预存储阶段：请参阅图16，第一栅极扫描信号控制第一晶体管T1导通；第二栅极扫描信号控制第二晶体管T2导通；第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6、第七开关S7、第八开关S8和第九开关S9均断开；多路复用器MUX响应于第一控制信号和第二控制信号，输出第一输入端的第二电压；第二电压通过第三运算放大器A3、第一晶体管T1继续传输至驱动晶体管DT的控制极；第二运算放大器A2的输入端空置；驱动晶体管DT的第一极电压由第一电压补偿至阈值补偿电压；该阈值补偿电压写入第一电容C0的第二极。
在数据补偿写入阶段(包括第一个子阶段和第二个子阶段)：请参阅图 17和图18，第一栅极扫描信号控制第一晶体管T1导通；第二栅极扫描信号控制第二晶体管T2导通；第一开关S1、第二开关S2、第三开关S3和第七开关S7断开；第四开关S4、第五开关S5和第六开关S6闭合；多路复用器MUX响应于第一控制信号和第二控制信号，输出第一输入端的数据电压。
控制器21将数据电压通过数模转换器DAC传输至多路复用器MUX的第一输入端；多路复用器MUX将数据电压通过第三运算放大器A3、第一晶体管T1传输至驱动晶体管DT的控制极；阈值补偿电压通过第二晶体管T2、第四开关S4传输至第一运算放大器A1的同相输入端，继而通过由第一运算放大器A1和第五开关S5组成的电压跟随器的输出端输出；之后，通过第六开关S6、第二运算放大器A2、第二晶体管T2馈回至驱动晶体管DT的第一极。
在此基础上，在数据补偿写入阶段的第一个子阶段：请参阅图17，第八开关S8闭合；第九开关S9断开；由第一运算放大器A1和第五开关S5组成的电压跟随器的输出端输出的阈值补偿电压，还通过第八开关S8传输至存储电容C2的第一极；存储电容C2充电，存储阈值补偿电压。
在数据补偿写入阶段的第二个子阶段：请参阅图18，第八开关S8断开；第九开关S9闭合；存储电容C2放电，将阈值补偿电压通过第九开关S9、模数转换器ADC传输至控制器21；控制器21根据第一信号和阈值补偿电压，确定驱动晶体管DT的实际特征值。
在老化感测阶段(包括第一个子阶段和第二个子阶段)：请参阅图19和图20，第一栅极扫描信号控制第一晶体管T1导通；第二栅极扫描信号控制第二晶体管T2导通；多路复用器MUX响应于第一控制信号和第二控制信号，输出第三输入端的第三电压，控制驱动晶体管DT关断；第三开关S3、第四开关S4、第五开关S5、第六开关S6和第七开关S7断开；多路复用器MUX将第三电压通过第三运算放大器A3、第一晶体管T1传输至驱动晶体管DT的控制极，控制驱动晶体管DT关断；发光器件PD放电输出第二电流。
需要说明的是，在老化感测阶段的第一个子阶段：请参阅图19，第一开关S1、第二开关S2和第八开关S8闭合；第九开关S9断开；第二电流通过第二晶体管T2、第一开关S1传输至第一运算放大器A1的反相输入端；基准电压通过第二开关S2传输至第一运算放大器A1的同相输入端；由积分电容C1和第一运算放大器A1组成的积分器，根据第二电流和基准电压，输出第二信号；第二信号包括电压信号和/或第二电流信号；第二信号通过第八开关S8，传输至存储电容C2的第一极；存储电容C2充电，存储第二信号。
在老化感测阶段的第二个子阶段：请参阅图20，第一开关S1、第二开关S2和第八开关S8断开；第九开关S9闭合；存储在存储电容C2的第二信号，通过第九开关S9、模数转换器ADC传输至控制器21；控制器21根据第二信号，确定发光器件PD的老化信息。
在第一校准阶段的第一个子阶段：请参阅图21，第一栅极扫描信号控制第一晶体管T1关断；第二栅极扫描信号控制第二晶体管T2关断；第四开关S4、第五开关S5、第七开关S7和第八开关S8闭合；第一开关S1、第二开关S2、第三开关S3、第六开关S6和第九开关S9断开；第一电压通过第二运算放大器A2、第四开关S4传输至第一运算放大器A1的同相输入端；由第一运算放大器A1与第五开关S5组成的电压跟随器输出第四电压；第四电压通过第八开关S8传输至存储电容C2的第一极；存储电容C2充电，存储第四电压。
在第一校准阶段的第二个子阶段：请参阅图22，第一栅极扫描信号控制第一晶体管T1关断；第二栅极扫描信号控制第二晶体管T2关断；第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6、第七开关S7和第八开关S8断开；第九开关S9闭合；存储电容C2放电，将第四电压通过第九开关S9、模数转换器ADC传输至控制器21；控制器21根据第四电压和第一电压的差值，修正电压感测子电路2232传输至控制器21的感测电压信号。
在第二校准阶段的第一个子阶段：请参阅图23，第一栅极扫描信号控制第一晶体管T1关断；第二栅极扫描信号控制第二晶体管T2关断；第二开关S2、第三开关S3和第八开关S8闭合；第一开关S1、第四开关S4、第五开关S5、第六开关S6、第七开关S7和第九开关S9断开。基准电压通过第二开关S2传输至第一运算放大器A1的同相输入端；基准电流通过第三开关S3传输至第一运算放大器A1的反相输入端，由第一运算放大器A1和积分电容C1组成的积分器输出第三信号；第三信号包括电压信号和/或第三电流信号；第三信号通过第八开关S8传输至存储电容C2的第一极；存储电容C2充电，存储第三信号。
在第二校准阶段的第二个子阶段：请参阅图24，第一栅极扫描信号控制第一晶体管T1关断；第二栅极扫描信号控制第二晶体管T2关断；第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6、第七开关S7和第八开关S8断开；第九开关S9闭合；存储电容C2放电，将第三电流信号通过第九开关S9、模数转换器ADC传输至控制器21；控制器21根据第三电流与基准电流的差值，修正电流感测子电路2231传输至控制器 21的感测电流信号。
由上可见，在图13所示的像素补偿装置2中，利用第一运算放大器A1与积分电容C1组成积分器，进行电流信号(包括第一电流信号和第二电流信号)的感测及输出；通过将第一运算放大器A1的反相输入端与其输出端连接，使其作为电压跟随器，进行电压信号(包括阈值补偿电压)的感测和输出。也即，本公开一些实施例中的像素补偿装置2通过复用第一运算放大器A1，完成电压感测和电流感测两项功能。如此，可以简化像素补偿装置2的电路结构，节省对应电子器件的占用空间，从而利用实现显示装置3的窄边框设计。
在一些实施例中，在对感测电路223进行校准前，还可以利用第一电压端U1对模数转换器ADC进行校准。示例性的，请参阅图25，在模数转换器ADC校准阶段：第一栅极扫描信号控制第一晶体管T1关断；第二栅极扫描信号控制第二晶体管T2关断；第一开关S1、第二开关S2、第三开关S3和第六开关S6断开；第四开关S4、第五开关S5、第七开关S7、第八开关S8和第九开关S9闭合；第一电压通过第二运算放大器A2、第四开关S4传输至第一运算放大器A1的同相输入端；由第一运算放大器A1与第五开关S5组成的电压跟随器输出第一电压；第一电压通过第八开关S8和第九开关S9传输至模数转换器ADC；模数转换器ADC输出第五电压至控制器21。这样，控制器21便能够根据第五电压与第一电压的差值，修正感测电路223传输至控制器21的感测信号(包括感测电流信号和感测电压信号)，以进一步保证感测信号的准确性，使像素补偿装置2对子像素PX的补偿更为精准。
需要说明的是，本公开一些实施例中的第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6、第七开关S7、第八开关S8或第九开关S9可以为任何能够通过控制信号实现打开和闭合的电子器件。示例性的，第一开关S1、第二开关S2、第三开关S3、第四开关S4、第五开关S5、第六开关S6、第七开关S7、第八开关S8或第九开关S9为开关型晶体管。该开关型晶体管包括P型晶体管或N型晶体管，通过其控制极上施加的对应控制信号控制其导通或关断。示例性的，所述控制信号由控制器21(例如TCON)提供。
本公开一些实施例中的显示装置3或像素补偿方法所能达到的有益效果与上述一些实施例中的像素补偿装置2所能达到的有益效果相同，此处不再赘述。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何 的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种像素补偿装置，包括：
    控制器；以及，
    与所述控制器连接的外部补偿电路，所述外部补偿电路位于像素外且与至少一个像素驱动电路连接；
    所述像素驱动电路包括驱动子电路；所述像素驱动电路的一个发光驱动周期包括初始化阶段、预存储阶段以及数据补偿写入阶段；
    所述外部补偿电路包括第一输入电路、第二输入电路和感测电路；
    所述第一输入电路与所述驱动子电路的第一端、所述感测电路分别连接，配置为：在所述初始化阶段向所述驱动子电路的第一端传输第一电压，在所述预存储阶段空置；以及，在数据补偿写入阶段向所述驱动子电路的第一端传输阈值补偿电压；
    所述第二输入电路与所述驱动子电路的控制端连接，配置为：在所述初始化阶段和所述预存储阶段向所述驱动子电路的控制端传输第二电压，以使所述驱动子电路的第一端的电压在所述预存储阶段由所述第一电压补偿至所述阈值补偿电压；
    其中，所述驱动子电路的第一端与发光器件连接，所述第一电压和所述阈值补偿电压均小于所述发光器件的开启电压；所述阈值补偿电压等于所述第二电压与所述驱动子电路的阈值电压之差；
    所述感测电路还与所述驱动子电路的第一端连接，配置为：在所述数据补偿写入阶段感测所述阈值补偿电压，并将所述阈值补偿电压传输至所述第一输入电路；
    所述控制器还与所述驱动子电路的控制端连接，配置为：在所述数据补偿写入阶段向所述驱动子电路的控制端传输数据电压。
  2. 根据权利要求1所述的像素补偿装置，其中，
    所述数据电压为所述控制器根据上一个所述发光驱动周期确定的所述驱动子电路的实际特征值修正后的电压。
  3. 根据权利要求1或2所述的像素补偿装置，其中，
    所述感测电路还与所述控制器连接，所述感测电路还配置为：在所述初始化阶段感测所述驱动子电路的第一端传输的第一电流，并将所述第一电流传输至所述控制器；以及，在所述数据补偿写入阶段将感测到的所述阈值补偿电压传输至所述控制器；
    所述控制器还配置为：根据所述第一电流和所述阈值补偿电压确定所述 驱动子电路的实际特征值，并根据所述实际特征值修正下一个所述数据补偿写入阶段中待传输的数据电压。
  4. 根据权利要求1～3中任一项所述的像素补偿装置，其中，
    所述发光驱动周期还包括老化感测阶段；
    所述第二输入电路还配置为：在所述老化感测阶段向所述驱动子电路的控制端传输第三电压，控制所述驱动子电路关断；
    所述感测电路还配置为：在所述老化感测阶段感测所述发光器件传输至所述驱动子电路的第一端的第二电流；
    所述控制器还配置为：根据所述第二电流确定所述发光器件的老化信息，并根据所述老化信息修正下一个所述数据补偿写入阶段待传输的数据电压。
  5. 根据权利要求4所述的像素补偿装置，其中，
    所述感测电路包括电压感测子电路，所述电压感测子电路与所述驱动子电路的第一端以及所述第一输入电路分别连接；
    所述电压感测子电路配置为：在所述数据补偿写入阶段感测所述阈值补偿电压，并将所述阈值补偿电压传输至所述第一输入电路。
  6. 根据权利要求5所述的像素补偿装置，其中，
    所述电压感测子电路还与所述控制器连接；
    所述电压感测子电路还配置为：在所述数据补偿写入阶段将感测到的所述阈值补偿电压传输至所述控制器。
  7. 根据权利要求5或6所述的像素补偿装置，其中，
    所述发光驱动周期还包括第一校准阶段；
    所述第一输入电路还配置为：在所述第一校准阶段将所述第一电压传输至所述电压感测子电路，以使所述电压感测子电路输出第四电压至所述控制器；
    所述控制器还配置为：根据所述第四电压与所述第一电压的差值，修正所述电压感测子电路传输至所述控制器的感测电压信号；所述感测电压信号包括所述阈值补偿电压。
  8. 根据权利要求5～7中任一项所述的像素补偿装置，其中，
    所述电压感测子电路包括所述第一运算放大器、第四开关以及第五开关；
    所述第一运算放大器的同相输入端还通过所述第四开关与所述驱动子电路的第一端连接；
    所述第一运算放大器的反相输入端还通过所述第五开关与所述第一运算放大器的输出端连接。
  9. 根据权利要求4～8中任一项所述的像素补偿装置，其中，
    所述感测电路包括电流感测子电路，所述电流感测子电路与所述驱动子电路的第一端以及所述控制器分别连接；
    所述电流感测子电路配置为：在所述初始化阶段感测第一电流，将所述第一电流传输至所述控制器；和/或，在所述老化感测阶段感测所述第二电流，将所述第二电流传输至所述控制器。
  10. 根据权利要求9所述的像素补偿装置，其中，
    所述发光驱动周期还包括第二校准阶段；
    所述电流感测子电路还与基准电流源连接；
    所述基准电流源配置为：在所述第二校准阶段将基准电流传输至所述电流感测子电路，以使所述电流感测子电路输出第三电流；
    所述控制器还配置为：根据所述第三电流与所述基准电流的差值，修正所述电流感测子电路传输至所述控制器的感测电流信号；所述感测电流信号包括所述第一电流和/或所述第二电流。
  11. 根据权利要求9或10所述的像素补偿装置，其中，
    所述电流感测子电路包括第一运算放大器、积分电容、第一开关以及第二开关；其中，
    所述第一运算放大器的同相输入端通过所述第二开关与基准电压端连接；
    所述第一运算放大器的反相输入端通过所述第一开关与所述驱动子电路的第一端连接；所述第一运算放大器的反相输入端还与所述积分电容的第一极连接；
    所述第一运算放大器的输出端与所述积分电容的第二极、所述控制器分别连接。
  12. 根据权利要求1～11中任一项所述的像素补偿装置，其中，
    所述第二输入电路包括多路复用器；所述多路复用器包括第一输入端、第二输入端以及输出端；
    所述第一输入端与第二电压端连接，配置为：接收所述第二电压端传输的所述第二电压；
    所述第二输入端与控制器连接，配置为：接收所述控制器传输的所述数据电压；
    所述多路复用器的输出端与所述驱动子电路的控制端连接，配置为：在所述初始化阶段和所述预存储阶段，将所述第二电压传输至所述驱动子电路 的控制端；在所述数据补偿写入阶段，将所述数据电压传输至所述驱动子电路的控制端。
  13. 根据权利要求12所述的像素补偿装置，其中，
    在所述发光驱动周期还包括老化感测阶段时，所述第二输入电路还包括第三输入端；
    所述第三输入端与第三电压端连接，配置为：接收所述第三电压端传输的第三电压；
    所述多路复用器的输出端还配置为：在所述老化感测阶段，将所述第三电压传输至所述驱动子电路的控制端。
  14. 根据权利要求12或13所述的像素补偿装置，其中，
    所述第二输入电路还包括第三运算放大器；
    所述第三运算放大器的同相输入端与所述多路复用器的输出端连接；
    所述第三运算放大器的输出端与所述驱动子电路的控制端连接；
    所述第三运算放大器的反相输入端与所述第三运算放大器的输出端连接。
  15. 根据权利要求1～14中任一项所述的像素补偿装置，其中，
    所述第一输入电路包括第二运算放大器、第六开关以及第七开关；
    所述第二运算放大器的同相输入端通过所述第六开关与所述感测电路连接；所述第二运算放大器的同相输入端还通过所述第七开关与第一电压端连接；
    所述第二运算放大器的反相输入端与所述第二运算放大器的输出端连接；
    所述第二运算放大器的输出端还与所述驱动子电路的第一端连接。
  16. 根据权利要求1～15中任一项所述的像素补偿装置，其中，
    所述外部补偿电路还包括存储电路，所述存储电路设置于所述感测电路与所述控制器之间；
    所述存储电路配置为：存储所述感测电路输出的感测信号；以及，响应于输出控制信号将所述感测信号传输至所述控制器；
    其中，所述感测信号至少包括所述阈值补偿电压。
  17. 根据权利要求16所述的像素补偿装置，其中，
    所述存储电路包括存储电容、第八开关以及第九开关；
    所述感测电路通过所述第八开关与所述存储电容的第一极连接；所述控制器通过所述第九开关与所述存储电容的第一极连接；所述存储电容的第二 极接地。
  18. 根据权利要求1～17中任一项所述的像素补偿装置，其中，
    所述驱动子电路包括驱动晶体管；
    其中，所述驱动晶体管的第一极为所述驱动子电路的第一端；所述驱动晶体管的控制极为所述驱动子电路的控制端。
  19. 一种像素补偿方法，应用于如权利要求1～18中任一项所述的像素补偿装置，其中，所述像素补偿方法包括多个发光驱动周期，一个所述发光驱动周期包括初始化阶段、预存储阶段以及数据补偿写入阶段；
    在所述初始化阶段：所述第一输入电路将所述第一电压传输至所述驱动子电路的第一端；所述第二输入电路将所述第二电压传输至所述晶体管的控制端，所述驱动子电路导通；
    在所述预存储阶段：所述第一输入电路空置；所述第二输入电路将所述驱动子电路的控制端电压维持在所述第二电压，以使所述驱动子电路的第一端电压由所述第一电压补偿至所述阈值补偿电压；
    在所述数据补偿写入阶段：所述控制器向所述驱动子电路的控制端传输所述数据电压；所述感测电路感测所述阈值补偿电压，并将其传输至所述第一输入电路；所述第一输入电路将所述阈值补偿电压馈回至所述驱动子电路的第一端。
  20. 根据权利要求19所述的像素补偿方法，其中，
    所述数据电压为所述控制器根据上一个所述发光驱动周期确定的所述驱动子电路的实际特征值修正后的电压。
  21. 根据权利要求19或20所述的像素补偿方法，其中，
    在所述初始化阶段：所述驱动子电路导通，输出第一电流；所述感测电路感测所述第一电流，并将其传输至所述控制器；
    在所述数据补偿写入阶段：所述感测电路将感测到的所述阈值补偿电压传输至所述控制器；所述控制器根据所述第一电流和所述阈值补偿电压确定所述驱动子电路的实际特征值，并根据所述实际特征值修正下一个所述数据补偿写入阶段中待传输的数据电压。
  22. 根据权利要求19～21中任一项所述的像素补偿方法，其中，所述发光驱动周期还包括老化感测阶段；
    所述像素补偿方法还包括：
    在所述老化感测阶段：所述第二输入电路向所述驱动子电路的控制端传输第三电压，控制所述驱动子电路关断；所述感测电路感测所述发光器件传 输至所述驱动子电路的第一端的第二电流；所述控制器根据所述第二电流确定所述发光器件的老化信息，并根据所述老化信息修正待传输的所述数据电压。
  23. 根据权利要求22所述的像素补偿方法，其中，
    所述控制器与多个所述外部补偿电路连接；所述外部补偿电路与多个所述像素驱动电路连接；
    不同的所述外部补偿电路中和/或同一个所述外部补偿电路中不同所述感测电路感测第一电流的时长相同；和/或，不同的所述外部补偿电路中和/或同一个所述外部补偿电路中不同所述感测电路感测所述第二电流的时长相同。
  24. 根据权利要求19～23中任一项所述的像素补偿方法，其中，
    所述感测电路包括所述电压感测子电路；
    所述发光驱动周期还包括第一校准阶段；
    所述像素补偿方法还包括：
    在所述第一校准阶段：所述第一输入电路将所述第一电压传输至所述电压感测子电路，以使所述电压感测子电路输出第四电压至所述控制器；所述控制器根据所述第四电压与所述第一电压的差值，修正所述电压感测子电路传输至所述控制器的感测电压信号。
  25. 根据权利要求19～24中任一项所述的像素补偿方法，其中，
    所述感测电路包括所述电流感测子电路；
    所述发光驱动周期还包括第二校准阶段；
    所述像素补偿方法还包括：
    在所述第二校准阶段：基准电流源将基准电流传输至所述电流感测子电路，以使所述电流感测子电路输出第三电流；所述控制器根据所述第三电流与所述基准电流的差值，修正所述电流感测子电路传输至所述控制器的感测电流信号。
  26. 一种显示装置，包括如权利要求1～18中任一项所述的像素补偿装置。
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