WO2021243751A1 - 一种静电防护线路、静电防护线路制程方法及显示面板 - Google Patents

一种静电防护线路、静电防护线路制程方法及显示面板 Download PDF

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Publication number
WO2021243751A1
WO2021243751A1 PCT/CN2020/096555 CN2020096555W WO2021243751A1 WO 2021243751 A1 WO2021243751 A1 WO 2021243751A1 CN 2020096555 W CN2020096555 W CN 2020096555W WO 2021243751 A1 WO2021243751 A1 WO 2021243751A1
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Prior art keywords
connection line
gate connection
gate
protection circuit
drain
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PCT/CN2020/096555
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English (en)
French (fr)
Inventor
徐丽
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武汉华星光电技术有限公司
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Priority to US17/254,910 priority Critical patent/US11876091B2/en
Publication of WO2021243751A1 publication Critical patent/WO2021243751A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements

Definitions

  • This application relates to the field of display technology, and in particular to an electrostatic protection circuit, a manufacturing process method of an electrostatic protection circuit, and a display panel.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the current small and medium-sized products are mostly active matrix liquid crystal displays (gate Driver on array (GOA) lines are evenly distributed on both sides of the display panel, limited by the size of the space, and the gate signal line is not protected against special electrostatic discharge (Electro-Static discharge, ESD) and is in a suspended state.
  • GAA gate Driver on array
  • ESD Electro-Static discharge
  • the active area (AA) (including the end of the gate signal line) has not been specially protected against ESD, and the pixels on the edge of the AA area are vulnerable to ESD damage to form a display. Bright spot on the edge of the panel.
  • the embodiments of the present application provide an electrostatic protection circuit, an electrostatic protection circuit manufacturing method, and a display panel, which can reduce edge bright spots caused by weak electrostatic discharge.
  • This application provides an electrostatic protection circuit, including:
  • a gate signal line, the gate signal line includes a first end and a second end;
  • a driving circuit the driving circuit is connected to the first end;
  • a gate connection line, the gate connection line is connected to the second end, and the gate connection line is at least partially bent;
  • the source drain is connected to an end of the gate connection line away from the second end, and partially covers an end of the gate connection line away from the second end.
  • an interlayer insulating layer is provided between the gate connection line and the source and drain, at least one through hole is provided on the interlayer insulating layer, and the gate connection line passes through the The through hole is connected to the source and drain.
  • the shape of the through hole is cylindrical, square column or truncated cone.
  • the width of the gate connection line is smaller than the width of the gate signal line.
  • the space after the gate connection line is bent is the space of one main pixel.
  • all the gate connection lines are bent.
  • the gate connection line is bent into a zigzag shape, a serpentine shape, a pulse shape, a concave-convex shape, a wave shape, or a zigzag shape.
  • This application provides a method for manufacturing an electrostatic protection circuit, including:
  • the gate signal line including a first end and a second end;
  • the source and drain are connected to an end of the gate connection line away from the second end.
  • the connecting the source and the drain at the end of the gate connection line away from the second end includes:
  • An interlayer insulating layer is provided on an end of the gate connection line away from the second end, and the interlayer insulating layer partially covers an end of the gate connection line away from the second end;
  • a source and drain are provided on the through hole and the interlayer insulating layer; wherein the gate connection line is connected to the source and drain through the through hole.
  • An embodiment of the present application provides a display panel including at least two of the static electricity protection circuits described above, and the static electricity protection circuit includes:
  • a gate signal line, the gate signal line includes a first end and a second end;
  • a driving circuit the driving circuit is connected to the first end;
  • a gate connection line, the gate connection line is connected to the second end, and the gate connection line is at least partially bent;
  • the source drain is connected to an end of the gate connection line away from the second end, and partially covers an end of the gate connection line away from the second end.
  • an interlayer insulating layer is provided between the gate connection line and the source and drain electrodes.
  • At least one through hole is provided on the interlayer insulating layer, and the gate connection line is connected to the source and drain through the through hole.
  • the shape of the through hole is cylindrical, square column or truncated cone.
  • the width of the gate connection line is smaller than the width of the gate signal line.
  • the space after the gate connection line is bent is the space of one main pixel.
  • all the gate connection lines are bent.
  • the gate connection line is bent into a zigzag shape, a serpentine shape, a pulse shape, a concave-convex shape, a wave shape, or a zigzag shape.
  • the electrostatic protection circuit is formed by an electrostatic protection circuit manufacturing method, and the electrostatic protection circuit manufacturing method includes:
  • the gate signal line including a first end and a second end;
  • the source and drain are connected to an end of the gate connection line away from the second end.
  • the connecting the source and the drain at the end of the gate connection line away from the second end includes:
  • An interlayer insulating layer is provided on an end of the gate connection line away from the second end, and the interlayer insulating layer partially covers an end of the gate connection line away from the second end;
  • a source and drain are provided on the through hole and the interlayer insulating layer; wherein the gate connection line is connected to the source and drain through the through hole.
  • the electrostatic protection circuit includes: a gate signal line, a driving circuit, a gate connection line, and a source and drain.
  • the gate signal line includes a first end and a second end, the driving circuit is connected to the first end, the gate connection line is connected to the second end, and the gate connection line is at least partially bent,
  • the source and drain are connected to an end of the gate connection line away from the second end, and partially cover an end of the gate connection line away from the second end.
  • FIG. 1 is a schematic diagram of a structure of an electrostatic protection circuit provided by an embodiment of the application.
  • FIG. 2 is a partial cross-sectional view of the connection between the gate connection line and the source and drain provided in an embodiment of the application.
  • FIG. 3 is a schematic flow chart of a method for manufacturing an electrostatic protection circuit according to an embodiment of the application.
  • FIG. 4 is a schematic diagram of a structure of a display panel provided by an embodiment of the application.
  • the embodiments of the present application provide an electrostatic protection circuit, an electrostatic protection circuit manufacturing method, and a display panel.
  • the electrostatic protection circuit will be described in detail below.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit 10 provided by an embodiment of the present application.
  • the electrostatic protection circuit 10 includes a gate signal line 101, a driving circuit 102, a gate connection line 103 and a source and drain 104.
  • the gate signal line 101 includes a first terminal 101a and a second terminal 101b, the driving circuit 102 is connected to the first terminal 101a, the gate connection line 103 is connected to the second terminal 101b, the gate connection line 103 is at least partially bent, and the source and drain 104 The end of the gate connection line 103 away from the second end 101b and partly covers the end of the gate connection line 103 away from the second end.
  • the electrostatic discharge through the bent gate connection line 103 can lose a part of the current, reduce its influence, and avoid bright spots on the edge of the panel caused by weak electrostatic discharge. .
  • the drive circuit 102 (gate driver on Array (GOA) is a circuit in which gate driver ICs (gate driver ICs) are arranged on the array substrate to replace the external driver chip.
  • GOA gate driver on Array
  • the application of GOA can reduce the production process, reduce the production cost of the product, improve the high integration of the display panel, and make the display panel thinner.
  • FIG. 2 is a partial cross-sectional view of the connection between the gate connection line and the source and drain provided in an embodiment of the present application.
  • An interlayer insulating layer 105 is provided between the gate connection line 103 and the source and drain 104, at least one through hole 106 is provided on the interlayer insulating layer 105, and the gate connection line 103 is connected to the source and drain 104 through the through hole 106.
  • the electrostatic discharge can be further protected. If the electrostatic discharge still exists after passing through the gate connection line 103, the through hole 106 will be blown up and the pixels in the effective display area will not be affected.
  • the through hole 106 shown in FIG. 2 uses a truncated cone shape as an example, but it is not a limitation on the shape of the through hole 106.
  • the shape of the through hole 106 is cylindrical, square column or truncated cone shape. Setting the through hole 106 into a cylindrical shape can uniformly distribute the stress received by the through hole 106, prevent deformation or cracking of the through hole 106 caused by uneven force, and ensure the connection between the gate connection line 103 and the source and drain 104. Setting the through hole 106 in a square column shape enables the source and drain electrodes 104 to be arranged in the through hole 106 to fit more closely and not easily fall off.
  • the through hole 106 in the shape of a truncated cone facilitates the arrangement of the source and drain 104, and enables the source and drain 104 to be arranged more flatly, and it is not easy to cause poor performance due to excessive bending. It is to ensure that the gate connection line 103 and the source and drain 104 At the same time of contact, the source and drain 104 can also obtain better working performance.
  • the width of the gate connection line 103 is smaller than the width of the gate signal line 101.
  • the gate connection line 103 is provided to reduce the defects caused by electrostatic discharge. The longer the length of the gate connection line 103, the better the attenuation effect on the electrostatic discharge. Therefore, the width of the gate connection line 103 is smaller than the width of the gate signal line 101, and the length of the gate connection line 103 can be set longer in a limited space, so as to better perform electrostatic protection.
  • the space after the gate connecting line 103 is bent is the space of one main pixel.
  • the grid connection line 103 is designed to be bent, so that the grid connection line 103 can better adapt to the product, and produce a better electrostatic protection effect for different products.
  • the gate connection lines 103 are all bent. Specifically, all the gate connection lines 103 are wound up. If the gate connecting wires 103 are all bent, the length of the gate connecting wires 103 can be set longer in a limited space, and the gate connecting wires 103 that need to pass after the electrostatic discharge is also longer, which can be more effectively weakened. The effect of electrostatic discharge on the circuit.
  • the gate connection line 103 is bent into a zigzag, serpentine, pulse shape, concave-convex shape, wave shape, or zigzag shape. These bending forms can bend a longer grid connection line 103 in a smaller space, so that the route of the electrostatic discharge path is longer, and the effect of reducing the electrostatic discharge is better.
  • the electrostatic protection circuit 10 includes a gate signal line 101, a driving circuit 102, a gate connection line 103, and a source and drain 104.
  • a gate signal line 101 By arranging an at least partially bent gate connection line 103 at one end of the gate signal line 101, electrostatic discharge (Electro-Static When discharge, ESD) passes, a part of the current is lost and its influence is weakened.
  • an interlayer insulating layer 105 is provided between the end of the gate connection line 103 away from the gate signal line 101 and the source and drain 103, and at least one through hole 106 is provided on the interlayer insulating layer 105.
  • the ESD passes through the gate After the wire 103 is connected, if the ESD still exists, the through hole 106 will be blown up, and the pixels in the effective display area will not be affected, and the bright spots at the edge of the panel caused by weak ESD can be avoided.
  • FIG. 3 is a schematic flowchart of a manufacturing method of an electrostatic protection circuit in an embodiment of the present application.
  • a gate signal line is provided.
  • the gate signal line includes a first end and a second end.
  • an interlayer insulating layer is provided at an end of the gate connection line away from the second end, and the interlayer insulating layer partially covers an end of the gate connection line away from the second end.
  • At least one through hole is provided on the interlayer insulating layer.
  • the source and drain electrodes are arranged on the through hole and the interlayer insulating layer.
  • the gate connection line is connected to the source and drain through the through hole.
  • the method for manufacturing an electrostatic protection circuit produces an electrostatic protection circuit, which includes a gate signal line, a driving circuit, a gate connection line, and a source and drain.
  • an at least partially bent gate connection line at one end of the gate signal line, a part of the current can be lost when the ESD passes through, and its influence can be reduced.
  • an interlayer insulating layer is provided between the end of the gate connection line away from the gate signal line and the source and drain, and at least one through hole is provided on the interlayer insulating layer. If the ESD passes through the gate connection line, the ESD remains Existing, it will blow up the through holes, will not affect the effective display area pixels, and can avoid the bright spots at the edge of the panel caused by weak ESD.
  • FIG. 4 is a schematic structural diagram of the display panel 100 provided by the embodiment of the present application.
  • the display panel 100 includes at least two of the above-mentioned static electricity protection circuit 10 and the signal line 20, and the static electricity protection circuit 10 is connected by the signal line 20.
  • the display panel 100 may also include other devices.
  • the source-drain signal lines 20 and other devices and their assembly in the embodiments of the present application are related technologies well known to those skilled in the art, and will not be repeated here.
  • the display panel 100 provided by the embodiment of the present application includes at least two of the above-mentioned electrostatic protection circuit 10 and signal line 20.
  • the electrostatic protection circuit 10 includes a gate signal line 101, a driving circuit 102, a gate connection line 103, and source and drain. ⁇ 104.
  • a part of the current can be lost when the ESD passes through, and its influence can be reduced.
  • an interlayer insulating layer 105 is provided between the end of the gate connecting line 103 away from the gate signal line 101 and the source and drain 103, and at least one through hole 106 is provided on the interlayer insulating layer 105.
  • the ESD passes through the gate After the wire 103 is connected, if the ESD still exists, the through hole 106 will be blown up, and the pixels in the effective display area will not be affected, and the bright spots at the edge of the panel caused by weak ESD can be avoided.

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Abstract

本申请实施例提供一种静电防护线路，该静电防护线路包括：栅极信号线、驱动电路、栅极连接线以及源漏极。通过在栅极信号线的一端设置弯折的栅极连接线，静电释放通过弯折的栅极连接线，可以损耗掉一部分电流，减弱其影响，避免弱静电释放造成的面板边缘亮点。

Description

一种静电防护线路、静电防护线路制程方法及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种静电防护线路、静电防护线路制程方法及显示面板。
 背景技术
薄膜晶体管液晶显示器（Thin Film Transistor -Liquid Crystal Display, TFT-LCD）产品目前工艺成熟，良率稳定，依然是很多手机、平板、车载显示屏幕的首选。目前的中小尺寸产品多是主动式矩阵液晶显示器（gate driver on array, GOA）线路均匀分布在显示面板两侧，受限于空间的大小，而栅极（Gate）信号线未作特殊的静电释放（Electro-Static discharge, ESD）防护，处于悬空状态。在TFT的制程中，ESD风险是一直存在的，有效显示区（Active Area, AA）（包括Gate信号线末端）并未做特殊的ESD防护，AA区边缘的像素易受到ESD炸伤而形成显示面板边缘的亮点。
 技术问题
本申请实施例提供一种静电防护线路、静电防护线路制程方法及显示面板，能够减少弱静电释放导致的边缘亮点。
 技术解决方案
本申请提供一种静电防护线路，包括：
栅极信号线，所述栅极信号线包括第一端与第二端；
驱动电路，所述驱动电路连接所述第一端；
栅极连接线，所述栅极连接线连接所述第二端，所述栅极连接线至少部分弯折；
源漏极，所述源漏极连接所述栅极连接线远离所述第二端的一端，且部分覆盖所述栅极连接线远离所述第二端的一端。
在一些实施例中，所述栅极连接线与所述源漏极之间设置有层间绝缘层，所述层间绝缘层上设置有至少一个通孔，所述栅极连接线通过所述通孔与所述源漏极连接。
在一些实施例中，所述通孔的形状为圆柱形、方柱形或圆台形。
在一些实施例中，所述栅极连接线的宽度小于所述栅极信号线的宽度。
在一些实施例中，所述栅极连接线弯折后的空间大小为一个主像素的空间大小。
在一些实施例中，所述栅极连接线全部弯折。
在一些实施例中，所述栅极连接线弯折为之字形、蛇形、脉冲形、凹凸折线形、波浪形或锯齿形。
本申请提供一种静电防护线路制程方法，包括：
提供一栅极信号线，所述栅极信号线包括第一端与第二端；
在所述第一端连接驱动电路；
在所述第二端连接栅极连接线，所述栅极连接线至少部分弯折；
在所述栅极连接线远离所述第二端的一端连接源漏极。
在一些实施例中，所述在所述栅极连接线远离所述第二端的一端连接源漏极包括：
在所述栅极连接线远离所述第二端的一端设置层间绝缘层，且所述层间绝缘层部分覆盖所述栅极连接线远离所述第二端的一端；
在层间绝缘层上设置至少一个通孔；
在所述通孔和所述层间绝缘层上设置源漏极；其中，所述栅极连接线通过所述通孔与所述源漏极连接。
本申请实施例提供一种显示面板，包括至少两个以上所述的静电防护线路，所述静电防护电路包括：
栅极信号线，所述栅极信号线包括第一端与第二端；
驱动电路，所述驱动电路连接所述第一端；
栅极连接线，所述栅极连接线连接所述第二端，所述栅极连接线至少部分弯折；
源漏极，所述源漏极连接所述栅极连接线远离所述第二端的一端，且部分覆盖所述栅极连接线远离所述第二端的一端。
在一些实施例中，所述栅极连接线与所述源漏极之间设置有层间绝缘层。
在一些实施例中，所述层间绝缘层上设置有至少一个通孔，所述栅极连接线通过所述通孔与所述源漏极连接。
在一些实施例中，所述通孔的形状为圆柱形、方柱形或圆台形。
在一些实施例中，所述栅极连接线的宽度小于所述栅极信号线的宽度。
在一些实施例中，所述栅极连接线弯折后的空间大小为一个主像素的空间大小。
在一些实施例中，所述栅极连接线全部弯折。
在一些实施例中，所述栅极连接线弯折为之字形、蛇形、脉冲形、凹凸折线形、波浪形或锯齿形。
在一些实施例中，所述静电防护线路是通过静电防护线路制程方法形成的，所述静电防护线路制程方法包括：
提供一栅极信号线，所述栅极信号线包括第一端与第二端；
在所述第一端连接驱动电路；
在所述第二端连接栅极连接线，所述栅极连接线至少部分弯折；
在所述栅极连接线远离所述第二端的一端连接源漏极。
在一些实施例中，所述在所述栅极连接线远离所述第二端的一端连接源漏极包括：
在所述栅极连接线远离所述第二端的一端设置层间绝缘层，且所述层间绝缘层部分覆盖所述栅极连接线远离所述第二端的一端；
在层间绝缘层上设置至少一个通孔；
在所述通孔和所述层间绝缘层上设置源漏极；其中，所述栅极连接线通过所述通孔与所述源漏极连接。
 有益效果
本申请实施例所提供的静电防护线路，包括：栅极信号线、驱动电路、栅极连接线以及源漏极。所述栅极信号线包括第一端与第二端，所述驱动电路连接所述第一端，所述栅极连接线连接所述第二端，所述栅极连接线至少部分弯折，所述源漏极连接所述栅极连接线远离所述第二端的一端，且部分覆盖所述栅极连接线远离所述第二端的一端。通过在栅极信号线的一端设置弯折的栅极连接线，静电释放通过弯折的栅极连接线，可以损耗掉一部分电流，减弱其影响，避免弱静电释放造成的面板边缘亮点。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的静电防护线路的一种结构示意图。
图2为本申请实施例提供的栅极连接线与源漏极连接处的局部切面图。
图3为本申请实施例提供的静电防护线路制程方法的一种流程示意图。
图4为本申请实施例提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明的是，在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
本申请实施例提供一种静电防护线路、静电防护线路制程方法及显示面板，以下对静电防护线路做详细介绍。
请参阅图1，图1是本申请实施例提供的静电防护线路10的一种结构示意图。该静电防护线路10包括栅极信号线101、驱动电路102、栅极连接线103以及源漏极104。栅极信号线101包括第一端101a与第二端101b，驱动电路102连接第一端101a，栅极连接线103连接第二端101b，栅极连接线103至少部分弯折，源漏极104连接栅极连接线103远离第二端101b的一端，且部分覆盖栅极连接线103远离所述第二端的一端。通过在栅极信号线101的一端设置弯折的栅极连接线103，静电释放通过弯折的栅极连接线103，可以损耗掉一部分电流，减弱其影响，避免弱静电释放造成的面板边缘亮点。
其中，驱动电路102（gate driver on array, GOA）是将栅极驱动电路（gate driver ICs）设置在阵列基板上，来代替外接驱动芯片的一种电路。应用GOA可以减少制作程序，降低产品生产成本，提高显示面板的高集成度，使显示面板更薄型化。
其中，请参阅图2，图2是本申请实施例提供的栅极连接线与源漏极连接处的局部切面图。栅极连接线103与源漏极104之间设置有层间绝缘层105，层间绝缘层105上设置有至少一个通孔106，栅极连接线103通过通孔106与源漏极104连接。通过在层间绝缘层105上设置通孔106，可对静电释放进一步防护，若静电释放通过栅极连接线103后仍然存在，则会炸伤通孔106，不影响有效显示区的像素。
其中，图2中所示通孔106以圆台形为实例，但并不是对通孔106的形状的限制。通孔106的形状为圆柱形、方柱形或圆台形。将通孔106设置为圆柱形可以使通孔106所受的应力均匀分布，防止受力不均造成的通孔106变形或开裂，保证栅极连接线103与源漏极104的连接。将通孔106设置为方柱形能够使源漏极104设置在通孔106中更贴合，不易脱落。将通孔106设置为圆台形方便源漏极104的设置，并且能够使源漏极104设置得更平坦，不易因过度弯折而产生性能不良，在保证栅极连接线103与源漏极104接触的同时，还能使源漏极104获得更好的工作性能。
其中，栅极连接线103的宽度小于栅极信号线101的宽度。栅极连接线103是为减小静电释放导致的不良而设置的，栅极连接线103的长度越长，对静电释放的减弱效果就越好。因此栅极连接线103的宽度小于栅极信号线101的宽度，能够在有限的空间内将栅极连接线103的长度设置的更长，从而更好地进行静电防护。
其中，栅极连接线103弯折后的空间大小为一个主像素的空间大小。依据各产品主像素大小不同，对栅极连接线103做弯折设计，可以使栅极连接线103更好的适应产品，对不同产品产生更优的静电防护效果。
其中，栅极连接线103全部弯折。具体地，将栅极连接线103全部盘起。栅极连接线103全部弯折，则可在有限的空间内将栅极连接线103的长度设置的更长，静电释放后所需经过的栅极连接线103也更长，能够更加有效地减弱静电释放对线路的影响。
其中，栅极连接线103弯折为之字形、蛇形、脉冲形、凹凸折线形、波浪形或锯齿形。这几种弯折形态能够在较小的空间内弯折更长的栅极连接线103，使静电释放途径的路线更长，对静电释放的减弱效果更好。
本申请实施例提供的静电防护线路10，包括栅极信号线101、驱动电路102、栅极连接线103以及源漏极104。通过在栅极信号线101的一端设置至少部分弯折的栅极连接线103，可在静电释放（Electro-Static discharge, ESD）通过时，损耗掉一部分电流，减弱其影响。另外，在栅极连接线103远离栅极信号线101一端与源漏极103之间设置有层间绝缘层105，并且层间绝缘层105上设置有至少一个通孔106，若ESD通过栅极连接线103之后，ESD仍然存在，则会炸伤通孔106，不影响有效显示区像素，能避免弱ESD造成的面板边缘亮点。
本申请实施例提供一种静电防护线路制程方法，以下对静电防护线路制程方法做详细介绍。请参阅图3，图3是本申请实施例中的静电防护线路制程方法的一种流程示意图。
201、提供一栅极信号线，栅极信号线包括第一端与第二端。
202、在第一端连接驱动电路。
203、在第二端连接栅极连接线，栅极连接线至少部分弯折。
204、在栅极连接线远离所述第二端的一端连接源漏极。
具体地，在栅极连接线远离所述第二端的一端设置层间绝缘层，且层间绝缘层部分覆盖所述栅极连接线远离所述第二端的一端。在层间绝缘层上设置至少一个通孔。在通孔和层间绝缘层上设置源漏极。其中，栅极连接线通过通孔与源漏极连接。设置通孔能够进一步进行静电防护，若静电释放通过栅极连接线之后，ESD仍然存在，则会炸伤通孔，而不影响有效显示区像素。
本申请实施例提供的静电防护线路制程方法，制成一种静电防护线路，包括栅极信号线、驱动电路、栅极连接线以及源漏极。通过在栅极信号线的一端设置至少部分弯折的栅极连接线，可在ESD通过时，损耗掉一部分电流，减弱其影响。另外，在栅极连接线远离栅极信号线一端与源漏极之间设置有层间绝缘层，并且层间绝缘层上设置有至少一个通孔，若ESD通过栅极连接线之后，ESD仍然存在，则会炸伤通孔，不影响有效显示区像素，能避免弱ESD造成的面板边缘亮点。
本申请实施例提供一种显示面板100，图4是本申请实施例提供的显示面板100的一种结构示意图。其中，显示面板100包括至少两个以上所述的静电防护线路10和信号线20，静电防护线路10通过信号线20连接。显示面板100还可以包括其他装置。本申请实施例中源漏极信号线20和其他装置及其装配是本领域技术人员所熟知的相关技术，在此不做过多赘述。
本申请实施例提供的显示面板100，包括至少两个以上所述的静电防护线路10和信号线20，静电防护线路10包括栅极信号线101、驱动电路102、栅极连接线103以及源漏极104。通过在栅极信号线101的一端设置至少部分弯折的栅极连接线103，可在ESD通过时，损耗掉一部分电流，减弱其影响。另外，在栅极连接线103远离栅极信号线101一端与源漏极103之间设置有层间绝缘层105，并且层间绝缘层105上设置有至少一个通孔106，若ESD通过栅极连接线103之后，ESD仍然存在，则会炸伤通孔106，不影响有效显示区像素，能避免弱ESD造成的面板边缘亮点。
以上对本申请实施例提供的静电防护线路、静电防护线路制程方法及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (18)

  1. 一种静电防护线路，其中，包括：
    栅极信号线，所述栅极信号线包括第一端与第二端；
    驱动电路，所述驱动电路连接所述第一端；
    栅极连接线，所述栅极连接线连接所述第二端，所述栅极连接线至少部分弯折；
    源漏极，所述源漏极连接所述栅极连接线远离所述第二端的一端，且部分覆盖所述栅极连接线远离所述第二端的一端。
  2. 根据权利要求1所述的静电防护线路，其中，所述栅极连接线与所述源漏极之间设置有层间绝缘层，所述层间绝缘层上设置有至少一个通孔，所述栅极连接线通过所述通孔与所述源漏极连接。
  3. 根据权利要求2所述的静电防护线路，其中，所述通孔的形状为圆柱形、方柱形或圆台形。
  4. 根据权利要求1所述的静电防护线路，其中，所述栅极连接线的宽度小于所述栅极信号线的宽度。
  5. 根据权利要求1所述的静电防护线路，其中，所述栅极连接线弯折后的空间大小为一个主像素的空间大小。
  6. 根据权利要求1所述的静电防护线路，其中，所述栅极连接线全部弯折。
  7. 根据权利要求1所述的静电防护线路，其中，所述栅极连接线弯折为之字形、蛇形、脉冲形、凹凸折线形、波浪形或锯齿形。
  8. 一种静电防护线路制程方法，其中，包括：
    提供一栅极信号线，所述栅极信号线包括第一端与第二端；
    在所述第一端连接驱动电路；
    在所述第二端连接栅极连接线，所述栅极连接线至少部分弯折；
    在所述栅极连接线远离所述第二端的一端连接源漏极。
  9. 根据权利要求8所述的静电防护线路制程方法，其中，所述在所述栅极连接线远离所述第二端的一端连接源漏极包括：
    在所述栅极连接线远离所述第二端的一端设置层间绝缘层，且所述层间绝缘层部分覆盖所述栅极连接线远离所述第二端的一端；
    在层间绝缘层上设置至少一个通孔；
    在所述通孔和所述层间绝缘层上设置源漏极；其中，所述栅极连接线通过所述通孔与所述源漏极连接。
  10. 一种显示面板，其中，包括至少两个静电防护线路，所述静电防护线路，包括：
    栅极信号线，所述栅极信号线包括第一端与第二端；
    驱动电路，所述驱动电路连接所述第一端；
    栅极连接线，所述栅极连接线连接所述第二端，所述栅极连接线至少部分弯折；
    源漏极，所述源漏极连接所述栅极连接线远离所述第二端的一端，且部分覆盖所述栅极连接线远离所述第二端的一端。
  11. 根据权利要求10所述的显示面板，其中，所述栅极连接线与所述源漏极之间设置有层间绝缘层，所述层间绝缘层上设置有至少一个通孔，所述栅极连接线通过所述通孔与所述源漏极连接。
  12. 根据权利要求11所述的显示面板，其中，所述通孔的形状为圆柱形、方柱形或圆台形。
  13. 根据权利要求10所述的显示面板，其中，所述栅极连接线的宽度小于所述栅极信号线的宽度。
  14. 根据权利要求10所述的显示面板，其中，所述栅极连接线弯折后的空间大小为一个主像素的空间大小。
  15. 根据权利要求10所述的显示面板，其中，所述栅极连接线全部弯折。
  16. 根据权利要求10所述的显示面板，其中，所述栅极连接线弯折为之字形、蛇形、脉冲形、凹凸折线形、波浪形或锯齿形。
  17. 根据权利要求10所述的显示面板，其中，所述静电防护线路是通过静电防护线路制程方法形成的，所述静电防护线路制程方法包括：
    提供一栅极信号线，所述栅极信号线包括第一端与第二端；
    在所述第一端连接驱动电路；
    在所述第二端连接栅极连接线，所述栅极连接线至少部分弯折；
    在所述栅极连接线远离所述第二端的一端连接源漏极。
  18. 根据权利要求17所述的显示面板，其中，所述在所述栅极连接线远离所述第二端的一端连接源漏极包括：
    在所述栅极连接线远离所述第二端的一端设置层间绝缘层，且所述层间绝缘层部分覆盖所述栅极连接线远离所述第二端的一端；
    在层间绝缘层上设置至少一个通孔；
    在所述通孔和所述层间绝缘层上设置源漏极；其中，所述栅极连接线通过所述通孔与所述源漏极连接。
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