WO2021238971A1 - Puce de semi-conducteur, multiplexeur et dispositif de communication - Google Patents

Puce de semi-conducteur, multiplexeur et dispositif de communication Download PDF

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Publication number
WO2021238971A1
WO2021238971A1 PCT/CN2021/095995 CN2021095995W WO2021238971A1 WO 2021238971 A1 WO2021238971 A1 WO 2021238971A1 CN 2021095995 W CN2021095995 W CN 2021095995W WO 2021238971 A1 WO2021238971 A1 WO 2021238971A1
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WO
WIPO (PCT)
Prior art keywords
isolation layer
wafer
sealing ring
lower wafer
seal ring
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PCT/CN2021/095995
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English (en)
Chinese (zh)
Inventor
蔡华林
庞慰
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诺思(天津)微系统有限责任公司
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Publication of WO2021238971A1 publication Critical patent/WO2021238971A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator

Definitions

  • the present invention relates to the technical field of filters, in particular to a semiconductor chip, a multiplexer and a communication device.
  • FIG. 1 is a schematic diagram of a structure of an acoustic wave filter in the prior art.
  • this filter 10 there are inductors 121 and 122 between the input terminal 131 and the output terminal 132, and a plurality of resonators (usually called series resonators) 101 to 104, and the connection point of each series resonator is between the ground terminal Resonators 111 to 113 (usually referred to as parallel resonators) and inductors 123 to 125 are respectively arranged on multiple branches (usually referred to as parallel branches) of.
  • a mass load layer is added to each parallel resonator, so that the frequency of the parallel resonator and the frequency of the series resonator are different to form the passband of the filter.
  • the quadruplexer includes four filters.
  • the frequency bands of the four filters (chips) are B3TX: 1710 ⁇ 1785MHz, B3RX: 1805 ⁇ 1880MHz, B1TX: 1920 ⁇ 1980MHz, and B1RX: 2110 ⁇ 2170MHz.
  • FIG. 2 is a diagram of the positional relationship between the four chips and the matching inductor in the existing quadruplexer. As shown in FIG. 2, the size of the quadruplexer 20 is relatively large, so the four chips and the electrical structure thereon have a certain distance from the matching inductor 21 on the packaging substrate, and the coupling between each other is small.
  • FIG. 3 is a diagram showing the positional relationship between the four chips and the matching inductor in the existing improved quadruplexer.
  • the original four chips are stacked up and down two by two, and the original four chips are reduced to two in the horizontal direction, thereby reducing the total area of the quadruple. It can be seen from FIG. 3 that since the relative position between the chip and the matching inductor 31 has not changed, the coupling remains unchanged.
  • the packaging substrate of the quadruple can be further reduced.
  • FIG. 4 is a diagram showing the positional relationship between the four chips and the matching inductor in another improved quadruple.
  • the matching inductor 41 in the filter 40 is located below the chip.
  • there is coupling between the matching inductor 41 and the chip and the increased coupling in the quadruple will deteriorate the isolation of the quadruple.
  • FIG. 5 is a cross-sectional view of two existing chips arranged one above the other
  • FIG. 6 is a plan view of the lower surface of the upper wafer in FIG. 5.
  • the resonator on the upper wafer is connected to the ground pin PAD below through the through hole of the docking pin PAD1 through the two layers of the wafer, and the resonator on the middle wafer passes through the docking pin PAD1
  • the through holes of a layer of the wafer are connected to the ground pin PAD below, and the package substrate is connected below the ground pin PAD, and the passive device is integrated in the package substrate.
  • a sealing ring is arranged between adjacent wafers, and the sealing ring is arranged outside the mating pin PAD1 to form a sealing structure.
  • the upper wafer includes series resonators S1 to S4, parallel resonators P1 to P3, input pin IN, input pin OUT, docking pins G1, G2, and isolation layer (the vertical line in the figure) Occupied area) and sealing ring.
  • the isolation layer needs to be connected to one of the docking pins PAD1 and the corresponding through hole to achieve grounding, or grounded through an additional docking pin and the corresponding through hole (the isolation layer is connected to the docking pin G2 in FIG. 6).
  • the invention provides a semiconductor chip, a multiplexer and a communication device.
  • An isolation layer is added between the sealing ring and the passive device to avoid coupling between the two, thereby improving the isolation of the multiplexer.
  • a semiconductor chip is provided.
  • the semiconductor chip of the present invention includes an upper wafer and a lower wafer, the bottom of the lower wafer is connected with a packaging substrate, a sealing ring is provided between the upper wafer and the lower wafer, and a sealing ring isolation layer is provided between the sealing ring and the lower wafer;
  • the inner and outer sides of the seal ring are respectively provided with an inner isolation layer of the seal ring and an outer isolation layer of the seal ring, wherein the inner isolation layer of the seal ring and the outer isolation layer of the seal ring are connected by a conductor.
  • the conductor is located between the sealing ring and the lower wafer.
  • the upper surface of the lower wafer is further provided with a resonator isolation layer, and the resonator isolation layer and the seal ring isolation layer or the isolation layer in the seal ring are an integrated structure;
  • a through hole is provided at the opposite position, and the mating pin between the upper wafer and the lower wafer is connected to the ground pin on the lower side of the lower wafer through the through hole.
  • At least one ground hole is provided in the lower wafer, a wire is provided in the ground hole, and the resonator isolation layer, the seal ring isolation layer, the inner isolation layer of the seal ring, or the outer isolation layer of the seal ring are connected to the ground via the wires in the ground hole. At least one ground pin is connected.
  • the packaging substrate includes a plurality of superimposed upper wafers and lower wafers, and the plurality of superimposed upper wafers and lower wafers include a plurality of ground holes, wherein the plurality of ground holes are vertically projected to the packaging substrate Located on the periphery of the passive device, the passive device is located on the surface or inside of the package substrate, or on the underside of the lower wafer.
  • the resonator is an acoustic wave resonator.
  • a multiplexer is provided.
  • the multiplexer of the present invention includes at least two sets of stacking units.
  • the stacking unit includes an upper wafer, a middle wafer, and a lower wafer.
  • the inner and outer sides of the ring are respectively provided with an inner isolation layer of the seal ring and an outer isolation layer of the seal ring, wherein the inner isolation layer of the seal ring and the outer isolation layer of the seal ring are connected by a conductor.
  • the conductor is located between the sealing ring and the middle or lower wafer where it is located.
  • the upper surface of the middle wafer and/or the lower wafer is further provided with a resonator isolation layer, and the resonator isolation layer and the seal ring isolation layer of the same layer or the inner isolation layer of the seal ring form an integrated structure;
  • a through hole is provided at a position opposite to the through hole in the lower wafer, and the mating pin between the upper wafer and the lower wafer is connected to the ground pin on the lower side of the lower wafer through the through hole.
  • At least one ground hole is provided in the middle wafer and/or the lower wafer, and a wire is provided in the ground hole, and the resonator isolation layer, the seal ring isolation layer, the inner isolation layer of the seal ring, or the outer isolation layer of the seal ring pass The wire in the ground hole is connected to at least one ground pin.
  • the multiple superimposing units include multiple ground holes, and the vertical projection of the multiple ground holes to the packaging substrate is located on the periphery of the passive device in the packaging substrate, and the passive device is located on the surface or inside of the packaging substrate, or Bottom side of the lower wafer.
  • the resonator is an acoustic wave resonator.
  • the multiplexer includes a first receiving chip, a first sending chip, a second receiving chip, and a second sending chip; the second sending chip and the first sending chip are superimposed to form a superimposing unit, and the second receiving chip and the first The receiving chip is superimposed to form a superimposing unit, or the second sending chip and the first receiving chip are superimposed to form a superimposing unit, and the first sending chip and the second receiving chip are superimposed to form a superimposing unit.
  • a communication device which includes the multiplexer according to the present invention.
  • yet another communication device which includes the semiconductor chip according to the present invention.
  • Fig. 1 is a schematic diagram of a filter topology according to the prior art
  • Figure 2 is a diagram showing the positional relationship between four chips and matching inductors in a conventional quadruple
  • Fig. 3 is a diagram of the positional relationship between the four chips and the matching inductor in the existing improved quadruplexer
  • Figure 4 is a diagram of the positional relationship between the four chips and the matching inductor in another improved quadruplexer
  • FIG. 5 is a cross-sectional view of two existing chips arranged one above the other;
  • Fig. 6 is a plan view of the lower surface of the upper wafer in Fig. 5;
  • FIG. 7 is a plan view of the upper wafer in the package structure provided by the embodiment of the present invention.
  • FIG. 8 is a schematic diagram of an isolation method using a sealing ring in the packaging structure provided by the embodiment of the present invention.
  • FIG. 9 is a schematic diagram of another isolation method using a seal ring in the packaging structure provided by the embodiment of the present invention.
  • FIG. 10 is a schematic diagram of an isolation mode of a multiplexer according to an embodiment of the present invention.
  • FIG. 11 is a schematic diagram of another isolation mode of the multiplexer according to the embodiment of the present invention.
  • FIG. 12 is a distribution diagram of ground holes in a multiplexer according to an embodiment of the present invention.
  • FIG. 13a is a comparison diagram of out-of-band suppression curves of a second transmitting chip in a quadruplexer according to an embodiment of the present invention
  • 13b is a comparison diagram of out-of-band suppression curves of the second receiving chip in the quadruplexer according to the embodiment of the present invention.
  • FIG. 13c is a comparison diagram of out-of-band suppression curves of the first transmitting chip in the quadruplexer according to the embodiment of the present invention.
  • FIG. 13d is a comparison diagram of out-of-band suppression curves of the first receiving chip in the quadruplexer according to the embodiment of the present invention.
  • FIG. 13e is a comparison curve of isolation between the second transmitting chip and the second receiving chip in the quadruplexer according to the embodiment of the present invention.
  • FIG. 13f is a comparison curve of isolation between the first transmitting chip and the first receiving chip in the quadruplexer according to the embodiment of the present invention.
  • FIG. 14a is a comparison diagram of out-of-band suppression curves of a second transmitting chip in a quadruplexer according to an embodiment of the present invention.
  • FIG. 14b is a comparison diagram of out-of-band suppression curves of the second receiving chip in the quadruplexer according to the embodiment of the present invention.
  • 14c is a comparison diagram of out-of-band suppression curves of the first transmitting chip in the quadruplexer according to the embodiment of the present invention.
  • 14d is a comparison diagram of out-of-band suppression curves of the first receiving chip in the quadruplexer according to the embodiment of the present invention.
  • FIG. 14e is a comparison curve of isolation between the second transmitting chip and the second receiving chip in the quadruplexer according to the embodiment of the present invention.
  • FIG. 14f is a comparison curve of isolation between the first transmitting chip and the first receiving chip in the quadruplexer according to the embodiment of the present invention.
  • a seal ring isolation layer is added to the chip packaging structure, and the seal ring isolation layer avoids/reduces the coupling between the seal ring and the passive components, thereby avoiding/reducing the degradation of the multiplexer isolation, as follows Be specific.
  • FIG. 7 is a plan view of the upper wafer in the package structure provided by the embodiment of the present invention. As shown in FIG. 7, the area formed by the vertical lines in the figure is an isolation layer. Compared with the plan view of the upper wafer shown in FIG. 6, the isolation layer covers the sealing ring.
  • the seal ring isolation layer is used to realize the isolation of the seal ring, wherein the seal ring isolation layer includes two forms.
  • FIG. 8 is a schematic diagram of an isolation method using a seal ring in the package structure provided by the embodiment of the present invention . As shown in Fig. 8, a sealing ring isolation layer is provided between the upper surface of the lower wafer and the sealing ring (and between the silicon boss carrying the sealing ring).
  • FIG. 9 is a schematic diagram of another isolation method using a seal ring in the packaging structure provided by the embodiment of the present invention. As shown in Figure 9, the seal ring isolation layer is provided on the upper surface of the lower wafer.
  • the conductor is a metal wire or a metal conductive sheet, etc., which is arranged between the sealing ring and the lower wafer.
  • the conductors can be connected in one piece of metal, or one or more can be connected across the sealing ring.
  • the upper surface of the lower wafer is provided with a resonator isolation layer.
  • the resonator isolation layer is used to avoid/reduce the coupling between the resonator and passive components.
  • the resonator isolation layer is closer to the lower wafer. Central.
  • the seal ring isolation layer is added, as shown in FIG. 7, preferably, the resonator isolation layer and the seal ring isolation layer or the inner isolation layer of the seal ring can be arranged as an integral structure.
  • the position of the isolation layer of the lower wafer opposite to the via hole needs to be provided with a through hole to ensure that the mating pin PAD1 can be connected to the ground pin PAD.
  • FIG. 10 is a schematic diagram of an isolation mode of the multiplexer according to the embodiment of the present invention. As shown in Figure 10, a sealing ring isolation layer is provided between the surface of the middle wafer and the sealing ring, and between the surface of the lower wafer and the sealing ring.
  • FIG. 11 is a schematic diagram of another isolation manner of the multiplexer according to the embodiment of the present invention.
  • the inner and outer sides of the middle wafer seal ring and the inner and outer sides of the lower wafer seal ring are respectively provided with an outer seal ring isolation layer and an inner seal ring isolation layer, wherein the inner isolation layer of the seal ring and the seal ring
  • the outer isolation layers are connected by a conductor (not shown in the figure), the conductor is a metal wire or a metal conductive sheet, etc.
  • the conductor is arranged between the sealing ring and the middle wafer/lower wafer.
  • the structure of the sealing isolation ring is not limited to the form shown in FIG. 10 and FIG. Both the middle wafer and the lower wafer are provided with a seal ring structure, and the seal ring isolation layer can adopt any form of seal ring isolation shown in FIG. 10 or FIG. 11.
  • Fig. 12 is a distribution diagram of ground holes in a multiplexer according to an embodiment of the present invention. As shown in Figure 12, ISO_G1, ISO_G2...ISO_G8 in the filter 50 are represented as grounding holes.
  • each superimposed unit includes multiple grounding holes, and multiple grounding holes are arranged On the surface or inside of the package substrate, or the periphery of the passive device (matching inductance) 51 on the underside of the lower wafer (according to the chip plan view of Figure 12), this arrangement can couple the passive device and the chip electrical structure Decrease, further increase the isolation effect.
  • the isolation method of the embodiment of the present invention includes two superimposing units, the second transmitting chip B3TX and the first transmitting chip B1TX are superimposed, and the second receiving chip B3RX and the first receiving chip B1RX are superimposed.
  • the second transmitting chip B3TX frequency band is 1710 ⁇ 1785MHz; the second receiving chip B3RX frequency band is 1805 ⁇ 1880MHz; the first transmitting chip B1TX frequency band is 1920 ⁇ 1980MHz; the first receiving chip B1RX frequency band is 2110 ⁇ 2170MHz.
  • Figures 13a to 13d are comparison diagrams of out-of-band suppression curves for four chips.
  • the solid line in the figure is the out-of-band suppression curve when the seal ring is increased in isolation, and the dashed line is the out-of-band suppression curve when the seal ring is not isolated.
  • Figure 13e is a comparison curve of the isolation between the second transmitting chip and the second receiving chip
  • Figure 13f is the comparison curve of the isolation between the first transmitting chip and the first receiving chip.
  • the solid line is the isolation curve when the sealing ring is isolated.
  • the dotted line is the isolation curve when the seal ring is not isolated. It can be seen from Figures 13a to 13f that when the seal ring in the quadruple is isolated by the seal ring isolation layer, its out-of-band suppression and isolation are greatly improved.
  • Figures 14a-14d are comparison diagrams of out-of-band suppression curves of four chips.
  • the solid line in the figure is the out-of-band suppression curve when grounding holes are added, and the dashed line is the out-of-band suppression curve when no grounding holes are provided.
  • Figure 14e is a comparison curve of the isolation between the second transmitting chip and the second receiving chip
  • Figure 14f is a comparison curve of the isolation between the first transmitting chip and the first receiving chip.
  • the solid line is the isolation curve when the ground hole is added, and the dashed line It is the isolation curve when there is no grounding hole. It can be seen from Figures 14a-14f that when a ground hole is added to the quadruplexer, the signal leakage of passive components can be avoided, thereby further improving the out-of-band suppression and isolation of the quadruplexer.

Abstract

La présente invention concerne le domaine technique des filtres, et en particulier une puce de semi-conducteur, un multiplexeur et un dispositif de communication. Dans la puce de semi-conducteur, une bague d'étanchéité entre tranches est isolée d'un dispositif passif également à l'aide d'une couche d'isolation ; et le couplage entre la bague d'étanchéité et le dispositif passif est évité/réduit par une couche d'isolation de bague d'étanchéité, ce qui permet d'éviter/de réduire la détérioration du degré d'isolation du multiplexeur.
PCT/CN2021/095995 2020-05-29 2021-05-26 Puce de semi-conducteur, multiplexeur et dispositif de communication WO2021238971A1 (fr)

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CN202010476283.2A CN111697938B (zh) 2020-05-29 2020-05-29 一种半导体芯片、多工器及通信设备
CN202010476283.2 2020-05-29

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CN110828950B (zh) * 2019-10-18 2022-05-10 天津大学 一种多工器
CN111697938B (zh) * 2020-05-29 2021-09-21 诺思(天津)微系统有限责任公司 一种半导体芯片、多工器及通信设备
CN115021711B (zh) * 2022-07-20 2022-11-18 苏州汉天下电子有限公司 一种半导体器件、通信设备及其制造方法

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