WO2021238971A1

WO2021238971A1 - Semiconductor chip, multiplexer, and communication device

Info

Publication number: WO2021238971A1
Application number: PCT/CN2021/095995
Authority: WO
Inventors: 蔡华林; 庞慰
Original assignee: 诺思(天津)微系统有限责任公司
Priority date: 2020-05-29
Filing date: 2021-05-26
Publication date: 2021-12-02
Also published as: CN111697938B; CN111697938A

Abstract

The present invention relates to the technical field of filters, and in particular, to a semiconductor chip, a multiplexer, and a communication device. In the semiconductor chip, a sealing ring between wafers is isolated from a passive device also using an isolation layer; and the coupling between the sealing ring and the passive device is avoided/reduced by a sealing ring isolation layer, thereby avoiding/reducing the deterioration of the isolation degree of the multiplexer.

Description

Semiconductor chip, multiplexer and communication equipment

Technical field

The present invention relates to the technical field of filters, in particular to a semiconductor chip, a multiplexer and a communication device.

Background technique

In recent years, the trend of miniaturization and high performance of communication equipment has accelerated, which has put forward higher challenges for the radio frequency front end. In the radio frequency communication front-end, on the one hand, it is necessary to achieve miniaturization by reducing the size of the chip and package substrate, on the other hand, it is necessary to achieve better performance by reducing the source of loss and better resonator design. In the existing filter structure, there are many passive components used for matching, and at the same time, it is necessary to introduce more inductance, capacitance, coupling and other structures to improve specific performance such as roll-off insertion loss.

A typical structure of a common filter is shown in FIG. 1, which is a schematic diagram of a structure of an acoustic wave filter in the prior art. In this filter 10, there are

inductors

121 and 122 between the input terminal 131 and the output terminal 132, and a plurality of resonators (usually called series resonators) 101 to 104, and the connection point of each series resonator is between the ground terminal Resonators 111 to 113 (usually referred to as parallel resonators) and inductors 123 to 125 are respectively arranged on multiple branches (usually referred to as parallel branches) of. A mass load layer is added to each parallel resonator, so that the frequency of the parallel resonator and the frequency of the series resonator are different to form the passband of the filter.

The quadruplexer includes four filters. The frequency bands of the four filters (chips) are B3TX: 1710～1785MHz, B3RX: 1805～1880MHz, B1TX: 1920～1980MHz, and B1RX: 2110～2170MHz. FIG. 2 is a diagram of the positional relationship between the four chips and the matching inductor in the existing quadruplexer. As shown in FIG. 2, the size of the quadruplexer 20 is relatively large, so the four chips and the electrical structure thereon have a certain distance from the matching inductor 21 on the packaging substrate, and the coupling between each other is small.

At present, a commonly adopted method is to further reduce the size of the quadruplexer by adjusting the placement position of the chip. FIG. 3 is a diagram showing the positional relationship between the four chips and the matching inductor in the existing improved quadruplexer. As shown in FIG. 3, in the filter 30, the original four chips are stacked up and down two by two, and the original four chips are reduced to two in the horizontal direction, thereby reducing the total area of the quadruple. It can be seen from FIG. 3 that since the relative position between the chip and the matching inductor 31 has not changed, the coupling remains unchanged. In order to further reduce the size of the quadruple, the packaging substrate of the quadruple can be further reduced. The shrinking of the packaging substrate will change the relative relationship between the matching inductance and the chip on the packaging substrate. Figure 4 is a diagram showing the positional relationship between the four chips and the matching inductor in another improved quadruple. As shown in FIG. 4, the matching inductor 41 in the filter 40 is located below the chip. In this structure, there is coupling between the matching inductor 41 and the chip, and the increased coupling in the quadruple will deteriorate the isolation of the quadruple.

5 is a cross-sectional view of two existing chips arranged one above the other, and FIG. 6 is a plan view of the lower surface of the upper wafer in FIG. 5. As shown in Figure 5, the resonator on the upper wafer is connected to the ground pin PAD below through the through hole of the docking pin PAD1 through the two layers of the wafer, and the resonator on the middle wafer passes through the docking pin PAD1 The through holes of a layer of the wafer are connected to the ground pin PAD below, and the package substrate is connected below the ground pin PAD, and the passive device is integrated in the package substrate. A sealing ring is arranged between adjacent wafers, and the sealing ring is arranged outside the mating pin PAD1 to form a sealing structure. As shown in Figure 6, the upper wafer includes series resonators S1 to S4, parallel resonators P1 to P3, input pin IN, input pin OUT, docking pins G1, G2, and isolation layer (the vertical line in the figure) Occupied area) and sealing ring. Wherein, the isolation layer needs to be connected to one of the docking pins PAD1 and the corresponding through hole to achieve grounding, or grounded through an additional docking pin and the corresponding through hole (the isolation layer is connected to the docking pin G2 in FIG. 6).

Summary of the invention

The invention provides a semiconductor chip, a multiplexer and a communication device. An isolation layer is added between the sealing ring and the passive device to avoid coupling between the two, thereby improving the isolation of the multiplexer.

To achieve the above objective, according to one aspect of the present invention, a semiconductor chip is provided.

The semiconductor chip of the present invention includes an upper wafer and a lower wafer, the bottom of the lower wafer is connected with a packaging substrate, a sealing ring is provided between the upper wafer and the lower wafer, and a sealing ring isolation layer is provided between the sealing ring and the lower wafer; Alternatively, the inner and outer sides of the seal ring are respectively provided with an inner isolation layer of the seal ring and an outer isolation layer of the seal ring, wherein the inner isolation layer of the seal ring and the outer isolation layer of the seal ring are connected by a conductor.

Optionally, the conductor is located between the sealing ring and the lower wafer.

Optionally, the upper surface of the lower wafer is further provided with a resonator isolation layer, and the resonator isolation layer and the seal ring isolation layer or the isolation layer in the seal ring are an integrated structure; A through hole is provided at the opposite position, and the mating pin between the upper wafer and the lower wafer is connected to the ground pin on the lower side of the lower wafer through the through hole.

Optionally, at least one ground hole is provided in the lower wafer, a wire is provided in the ground hole, and the resonator isolation layer, the seal ring isolation layer, the inner isolation layer of the seal ring, or the outer isolation layer of the seal ring are connected to the ground via the wires in the ground hole. At least one ground pin is connected.

Optionally, the packaging substrate includes a plurality of superimposed upper wafers and lower wafers, and the plurality of superimposed upper wafers and lower wafers include a plurality of ground holes, wherein the plurality of ground holes are vertically projected to the packaging substrate Located on the periphery of the passive device, the passive device is located on the surface or inside of the package substrate, or on the underside of the lower wafer.

Optionally, the resonator is an acoustic wave resonator.

According to another aspect of the present invention, a multiplexer is provided.

The multiplexer of the present invention includes at least two sets of stacking units. The stacking unit includes an upper wafer, a middle wafer, and a lower wafer. There are sealing rings between the lower wafers, and a sealing ring isolation layer is provided between the sealing ring and the middle wafer and/or between the sealing ring and the lower wafer; or, the sealing of the middle wafer and/or the lower wafer The inner and outer sides of the ring are respectively provided with an inner isolation layer of the seal ring and an outer isolation layer of the seal ring, wherein the inner isolation layer of the seal ring and the outer isolation layer of the seal ring are connected by a conductor.

Optionally, the conductor is located between the sealing ring and the middle or lower wafer where it is located.

Optionally, the upper surface of the middle wafer and/or the lower wafer is further provided with a resonator isolation layer, and the resonator isolation layer and the seal ring isolation layer of the same layer or the inner isolation layer of the seal ring form an integrated structure; A through hole is provided at a position opposite to the through hole in the lower wafer, and the mating pin between the upper wafer and the lower wafer is connected to the ground pin on the lower side of the lower wafer through the through hole.

Optionally, at least one ground hole is provided in the middle wafer and/or the lower wafer, and a wire is provided in the ground hole, and the resonator isolation layer, the seal ring isolation layer, the inner isolation layer of the seal ring, or the outer isolation layer of the seal ring pass The wire in the ground hole is connected to at least one ground pin.

Optionally, the multiple superimposing units include multiple ground holes, and the vertical projection of the multiple ground holes to the packaging substrate is located on the periphery of the passive device in the packaging substrate, and the passive device is located on the surface or inside of the packaging substrate, or Bottom side of the lower wafer.

Optionally, the resonator is an acoustic wave resonator.

Optionally, the multiplexer includes a first receiving chip, a first sending chip, a second receiving chip, and a second sending chip; the second sending chip and the first sending chip are superimposed to form a superimposing unit, and the second receiving chip and the first The receiving chip is superimposed to form a superimposing unit, or the second sending chip and the first receiving chip are superimposed to form a superimposing unit, and the first sending chip and the second receiving chip are superimposed to form a superimposing unit.

According to another aspect of the present invention, a communication device is provided, which includes the multiplexer according to the present invention.

According to another aspect of the present invention, there is provided yet another communication device, which includes the semiconductor chip according to the present invention.

Description of the drawings

For the purpose of illustration and not limitation, the present invention will now be described according to preferred embodiments of the present invention, particularly with reference to the accompanying drawings, in which:

Fig. 1 is a schematic diagram of a filter topology according to the prior art;

Figure 2 is a diagram showing the positional relationship between four chips and matching inductors in a conventional quadruple;

Fig. 3 is a diagram of the positional relationship between the four chips and the matching inductor in the existing improved quadruplexer;

Figure 4 is a diagram of the positional relationship between the four chips and the matching inductor in another improved quadruplexer;

FIG. 5 is a cross-sectional view of two existing chips arranged one above the other;

Fig. 6 is a plan view of the lower surface of the upper wafer in Fig. 5;

7 is a plan view of the upper wafer in the package structure provided by the embodiment of the present invention;

8 is a schematic diagram of an isolation method using a sealing ring in the packaging structure provided by the embodiment of the present invention;

9 is a schematic diagram of another isolation method using a seal ring in the packaging structure provided by the embodiment of the present invention;

FIG. 10 is a schematic diagram of an isolation mode of a multiplexer according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of another isolation mode of the multiplexer according to the embodiment of the present invention;

FIG. 12 is a distribution diagram of ground holes in a multiplexer according to an embodiment of the present invention;

FIG. 13a is a comparison diagram of out-of-band suppression curves of a second transmitting chip in a quadruplexer according to an embodiment of the present invention;

13b is a comparison diagram of out-of-band suppression curves of the second receiving chip in the quadruplexer according to the embodiment of the present invention;

FIG. 13c is a comparison diagram of out-of-band suppression curves of the first transmitting chip in the quadruplexer according to the embodiment of the present invention;

FIG. 13d is a comparison diagram of out-of-band suppression curves of the first receiving chip in the quadruplexer according to the embodiment of the present invention;

FIG. 13e is a comparison curve of isolation between the second transmitting chip and the second receiving chip in the quadruplexer according to the embodiment of the present invention;

FIG. 13f is a comparison curve of isolation between the first transmitting chip and the first receiving chip in the quadruplexer according to the embodiment of the present invention;

FIG. 14a is a comparison diagram of out-of-band suppression curves of a second transmitting chip in a quadruplexer according to an embodiment of the present invention;

FIG. 14b is a comparison diagram of out-of-band suppression curves of the second receiving chip in the quadruplexer according to the embodiment of the present invention;

14c is a comparison diagram of out-of-band suppression curves of the first transmitting chip in the quadruplexer according to the embodiment of the present invention;

14d is a comparison diagram of out-of-band suppression curves of the first receiving chip in the quadruplexer according to the embodiment of the present invention;

FIG. 14e is a comparison curve of isolation between the second transmitting chip and the second receiving chip in the quadruplexer according to the embodiment of the present invention;

FIG. 14f is a comparison curve of isolation between the first transmitting chip and the first receiving chip in the quadruplexer according to the embodiment of the present invention.

Detailed ways

In the embodiment of the present invention, a seal ring isolation layer is added to the chip packaging structure, and the seal ring isolation layer avoids/reduces the coupling between the seal ring and the passive components, thereby avoiding/reducing the degradation of the multiplexer isolation, as follows Be specific.

FIG. 7 is a plan view of the upper wafer in the package structure provided by the embodiment of the present invention. As shown in FIG. 7, the area formed by the vertical lines in the figure is an isolation layer. Compared with the plan view of the upper wafer shown in FIG. 6, the isolation layer covers the sealing ring.

In the embodiment of the present invention, the seal ring isolation layer is used to realize the isolation of the seal ring, wherein the seal ring isolation layer includes two forms. FIG. 8 is a schematic diagram of an isolation method using a seal ring in the package structure provided by the embodiment of the present invention . As shown in Fig. 8, a sealing ring isolation layer is provided between the upper surface of the lower wafer and the sealing ring (and between the silicon boss carrying the sealing ring). FIG. 9 is a schematic diagram of another isolation method using a seal ring in the packaging structure provided by the embodiment of the present invention. As shown in Figure 9, the seal ring isolation layer is provided on the upper surface of the lower wafer. It is divided into a seal ring inner isolation layer and a seal ring outer isolation layer, which are located on the inside and outside of the seal ring, and pass between the two A conductor (not shown in the figure) is connected. The conductor is a metal wire or a metal conductive sheet, etc., which is arranged between the sealing ring and the lower wafer. The conductors can be connected in one piece of metal, or one or more can be connected across the sealing ring.

As shown in Figure 5, the upper surface of the lower wafer is provided with a resonator isolation layer. The resonator isolation layer is used to avoid/reduce the coupling between the resonator and passive components. The resonator isolation layer is closer to the lower wafer. Central. When the seal ring isolation layer is added, as shown in FIG. 7, preferably, the resonator isolation layer and the seal ring isolation layer or the inner isolation layer of the seal ring can be arranged as an integral structure. Wherein, the position of the isolation layer of the lower wafer opposite to the via hole needs to be provided with a through hole to ensure that the mating pin PAD1 can be connected to the ground pin PAD.

FIG. 10 is a schematic diagram of an isolation mode of the multiplexer according to the embodiment of the present invention. As shown in Figure 10, a sealing ring isolation layer is provided between the surface of the middle wafer and the sealing ring, and between the surface of the lower wafer and the sealing ring. FIG. 11 is a schematic diagram of another isolation manner of the multiplexer according to the embodiment of the present invention. As shown in Figure 11, the inner and outer sides of the middle wafer seal ring and the inner and outer sides of the lower wafer seal ring are respectively provided with an outer seal ring isolation layer and an inner seal ring isolation layer, wherein the inner isolation layer of the seal ring and the seal ring The outer isolation layers are connected by a conductor (not shown in the figure), the conductor is a metal wire or a metal conductive sheet, etc. The conductor is arranged between the sealing ring and the middle wafer/lower wafer.

In the quadruple provided by the embodiment of the present invention, the structure of the sealing isolation ring is not limited to the form shown in FIG. 10 and FIG. Both the middle wafer and the lower wafer are provided with a seal ring structure, and the seal ring isolation layer can adopt any form of seal ring isolation shown in FIG. 10 or FIG. 11.

In the embodiment of the present invention, the resonator isolation layer and the seal ring isolation layer (the inner isolation layer of the seal ring and the outer isolation layer of the seal ring) are connected to the ground pin through the ground hole. Ground, the signal will not cause signal leakage between the chips, which can further improve the isolation of the multiplexer. In addition, the operation of forming a ground hole on the wafer does not increase the manufacturing process of the semiconductor package structure/quadruplexer, and thus does not increase the manufacturing difficulty and cost of the semiconductor package structure/quadruplexer. Fig. 12 is a distribution diagram of ground holes in a multiplexer according to an embodiment of the present invention. As shown in Figure 12, ISO_G1, ISO_G2...ISO_G8 in the filter 50 are represented as grounding holes. From the grounding hole distribution in the figure, each superimposed unit includes multiple grounding holes, and multiple grounding holes are arranged On the surface or inside of the package substrate, or the periphery of the passive device (matching inductance) 51 on the underside of the lower wafer (according to the chip plan view of Figure 12), this arrangement can couple the passive device and the chip electrical structure Decrease, further increase the isolation effect.

The effect of the isolation method of the embodiment of the present invention will be described below. Taking a quadruple as an example, it includes two superimposing units, the second transmitting chip B3TX and the first transmitting chip B1TX are superimposed, and the second receiving chip B3RX and the first receiving chip B1RX are superimposed. Among them, the second transmitting chip B3TX frequency band is 1710～1785MHz; the second receiving chip B3RX frequency band is 1805～1880MHz; the first transmitting chip B1TX frequency band is 1920～1980MHz; the first receiving chip B1RX frequency band is 2110～2170MHz. Figures 13a to 13d are comparison diagrams of out-of-band suppression curves for four chips. The solid line in the figure is the out-of-band suppression curve when the seal ring is increased in isolation, and the dashed line is the out-of-band suppression curve when the seal ring is not isolated. Figure 13e is a comparison curve of the isolation between the second transmitting chip and the second receiving chip, and Figure 13f is the comparison curve of the isolation between the first transmitting chip and the first receiving chip. In the figure, the solid line is the isolation curve when the sealing ring is isolated. The dotted line is the isolation curve when the seal ring is not isolated. It can be seen from Figures 13a to 13f that when the seal ring in the quadruple is isolated by the seal ring isolation layer, its out-of-band suppression and isolation are greatly improved.

Figures 14a-14d are comparison diagrams of out-of-band suppression curves of four chips. The solid line in the figure is the out-of-band suppression curve when grounding holes are added, and the dashed line is the out-of-band suppression curve when no grounding holes are provided. Figure 14e is a comparison curve of the isolation between the second transmitting chip and the second receiving chip, and Figure 14f is a comparison curve of the isolation between the first transmitting chip and the first receiving chip. In the figure, the solid line is the isolation curve when the ground hole is added, and the dashed line It is the isolation curve when there is no grounding hole. It can be seen from Figures 14a-14f that when a ground hole is added to the quadruplexer, the signal leakage of passive components can be avoided, thereby further improving the out-of-band suppression and isolation of the quadruplexer.

The foregoing specific implementations do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that, depending on design requirements and other factors, various modifications, combinations, sub-combinations, and substitutions can occur. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

A semiconductor chip includes an upper wafer and a lower wafer, the bottom of the lower wafer is connected with a packaging substrate, and a sealing ring is arranged between the upper wafer and the lower wafer, and is characterized in that:

A sealing ring isolation layer is provided between the sealing ring and the lower wafer;

or,

The inner side and the outer side of the sealing ring are respectively provided with an inner sealing ring and an outer sealing ring, wherein the inner insulating layer of the sealing ring and the outer insulating layer of the sealing ring are connected by a conductor.
The semiconductor chip of claim 1, wherein the conductor is located between the sealing ring and the lower wafer.
The semiconductor chip according to claim 1, wherein the upper surface of the lower wafer is further provided with a resonator isolation layer, and the resonator isolation layer and the seal ring isolation layer or the inner isolation layer of the seal ring are an integrated structure;

In this integrated structure, a through hole is provided at a position opposite to the via hole in the lower wafer, and the docking pin between the upper wafer and the lower wafer is connected to the ground on the lower side of the lower wafer through the through hole Pin.
The semiconductor chip of claim 1, wherein at least one ground hole is provided in the lower wafer, a wire is provided in the ground hole, a resonator isolation layer, a seal ring isolation layer, an inner isolation layer of the seal ring, or a seal ring The outer isolation layer is connected to at least one ground pin through a wire in the ground hole.
The semiconductor chip of claim 3, wherein the package substrate comprises a plurality of superimposed upper wafers and lower wafers, and the plurality of superimposed upper wafers and lower wafers comprise a plurality of ground holes, wherein, The vertical projection of the multiple ground holes to the packaging substrate is located on the periphery of the passive device, which is located on the surface or inside of the packaging substrate, or on the underside of the lower wafer.
The semiconductor chip according to claim 3, 4 or 5, wherein the resonator is an acoustic wave resonator.
A multiplexer includes at least two sets of stacking units. The stacking unit includes an upper wafer, a middle wafer, and a lower wafer. The bottom of the lower wafer is connected to a packaging substrate. There are sealing rings between the lower wafers, which are characterized in that:

A sealing ring isolation layer is provided between the sealing ring and the middle wafer and/or between the sealing ring and the lower wafer;

or,

The inner and outer sides of the seal ring located in the middle wafer and/or the lower wafer are respectively provided with an inner seal ring isolation layer and an outer seal ring isolation layer, wherein the inner isolation layer of the seal ring and the outer isolation layer of the seal ring are connected by a conductor .
The multiplexer according to claim 1, wherein the conductor is located between the sealing ring and the middle wafer or the lower wafer where it is located.
The multiplexer according to claim 7, wherein the upper surface of the middle wafer and/or the lower wafer is further provided with a resonator isolation layer, the resonator isolation layer and the same layer of the seal ring isolation layer or seal ring The inner isolation layer is a one-piece structure;

In this integrated structure, a through hole is provided at a position opposite to the via hole in the lower wafer, and the docking pin between the upper wafer and the lower wafer is connected to the ground on the lower side of the lower wafer through the through hole Pin.
The multiplexer according to claim 7, wherein at least one ground hole is provided in the middle wafer and/or the lower wafer, a wire is provided in the ground hole, a resonator isolation layer, a sealing ring isolation layer, and The isolation layer inside the ring or the isolation layer outside the sealing ring is connected to at least one ground pin through a wire in the ground hole.
The multiplexer according to claim 10, wherein the plurality of superimposing units includes a plurality of ground holes, and the vertical projection of the plurality of ground holes to the package substrate is located on the periphery of the passive device in the package substrate, and the The source device is located on the surface or inside of the package substrate, or on the underside of the lower wafer.
The multiplexer according to claim 9, 10 or 11, wherein the resonator is an acoustic wave resonator.
The multiplexer according to claim 9, 10 or 11, wherein the multiplexer comprises a first receiving chip, a first sending chip, a second receiving chip, and a second sending chip;

The second sending chip and the first sending chip are superimposed to form a superimposing unit, and the second receiving chip and the first receiving chip are superimposed to form a superimposing unit,

or,

The second sending chip and the first receiving chip are superimposed to form a superimposing unit, and the first sending chip and the second receiving chip are superimposed to form a superimposing unit.
A communication device, characterized by comprising the multiplexer according to any one of claims 7 to 13.
A communication device, characterized by comprising the semiconductor chip according to any one of claims 1 to 6.