WO2021143519A1

WO2021143519A1 - Multiplexer

Info

Publication number: WO2021143519A1
Application number: PCT/CN2020/140939
Authority: WO
Inventors: 庞慰; 蔡华林
Original assignee: 诺思(天津)微系统有限责任公司
Priority date: 2020-01-16
Filing date: 2020-12-29
Publication date: 2021-07-22
Also published as: CN111245386A; CN111245386B

Abstract

A multiplexer, comprising at least two chip sets, wherein each chip set comprises two chips located in the same frequency band, which are a receiving chip and a transmitting chip, respectively; two chips of different frequency bands are superimposed so as to form a plurality of stacked structures; for an upper chip and a lower chip in each stacked structure, there is an defined interval between the two and vertical projections of the two have a staggered region (1); and a defined distance (2) is provided between adjacent stacked structures. Changing the chips from the original flat layout to the stacked layout may greatly reduce the plane area in terms of size, and by means of adjusting the chip thickness, may also enable the overall thickness to no longer increase in terms of thickness. Each chip of the multiplexer occupies a smaller area, thereby facilitating the miniaturization of products.

Description

A multiplexer

Technical field

The present invention relates to the technical field of filters, in particular to a multiplexer.

Background technique

With the acceleration of the trend of miniaturization and high performance of communication equipment, higher challenges are presented to the size and performance of the RF front-end. Due to the gradual increase in frequency bands, more filters occupy a larger terminal size, which is in line with miniaturization. The trend is contrary. In the radio frequency communication front-end, reducing the chip size is on the one hand to reduce the manufacturing size of the chip itself, and on the other hand to reduce the spacing of the package, but the reduction of the package spacing will bring a great test of the process and the impact of yield. Therefore, it is very important to reduce the manufacturing size of the chip itself.

In a traditional duplexer or multiplexer, there are multiple chips arranged in a plane, and the size that can be reduced is limited, and the smaller the chip spacing, the greater the mutual coupling, which will also seriously deteriorate the overall performance of the chip.

Summary of the invention

In view of this, the main purpose of the present invention is to provide a multiplexer that can reduce the size of the chip while ensuring the performance of the chip.

In order to achieve the above objective, according to one aspect of the present invention, a multiplexer is provided. The multiplexer includes at least two chipsets, and each chipset includes two chips in the same frequency band, which are a receiving chip and a chip. Transmitting chip; two chips of different frequency bands are superimposed and arranged to form a plurality of stacked structures; for the chip located above and the chip located below in each stacked structure, there is a defined interval between the two and the vertical projection of the two Staggered area; a defined distance is provided between adjacent stacked structures.

Optionally, the area of the staggered area is 0-100% compared with the area of any vertical projection.

Optionally, a first extension is provided in the lateral direction of the upper chip, a second extension is provided in the lateral direction of the lower chip, the vertical projection of the upper chip and the first extension and the lower chip and the second extension The vertical projections of the parts coincide.

Optionally, the first extension portion is provided with a signal line and/or a ground line; and/or, the second extension portion is provided with a signal line and/or a ground line.

Optionally, a packaging substrate is further included, and a plurality of chip sets are packaged by the packaging substrate.

Optionally, in each set of stacked structures, the chip located above includes a first wafer, and the first wafer is provided with a first resonator layout area including a plurality of resonators; the chip located below includes a second wafer, The second wafer is provided with a second resonator layout area including a plurality of resonators; the vertical projection of the first resonator layout area and the vertical projection of the second resonator layout area form a coincident area and a non-conforming area. Coincident area; the first resonator layout area is provided with a plurality of pins, and the vertical projection of the pins is located in the non-coincident area.

Optionally, the chip located above further includes a third wafer or thin layer used for packaging and packaging the first wafer; the chip located below further includes a fourth wafer used for packaging and packaging the second wafer.

Optionally, a metal isolation layer is provided between the third wafer or thin layer and the second wafer, and the metal isolation layer overlaps the overlapping area, and the metal isolation layer is connected to a ground pin.

Optionally, the thickness of the first wafer and the second wafer is 50 um to 200 um.

According to the technical solution of the present invention, the chip is changed from the original flat layout to the stacked layout, in terms of size, the plane area can be greatly reduced; and in terms of thickness, the thickness of the chip can also be adjusted to prevent the overall thickness from increasing. The area occupied by each chip of the multiplexer in the present invention is smaller, so it is beneficial to miniaturization of the product.

Description of the drawings

For purposes of illustration and not limitation, the present invention will now be described according to preferred embodiments of the present invention, particularly with reference to the accompanying drawings, in which:

Figure 1 Front view of the existing multiplexer packaging structure;

Figure 2 is a front view of a stacked structure of this embodiment;

Figure 3 is a front view of another stacked structure of this embodiment;

4 is a cross-sectional view of the stack structure of this embodiment;

Figure 5 is another cross-sectional view of the stack structure of this embodiment;

Figure 6 is a top view of the stack structure of this embodiment;

FIG. 7 is a schematic diagram of adding a metal isolation layer to the stacked structure of this embodiment;

FIG. 8 is a comparison diagram of the passband of B3TX in the stacked structure of this embodiment;

FIG. 9 is a comparison diagram of the passband of B3RX in the stacked structure of this embodiment;

FIG. 10 is a comparison diagram of the passband of B1TX in the stack structure of this embodiment;

FIG. 11 is a comparison diagram of the passband of B1RX in the stacked structure of this embodiment;

FIG. 12 is a comparison diagram of out-of-band suppression of B3TX in the stacked structure of this embodiment;

FIG. 13 is a comparison diagram of out-of-band suppression of B3RX in the stacked structure of this embodiment;

FIG. 14 is a comparison diagram of out-of-band suppression of B1TX in the stacked structure of this embodiment;

FIG. 15 is a comparison diagram of out-of-band suppression of B1RX in the stacked structure of this embodiment;

16 is a comparison diagram of isolation between B3TX and B3RX in the stacked structure of this embodiment;

FIG. 17 is a comparison diagram of isolation between B1TX and B1RX in the stacked structure of this embodiment.

In the above-mentioned comparison figures, the dashed line and the solid line overlap more.

In the picture:

1: Interleaved area; 2: Pitch; 3: Package substrate; 4: First wafer; 5: Second wafer; 6: Third wafer; 7: Fourth wafer; 8: First resonator layout area ; 9: second resonator layout area; 10: overlap area; 11: pin; 12: metal isolation layer.

Detailed ways

2 is a front view of a stack structure of this embodiment, FIG. 3 is a front view of another stack structure of this embodiment, in FIG. 2 and FIG. 3, the left diagonally shaded area is one of the adjacent stack structures There is a limited spacing 2 between them, and the vertical line shaded area is the staggered area 1. In the above figures, the quadruplexer is taken as an example. In the figure, B1RX and B1TX are a set of chips, and B3RX and B3TX are a set of chips.

As shown in Figures 2 and 3, compared with the traditional multiplexer, in terms of structure, the multiplexer provided in this embodiment includes at least two chip sets, and each chip set includes two chips located in the same frequency band. The chips are the receiving chip and the transmitting chip; two chips of different frequency bands are superimposed to form multiple stacked structures; for each stacked structure, the chip located above and the chip located below have a defined interval between the two And the vertical projection of the two has a staggered area 1; a defined distance 2 is provided between adjacent stacked structures.

In the stacked structure, the chips are stacked in pairs, in which, in order to prevent deterioration of isolation, avoid stacking of receiving chips and sending chips in the same group. In the superimposed structure, with the viewing angle directions in Figs. 2 and 3, the chips can be superimposed in the height direction or in the length direction. Among them, the area of the staggered area 1 is 0-100% compared with the area of any vertical projection. In the figure, the vertical shaded area is indicated as staggered area 1. The minimum area of the staggered area 1 is 0, that is, the original distance between the two chips is reduced when superimposed, and the vertical projections of the two chips are aligned, and the maximum is 100%, that is, the two chips are completely superimposed directly above and below.

In this embodiment, when the area ratio of the staggered area 1 is greater than 0 and less than 100%; the chip located above is provided with a first extension in the lateral direction, the chip located below is provided with a second extension in the lateral direction, and the chip located above is provided with a second extension in the lateral direction. And the vertical projection of the first extension part coincides with the vertical projection of the chip below and the second extension part. In the above structure, the upper and lower chips are arranged staggered. In order to prevent the upper chip from being partially suspended, a second extension is provided below it; at the same time, a first extension is provided on the upper chip so that the upper and lower chips are included. The size of the chip is the same. The first extension portion and the second extension portion may have a wafer structure, the wafer of the first extension portion is integrated with the wafer of the upper chip, and the wafer of the second extension portion is integrated with the wafer of the lower chip. These two extensions can be equipped with signal lines, ground lines and other lines, which means that the area available for wiring in the chip is increased, which helps to avoid sensitive traces, prevents the performance of the device from deteriorating, and helps increase Take the number of lines to reduce parasitic inductance.

4 and 5 are cross-sectional views of the stack structure of this embodiment. Compared with FIG. 4, FIG. 5 has a layer of wafer removed, and the upper chip is sealed by covering a layer of film-like structure or by other sealing materials. In this embodiment, the chip located above further includes a third wafer 6 or a thin layer for packaging and packaging the first wafer 4; the chip located below also includes a fourth wafer 6 or thin layer for packaging and packaging the second wafer 5. Wafer 7. As shown in FIG. 4, the stacked chip has a four-layer structure composed of the first wafer 4, the second wafer 5, the third wafer 6 and the fourth wafer 7, or, as shown in FIG. 5, the first wafer A three-layer structure consisting of a wafer 4, a second wafer 5 and a fourth wafer 7 (thin layers are not shown). Among them, the three-dimensional stacking method is used to effectively reduce the plane area of the multiplexer, but the thickness of the overall structure will increase. In this embodiment, the overall thickness is reduced by reducing the thickness of the wafer. Preferably, the thickness of the wafer is 50 um to 200 um.

In this embodiment, as shown in FIG. 2 and FIG. 3, the multiplexer further includes a packaging substrate 3, and multiple chip sets are packaged by the packaging substrate 3. The packaging structure includes a plurality of stacked structures, adjacent stacked structures have a defined spacing 2 between them, and the packaging substrate 3 wraps the chip set into an integral structure.

In the above structure, the chip adopts the form of three-dimensional stacking to reduce the plane size, but there may be greater coupling. Therefore, further reasonable layout is required to improve isolation, reduce coupling, and avoid performance degradation. As shown in FIG. 6, in each stack structure of this embodiment, the chip located above includes a first wafer 4, and the first wafer 4 is provided with a first resonator layout area 8 including a plurality of resonators; The chip includes a second wafer 5 on which is provided a second resonator layout area 9 containing multiple resonators; a vertical projection of the first resonator layout area 8 and a second resonator layout area 9 The vertical projection of φ forms a coincident area 10 and a non-coincident area; a plurality of pins 11 are provided in the first resonator layout area 8, and the vertical projection of the pins 11 is located in the non-coincident area. Among them, in FIG. 6, GND_TX, ANT_TX and TX are pins located on the second resonator layout area 9.

Among them, pin 11 includes input pins, output pins, isolation pins, ground pins, etc. If it is necessary to effectively isolate the chip located above and the chip located below, avoiding/reducing performance degradation, structural aspects The pins 11 need to be arranged in the non-coincident area, and the pins 11 are all located in the layout plane parallel to the resonator (that is, the plane where the screen or paper is located) or in the horizontal direction away from the second resonator layout area 9, and, When the pin 11 is routed, it will not pass through the second resonator layout area 9. This structure realizes the "horizontal isolation" between the upper chip and the lower chip. Through the isolation structure, the coupling can be reduced. Thereby reducing the deterioration of product performance. Among them, for horizontal isolation, the farther the pin 11 is from the second resonator layout area 9, the better the isolation effect.

In this embodiment, a metal isolation layer 12 is provided between the third wafer 6 or the thin layer and the second wafer 5. When the stacking mechanism is four layers, the metal isolation layer 12 is provided on the third wafer as shown in FIG. Between the circle 6 and the second wafer 5, when the stack structure is three layers, the metal isolation layer 12 is provided between the thin layer and the second wafer 5. The thin layer is not shown in FIG. The isolation layer 12 is disposed on the second wafer 5, that is, the position indicated by the arrow in FIG. 7. The metal isolation layer 12 overlaps with the overlapping area 10, and the metal isolation layer 12 is connected to a ground pin, that is, the GND_TX in the overlapping area in FIG. 6. The metal isolation layer 12 needs to be grounded, which can isolate the upper chip from the lower chip; wherein, the larger the area of the metal isolation layer 12, the better the isolation. The metal isolation layer 12 is separating the first wafer 4 from the first wafer 4 and the second wafer. The resonator on the second wafer 5 can be increased as much as possible. If the area is the same as the area of the first wafer 4, if the extension is included, it will be the same as the total area of the first wafer 4 and the extension. The same, where the metal isolation layer 12 is hollowed out at positions corresponding to the signal connection line and the ground connection line, so that the line can pass through normally. Among them, the metal isolation layer 12 may be a planar metal layer, a grid-like metal layer, etc., and the metal isolation layer 12 of different structures should fall within the protection scope of this patent. The metal isolation layer 12 can achieve "longitudinal isolation" and be isolated from "horizontal isolation", which can further improve the isolation of the chip.

In this embodiment, the coupling is reduced by combining the above-mentioned "horizontal isolation" and "vertical isolation". Compared with the traditional structure, the performance of the multiplexer is not deteriorated. As shown in FIG. 8, it is a comparison diagram of the passband of B3TX, where the solid line is the insertion loss of the solution of the embodiment, and the dashed line is the insertion loss of the traditional structure. Figure 9 is a comparison diagram of the passband of B3RX, the solid line is the insertion loss of the solution of this embodiment, and the dashed line is the insertion loss of the traditional structure; Figure 10 is the comparison diagram of the passband of B1TX, and the solid line is the insertion loss of the solution of this embodiment. The dashed line is the insertion loss of the traditional structure. FIG. 11 is a comparison diagram of the passband of the B1RX. The solid line is the insertion loss of the solution of the embodiment, and the dashed line is the insertion loss of the traditional structure.

Figure 12 is a comparison diagram of out-of-band suppression of B3TX. The solid line in the figure is the insertion loss of the solution of this embodiment, and the dashed line is the insertion loss of the traditional structure. Figure 13 is a comparison diagram of the out-of-band suppression of B3RX. In the figure, the solid line is the insertion loss. For the insertion loss of the embodiment scheme, the dashed line is the insertion loss of the traditional structure; Figure 14 is a comparison diagram of the out-of-band suppression of B1TX, in the figure, the solid line is the insertion loss of the embodiment scheme, and the dashed line is the insertion loss of the traditional structure, Figure 15 It is a comparison diagram of out-of-band suppression of B1RX. In the figure, the solid line is the insertion loss of the solution of the embodiment, and the dashed line is the insertion loss of the traditional structure.

Figure 16 is a comparison diagram of isolation between B3TX and B3RX. The solid line in the figure is the insertion loss of the solution of this embodiment, and the dashed line is the insertion loss of the traditional structure. Figure 17 is the comparison diagram of the isolation between B1TX and B1RX. The solid line in the figure is For the insertion loss of the solution of this embodiment, the dashed line is the insertion loss of the traditional structure.

As shown in FIG. 8 to FIG. 17, the performance of the multiplexer in this embodiment is basically the same as that of the conventional structure, and therefore, there is no deterioration or significant deterioration in performance. In the case of realizing the stacking and shrinking structure, the performance of the multiplexer is maintained. Therefore, it is beneficial to reduce the size of the product, and the overall development is towards miniaturization.

The foregoing specific implementations do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that, depending on design requirements and other factors, various modifications, combinations, sub-combinations, and substitutions can occur. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

A multiplexer, characterized in that,

The multiplexer includes at least two chip sets, and each chip set includes two chips located in the same frequency band, which are a receiving chip and a transmitting chip, respectively;

Two chips of different frequency bands are superimposed to form multiple stacked structures;

For the chip located above and the chip located below each stacked structure, there is a defined interval between them and the vertical projection of the two has a staggered area (1);

A defined distance (2) is provided between adjacent stacked structures.
The multiplexer according to claim 1, wherein the area of the staggered area (1) is 0-100% compared with the area of any one of the vertical projections.
The multiplexer according to claim 2, wherein:

The chip located above is provided with a first extension in the lateral direction, and the chip located at the lower is provided with a second extension in the lateral direction. The vertical projection of the upper chip and the first extension and the vertical projection of the lower chip and the second extension are vertical. The projections coincide.
The multiplexer according to claim 3, wherein:

The first extension part is provided with a signal line and/or a ground line; and/or,

The second extension part is provided with a signal line and/or a ground line.
The multiplexer according to claim 1, further comprising a packaging substrate (3), and a plurality of chip sets are packaged by the packaging substrate (3).
The multiplexer according to claim 1, characterized in that, in each stack structure, the chip located above comprises a first wafer (4), and the first wafer (4) is provided with a plurality of resonators The first resonator layout area (8);

The chip located below includes a second wafer (5), and a second resonator layout area (9) containing a plurality of resonators is provided on the second wafer (5);

The vertical projection of the first resonator layout area (8) and the vertical projection of the second resonator layout area (9) form an overlapping area (10) and a non-overlapping area; the first resonator layout area (8) A plurality of pins (11) are arranged inside, and the vertical projection of the pins (11) is located in the non-coincident area.
The multiplexer according to claim 6, characterized in that the chip located above further comprises a third wafer (6) or a thin layer for encapsulating and packaging the first wafer (4);

The chip located below also includes a fourth wafer (7) for encapsulating and packaging the second wafer (5).
The multiplexer according to claim 7, wherein a metal isolation layer (12) is provided between the third wafer (6) or thin layer and the second wafer (5), and the metal isolation layer (12) It overlaps with the overlap area (10), and the metal isolation layer (12) is connected to the ground pin.
The multiplexer according to claim 6, characterized in that the thickness of the first wafer (4) and the second wafer (5) is 50um-200um.