WO2021073257A1

WO2021073257A1 - Multiplexer

Info

Publication number: WO2021073257A1
Application number: PCT/CN2020/111346
Authority: WO
Inventors: 庞慰; 蔡华林
Original assignee: 天津大学; 诺思(天津)微系统有限责任公司
Priority date: 2019-10-18
Filing date: 2020-08-26
Publication date: 2021-04-22
Also published as: CN110828441A

Abstract

The present invention relates to the technical field of communication devices, and in particular to a multiplexer, comprising a first chip and a second chip, the first chip and the second chip being provided in a stacked manner. The first chip comprises a first wafer and a second wafer, and the first wafer is provided with a first resonator layout area containing a plurality of resonators. The second chip comprises a third wafer and a fourth wafer, and the third wafer is provided with a second resonator layout area containing a plurality of resonators. In the technical solution of the present invention, the size of the chip is further reduced compared with that in the prior art, thereby facilitating the miniaturization of the multiplexer.

Description

A multiplexer

Technical field

The present invention relates to the technical field of communication equipment, in particular to a multiplexer.

Background technique

With the acceleration of the miniaturization and high-performance trend of communication equipment, higher challenges are presented to the size and performance of the RF front-end. Due to the gradual increase in frequency bands, more filters occupy a larger terminal size, which is in line with miniaturization. The trend is contrary.

In the radio frequency communication front-end, reducing the chip size is on the one hand to reduce the manufacturing size of the chip itself, and on the other hand to reduce the package spacing, but the reduction of the package spacing will bring great challenges to the process and the impact of yield. Therefore, it is very important to reduce the manufacturing size of the chip itself. In a traditional duplexer or multiplexer, multiple chips are arranged in a plane, and the size that can be reduced is limited, and the smaller the chip spacing, the greater the coupling between each other, which will also seriously deteriorate the overall performance of the chip.

Summary of the invention

In view of this, the main purpose of the present invention is to provide a multiplexer that helps reduce the plane area occupied by the chip.

In order to achieve the above objective, according to one aspect of the present invention, a multiplexer is provided, which includes a first chip and a second chip that are superimposed; the first chip includes a first wafer and is used for packaging the first chip. The second wafer of the wafer, the first wafer is provided with a first resonator layout area including a plurality of resonators; the second chip includes a third wafer and is used for packaging the third wafer The fourth wafer is provided with a second resonator layout area including a plurality of resonators on the third wafer.

Optionally, the second wafer is adjacently arranged on the third wafer, and the vertical projection of the first resonator layout area and the vertical projection of the second resonator layout area form an overlapping area And a non-coincident area, a plurality of first pins are arranged in the first resonator layout area, and the vertical projection of the first pins is located in the non-coincident area.

Optionally, the thickness of the first wafer, the second wafer, the third wafer, and the fourth wafer is 50 um to 200 um.

Optionally, a metal isolation layer is provided between the second wafer and the third wafer, the metal isolation layer overlaps the overlapping area, and the metal isolation layer is connected to a ground pin.

Optionally, the vertical projections of the metal isolation layer and the overlapping area coincide.

Optionally, a capacitor and/or an inductor are integratedly arranged on the first wafer outside the first resonator layout area; and/or the third wafer is located on the second resonator layout area A capacitor and/or inductor are integrated externally.

Optionally, the dielectric constant of the second wafer and the third wafer is smaller than the dielectric constant of the first wafer and the fourth wafer.

Optionally, the third wafer is composed of the second resonator layout area and a non-resonator layout area; the vertical projections of a plurality of the first pins fall in the non-resonator layout area.

Optionally, the first resonator layout area is covered with the first wafer.

Optionally, the first pin includes a plurality of ground pins.

According to the technical scheme of the present invention, the first chip and the second chip that were originally arranged side by side are changed to a superimposed arrangement, which reduces the area occupied on the plane in structure, and the height can be restricted by reducing the thickness of the wafer; the present invention Compared with the prior art, the chip size in the technical solution is further reduced, which is conducive to the miniaturization of the multiplexer.

Description of the drawings

For the purpose of illustration and not limitation, the present invention will now be described according to preferred embodiments of the present invention, particularly with reference to the accompanying drawings, in which:

Figure 1 shows a cross-sectional view of the first chip and the second chip of the multiplexer superimposed;

FIG. 2 shows a top view of the first chip and the second chip of the multiplexer after being superimposed;

Figure 3 shows a top view of another superimposed structure of the first chip and the second chip of the multiplexer;

Figure 4 shows a top view of another superimposed structure of the first chip and the second chip of the multiplexer;

Figure 5 shows a top view of adding a metal isolation layer;

Figure 6 shows a comparison diagram of isolation;

Figure 7 shows a comparison diagram of isolation after adding horizontal isolation;

Figure 8 shows a comparison diagram of isolation after adding horizontal isolation and longitudinal isolation;

Figure 9 shows a front view of the integrated capacitor;

Figure 10 shows a front view of the integrated inductor;

FIG. 11 shows a cross-sectional view of the first chip and the second chip of the multiplexer with arrows pointing;

Figure 12 shows a schematic diagram of isolation improvement;

Figure 13 shows a top view of the resonators arranged in the vacant part;

Figure 14 shows a top view of adding an additional fourth ground pin;

Figure 15 shows a schematic diagram of the relationship between inductance value and roll-off;

Figure 16 shows a schematic diagram of the relationship between inductance and out-of-band suppression.

In the picture:

1: first wafer; 2: second wafer; 3: third wafer; 4: fourth wafer; 5: metal isolation layer; 11: first resonator layout area; 12: first pin; 13: integrated capacitor; 14: integrated inductor; 31: second resonator layout area; 32: second pin.

Detailed ways

1-16, an embodiment of the present invention provides a multiplexer, including a first chip and a second chip that are superimposed; the first chip includes a first wafer 1 and a package for packaging the first wafer 1. The second wafer 2, the first wafer 1 is provided with a first resonator layout area 11 containing multiple resonators; the second chip includes a third wafer 3 and a fourth wafer for packaging the third wafer 3 Circle 4, the third wafer 3 is provided with a second resonator layout area 31 containing multiple resonators. The first chip is a receiving chip or a sending chip, and the corresponding second chip is a sending chip or a receiving chip.

In the embodiment of the present invention, the structural improvement of the multiplexer is to change the first chip and the second chip arranged side by side in the horizontal direction to a vertical superimposed arrangement. Among them, the superposition setting will inevitably lead to a reduction in the area occupied by the product and an increase in the height (as shown in Figure 1). In response to the increase in height, the thickness of the first wafer 1, the second wafer 2, the third wafer 3, and the fourth wafer 4 are changed (thinner wafers are selected) to control the overall thickness of the product so that In the case of stacking, it can also maintain the same height as the original multiplexer. Preferably, the wafer can be polished to reduce its thickness, such as the first wafer 1, the second wafer 2, and the third wafer. The thickness of the wafer 3 and the fourth wafer 4 after polishing is 50um-200um. This structure can ensure that the overall volume of the product is reduced; theoretically, the stacking method can reduce the area by 50%. However, considering the connection relationship between the chips and the different areas of multiple chips, the actual stacking After setting, the area cannot be reduced by 50%, but generally around 30%-40%.

In the technical solution disclosed in the embodiment of the present invention, the superposition of the first chip and the second chip may cause greater coupling and deteriorate product performance. Therefore, product performance can be further optimized by changing the structure and improving isolation.

In the technical solution of this embodiment, the second wafer 2 is adjacently arranged on the third wafer 3, and the vertical projection of the first resonator layout area 11 and the vertical projection of the second resonator layout area 31 form an overlapping area and Non-coincident area; the first resonator layout area is provided with a plurality of first pins 12, and the second resonator layout area 31 is provided with a plurality of second pins 32; wherein, the first pin 12 and the second tube Pin 32 includes input pins, output pins, isolation pins, ground pins, and so on. The vertical projections of the plurality of first pins 12 are located in the non-coincident area. If you need to effectively isolate the first chip and the second chip to avoid/reduce performance degradation, the first pin 12 needs to be arranged in a non-coincident area in terms of structure, and the first pin 12 is parallel to the resonator. The layout plane (that is, the plane where the screen or paper is located) or the horizontal direction is far away from the second resonator layout area 31, and the first pin 12 does not pass through the second resonator layout area when the wiring is set 31. This structural form realizes the "horizontal isolation" between the first chip and the second chip. Through this isolation structure, the coupling can be reduced, thereby reducing product performance degradation. For horizontal isolation, the farther the first pin 12 is from the second resonator layout area 31, the better the isolation effect.

In the first chip, in addition to the first pin 12, other auxiliary structures are provided on the first resonator layout area 11, such as multiple metal layers, vertical metal pillars, etc., in order to improve isolation and avoid/reduce The performance deteriorates, and the vertical projection of the auxiliary structure is also set in the non-coincident area.

In the embodiment of the present invention, the isolation structure can also be provided with "longitudinal isolation", that is, the vertical direction in the viewing angle of FIG. 1. Specifically, a metal isolation layer 5 may be provided between the second wafer 2 and the third wafer 3. The isolation layer 5 overlaps with the overlapping area of the first resonator layout area 11 and the second resonator layout area 31, and the metal isolation layer 5 is connected to the ground pin. The metal isolation layer 5 needs to be grounded, which can isolate the first chip and the second chip; wherein, the larger the area of the metal isolation layer 5, the better the isolation. Preferably, the vertical projection of the metal isolation layer 5 and the overlapping area Coincide. Among them, the metal isolation layer 4 may be a planar metal layer, a grid-like metal layer, and other layer structures that have an isolation effect.

As shown in FIG. 2, a top view of the first chip and the second chip of the multiplexer after being superimposed is shown. The second wafer 2 and the fourth wafer 4 are not shown in the figure, and the rectangle acfh represents the first wafer 1. And the overall outline of the third wafer 3; rectangle bcfg represents the first resonator layout area 11; rectangle jdei represents the second resonator layout area 31, rectangle kdel represents the overlap area, rectangle bcdk and rectangle lefg represent the first wafer 1 The rectangle jkli represents the non-overlapping area on the third wafer 3. It can be seen from FIG. 2 that the first pin 12 on the first wafer 1 is located away from the second resonator layout area 31. Wherein, Figure 2 is only one of the superimposing forms. The superimposing forms in this embodiment also include but are not limited to the following forms. As shown in Figure 3, the overlapping area is on the left, or, as shown in Figure 4, the overlapping The area is in the middle. As shown in Figure 5, the figure is a schematic diagram of the structure when the metal isolation layer 5 is provided, that is, the area surrounded by the thick black solid line in the figure. The larger the area of the area, the better the isolation effect.

As shown in Figure 6, the figure is a comparison diagram of isolation, where the dotted line is the isolation of the side-by-side structure, the solid line is the isolation of the stacked structure, and the solid line is the curve without horizontal and vertical isolation. It can be seen that the left side deteriorates by about 5dB, and the right side deteriorates by more than 10dB. As shown in FIG. 7, the graph is a curve of the horizontal isolation after adding the horizontal isolation to the stacked structure, but the longitudinal isolation is not added. It can be seen that the deterioration degree has a certain improvement compared with the curve in FIG. 5. As shown in Figure 8, in the stacked structure, horizontal isolation and vertical isolation are added at the same time, the left side is improved by about 3dB, and the right side is improved by more than 10dB.

In a preferred implementation of this embodiment, a capacitor and/or inductor are integrated on the first wafer 1 located outside the first resonator layout area 11; and/or the third wafer 3 is located at the second resonator layout area 31 A capacitor and/or inductor are integrated externally. As shown in FIG. 9, the capacitor 13 is integrated in the area outside the first resonator layout area 11 on the first wafer 1. The capacitor can be the finger capacitor or the plate capacitor or other types of capacitors in the above figure; as shown in FIG. The inductor 14 is integrated on the first wafer 1 outside the first resonator layout area 11. The integrated capacitor 13 and the inductor 14 can eliminate the matching components. On the one hand, the reduction of the matching components can reduce the number of layers of the substrate and reduce the chip thickness and substrate cost. On the other hand, the reduction of off-chip passive components can reduce the size of the entire RF front-end And cost. At the same time, the integrated inductor or capacitor can improve the roll-off, increase the bandwidth, increase the out-of-band transmission zero point and improve the suppression at a specific frequency.

As shown in FIG. 11, the figure is a cross-sectional view of the first chip and the second chip of the multiplexer after being superimposed. The arrows in the figure point to the second wafer 2 and the third wafer 3. In the prior art, a silicon substrate is used. Due to the large dielectric constant of the silicon substrate, the upper and lower two pass through the high dielectric constant medium, and the coupling capacitance is large, so it has a certain impact on the performance of the duplexer. In order to improve this part to improve the isolation, The materials of the second wafer 2 and the third wafer 3 can be replaced, that is, the dielectric constant of the second wafer 2 and the third wafer 3 is smaller than the dielectric constant of the first wafer 1 and the fourth wafer 4. The second wafer 2 and the third wafer 3 are changed to low-dielectric constant materials, which can reduce coupling. As shown in Figure 12, the isolation is improved after the use of low dielectric constant materials. The solid line is the improved curve, and the improvement range is about 2-3dB.

In the preferred embodiment of the present invention, the areas of the first wafer 1 and the third wafer 3 can be further utilized to a greater extent. For the first wafer 1, the first resonator layout area 11 is covered with the first crystal. Circle 1; for the third wafer 3, as shown in FIG. 13, the third wafer 3 is composed of the second resonator layout area 31 and the non-resonator layout area; the vertical projection of the first pin 12 falls on the non-resonator layout area. Resonator layout area. In this structure, all the vacant areas of the first wafer 1 and the third wafer 3 are used for arranging resonators, and the area utilization is high, so that the area of the wafer can be further reduced.

In a preferred implementation manner of the embodiment of the present invention, the first pin 12 includes a plurality of ground pins. In the stacked structure, the first chip is located at the top end, and the grounding traces need to pass through the second wafer 2, the third wafer 3, and the fourth wafer 4. For the first wafer 1, the parasitic inductance will increase. There is a certain deterioration in the roll-off, and the transmission zero point of the out-of-band suppression will move, and the high-frequency suppression will deteriorate. Therefore, as shown in Figure 14, additional ground pins are added to reduce inductance to improve roll-off and far-band suppression.

As shown in Figure 15, the solid line is the roll-off when the inductance is small, and the dashed line is the roll-off when the inductance is large. It can be seen from the figure that the smaller the inductance, the better the roll-off. As shown in Figure 16, the solid line is the out-of-band suppression when the inductance is small, and the dashed line is the out-of-band suppression when the inductance is large. From this figure, it can be seen that the smaller the inductance, the better the far-band suppression.

The foregoing specific implementations do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that, depending on design requirements and other factors, various modifications, combinations, sub-combinations, and substitutions can occur. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

A multiplexer, characterized in that it comprises a first chip and a second chip that are superimposed;

The first chip includes a first wafer (1) and a second wafer (2) for packaging the first wafer (1), and the first wafer (1) is provided with a plurality of The first resonator layout area (11) of the resonator;

The second chip includes a third wafer (3) and a fourth wafer (4) for packaging the third wafer (3), and the third wafer (3) is provided with a plurality of The second resonator layout area of the resonator (31).
The multiplexer according to claim 1, wherein the second wafer (2) is adjacently arranged on the third wafer (3), and the first resonator layout area ( The vertical projection of 11) and the vertical projection of the second resonator layout area (31) form an overlapping area and a non-overlapping area;

A plurality of first pins (12) are provided in the first resonator layout area (11), and the vertical projection of the first pins (12) is located in the non-coincident area.
The multiplexer according to claim 1, wherein the first wafer (1), the second wafer (2), the third wafer (3) and the fourth wafer The thickness of the circle (4) is 50um～200um.
The multiplexer according to claim 1 or 2, wherein a metal isolation layer (5) is provided between the second wafer (2) and the third wafer (3), and the metal The isolation layer (5) overlaps the overlap area, and the metal isolation layer (5) is connected to a ground pin.
The multiplexer according to claim 4, characterized in that the vertical projection of the metal isolation layer (5) and the overlapping area coincide.
The multiplexer according to claim 1, wherein:

A capacitor (13) and/or an inductor (14) are integratedly arranged on the first wafer (1) outside the first resonator layout area (11);

And/or

A capacitor (13) and/or an inductor (14) are integratedly arranged on the third wafer (3) outside the second resonator layout area (31).
The multiplexer according to claim 1, wherein the dielectric constant of the second wafer (2) and the third wafer (3) is smaller than that of the first wafer (1) and the The dielectric constant of the fourth wafer (4) is described.
The multiplexer according to claim 2, wherein:

The third wafer (3) is composed of the second resonator layout area (31) and a non-resonator layout area;

The vertical projections of the plurality of first pins (12) fall within the non-resonator layout area.
The multiplexer according to claim 1 or 8, wherein the first resonator layout area (11) is filled with the first wafer (1).
The multiplexer according to claim 1, wherein the first pin (12) includes a plurality of ground pins.