WO2021143519A1 - Multiplexeur - Google Patents

Multiplexeur Download PDF

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Publication number
WO2021143519A1
WO2021143519A1 PCT/CN2020/140939 CN2020140939W WO2021143519A1 WO 2021143519 A1 WO2021143519 A1 WO 2021143519A1 CN 2020140939 W CN2020140939 W CN 2020140939W WO 2021143519 A1 WO2021143519 A1 WO 2021143519A1
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WO
WIPO (PCT)
Prior art keywords
chip
wafer
area
multiplexer
extension
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Application number
PCT/CN2020/140939
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English (en)
Chinese (zh)
Inventor
庞慰
蔡华林
Original Assignee
诺思(天津)微系统有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 诺思(天津)微系统有限责任公司 filed Critical 诺思(天津)微系统有限责任公司
Publication of WO2021143519A1 publication Critical patent/WO2021143519A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/70—Multiple-port networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source

Definitions

  • the present invention relates to the technical field of filters, in particular to a multiplexer.
  • the main purpose of the present invention is to provide a multiplexer that can reduce the size of the chip while ensuring the performance of the chip.
  • a multiplexer includes at least two chipsets, and each chipset includes two chips in the same frequency band, which are a receiving chip and a chip. Transmitting chip; two chips of different frequency bands are superimposed and arranged to form a plurality of stacked structures; for the chip located above and the chip located below in each stacked structure, there is a defined interval between the two and the vertical projection of the two Staggered area; a defined distance is provided between adjacent stacked structures.
  • the area of the staggered area is 0-100% compared with the area of any vertical projection.
  • a first extension is provided in the lateral direction of the upper chip
  • a second extension is provided in the lateral direction of the lower chip
  • the vertical projection of the upper chip and the first extension and the lower chip and the second extension coincide.
  • the first extension portion is provided with a signal line and/or a ground line; and/or, the second extension portion is provided with a signal line and/or a ground line.
  • a packaging substrate is further included, and a plurality of chip sets are packaged by the packaging substrate.
  • the chip located above includes a first wafer, and the first wafer is provided with a first resonator layout area including a plurality of resonators; the chip located below includes a second wafer, The second wafer is provided with a second resonator layout area including a plurality of resonators; the vertical projection of the first resonator layout area and the vertical projection of the second resonator layout area form a coincident area and a non-conforming area.
  • the first resonator layout area is provided with a plurality of pins, and the vertical projection of the pins is located in the non-coincident area.
  • the chip located above further includes a third wafer or thin layer used for packaging and packaging the first wafer; the chip located below further includes a fourth wafer used for packaging and packaging the second wafer.
  • a metal isolation layer is provided between the third wafer or thin layer and the second wafer, and the metal isolation layer overlaps the overlapping area, and the metal isolation layer is connected to a ground pin.
  • the thickness of the first wafer and the second wafer is 50 um to 200 um.
  • the chip is changed from the original flat layout to the stacked layout, in terms of size, the plane area can be greatly reduced; and in terms of thickness, the thickness of the chip can also be adjusted to prevent the overall thickness from increasing.
  • the area occupied by each chip of the multiplexer in the present invention is smaller, so it is beneficial to miniaturization of the product.
  • FIG. 1 Front view of the existing multiplexer packaging structure
  • Figure 2 is a front view of a stacked structure of this embodiment
  • Figure 3 is a front view of another stacked structure of this embodiment.
  • Figure 5 is another cross-sectional view of the stack structure of this embodiment.
  • Figure 6 is a top view of the stack structure of this embodiment.
  • FIG. 7 is a schematic diagram of adding a metal isolation layer to the stacked structure of this embodiment.
  • FIG. 8 is a comparison diagram of the passband of B3TX in the stacked structure of this embodiment.
  • FIG. 9 is a comparison diagram of the passband of B3RX in the stacked structure of this embodiment.
  • FIG. 10 is a comparison diagram of the passband of B1TX in the stack structure of this embodiment.
  • FIG. 11 is a comparison diagram of the passband of B1RX in the stacked structure of this embodiment.
  • FIG. 12 is a comparison diagram of out-of-band suppression of B3TX in the stacked structure of this embodiment.
  • FIG. 13 is a comparison diagram of out-of-band suppression of B3RX in the stacked structure of this embodiment.
  • FIG. 14 is a comparison diagram of out-of-band suppression of B1TX in the stacked structure of this embodiment.
  • FIG. 15 is a comparison diagram of out-of-band suppression of B1RX in the stacked structure of this embodiment.
  • 16 is a comparison diagram of isolation between B3TX and B3RX in the stacked structure of this embodiment
  • FIG. 17 is a comparison diagram of isolation between B1TX and B1RX in the stacked structure of this embodiment.
  • FIG. 2 is a front view of a stack structure of this embodiment
  • FIG. 3 is a front view of another stack structure of this embodiment
  • the left diagonally shaded area is one of the adjacent stack structures There is a limited spacing 2 between them
  • the vertical line shaded area is the staggered area 1.
  • the quadruplexer is taken as an example.
  • B1RX and B1TX are a set of chips
  • B3RX and B3TX are a set of chips.
  • the multiplexer provided in this embodiment includes at least two chip sets, and each chip set includes two chips located in the same frequency band.
  • the chips are the receiving chip and the transmitting chip; two chips of different frequency bands are superimposed to form multiple stacked structures; for each stacked structure, the chip located above and the chip located below have a defined interval between the two And the vertical projection of the two has a staggered area 1; a defined distance 2 is provided between adjacent stacked structures.
  • the chips are stacked in pairs, in which, in order to prevent deterioration of isolation, avoid stacking of receiving chips and sending chips in the same group.
  • the chips can be superimposed in the height direction or in the length direction.
  • the area of the staggered area 1 is 0-100% compared with the area of any vertical projection.
  • the vertical shaded area is indicated as staggered area 1.
  • the minimum area of the staggered area 1 is 0, that is, the original distance between the two chips is reduced when superimposed, and the vertical projections of the two chips are aligned, and the maximum is 100%, that is, the two chips are completely superimposed directly above and below.
  • the chip located above is provided with a first extension in the lateral direction
  • the chip located below is provided with a second extension in the lateral direction
  • the chip located above is provided with a second extension in the lateral direction.
  • the vertical projection of the first extension part coincides with the vertical projection of the chip below and the second extension part.
  • the upper and lower chips are arranged staggered. In order to prevent the upper chip from being partially suspended, a second extension is provided below it; at the same time, a first extension is provided on the upper chip so that the upper and lower chips are included. The size of the chip is the same.
  • the first extension portion and the second extension portion may have a wafer structure, the wafer of the first extension portion is integrated with the wafer of the upper chip, and the wafer of the second extension portion is integrated with the wafer of the lower chip.
  • These two extensions can be equipped with signal lines, ground lines and other lines, which means that the area available for wiring in the chip is increased, which helps to avoid sensitive traces, prevents the performance of the device from deteriorating, and helps increase Take the number of lines to reduce parasitic inductance.
  • FIG. 4 and 5 are cross-sectional views of the stack structure of this embodiment.
  • FIG. 5 has a layer of wafer removed, and the upper chip is sealed by covering a layer of film-like structure or by other sealing materials.
  • the chip located above further includes a third wafer 6 or a thin layer for packaging and packaging the first wafer 4; the chip located below also includes a fourth wafer 6 or thin layer for packaging and packaging the second wafer 5.
  • Wafer 7. As shown in FIG. 4, the stacked chip has a four-layer structure composed of the first wafer 4, the second wafer 5, the third wafer 6 and the fourth wafer 7, or, as shown in FIG.
  • the first wafer A three-layer structure consisting of a wafer 4, a second wafer 5 and a fourth wafer 7 (thin layers are not shown).
  • the three-dimensional stacking method is used to effectively reduce the plane area of the multiplexer, but the thickness of the overall structure will increase.
  • the overall thickness is reduced by reducing the thickness of the wafer.
  • the thickness of the wafer is 50 um to 200 um.
  • the multiplexer further includes a packaging substrate 3, and multiple chip sets are packaged by the packaging substrate 3.
  • the packaging structure includes a plurality of stacked structures, adjacent stacked structures have a defined spacing 2 between them, and the packaging substrate 3 wraps the chip set into an integral structure.
  • the chip located above includes a first wafer 4, and the first wafer 4 is provided with a first resonator layout area 8 including a plurality of resonators;
  • the chip includes a second wafer 5 on which is provided a second resonator layout area 9 containing multiple resonators; a vertical projection of the first resonator layout area 8 and a second resonator layout area 9
  • the vertical projection of ⁇ forms a coincident area 10 and a non-coincident area; a plurality of pins 11 are provided in the first resonator layout area 8, and the vertical projection of the pins 11 is located in the non-coincident area.
  • GND_TX, ANT_TX and TX are pins located on
  • pin 11 includes input pins, output pins, isolation pins, ground pins, etc. If it is necessary to effectively isolate the chip located above and the chip located below, avoiding/reducing performance degradation, structural aspects
  • the pins 11 need to be arranged in the non-coincident area, and the pins 11 are all located in the layout plane parallel to the resonator (that is, the plane where the screen or paper is located) or in the horizontal direction away from the second resonator layout area 9, and, When the pin 11 is routed, it will not pass through the second resonator layout area 9.
  • This structure realizes the "horizontal isolation" between the upper chip and the lower chip. Through the isolation structure, the coupling can be reduced. Thereby reducing the deterioration of product performance.
  • a metal isolation layer 12 is provided between the third wafer 6 or the thin layer and the second wafer 5.
  • the metal isolation layer 12 is provided on the third wafer as shown in FIG.
  • the metal isolation layer 12 is disposed on the second wafer 5, that is, the position indicated by the arrow in FIG. 7.
  • the metal isolation layer 12 overlaps with the overlapping area 10, and the metal isolation layer 12 is connected to a ground pin, that is, the GND_TX in the overlapping area in FIG. 6.
  • the metal isolation layer 12 needs to be grounded, which can isolate the upper chip from the lower chip; wherein, the larger the area of the metal isolation layer 12, the better the isolation.
  • the metal isolation layer 12 is separating the first wafer 4 from the first wafer 4 and the second wafer.
  • the resonator on the second wafer 5 can be increased as much as possible. If the area is the same as the area of the first wafer 4, if the extension is included, it will be the same as the total area of the first wafer 4 and the extension. The same, where the metal isolation layer 12 is hollowed out at positions corresponding to the signal connection line and the ground connection line, so that the line can pass through normally.
  • the metal isolation layer 12 may be a planar metal layer, a grid-like metal layer, etc., and the metal isolation layer 12 of different structures should fall within the protection scope of this patent.
  • the metal isolation layer 12 can achieve "longitudinal isolation” and be isolated from “horizontal isolation”, which can further improve the isolation of the chip.
  • FIG. 8 it is a comparison diagram of the passband of B3TX, where the solid line is the insertion loss of the solution of the embodiment, and the dashed line is the insertion loss of the traditional structure.
  • Figure 9 is a comparison diagram of the passband of B3RX, the solid line is the insertion loss of the solution of this embodiment, and the dashed line is the insertion loss of the traditional structure;
  • Figure 10 is the comparison diagram of the passband of B1TX, and the solid line is the insertion loss of the solution of this embodiment.
  • FIG. 11 is a comparison diagram of the passband of the B1RX.
  • the solid line is the insertion loss of the solution of the embodiment, and the dashed line is the insertion loss of the traditional structure.
  • Figure 12 is a comparison diagram of out-of-band suppression of B3TX.
  • the solid line in the figure is the insertion loss of the solution of this embodiment, and the dashed line is the insertion loss of the traditional structure.
  • Figure 13 is a comparison diagram of the out-of-band suppression of B3RX. In the figure, the solid line is the insertion loss.
  • the dashed line is the insertion loss of the traditional structure;
  • Figure 14 is a comparison diagram of the out-of-band suppression of B1TX, in the figure, the solid line is the insertion loss of the embodiment scheme, and the dashed line is the insertion loss of the traditional structure,
  • Figure 15 It is a comparison diagram of out-of-band suppression of B1RX.
  • the solid line is the insertion loss of the solution of the embodiment, and the dashed line is the insertion loss of the traditional structure.
  • Figure 16 is a comparison diagram of isolation between B3TX and B3RX.
  • the solid line in the figure is the insertion loss of the solution of this embodiment, and the dashed line is the insertion loss of the traditional structure.
  • Figure 17 is the comparison diagram of the isolation between B1TX and B1RX.
  • the solid line in the figure is For the insertion loss of the solution of this embodiment, the dashed line is the insertion loss of the traditional structure.
  • the performance of the multiplexer in this embodiment is basically the same as that of the conventional structure, and therefore, there is no deterioration or significant deterioration in performance.
  • the performance of the multiplexer is maintained. Therefore, it is beneficial to reduce the size of the product, and the overall development is towards miniaturization.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

La présente invention concerne un multiplexeur, comprenant au moins deux ensembles de puces, chaque ensemble de puces comprenant deux puces situées dans la même bande de fréquences, qui sont une puce de réception et une puce de transmission, respectivement ; deux puces de différentes bandes de fréquence sont superposées de manière à former une pluralité de structures empilées ; pour une puce supérieure et une puce inférieure dans chaque structure empilée, il y a un intervalle défini entre les deux saillies verticales des deux ayant une région en quinconce (1) ; et une distance définie (2) est disposée entre des structures empilées adjacentes. Le changement des puces de l'agencement plat d'origine à l'agencement empilé peut considérablement réduire la surface plane en termes de taille, et par le réglage de l'épaisseur de la puce, peut également permettre à l'épaisseur globale de ne plus augmenter en termes d'épaisseur. Chaque puce du multiplexeur occupe une zone plus petite, ce qui facilite la miniaturisation des produits.
PCT/CN2020/140939 2020-01-16 2020-12-29 Multiplexeur WO2021143519A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010046144.6A CN111245386B (zh) 2020-01-16 2020-01-16 一种多工器
CN202010046144.6 2020-01-16

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WO2021143519A1 true WO2021143519A1 (fr) 2021-07-22

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Publication number Priority date Publication date Assignee Title
CN111245386B (zh) * 2020-01-16 2021-06-01 诺思(天津)微系统有限责任公司 一种多工器

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US20120049978A1 (en) * 2010-08-27 2012-03-01 Wei Pang Vertically integrated module in a wafer level package
CN109120239A (zh) * 2017-06-23 2019-01-01 株式会社村田制作所 多工器、发送装置以及接收装置
CN110492864A (zh) * 2019-08-09 2019-11-22 天津大学 一种体声波滤波器的封装结构及该滤波器的制造方法
CN111245386A (zh) * 2020-01-16 2020-06-05 诺思(天津)微系统有限责任公司 一种多工器
CN111244083A (zh) * 2020-01-21 2020-06-05 诺思(天津)微系统有限责任公司 一种多工器及其制造方法

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US6407649B1 (en) * 2001-01-05 2002-06-18 Nokia Corporation Monolithic FBAR duplexer and method of making the same
DE102005026243B4 (de) * 2005-06-07 2018-04-05 Snaptrack, Inc. Elektrisches Bauelement und Herstellungsverfahren
US10367470B2 (en) * 2016-10-19 2019-07-30 Qorvo Us, Inc. Wafer-level-packaged BAW devices with surface mount connection structures
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Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120049978A1 (en) * 2010-08-27 2012-03-01 Wei Pang Vertically integrated module in a wafer level package
CN109120239A (zh) * 2017-06-23 2019-01-01 株式会社村田制作所 多工器、发送装置以及接收装置
CN110492864A (zh) * 2019-08-09 2019-11-22 天津大学 一种体声波滤波器的封装结构及该滤波器的制造方法
CN111245386A (zh) * 2020-01-16 2020-06-05 诺思(天津)微系统有限责任公司 一种多工器
CN111244083A (zh) * 2020-01-21 2020-06-05 诺思(天津)微系统有限责任公司 一种多工器及其制造方法

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