WO2021213349A1

WO2021213349A1 - Filter element, multiplexer, and communication device

Info

Publication number: WO2021213349A1
Application number: PCT/CN2021/088256
Authority: WO
Inventors: 蔡华林; 庞慰
Original assignee: 诺思(天津)微系统有限责任公司
Priority date: 2020-04-20
Filing date: 2021-04-20
Publication date: 2021-10-28
Also published as: CN111464148B; CN111464148A

Abstract

A filter element. A filter layout of the filter element comprises multiple resonators constituting a filter, and comprises an input pin, an output pin, and one or more grounding pins. A packaging substrate of the filter element comprises an input pin, an output pin, and one or more grounding pins. A layout structure further comprises a metal connecting line connected to the grounding pins, a part of the metal connecting line closes to the input pin, and the other part closes to the output pin, so that coupling capacitance is formed between an input end and an output end of the filter; and/or the inner portion or the surface of the packaging substrate further comprises a metal connecting line connected to the grounding pins; a part of the metal connecting line closes to the input pin, and the other part closes to the output pin, so that coupling capacitance is formed between the input end and the output end of the filter.

Description

Filter components and multiplexers and communication equipment

Technical field

The present invention relates to the field of filter technology, in particular to a filter element, multiplexer and communication equipment.

Background technique

In recent years, the trend of miniaturization and high performance of communication equipment has accelerated, which has put forward higher challenges for the radio frequency front end. In the radio frequency communication front end, bulk acoustic wave filters are widely used.

In order to prevent the stacked structure of the BAW filter from being affected by the environment, which will reduce the performance and reliability of the filter, the first packaging method is to use two upper and lower wafers for packaging. The metal bond is used for sealing in the middle to ensure good air tightness. The chip for manufacturing the resonator is connected to the lower metal pin PAD through the through hole of the package chip. This structure is then welded to the package substrate, and the whole is covered with plastic packaging material to obtain the final filter chip. This packaging form can ensure air tightness, so that the reliability of the filter can be guaranteed, and it will not be affected by external humidity and other gases and impurities to the performance of the filter. However, there are two disadvantages: on the one hand, the through-hole traces connecting the two chips are longer, which brings greater metal loss, which will worsen the insertion loss; on the other hand, because the metal bond between the two chips must be realized Therefore, it is necessary to add a metal ring (or called a seal ring) for sealing and bonding around the resonator pattern. Because the metal ring needs to have a certain width to ensure reliable bonding, and it must resonate with all internal resonators. The pattern of the device has a certain distance, so the metal ring will occupy a larger area. Generally speaking, the area occupied by the metal ring is between 20% and 30%. So in this respect, the cost equivalent to each chip will increase by 20% to 30%. And because of the use of packaged chips, the cost is further increased.

The second packaging method in the prior art is to directly connect metal solder balls on the chip for manufacturing the resonator, and then solder the chip on the packaging substrate through the metal balls, and cover the top of the chip with a sealed isolation structure, such as a film structure or Other forms of isolation structure are used to isolate the internal structure from the outside, and then cover the plastic material to obtain the final filter element. On the one hand, this packaging method avoids the metal ring used for hermetic bonding and reduces the chip area. On the other hand, it also removes the wafer below for hermetic bonding, which further reduces the cost. In addition, since the chip for manufacturing the resonator is directly connected to the package substrate, and the connection through hole with the chip packaged below is also removed, the metal loss in this area is also eliminated, so the overall insertion loss is also improved.

In the process of implementing the present invention, the inventor found that the filter obtained by the second packaging method cannot use the input and output generated by the first packaging method and the capacitive and inductive coupling to the ground, and its performance will be affected. Specifically, since the capacitive coupling between input and output cannot be formed by a metal ring, the out-of-band suppression, especially the right-side out-of-band suppression, will be greatly deteriorated.

Summary of the invention

In view of this, the present invention proposes a filter element, multiplexer, and communication device, which can improve the right side suppression of the filter passband without using a lower wafer and a sealing ring.

To achieve the above objective, according to one aspect of the present invention, a filter element is provided.

The filter layout of the filter element of the present invention includes multiple resonators that make up the filter, and includes input pins, output pins, and one or more ground pins; the package substrate of the filter element includes input Pin, output pin, one or more ground pins; the layout structure also includes a metal connection line connected to the ground pin; a part of the metal connection line is close to the input pin, and the other part is close to the output Pin to form a coupling capacitor between the input end and the output end of the filter; and/or, the inside or surface of the package substrate further includes a metal connection wire connected to the ground pin; the metal connection A part of the wire is close to the input pin, and the other part is close to the output pin, so that a coupling capacitor is formed between the input end and the output end of the filter.

Optionally, the metal connecting lines are arranged along the edges of the layout, and form a closed metal ring or an unclosed metal fold line.

Optionally, the metal connection lines are arranged along the edge of the package substrate, and form a closed metal ring or an unclosed metal fold line; or, the metal connection lines are arranged along the middle of the package substrate and are connected to the ground. The pins are connected and form a non-closed metal fold line.

Optionally, the metal connecting wires are distributed on different layers of the chip where the multiple resonators are located.

Optionally, the metal connecting wires are distributed on different layers of the packaging substrate.

Optionally, the capacitance value of the coupling capacitor is between 0.5 fF and 5 fF.

Optionally, the capacitance value of the coupling capacitor is between 1fF and 3fF.

Optionally, the pins of the filter chip are connected to the metal traces on the top of the package substrate via metal balls; the upper and periphery of the filter chip are covered with a sealing layer.

According to the second aspect of the present invention, there is provided a multiplexer including the filter element of the present invention.

According to a third aspect of the present invention, there is provided a communication device including the filter element of the present invention.

According to the technical solution of the present invention, the required coupling is formed on the layout of the resonator or on the package substrate through a specific metal connection, so as to move the corresponding out-of-band zero point, thereby helping to improve the passband of the filter. Right side inhibition.

Description of the drawings

For purposes of illustration and not limitation, the present invention will now be described according to preferred embodiments of the present invention, particularly with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of the first packaging method according to the prior art;

Fig. 2 is a schematic diagram of a second packaging method according to the prior art;

3A and 3B are schematic diagrams of patterns of an upper wafer and a lower wafer of a bulk acoustic wave filter in the prior art, respectively;

Fig. 4 is a filter layout according to a second packaging method in the prior art;

5A and 5B are schematic diagrams of generating capacitance according to the seal ring of the prior art;

6A to 6D are schematic diagrams of performing circuit analysis on the coupling between the input and output ends of the filter in the prior art in the embodiment of the present invention;

FIG. 7 is a schematic diagram of analyzing the influence of grounding and non-grounding of the seal ring on out-of-band suppression in the embodiment of the present invention;

8A to 8F are schematic diagrams of connecting wires on the layout of the resonator according to an embodiment of the present invention to form a coupling capacitor;

FIG. 9 is a schematic diagram of a pattern on a packaging substrate according to the prior art;

10A to 10F are schematic diagrams of forming a coupling capacitor on the surface of a package substrate through a connecting line according to an embodiment of the present invention;

10G to 10I are schematic diagrams of forming a coupling capacitor in the middle of the package substrate through a section of connecting line according to an embodiment of the present invention;

11A and 11B are schematic diagrams of improving the suppression of the filter on the right side by increasing the coupling capacitance between the input and output according to an embodiment of the present invention;

Figure 12A and Figure 12B are based on Figure 11A and Figure 11B, after increasing the coupling capacitance to 4fF;

FIG. 13 is a schematic diagram of a comparison of insertion loss according to an embodiment of the present invention.

Detailed ways

In the embodiment of the present invention, through the analysis of the reasons for the degradation of the out-of-band suppression on the right side, the required coupling is formed on the layout of the resonator or on the package substrate through a specific metal connection, so as to move the corresponding out-of-band zero point ,Improve the inhibition of the right side.

The above two packaging methods will be further explained below. Fig. 1 is a schematic diagram of the first packaging method according to the prior art. As shown in Figure 1, the first packaging method uses wafer-level packaging. In the packaging structure (Molding), wafer 1 (wafer1) is used as the upper wafer to manufacture resonators and pins (PAD), and wafer 2 (wafer2) As the lower wafer, pins (PAD) are made on the upper and lower sides, and through holes are made at the position of the PAD, and the signal and ground on wafer1 are connected through the through holes.

The PAD under Wafer2 is connected to the top metal trace of the package substrate (Laminate) through a solder ball or other metal balls (bump). Laminate can include multiple layers of metal with a dielectric layer in the middle to form a multilayer structure. The metal layers of each layer can integrate passive devices and provide connections between some pins. Finally, after wafer1 and wafer2 are sealed by metal bonding, they are covered with plastic encapsulant for packaging. The molding compound uses epoxy resin, or other special packaging materials used to improve power capacity or performance and reduce costs.

Fig. 2 is a schematic diagram of a second packaging method according to the prior art. As shown in Figure 2, compared with the first packaging method, the main difference of the second packaging method is that the wafer2 below is removed, and the PAD on the wafer1 with the resonator (Resonator) is directly connected to the package substrate (Laminate ) On the top metal trace (Top metal). Because it is necessary to ensure that the resonator on wafer1 is in a sealed state to avoid the influence of the external environment, it is necessary to cover the sealing layer above wafer1 to isolate the internal resonator from the external environment. Finally, plastic encapsulant is covered on the structure for encapsulation.

3A and 3B are schematic diagrams of the patterns of the upper wafer and the lower wafer of the bulk acoustic wave filter in the prior art, respectively. The sealring around Figure 3A is the metal sealing ring of wafer1. The sealing ring needs to have a certain width to ensure the reliability of the seal. At the same time, it needs to have a certain distance from the internal resonator, so it needs to occupy a large area, which generally occupies the entire area. 20%-30% of a die. In the figure, S1 to S4 are series resonators, P1 to P3 are parallel resonators, and the number of series and parallel resonators is not limited. The connecting lines between the various resonators in the figure are omitted. The surrounding area in Figure 3B is the sealing ring of wafer2, and the two wafers are bonded together by wafer-level bonding to ensure good sealing of the internal resonator. At the same time, through holes will be made on the PAD of wafer2 and connected to the other side of wafer2, and the other side will also be made of PAD to connect with other package structures.

Fig. 4 is a layout of a filter according to a second packaging method in the prior art. This packaging method only uses wafer1, and the metal sealing ring structure on wafer1 is removed. The input pin IN, output pin OUT and ground pin G1, G2 are directly connected to the bump metal ball, and the bump metal ball is connected to the package. On the substrate. This method removes wafer2 on the one hand, and sealring on the other. There are more dies per wafer, which greatly reduces the cost; at the same time, because the connection vias between wafer1 and wafer2 are removed, This part of the metal loss is eliminated, and the insertion loss will also be significantly improved.

Figures 5A and 5B are schematic diagrams of capacitance generated by a seal ring according to the prior art. As shown in Figure 5A and Figure 5B, the sealing ring Sealring has a certain distance from the input and output PADs (IN and OUT), which will generate capacitors C1 and C2, thereby forming a coupling effect. When the sealring is removed, the coupling capacitance between IN and OUT is also removed.

6A to 6D are schematic diagrams of performing circuit analysis on the coupling between the input and output ends of the filter in the prior art in the embodiment of the present invention. In Fig. 6A, there is capacitive coupling between the input end and the output end (shown by the black dots in the figure, the same below), and the out-of-band transmission zero point will move, which changes the out-of-band suppression characteristics of the filter. In FIG. 6B, there is capacitive coupling between the input and output ends, and the sealring, as a section of transmission line, has the effect of the capacitance and inductance elements in the box. In Figure 6C, a certain section of the sealring is grounded, thereby forming an inductance with the ground. In Fig. 6D, a certain section of the sealring is grounded to have ground inductance. At the same time, considering the sealring as a section of transmission line, it has the effect of the capacitance and inductance elements in the box.

FIG. 7 is a schematic diagram of analyzing the influence of grounding and non-grounding of the seal ring on out-of-band suppression in the embodiment of the present invention. The solid line and the dashed line in FIG. 7 correspond to grounding and non-grounding, respectively. It can be seen from Figure 7 that the out-of-band suppression characteristics can be improved by adjusting the grounding.

Based on the above analysis, in the embodiment of the present invention, the filter element adopts the second packaging method, and a connecting wire is used to form a capacitor. Because after removing the sealring, the coupling between the input and the output is eliminated, and the right side of the filter out-of-band suppression will deteriorate. Therefore, an additional coupling capacitor between the input and output is needed to improve the right-side out-of-band suppression. The connecting wires can be arranged on the resonator layout, the package substrate, or both.

8A to 8F are schematic diagrams of connecting wires on the layout of the resonator according to an embodiment of the present invention to form a coupling capacitor. As shown in Figures 8A to 8F, when the second packaging method is used, connecting wires 8A to 8F can be provided on wafer1, and the connecting wires 8A to 8F in each figure are respectively connected to ground pins G1 or G2 to form a closed ring or Unclosed polyline. The shape and size of the broken line can be changed according to the layout and the size of the chip boundary. The broken line needs to be arranged between the input pin IN and the output pin OUT on the chip. IN and OUT have a certain distance and enclosing length. The distance and enclosing length determine the size of the capacitor. The broken line can be routed on different layers inside the chip, and it is necessary to avoid the pattern of the internal resonator as much as possible, and only establish an electrical coupling relationship between IN and OUT. At the same time, it is necessary to consider the manufacturing rules of the chip edge, and try not to increase the chip size.

Fig. 9 is a schematic diagram of a pattern on a package substrate (Laminate) according to the prior art. The circular pad in the middle of FIG. 9 is connected to the ground pins G1 and G2, and the bottom is the through hole in the package substrate. Figures 10A to 10I also have similar circular pads. 10A to 10F are schematic diagrams of forming a coupling capacitor on the surface of a package substrate (Laminate) through a section of connecting lines (10A-10F) according to an embodiment of the present invention. As shown in FIGS. 10 to 10F, the connecting lines may be distributed along the edge of the package substrate. FIGS. 10G to 10I are schematic diagrams of forming a coupling capacitor through a section of connecting wires (10G to 10I) in the middle of the package substrate according to an embodiment of the present invention. The middle here is not limited to the geometric center of the package substrate, but relative to the above-mentioned distribution along the edge of the package substrate. When the wire is connected to the ground pin, it can be directly connected to the ground pin, as shown in Fig. 10H and Fig. 10I; or as shown in Fig. 10G, the connecting wire is connected to the middle circular pad. It is not on the same layer as the ground pin, so it is connected to the ground pin through a through hole. After the sealring is removed, according to the embodiment of the present invention, traces are formed on the surface or inside of the package substrate, and can also be distributed in layers in the package substrate, and the design flexibility can be further increased by coupling with G1 and G2. The connection line needs to be arranged on the substrate between the input pin IN and the output pin OUT. IN and OUT have a certain distance and enclosing length. The distance and enclosing length determine the size of the capacitor. The connecting wires can be routed on different layers inside the substrate, and it is necessary to avoid the wires in the inner substrate as much as possible, and only establish an electrical coupling relationship between IN and OUT. At the same time, it is necessary to consider the manufacturing rules of the edge of the package substrate, and try not to increase the size of the substrate.

11A and 11B are schematic diagrams of improving the suppression of the filter on the right side by increasing the coupling capacitance between the input and output according to an embodiment of the present invention. After removing the sealring, the solid line in the figure corresponds to increasing the coupling capacitance, and the dashed line corresponds to not increasing the coupling capacitance. Fig. 11A shows the suppression of the adjacent zone, and Fig. 11B shows the suppression of the far zone. It can be seen from the figure that through the addition of the coupling capacitor, the transmission zero point near 2.52GHz on the right moves to near 2.54GHz, so as to ensure that the suppression above 2.54GHz is improved. The frequency bands in this area have B7 transmitter frequency (2.5GHz～2.57GHz), B41 (2.496GHz～2.69GHz). For far band suppression, there is almost no effect. The capacitance formed in the above figure is about 2fF (Flying method).

Figures 12A and 12B are based on Figures 11A and 11B, after increasing the coupling capacitance to 4fF. It can be seen from FIG. 12A and FIG. 12B that although the right side suppression is further improved, and the far-band suppression (see FIG. 12B) is also improved, the left side suppression has deteriorated, so the aforementioned coupling capacitor needs to be within a certain range. This interval can be limited to 0.5fF to 5fF, and further, it can be limited to 1fF to 3fF.

In addition, because wafer2 is not used, there is no through hole for connecting wafer1 and wafer2, so the metal resistance loss is reduced, and the insertion loss is improved. As shown in FIG. 13, FIG. 13 is a schematic diagram of insertion loss comparison according to an embodiment of the present invention, in which the solid line corresponds to the embodiment of the present invention, and the dotted line corresponds to a situation where wafer1 and wafer2 are connected through holes when wafer2 is present. It can be seen from FIG. 13 that with the technical solution of the embodiment of the present invention, the insertion loss of the filter is improved by more than 0.1 dB.

The foregoing specific implementations do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that, depending on design requirements and other factors, various modifications, combinations, sub-combinations, and substitutions can occur. Any modification, equivalent replacement and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

A filter element,

The filter layout of the filter element includes multiple resonators that make up the filter, and includes input pins, output pins, and one or more ground pins;

The packaging substrate of the filter element includes input pins, output pins, and one or more ground pins;

It is characterized by

The layout structure also includes a metal connection line connected to the ground pin; a part of the metal connection line is close to the input pin, and the other part is close to the output pin, so that the input end and the output end of the filter are different from each other. Form a coupling capacitor between;

And/or,

The inside or surface of the package substrate also includes a metal connection wire connected to the ground pin; a part of the metal connection wire is close to the input pin, and the other part is close to the output pin, so that the input end of the filter is connected to the ground pin. A coupling capacitor is formed between the output terminals.
The filter element according to claim 1, wherein:

The metal connecting lines are arranged along the edges of the layout and form a closed metal ring or an unclosed metal fold line.
The filter element according to claim 1, wherein:

The metal connecting lines are arranged along the edge of the packaging substrate, and form a closed metal ring or an unclosed metal fold line;

Alternatively, the metal connection line is arranged along the middle of the package substrate, connected to the ground pin, and forms an unclosed metal fold line.
The filter element according to claim 1, wherein:

The metal connecting lines are distributed on different layers of the chip where the multiple resonators are located.
The filter element according to claim 1, wherein:

The metal connecting wires are distributed on different layers of the packaging substrate.
The filter element according to claim 1, wherein:

The capacitance value of the coupling capacitor is between 0.5 fF and 5 fF.
The filter element according to claim 6, wherein:

The capacitance value of the coupling capacitor is between 1fF and 3fF.
The filter element according to any one of claims 1 to 7, characterized in that:

The pins of the filter chip are connected to the metal traces on the top of the package substrate via metal balls;

The upper and periphery of the filter wafer are covered with a sealing layer.
A multiplexer, characterized by comprising the filter element according to any one of claims 1 to 8.
A communication device, characterized by comprising the filter element according to any one of claims 1 to 8.