WO2009001312A2

WO2009001312A2 - Packaged device for common mode filtering and esd protection

Info

Publication number: WO2009001312A2
Application number: PCT/IB2008/052550
Authority: WO
Inventors: Michael Joehren; Dirk Wittorf; Horst Roehm; Frank Burmeister
Original assignee: Nxp B.V.
Priority date: 2007-06-28
Filing date: 2008-06-25
Publication date: 2008-12-31
Also published as: WO2009001312A3

Abstract

The packaged device of the invention combines common mode filtering and ESD protection and is tuned to give optimum common mode protection at RF frequencies in use for mobile telephony, particularly, the lower frequency band of GSM. The package comprises a common mode choke followed by an ESD bridge including diodes.

Description

PACKAGED DEVICE FOR COMMON MODE FILTERING AND ESD PROTECTION

The plurality of portable apparatus, such as portable computers, mobile phones and audioplayers, and all their accessories such as hand sets and mouses sets increasing demands to signal integrity and to the protection of components inside such apparatus.

One important cause of loss of signal integrity is common mode interference. Common mode interference between a first and a second high frequency component may lead thereto, that within a certain timeframe substantial noise is provided. Particularly in case of digitized signals, this may result in a wrong signal. The interference may result in a shift of a reference voltage level, and as a result, data superposed on the voltage is not recognized anymore as '0' or ' 1', but merely as '1 '. The first high frequency component is for instance a mobile phone, while the second high frequency component is a cable connected to a personal computer. Alternatively, the second component may be a cable connected to the mobile phone, since the mobile phone may be the cause of the interference on a cable attached to itself.

This problem of common mode rejection is expected to increase dramatically, as the universal standard bus (USB) is increasingly applied for the connection of a variety of accessories: memory sticks, mouses, power cables, head sets, keyboards, etc. The problem may be so problematic that reading or writing over the bus turns out impossible, or should be restarted. While such a restart is principally possible in the case of data transfer, it will not be acceptable at all in case of the transmission of audio signals over a USB bus; the human ears are very sensitive.

An additional complication is the use of even higher frequencies, which are needed to obtain sufficient speed of datatransfer. The higher frequencies increase the problem of common mode rejection and lead to unexpected spurious effects originating in the RF behaviour of high frequency signals. Reflection of signals where a mechanical transition is imperfect is a cause of substantial loss of signal integrity.

It is thus an object of the present invention to provide a solution that reduces signal integrity problems, particularly in view of common mode interference. This object is solved in an electronic device of the kind mentioned in the opening paragraph, comprising means for common mode protection and an ESD-protection element.

It was found in simulations leading to the invention that the combination of ESD protection and common mode protection means within a single device is beneficial to the quality of the common mode protection.

Particularly, in one advantageous embodiment, the device means is designed so as to have a self-resonance at a frequency corresponding to a frequency band of a wireless transmission. More particularly, the lower frequency band of the GSM specification (900 MHz) is chosen as this frequency band. Due to the self- resonance, the common mode filtering is very good. Experiments have shown, unexpectedly, that a reduction of the common mode signals to a level of less than -35 dB can be achieved. This is unexpectedly beneficial; mobile phone manufacturer ideally would like to see a common mode interference of less than -30 dB, but one is happy in practice by reducing the common mode interference to -20 dB, or even - 1OdB.

In order to achieve such self-resonance, components in the integrated device need to be designed together so as to achieve at optimum filter performance. ESD protection means usually comprise diodes. These diodes have a capacitance that contributes to the filter operation of the overall device.

Moreover, an integrated device is preferred. For frequencies above 200 MHz, the high frequency aspects are so important that a normal distance between a discrete ESD protection device and a discrete common mode choke has a substantial impact on the overall performance. This is particularly relevant for signals transmitted with the USB protocol. This protocol makes use of differential signals with superimposed thereon data. The data should be read out again. It may not be possible to get the original data, when a shift in the signal level has occurred due to a common mode interference. Moreover, the interconnects in an environment making use of a USB bus and a USB transmitter are usually not symmetrical. This may give the further failure mode that in the USB transmitter a common mode signal is converted into a differential signal, i.e. signal portions would be created.

The ESD protection device is suitably defined between the common mode choke and input terminal of a dataline. In view of the differential signals, a pair of datalines (commonly referred to as D- and D+) is common, and there is a connection to the ESD protection device from each of those.

Suitably, the ESD protection device is provided with a semiconductor substrate in which diodes are defined. In order to reduce parasitic capacitance, it has been found suitable to use a series connection of relatively small diodes for each data line. The series connection of diodes is coupled between a supply line and ground, while the signal from the dataline is connected between the first and second diode in series. A relatively large diode is connected in parallel to the diode series. This relatively large diode is able to withstand ESD pulses. Due to the preferred direction of the signal through a diode, the ESD pulse will preferentially flow through the relatively large diode. The small diodes are suitably rail to rail diodes with a capacitance in the order of 1 pF. The large diode is suitably a Zener diode with a capacitance in the order of 40 pF. The resulting capacitance will be preferably less than 3 pF and preferably less than 1,5 pF. Such a small internal capacitance provides enhanced RF performance, as the magnitude of the internal capacitance poses a limit to the frequency of data transmission. An internal capacitance of a few pF or less allows transmitting of data at frequencies of 500 MHz.

In a further embodiment, the common mode rejection filter is provided with a magnetic core that is defined in a package of the ESD protection device. Turns around the core may be constructed as a combination of interconnects in or on a package carrier and additional interconnects around the core. Such additional interconnects may be created as bondwires, or alternatively as metal clips. The magnetic core is locally interrupted to create a gap and therewith to enhance or tune the magnetic field.

It is an important advantage of this embodiment that there is a direct connection from the input to the output terminal of the device through the common mode rejection filter on the level of the package carrier. The number of connections that may lead to loss of signal integrity at high frequencies is therewith substantially reduces.

A single magnetic core allows the manufacture of a one channel common mode filter and corresponding ESD protection. However, one usually has more than one connection; for instance one may have a connector with two USB buses. In order to meet this application, in one embodiment, the invention comprises a two-channel common mode filter and corresponding ESD protection. Suitably, thereto, a first and a second magnetic core are integrated into the package. Due to the use of the core of magnetic material, particularly a ferrite material, the magnetic fields are present within the magnetic core only, and no additional shielding is needed between the first and second core. It will be understood by the skilled person that the second core also is provided with windings to establish a common mode filter. In a further embodiment, the first and second cores are arranged concentrically around the ESD protections. This turns out a proper layout. In another embodiment, the ESD protections for the first and the second channels are integrated into a single semiconductor device.

The provision of more than one core is believed to be very advantageous for future connectors, in which busses are provided that operate according to different versions of a standard, or even according to different standards. At least, such future connectors are expected by the current Applicant. Such different versions usually operate at different frequencies, and thus need different types of common mode filtering. The provision of more than one core allows that each of the cores is dedicated to a specific frequency band.

In an interesting embodiment, the semiconductor device is provided with a a bond pad structure with an underbump metallization extending above a passivation layer and a bond pad, which is coupled to the underbump metallization in an aperture in the passivation layer, with a surface area that is reduced in comparison to the underbump metallization. One example hereof is a split of the bond pad into an inner area and a preferably ring-shaped area , which are connected merely locally. Such a bond pad structure has been found advantageous to minimize the internal, parasitic capacitance. This parasitic capacitance has turned out to be due, at least partially, to parasitic coupling between bond pads and a conductive zone in the substrate. Moreover, such a bond pad structure has been found to withstand and dissipate stress due to forces during wirebonding or as a consequence of thermal cycling. It has been described in Applicant's non-prepublished European patent application EP 07104613.0 (PH007867). Another example is the limitation of the bond pad to the inner area only. The inner area should be understood as being just larger than the aperture in the passivation layer. This aperture in the passivation layer may have a diameter comparable to the thickness of the passivation layer. Preferably, it has a diameter which is less than fivefold the thickness of the passivation layer, and more preferably less than twice the thickness of the passivation layer. In an important implementation, the package carrier is defined as a leadframe carrier with a sacrificial layer. The sacrificial layer may be removed partially or completely after the provision of an encapsulation around the core and the ESD protection device. The use of such leadframe carrier allows that the pathlengths to the terminals is very short. In an even further embodiment, use is made of a leadframe carrier with a first and a second layer which can be patterned independently from each other. The patterning may be carried out with etching from opposite sides of the carrier, before and after the provision of the encapsulation. The second layer acts thus as a sacrificial layer, but will be removed only partially. The use of such a carrier allows the integration of the inductor turns into the first, upper layer only. As a result the turns remain further away from an external component than the terminals. As such, they are less prone to contamination. If desired, the turns around the core may be protected by an additional electrically insulating protection layer, that is applied after patterning of the second layer.

In an even further embodiment, the integrated device of ESD protection and common mode rejection filter is integrated into a connector. While a connector is primarily recognized as a mechanical interface, it needs to be designed properly so as to meet the requirements of the electrical standard it is used for. One such requirement is the wave resistance (German: Wellenwiderstand) that is defined to be 45 Ω for a single line and 90 Ω for a pair of differential lines. By accurately designing, it turns out possible to meet this requirement in the connector. However, it is troublesome to design the apparatus as a whole, including connector, carrier - generally printed circuit board- integrated circuits etc. Any imperfection in the design tends to lead to reflections that impact the signal integrity. This impact is increasingly important with increasing frequency. Moreover, the design is problematic and the results are not very predictable.

By integrating the device into the connector, the signal is filtered before accessing the printed circuit board. The signal to noise ratio is thus better. A non-ideality in the design will evidently impact the signal strength, but the signal can still be recognized properly. In other words, the design complexity of the printed circuit board reduces,

The integration of the integrated device according to the invention into a connector turns out to have an additional advantage: the parasitic capacitance of the ESD protection device may be balanced against a parasitic inductance of the connector. As known to the skilled person in the field of RF design, a balancing of inductors and capacitors may lead to cancellation of the effect. Alternatively, the parasitic capacitance can be taken into account in the design of the common mode choke, and vice versa. Furthermore, when with increasing frequencies the limits to parasitic capacitance are reduced, such a cancellation is a method to meet this requirement without reducing the quality of the ESD protection.

In order to integrate the packaged device into a connector, it may be suitable to assemble it first to a carrier. Such a carrier may have apertures that are designed to fit to leads of the connector. In such a manner, the packaged device may be integrated into the connector without substantial redesign of the connector. Alternatively, it is possible that the packaged device comprises such a carrier. The inductor is then assembled on top of the carrier. The semiconductor device may be assembled on top of the carrier or even into the carrier. It is even not excluded that also the inductor is integrated into the carrier. The carrier is preferably a multilayer printed circuit board. Techniques for assembling components into printed circuit boards are studied intensively in recent years. A connector with such integrated carrier and thereon an ESD protection element is described in the non-prepublished application 07110071.3 (internal reference PH008168EP1), which is included herein by reference.

The invention further relates to a method of signal transmission of a first signal over a port attached to an apparatus in the neighbourhood of a device for wireless transmission of signals according to a protocol. In accordance with the invention the first signal is transmitted through an integrated device comprises both ESD protection means and means for common mode protection. Particularly the device is designed so as to have self-resonance within a frequency band of the wireless transmission protocol. Particularly, this frequency band corresponds to the 900 MHz frequency band of the GSM protocol. The port is preferably a port designed in accordance with the USB protocol, more specific USB2.0, USB2.0 high speed, USB3.0 or more advanced versions thereof. Alternatively, use could be made of the HDMI protocol.

These and other aspects of the invention will be further elucidated with reference to the figures, in which: Fig 1 shows an electrical diagram of a first embodiment of the invention;

Fig. 2 shows a package outline of the packaged device according to the invention;

Fig. 3 shows a graph for the device of Fig. 1, in which the impedance is shown as a function of the frequency;

Fig. 4 shows another graph for the device of Fig. 1, in which the insertion loss is shown as a function of the frequency;

Fig. 5 shows an eye-diagram for the device of Fig.1;

Fig. 6 shows an electrical diagram of a second embodiment of the invention;

Fig. 7 shows a further schematic drawing of the second embodiment of the invention;

Fig. 8-15 show several steps in the manufacture of the packaged device as shown in Fig. 2

Fig. 16-19 show a second embodiment for the manufacture of the device;

Fig. 20-21 show a specific shape for the core in line with the second embodiment, and

Fig. 22-23 show a third embodiment for the manufacture of the device.

Fig. 1 shows an electrical diagram of a first embodiment of the invention. This diagram shows a one-channel common mode filter with integrated ESD protection. The packaged device of this embodiment is a one channel, two line common mode filter with integrated ESD protection up to ±8 kV contact discharge according IEC61000-4-2, level 4. The input terminals of the device are shown as D+ and D-, indicating the differential nature of the input signals. Connected between the input terminals and output terminals is a common mode filter, also referred to as a common mode choke. Between the input terminals and the common mode choke connections are made to the ESD protection circuit. This is advantageous so as to prevent that any high voltage pulses enter the common mode filter. Due to the turns defined therein, the high voltage pulses might be destructive. Otherwise, they would be destructive for an integrated circuit coupled to the output terminals. The ESD protection circuits comprises two parallel pairs of series connected diodes. The connections to the input terminals are present between the first and the second diode of each pair. In the case that there are more channels, the number of pairs will most probably be larger than two. The pairs of diodes are connected between a voltage source V_cc and ground. The voltage source is in this example 5.5 V, but that is variable. Due to their reverse connection, a current will primarily flow from the connection to the V_cc and then through a further ESD protection element between V_cc and ground. The third protection element, in this example also a diode of larger size, will then act as the primary ESD protection element. Due to its large size, it can withstand high voltage pulses and lead them away with limited resistance only. The third protection element is preferably a Zener diode with an internal capacitance of f.i. 40 pF. The other diodes have an internal capacitance of 1 pF. Due to these pairs of ultra-low capacity rail-to-rail diodes and the additional Zener diode, a protection to downstream signal and supply components against Electrostatic Discharge voltages as high as ±8 kV contact discharge according IEC61000-4-2, level 4 is provided. Due to the rail-to-rail diodes being connected to the Zener diode, the protection is working independent form the availability of a supply voltage. Its

Fig. 2 shows a drawing of one embodiment of a package outline of the device of the invention. The device comprises a number of terminals 1-6. Terminal 1 is input of the positive differential signal D+ IN, terminal 2 is input of the negative differential signal D- IN, terminal 3 is supply voltage Vcc, terminal 4 is Ground (GND), terminal 5 is output of the negative differential signal D- OUT, and terminal 6 is output of the positive differential signal D+ OUT. Additionally, a die pad is present. As will be further shown with reference to Fig 8-15 and further, the terminals are anchored into an encapsulation of electrically insulating material. This encapsulation further covers a semiconductor device in which ESD protection elements are defined, and a magnetic core. Turns around the magnetic core are partially defined as patterns 12 anchored in the encapsulation, and partially as wires or the like. The turns are present of a first winding or of a second winding. These windings are coupled through the magnetic core, so as to constitute the common mode filter. As will be seen, the turns of the D+ connection are neighboured by turns of the D- connection and vice versa. As will be recognized, an input terminal D+ IN, D- IN, is connected to a corresponding output terminal D+ OUT, D- OUT through the winding of the common mode filter. In this respect, a signal does not need to enter the semiconductor device, with the beneficial result of minimal reflections and adequate performance. Additionally, the internal resistance of the channel is very low, for instance 0.9 Ohm per channel.

The device of the invention provides a high performance way to eliminate common mode noise from IEEE 1394/FireWire, USB2.0 and other twisted pair interfaces. Fig. 3 shows a graph in which the impedance of the common mode filter is set out against the frequency. This graph demonstrates that the impedance of the common mode signal is significantly higher than that of the differential signal - the impedance is set out on a logarithmic scale. As a result, the common mode filter suppresses the common mode signal more severely than the differential signal. The suppression levels of the differential signal are nevertheless acceptable, even at RF frequencies: at 100 MHz, the impedance is approximately 15 Ohm, at 300 MHz, the impedance of the differential signal is approximately 40 Ohms. The results were obtained in a standard test on a test board, with 50 Ohm resistor positioned on the input and the output for both D+ and D- lines.

In Fig. 4, the insertion loss is shown as a function of the frequency for both the common mode signal and the differential signal. The present example provides over 30 dB attenuation of common mode noise at 1.2 GHz while differential mode signal extend out to more than 1 GHz before reaching the 3 dB point. Here, it turns out that the capacitance of the protection elements and the inductance of the common mode filter are optimized to give a self-resonance with a substantial attenuation. The level is less than -35 dB insertion loss. It is observed that the self- resonance in this example is defined at 1.2 GHz. In a further optimization, it can be tuned to be equal to the frequency of the GSM band. Such a further optimization involves the increase of the capacitance of the ESD protection. Alternatively, the inductance of the common mode filter may be increased. The latter is less preferred, since this will lead to changes in the characteristics of the common mode filter. Evidently, a combination of increase of the capacitance of the ESD protection and of the inductance of the common mode filter is a further option.

The self-resonance - also referred to as notch - is surprising and very advantageous. RF signals from a mobile phone constitute a major cause of common mode interference near or in connectors such as USB busses. The suppression of exactly that frequency band is thus very advantageous. In addition to USB lines and busses, such as a USB2.0 line, the use of the packaged device is considered beneficial for IEEE1394 lines for personal computers, DVC, STB, LVDS, panel link line for liquid crystal display panels, etc.

Fig. 5 shows a so-called eye-diagram. The lines on this eye-diagram show whether there is any disturbance on the differential mode signal. The eye diagram was measured for a data rate of 480 Mbps. This corresponds to the USB2.0 high speed standard. It is shown that the packaged device of the invention has virtually no impact to the differential mode signal at 480 Mbps.

Fig. 6 shows an electrical diagram of a second embodiment of the invention. This embodiment illustrates how the packaged device of the invention comprises common mode filtering and ESD protection is integrated into a connector 200, for instance a USB connector. Such integration has an important advantage that the internal capacitance of the packaged device, particularly the ESD protection, can be matched with the parasitic inductance of the connector. The schematic diagram largely corresponds to the schematic diagram of Fig. 1, with the difference that the ground and the supply voltage are embodied as bus lines in the connector. In that sense, the layout of the package terminals will probably need amendment so as to be aligned with the busses. Moreover, it may be preferred to apply a package with leads so as to fit to the leads 220 of the connector 200, that generally have a lower resolution than the terminals of the packaged device. Alternatively, one may use an intermediate carrier.

Fig. 7 shows an electrical diagram of the second embodiment of the invention. This shows more clearly how the leads 220 of the connector 200 extend out of the connector. Internally, they are connected through an intermediate carrier 230 to the packaged device 2 of the invention.

Figs. 8-15 illustrate successive steps of a first preferred way of carrying out the method for manufacturing a packaged device according to the present invention comprising both an ESD protection element and a common mode filter

In a first step, which is illustrated by Fig. 8, a package carrier 10 having a supporting surface 11 and a pattern 12 of electrically conductive elements which are arranged on the supporting surface 11 is provided. The package carrier 10 comprises copper, whereas the electrically conductive pattern 12 comprises gold- plated copper. Within the scope of the present invention, other suitable materials are feasible.

In the shown example, the electrically conductive pattern 12 comprises a number of relatively large connection pads 13, a number of relatively small connection pads 14, and a number of coil tracks 15 extending next to each other. Although the coil tracks 15 are arranged at a relatively small distance with respect to each other, none of the coil tracks 15 contacts another of the coil tracks 15.

In a second step, which is illustrated by Fig. 9, a further carrier 20 supporting a number of electrically conductive wires 21 is provided. Preferably, the wires 21 extend parallel with respect to each other, which is the case in the example as shown. A suitable material for the carrier 20 is aluminum. In any case, it is preferred for the carrier 20 to comprise another material than the substrate 10.

Fig. 9 illustrates how the further carrier 20 and the wires 21 may initially be part of a larger sheet 25. In such a case, the further carrier 20 is obtained by cutting off a piece of the larger sheet 25. Furthermore, Fig. 2 illustrates how the carrier 20 and the wires 21 are bent in order to obtain a loop-shape. In the process, end portions 22 of the wires 21 and underlying end portions 23 of the further carrier 20 are bent outwardly with respect to the loop.

In a third step, which is illustrated by Fig. 10, a core element 30 is provided. A suitable material for the core element 30 is ferrite. In the shown example, the core element 30 is shaped like a fully closed ring. Within the scope of the present invention, the core element 30 may have another suitable shape. The core element 30 is placed on the substrate 10, such that substantial parts of the coil tracks 15 are covered by the core element 30, wherein only end portions 16 of the coil tracks 15 are left free, on both sides of the core element 30.

In a fourth step, which is illustrated by Fig. 11, the further carrier 20 having the wires 21 is put in place on the package carrier 10, and the end portions 22 of the wires 21 are connected to the end portions 16 of the coil tracks 15. In the process, a portion of the core element 30 is surrounded by the further carrier 20 and the wires 21 arranged thereon.

It is noted that the coil tracks 15 and the wires 21 are not extending parallel with respect to each other, otherwise one wire 21 would only be connected to one coil track 15, and no coil would be obtained. Instead, each of the end portions 22 of each wire 21 is connected to another coil track 15. In the shown example, the end portions 22 of each wire 21 are connected to adjacent coil tracks 15, so that a single coil 35 is obtained on the basis of the interconnected coil tracks 15 and wires 21.

In a fifth step, the further carrier 20 is selectively removed by wet chemical etching. The obtained appearance of the whole of the package carrier 10, the core element 30 and the coil 35 is illustrated by Fig. 12.

Preferably, prior to putting the carrier 20 in place on the package carrier 10 and establishing connections between the coil tracks 15 and the wires 21, quantities of electrically insulating material are applied to the wires 21 such as to form members 24 for supporting and spacing the wires 21. This is especially preferred in case the wires 21 are relatively thin, as in such case, there is a risk of the wires 21 contacting each other and/or the core element 30, wherein a short circuit may be created. By means of the application of the electrically insulating material, this risk is reduced to zero. The members 24 are shown in the illustration of the whole of the electrically conductive pattern 12, the core element 30 and the coil 35 as given by Fig. 13.

In a sixth step, which is illustrated by Fig. 14, a semiconductor device 40 comprising an ESD protection element is arranged in the space enclosed by the core element 30, and is connected to the relatively small connection pads 14 of the electrically conductive pattern 12 of the package carrier 10. The circuit diagram of this semiconductor device is elucidated in more detail with reference to Fig. 1

In a seventh step, which is illustrated by Fig. 15, an encapsulation is applied to the supporting surface 11 of the package carrier 10. This step may be carried out in any suitable manner, for example by applying a technique known as overmolding. Furthermore, the material may be any suitable type of material, for example epoxy. The core element 30, the wires 21 and the microelectronic element 40 are embedded in the material, and a robust package is obtained.

In an eighth step, the package carrier 10 is removed by wet chemical etching. This is possible in that the encapsulation has taken over the carrying function. When this step has been performed, the packaged device 1 as illustrated by Fig. 9 is obtained, which is a ready-to-use product that is connectable to another electronic device through the electrically conductive pattern 12. The dimensions of the resulting packaged device may be in the millimeter range. For example, the length en the width of the device may be about 3 mm, while the height of the device may be about 0.7 mm. Figs. 16-19 illustrate successive steps of a second preferred way of carrying out the method for manufacturing a microelectronic device 2 according to the present invention.

In a first step, which is illustrated by Fig. 16, a package carrier 10 having a supporting surface 11 and a pattern 12 of electrically conductive elements which are arranged on the supporting surface 11 is provided. The package carrier 10 comprises copper, whereas the electrically conductive pattern 12 comprises gold- plated copper. Within the scope of the present invention, other suitable materials are feasible.

In the shown example, the electrically conductive pattern 12 comprises a number of connection pads 13, a number of connection tracks 18 being connected to the connection pads 13, and a number of coil tracks 15 extending next to each other. In particular, the coil tracks 15 are extending substantially parallel with respect to each other, wherein none of the coil tracks 15 contacts another of the coil tracks 15.

In a second step, which is illustrated by Fig. 17, a semiconductor device 40 comprising a plurality of ESD protection elements, i.e. diodes, is provided. The device 40 is arranged on the supporting surface 11 of the package carrier 10. In the process, any suitable known technique may be applied, for example a technique known as flip chip, which is suitable to be used for the purpose of connecting the semiconductor device 40 to the connection tracks 18. Furthermore, in this step in the process of manufacturing the packaged device 2, an under fill may be provided. Alternatively, use can be made of wirebonding. This wirebonding may then be carried out in the fourth step, as will be described hereinafter.

In a third step, which is illustrated by Fig. 18, a core element 30 is provided and placed on the package carrier 10. A suitable material for the core element 30 is a material known as ferroxcube, which is known commercially as a specific type of ferrite material. Another ferrite material is also suitable. In the shown example, the core element 30 is shaped like a fully closed ring. Within the scope of the present invention, the core element 30 may have another suitable shape, although the ring-shape is advantageous in view of the performance of the packaged device 2.

When the core element 30 has been placed on the package carrier 10, substantial parts of the coil tracks 15 are covered by the core element 30, wherein only end portions 16 of the coil tracks 15 are left free, on both sides of the core element 30. In a fourth step, which is illustrated by Fig. 19, two coils 35, 36 are obtained by providing wires 21 and connecting end portions 22 of the wires 21 to the end portions 16 of the coil tracks 15 by means of wirebonding. It is noted that the coil tracks 15 and the wires 21 are not extending parallel with respect to each other, otherwise one wire 21 would only be connected to one coil track 15, and no coils 35, 36 would be obtained. Instead, each of the end portions 22 of each wire 21 is connected to another coil track 15. In the shown example, the end portions 22 of each wire 21 are connected to coil tracks 15 between which another coil track 15 is extending, so that two coils 35, 36 are obtained on the basis of the interconnected coil tracks 15 and wires 21, wherein the windings 37 of the coils 35, 36 are alternating with each other.

Furthermore, in the fourth step, in case the semiconductor device 40 has not yet been connected to the connection tracks 18, the wirebonding technique may also be applied for the purpose of establishing connections between the microelectronic element 40 and the connection tracks 18.

After the fourth step has been carried out, all functional elements of the microelectronic device 2 are put in place and are interconnected in the proper manner. The microelectronic device 2 may be finished in subsequent steps of applying encapsulating material to the supporting surface 11 of the package carrier 10 for the purpose of enclosing and protecting the functional elements of the packaged device 2; and removing the package carrier 10, at least partially.

Preferably, at least a portion of the core element 30 that is intended to be positioned inside the coils 35, 36 is coated with an electrically insulating material. In this way, the windings 37 of the coils 35, 36 are prevented from touching each other electrically. The coating may be omitted in case the wires 21 are electrically insulated.

An advantage of providing the wires 21 and connecting the wires 21 by applying wirebonding over providing the wires 21 on a further carrier 20 is that there is no need for an additional step of removing such a further carrier 20.

In a preferred embodiment, the core element 30 comprises studs 31 which are arranged at a bottom side of the core element 30, i.e. the side facing the supporting surface 11 of the substrate 10 when the core element 30 has been put in place on the substrate 10. Fig. 20 diagrammatically shows a bottom view and a side view of a core element 30 having such studs 31. By means of the studs 31, it is achieved that space is present between the bottom side of the core element 30 and the supporting surface 11 of the package carrier 10. As a result, when material such as epoxy is applied to the supporting surface 11 , the material is allowed to flow around the core element 30, wherein there is no risk of air getting entrapped between the bottom side of the core element 30 and the supporting surface 11 of the substrate 10. In this way, the manufacturability is improved.

By applying the above-described method, a packaged device 1 , 2 having a core element 30 and at least one coil 35, 36 arranged around the core element 30 is manufactured. The core element 30 is put in place prior to closing the windings 37 of the coil 35, 36, wherein it is possible for the core element 30 to consist of only one piece and have a closed shape such as a ring-shape. In case of two or more coils 35, 36 being provided, the windings 37 of the coils 35, 36 may be located next to each other, wherein the coils 35, 36 are extending in the same line, but the coils 35, 36 may also be extending at different locations. As an illustration, in Fig. 21, elements of a microelectronic device having a ring-shaped core element 30 and two coils 35, 36 are shown, wherein the coils 35, 36 are arranged around different parts of the core element 30.

Figs. 22 and 23 diagrammatically show a sectional view of a layered package carrier 10, a core element 30 and wires 21 which are used in a third preferred process of manufacturing the microelectronic device. The layered package carrier 10 comprises a top layer of electrically conductive tracks 15a which are arranged on the supporting surface 11 of the package carrier 10. Furthermore, the layered package carrier 10 comprises an intermediate layer of electrically conductive tracks 15b and a bottom layer of electrically conductive tracks 15 c, which are both arranged underneath the supporting surface 11 of the package carrier 10. In the shown example, both the intermediate layer of tracks 15b and the bottom layer of tracks 15c are accessible from the side of the supporting surface 11, through electrically conductive connection elements 19.

It is noted that in the third preferred process of manufacturing the packaged device, the layered package carrier 10 is not removed. For example, the layered package carrier 10 comprises a material known as PCB. Alternatively, it may comprise a plurality of metal layers, allowing separate etching from the top side and from the bottom side, before and after encapsulation. Groups of wires 21a, 21b, 21c are provided, which are connected to the tracks 15a, 15b, 15c of every layer. In this way, multiple- layered windings 37 of the at least one coil 35, 36 are realized. In the shown example, as the substrate 10 comprises three layers of tracks 15a, 15b, 15c, windings 37 having three layers are obtained.

It is important that the wires 21a, 21b, 21c of the various layers of the windings 37 are not capable of making an electrical connection. Therefore, it is an advantageous option to use electrically insulated wires 21. Another solution, which is illustrated by Figs. 22 and 23, is found in giving the wires 21a, 21b, 21c which are attached to the different layers of tracks 15a, 15b, 15c different loop heights.

In order to have a good magnetic coupling between the core element 30 and the wires 21, a preferred configuration is a configuration in which the loops of the wires 21 are as close as possible to the core element 30. In this respect, it is an option to adjust the shape of the circumference of the cross-section of the core element 30. In Fig. 23, an advantageous option is illustrated, namely an option according to which the cross-section of the core element 30 has the shape of a trapezium. In general, according to this option, the bottom side of the core element 30 has larger dimensions than a top side of the core element 30, so that the cross-section of the core element 30 has a tapering appearance.

It will be clear to a person skilled in the art that the scope of the present invention is not limited to the examples discussed in the foregoing, but that several amendments and modifications thereof are possible without deviating from the scope of the present invention as defined in the attached claims.

For reasons of clarity, the following explanation of basic terms used throughout the application is added. The terms 'RF' and 'high-frequency'mean in the context of the present application that the frequency at which the data signals are transmitted are in the RF range, e.g. at least 100 MHz. Particularly, the present invention addresses connectors for use at frequencies of at least 400 MHz, and more particularly connectors for use in accordance with the Universal Serial Bus (USB) 2.0, 3.0 and further versions. USB 2.0 uses for instance 450 MHz, USB 3.0 uses 3.0 GHz.

The terms 'high speed' or "high data rate" mean in the context of the present application that the frequency at which the data signals are transmitted are in the RF range.

In the context of this application the term "connector" or "electrical connector" can be anything which reminds of a connector, i.e., can be a standard USB connector, e.g. an USB connector according to the respective technical international standard for USB connectors, a mini-USB, a Display Port, a High Definition Multimedia Interface (HDMI), an Instrument Neutral Distributed Interface (INDI) and or any other interface.

The ESD protection of the present invention preferably is a system level protection. Such protections are preferably provided at the input of the system, so as to protect the system against damage or breakdown due to electrostatic discharge during use. It is particularly used in portable equipment such as mobile phones, portable computers etc, for at least one of following reasons: first, there are very many user interfaces, which increases the risk of an ESD event. Secondly, a portable apparatus may be used even under harsh conditions, such as in a desert or when it is freezing. Thirdly, the electronic system is often located very near to the user interface. In view thereof, protections up to 15 kV, preferably at least for 1000 strikes, as measured in accordance with Human Base Model as known to the skilled person, are prescribed.

Such an ESD protection cannot be integrated appropriately with an integrated circuit, particularly integrated circuits of advanced technology such as made in C90 and beyond. Instead, use is made of discrete or semi-discrete components, the latter usually comprising a combination of a number of active elements, e.g. diodes, and passive elements, for filtering purposes.

The present invention comprises the perception that it is an inherent problem in the design of these system level ESD protections that their protecting character may not hamper the signal transmission, which is generally large at system inputs. This high level of signal transmission particularly occurs where a wired bus connection is present as a system input. An example is the aforementioned USB bus. In view of the needed speed of such bus connection, the frequency of the connection is increased. Hence, the system level ESD protection must be designed in a manner so as not to hamper the signal transmission at RF frequencies. Here, matters start to become really complex, since at RF frequencies the impedance of any interconnect or other element has to be taken into account in order to maintain a proper signal to noise ratio. Moreover, undesired signal interaction may occur at a harmonic frequency of the frequency in use. Additionally, common mode interference must be filtered to provide better performance.

Claims

CLAIMS:

1. A packaged electronic device comprising a common mode filter and an ESD protection element.

2. A packaged device as claimed in Claim 1, wherein the device is designed so that the common mode filter has its optimum filtering in a frequency band of a wireless transmission standard.

3. A packaged device as claimed in Claim 2, wherein the frequency band is chosen to be the 900 MHz frequency band of the GSM transmission standard.

4. A packaged device as claimed in any of the previous Claims, wherein the common mode filter comprises a magnetic core that is provided around a semiconductor device comprising the ESD protection element, which core and which semiconductor device are encapsulated in an electrically insulating encapsulation.

5. A packaged device as claimed in Claim 4, wherein a first and a second inductor are defined around the magnetic core, each inductor having a plurality of turns, which turns are partially defined as part of a package carrier.

6. A packaged device as claimed in Claim 5, wherein the package carrier is a leadframe carrier comprising a first and a second conductive layer, each patterned according to a individual specified pattern, and wherein the turns of the inductors are present in the first conductive layer, while a corresponding portion of the second conductive layer is removed.

7. A high-frequency electrical connector (8) with an input terminal for a signal from an external source, an output terminal to an integrated circuit, and a ground terminal, in which connector an packaged device according any of the previous claims is integrated.

8. The connector as claimed in Claim 1, wherein the connector is designed for the transmission of signals according to a USB protocol.

9. A system comprising a system carrier, an integrated circuit and a connector for the provision of signals from and to an external source according to a specified protocol, wherein the connector according to any of the preceding claims 7 and 8 is present.

10. Use of the packaged device as claimed in any of the Claims 1 to 6 and use of the connector as claimed in any of the preceding claims 7 and 8 for transmitting signals above 200 MHz.