WO2021238464A1 - 显示面板及其裂纹检测方法、显示装置 - Google Patents

显示面板及其裂纹检测方法、显示装置 Download PDF

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Publication number
WO2021238464A1
WO2021238464A1 PCT/CN2021/086756 CN2021086756W WO2021238464A1 WO 2021238464 A1 WO2021238464 A1 WO 2021238464A1 CN 2021086756 W CN2021086756 W CN 2021086756W WO 2021238464 A1 WO2021238464 A1 WO 2021238464A1
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WIPO (PCT)
Prior art keywords
area
line
terminal
output signal
series
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PCT/CN2021/086756
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English (en)
French (fr)
Inventor
王予
张毅
刘庭良
罗昶
张昊
杨慧娟
尚庭华
周洋
于鹏飞
张顺
姜晓峰
李慧君
韩林宏
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/628,228 priority Critical patent/US11922838B2/en
Publication of WO2021238464A1 publication Critical patent/WO2021238464A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a display panel, a crack detection method thereof, and a display device.
  • OLED organic light-emitted diode
  • FMLOC Flexible Multi-Layer On Cell
  • PCD Panel Crack Detection
  • an embodiment of the present disclosure provides a display panel including a display area and a peripheral area located at the periphery of the display area, and the display panel includes:
  • the first insulating structure layer is located on one side of the substrate
  • the first crack detection line is located on the side of the first insulating structure layer away from the substrate, and the first crack detection line is located in the peripheral area and arranged around the display area;
  • the second insulating structure layer is located on the side of the first crack detection line away from the substrate;
  • the second crack detection line is located on the side of the second insulating structure layer away from the substrate, and the second crack detection line is located in the peripheral area and arranged around the display area,
  • One end of the first crack detection line is configured to receive a detection signal, the other end is configured to output a first output signal, one end of the second crack detection line is configured to receive a detection signal, and the other end is configured to output a second output signal.
  • the peripheral area includes a first area provided with a binding area, a second area provided opposite to the first area, and a connection between the first area and the second area.
  • the third area and the fourth area are set relative to each other,
  • the first crack detection line includes a first end point and a second end point located in a first area, and the first crack detection line is disposed in the first area, the second area, the third area, and the display area around the display area.
  • one of the first end point and the second end point is configured to receive a detection signal, and the other is configured to output a first output signal.
  • the peripheral area includes a first area provided with a binding area, and a third area and a fourth area oppositely provided on both sides of the first area
  • the first crack detection line includes A first series line and a second series line
  • the first series line includes a first end point and a third end point located in a first area
  • the first series line is located in the first area and the third area
  • the second series line includes a second end and a fourth end located in a first area
  • the second series line is located in the first area and the fourth area
  • One of the first endpoint and the third endpoint is configured to receive a detection signal, and the other is configured to output a first output signal
  • One of the second terminal and the fourth terminal is configured to receive a detection signal, and the other is configured to output a third output signal.
  • the display panel includes n columns of sub-pixels and n data lines located in the display area, and the n columns of sub-pixels are connected to the n data lines,
  • the display panel further includes a fourth control unit and a test control terminal located in the first area, the third terminal is configured to receive a detection signal, and the fourth control unit is connected to the test control terminal and the first The terminal is connected to the xth data line, and the fourth control unit is configured to provide the signal of the first terminal to the xth data line under the control of the test control terminal signal to control the xth column
  • the light-emitting state of the pixel where x is a natural number, and 1 ⁇ x ⁇ n.
  • the display panel further includes a fifth control unit located in the first area, the fourth end point is configured to receive a detection signal, the fifth control unit and the test control end, The second end point is connected to the yth data line, and the fifth control unit is configured to provide the yth data line with the signal of the second end point under the control of the test control terminal signal to control the yth data line.
  • the light-emitting state of the sub-pixels in the y column where y is a natural number, and 1 ⁇ y ⁇ n.
  • the peripheral area includes a first area provided with a binding area, a second area provided opposite to the first area, and a connection between the first area and the second area.
  • the third area and the fourth area are set relative to each other,
  • the second crack detection line includes a seventh end point and an eighth end point located in the first area, and the second crack detection line is arranged in the first area, the second area, the third area, and the first area around the display area.
  • one of the seventh end point and the eighth end point is configured to receive a detection signal, and the other is configured to output a second output signal.
  • the peripheral area includes a first area provided with a binding area, and a third area and a fourth area oppositely provided on both sides of the first area
  • the second crack detection line includes A third series line and a fourth series line
  • the third series line includes a seventh end point and a ninth end point located in the first area
  • the third series line is located in the first area and the third area
  • the fourth series line includes an eighth end point and a tenth end point located in the first area
  • the fourth series line is located in the first area and the fourth area
  • One of the seventh endpoint and the ninth endpoint is configured to receive a detection signal, and the other is configured to output a second output signal
  • One of the eighth endpoint and the tenth endpoint is configured to receive a detection signal, and the other is configured to output a fourth output signal.
  • the display panel includes n columns of sub-pixels and n data lines located in the display area, and the n columns of sub-pixels are connected to the n data lines,
  • the display panel further includes a first control unit and a test control terminal located in the first area, the ninth terminal is configured to receive a detection signal, and the first control unit is connected to the test control terminal and the seventh terminal.
  • the terminal is connected to the i-th data line, and the first control unit is configured to provide the signal of the seventh terminal to the i-th data line under the control of the test control terminal signal to control the sub-pixels in the i-th column.
  • the light-emitting state where i is a natural number, and 1 ⁇ i ⁇ n.
  • the display panel further includes a second control unit located in the first area, the tenth end point is configured to receive a detection signal, the second control unit and the test control end,
  • the eighth terminal is connected to the j-th data line, and the second control unit is configured to provide the signal of the eighth terminal to the j-th data line under the control of the test control terminal signal to control the The light-emitting state of the sub-pixels in column j, where j is a natural number, and 1 ⁇ j ⁇ n.
  • the display panel further includes a plurality of third control units and test data terminals located in the first area, and each of the third control units is connected to the test control terminal and the test data terminal. Connected to a data line, the third control unit is configured to provide the signal of the test data terminal to the corresponding data line under the control of the test control terminal signal to control the corresponding sub-pixel column to be in the first light-emitting state.
  • the display panel includes a driving structure layer on one side of the substrate, the driving structure layer includes a thin film transistor, the first crack detection line and the source and drain metal layer of the thin film transistor It is arranged in the same layer, and the first insulating structure layer includes an insulating layer arranged between adjacent layers of the thin film transistor; or,
  • the display panel includes a driving structure layer on one side of the substrate, and the driving structure layer includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, An interlayer insulating layer and a source/drain metal layer, the first crack detection line and the source/drain metal layer are arranged in the same layer, and the first insulating structure layer includes a first gate insulating layer, a second gate insulating layer, and an interlayer Insulating layer; or,
  • the display panel includes a driving structure layer on one side of the substrate, and the driving structure layer includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, An interlayer insulating layer and a source-drain metal layer, the first crack detection line and the second gate metal layer are arranged in the same layer, and the first insulating structure layer includes a first gate insulating layer and a second gate insulating layer; or ,
  • the display panel includes a driving structure layer on one side of the substrate, and the driving structure layer includes an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, An interlayer insulating layer and a source-drain metal layer, a part of the first crack detection line is arranged in the same layer as the source and drain metal layer, and a part is arranged in the same layer as the second gate metal layer, and the first insulating structure layer It includes a first gate insulating layer and a second gate insulating layer.
  • the display panel includes a touch structure layer located on a side of the second insulating structure layer away from the substrate, and the touch structure layer includes a stacking transfer metal layer, a touch The insulating layer and the touch electrode layer, the second crack detection line and the touch electrode layer are provided in the same layer, or the second crack detection line and the transition metal layer are provided in the same layer.
  • the present disclosure also provides a method for detecting cracks in a display panel.
  • the display panel includes a display area and a peripheral area at the periphery of the display area.
  • the display panel includes a substrate and a first An insulating structure layer, a first crack detection line on the side of the first insulation structure layer away from the substrate, a second insulation structure layer on the side of the first crack detection line away from the substrate, and a The second crack detection line on the side of the two insulating structure layers away from the substrate,
  • the peripheral area includes a first area provided with a binding area, a second area disposed opposite to the first area, and a third area and a second area connected to the first area and the second area and disposed oppositely.
  • the first crack detection line includes a first end point and a second end point located in a first area, and the first crack detection line is disposed in the first area, the second area, the third area, and the display area around the display area.
  • the fourth area is a first end point and a second end point located in a first area, and the first crack detection line is disposed in the first area, the second area, the third area, and the display area around the display area.
  • the second crack detection line includes a third series line and a fourth series line
  • the third series line includes a seventh end point and a ninth end point located in the first area
  • the third series line is located in the first area
  • the fourth series line includes an eighth end point and a tenth end point located in the first area
  • the fourth series line is located in the first area and the fourth area
  • the crack detection method includes:
  • the display panel includes n columns of sub-pixels and n data lines located in the display area, the n columns of sub-pixels are connected to the n data lines, and the display panel further includes A first control unit, a second control unit, and a test control terminal in a region, the first control unit is connected to the test control terminal, the seventh terminal, and the i-th data line, and the second control unit is connected to the The test control terminal, the eighth terminal and the j-th data line are connected, wherein i and j are all natural numbers, 1 ⁇ i ⁇ n, 1 ⁇ j ⁇ n, i and j are different from each other,
  • Applying a detection signal to the ninth terminal, receiving a second output signal output by the seventh terminal, and judging whether a crack occurs at the position where the third series line is located according to the second output signal includes:
  • the nine terminals apply a first level signal, and a conduction signal is applied to the test control terminal.
  • the i-th data line receives the second output signal output by the seventh terminal.
  • Applying a detection signal to the tenth end point, receiving a fourth output signal output by the eighth end point, and judging whether a crack occurs at the position where the fourth series line is located according to the fourth output signal includes:
  • the tenth terminal applies a first level signal, and a conduction signal is applied to the test control terminal.
  • the j-th data line receives the fourth output signal output by the eighth terminal.
  • the present disclosure also provides a method for detecting cracks in a display panel.
  • the display panel includes a display area and a peripheral area at the periphery of the display area.
  • the display panel includes a substrate and a first An insulating structure layer, a first crack detection line on the side of the first insulation structure layer away from the substrate, a second insulation structure layer on the side of the first crack detection line away from the substrate, and a The second crack detection line on the side of the two insulating structure layers away from the substrate,
  • the peripheral area includes a first area provided with a binding area, and a third area and a fourth area oppositely provided on both sides of the first area.
  • the first crack detection line includes a first series circuit and a second series connection.
  • the second crack detection line includes a third series line and a fourth series line
  • the first series line includes a first end and a third end located in a first area
  • the first series line is located in the In the first area and the third area
  • the second series line includes a second end and a fourth end located in the first area
  • the second series line is located in the first area and the fourth area
  • the third series line includes a seventh end point and a ninth end point located in the first area
  • the third series line is located in the first area and the third area
  • the fourth series line includes a seventh end point located in the first area.
  • the eighth end point and the tenth end point, the fourth series line is located in the first area and the fourth area
  • the crack detection method includes:
  • the display panel includes n columns of sub-pixels and n data lines located in the display area, and the n columns of sub-pixels are connected to the n data lines,
  • the display panel also includes a first control unit, a second control unit, a fourth control unit, a fifth control unit, and a test control terminal located in the first area.
  • the first control unit and the test control terminal The seventh terminal is connected to the i-th data line
  • the second control unit is connected to the test control terminal, the eighth terminal, and the j-th data line
  • the fourth control unit is connected to the test control Terminal, the first end point and the xth data line
  • the fifth control unit is connected to the test control end, the second end point and the yth data line, where i, j, x, y are all natural numbers, 1 ⁇ i ⁇ n, 1 ⁇ j ⁇ n, 1 ⁇ x ⁇ n, 1 ⁇ y ⁇ n, and i, j, x, and y are different from each other,
  • the xth data line receives the first output signal output by the first terminal, when the xth data line When the column of sub-pixels is in the first light-emitting state, there is no crack at the position where the first series circuit is located.
  • the x-th column of sub-pixels is in the second light-emitting state, a crack occurs at the position of the first series circuit.
  • the yth data line receives the third output signal output by the second end point, when the yth column sub-pixel When in the first light-emitting state, there is no crack at the position where the second series circuit is located, and when the sub-pixels in the y-th column are in the second light-emitting state, a crack occurs at the position where the second series circuit is located.
  • the i-th data line receives the second output signal output by the seventh terminal, when the i-th column of sub-pixels When in the first light-emitting state, there is no crack at the position where the third series circuit is located, and when the sub-pixel in the i-th column is in the second light-emitting state, a crack occurs at the position where the third series circuit is located.
  • Receiving the fourth output signal of the eighth terminal, and judging whether a crack occurs at the position of the fourth series line according to the fourth output signal includes: the jth data line receives the fourth output signal output by the eighth terminal, when the jth column of sub-pixels When in the first light-emitting state, no crack occurs at the position where the fourth series circuit is located, and when the sub-pixels in the j-th column are in the second light-emitting state, a crack occurs at the position where the fourth series circuit is located.
  • the present disclosure also provides a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of a plane structure of a display panel
  • FIG. 2 is a schematic diagram of a planar structure of a display panel in an exemplary embodiment of the present disclosure
  • Fig. 3 is a schematic diagram of the cross-sectional structure of C-C in Fig. 2;
  • FIG. 4 is a schematic diagram of a planar structure of a display panel in an exemplary embodiment of the present disclosure
  • Fig. 5 is an enlarged schematic diagram of part D in Fig. 4;
  • FIG. 6 is a schematic diagram of a planar structure of a display panel in an exemplary embodiment of the present disclosure
  • Fig. 7 is an enlarged schematic diagram of part E in Fig. 6;
  • FIG. 8 is a schematic diagram of a crack detection method of a display panel in an exemplary embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a crack detection method of a display panel in an exemplary embodiment of the present disclosure.
  • the terms “installed”, “connected”, and “connected” should be interpreted broadly unless otherwise clearly defined and limited. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • installed can be a fixed connection, or a detachable connection, or an integral connection
  • it can be a mechanical connection or an electrical connection
  • it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, channel region, and source electrode .
  • the channel region refers to a region through which current mainly flows.
  • it can be the drain electrode of the first electrode and the source electrode of the second electrode, or it can be the source electrode of the first electrode and the drain electrode of the second electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • electrical connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore also includes a state where an angle of 85° or more and 95° or less is included.
  • FIG. 1 is a schematic diagram of a plane structure of a display panel, which is a display panel adopting FMLOC technology.
  • the display panel may include a display substrate and a touch structure layer on the display substrate.
  • the display substrate may include a base, a driving structure layer on the base, a light emitting structure layer on a side of the driving structure layer away from the base, and an encapsulation layer on a side of the light emitting structure layer away from the base.
  • the touch structure layer is located on the side of the packaging layer away from the substrate.
  • the driving structure layer may include an active layer, a first gate insulating layer, a first gate electrode layer, a second gate insulating layer, a second gate electrode layer, an interlayer insulating layer, and a source and drain electrode layer.
  • the touch structure layer may include a transfer metal layer, a touch insulation layer, and a touch electrode layer that are sequentially stacked.
  • the display panel includes a display area 100 and a peripheral area 200 located at the periphery of the display area 100.
  • the display panel further includes a first crack detection line, which is located in the peripheral area 200 and arranged around the display area 100.
  • the first crack detection line may include a first series line 11, a second series line 12 and a fifth line segment 13.
  • the first crack detection line may be provided in the same layer as the source and drain electrode layer or the second gate electrode layer.
  • the display panel further includes a second crack detection line, which is located in the peripheral area 200 and arranged around the display area 100.
  • the second crack detection line may include a third series line 21 and a fourth series line 22.
  • the second crack detection line can be arranged in the same layer as the touch electrode layer.
  • the third end point M3 of the first series line 11 and the seventh end point M7 of the third series line 21 are connected by a via hole in the peripheral area 200, and the ninth end point M9 of the third series line 21 is connected to the fifth line segment.
  • One end point M3' of 13 is connected by a via hole in the peripheral area 200
  • the other end point M4' of the fifth line segment 13 and the tenth end point M10 of the fourth series line 22 are connected by a via hole in the peripheral area 200
  • the fourth series line 22 The eighth terminal M8 and the fourth terminal M4 of the second series circuit 12 are connected by a via in the peripheral area 200.
  • the first crack detection line and the second crack detection line are connected in series to form an integral loop.
  • a detection signal can be applied to the first terminal M1 through the first solder pad P1, and the output signal of the second terminal M2 can be received through the second solder pad P2. According to the state of the output signal, it can be judged whether the display panel has cracks. . When it is determined that a crack is generated in the peripheral area 200 of the display panel, since the second crack detection line and the first crack detection line are connected in series as an integral loop, it is impossible to determine whether the crack is generated at the position (display substrate) where the first crack detection line is located. The position where the second crack detection line is located (touch structure layer).
  • a detection signal can also be applied through the third solder pad P3 and the fourth solder joint P4.
  • a bright line appears in the display area of the display panel, it is determined that the display panel is cracked.
  • the first series circuit 11 and the third series circuit 21 are connected in series as a whole, and the second series circuit 12 and the third series circuit 22 are connected in series as a whole, although it can be judged whether there are cracks on the left and right sides of the display panel, However, it is still impossible to determine whether the crack is generated on the display substrate or the touch structure layer.
  • the routing of the first crack detection line and the second crack detection line is simple, it can be judged whether there are cracks in the peripheral area of the display panel, but the display substrate and the touch structure layer can only be integrated.
  • For crack detection it is impossible to perform a single-item crack detection, and it is impossible to determine the location of the crack, which is not conducive to the accurate positioning of the crack in the process of product production and related bad analysis, and reduces the production capacity and product performance.
  • FIG. 2 is a schematic diagram of a plan structure of a display panel in an exemplary embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a cross-sectional structure of C-C in FIG. 2.
  • the display panel includes a display area 100 and a peripheral area 200 located at the periphery of the display area 100.
  • the display panel may include a substrate 30, a first insulating structure layer 61 located on the side of the substrate 30, a first crack detection line located on the side of the first insulating structure layer 61 away from the substrate 30, and A crack detection line is located on the side of the second insulating structure layer 62 away from the substrate 30, and a second crack detection line is located on the side of the second insulating structure layer 62 away from the substrate 30.
  • the first crack detection line is located in the peripheral area 200 and is set around the display area 100
  • the second crack detection line is located in the peripheral area 200 and is set around the display area 100.
  • One end of the first crack detection line is configured to receive a detection signal, and the other end is configured to output a first output signal.
  • One end of the second crack detection line is configured to receive a detection signal, and the other end is configured to output a second output signal.
  • the first crack detection line and the second crack detection line are located in different layers, and the first crack detection line is configured to receive the detection signal at one end and generate the first output signal at the other end; the second crack detection line It is configured to receive a detection signal at one end and generate a second output signal at the other end, so that it can be determined whether a crack is generated at the location of the first crack detection line according to the first output signal, and whether a crack is generated at the location of the second crack detection line according to the second output signal , It realizes the separate detection of the cracks at the location of the first crack detection line and the location of the second crack detection line, so that the location of the crack can be detected, which is conducive to the accurate location of the crack in the process of product production and related failure analysis , Improve production capacity and product performance.
  • the display panel includes a driving structure layer 31 located on a side of the substrate 30, a light emitting structure layer 32 located on a side of the driving structure layer 31 away from the substrate 30, and a light emitting structure layer 32 located away from the light emitting structure layer.
  • the driving structure layer 31 includes a thin film transistor
  • the first crack detection line is provided in the same layer as the source and drain metal layers of the thin film transistor
  • the first insulating structure layer may include An insulating layer between adjacent layers of thin film transistors.
  • the driving structure layer may include an active layer on the substrate, a gate insulating layer on the active layer, a gate metal layer on the gate insulating layer, an interlayer insulating layer on the gate metal layer, and an interlayer insulating layer.
  • the source and drain metal layer on the layer, the first crack detection line is located on the interlayer insulating layer.
  • the first insulating structure layer includes a gate insulating layer and an interlayer insulating layer that are sequentially stacked in the peripheral region.
  • the driving structure layer 31 may include an active layer 311, a first gate insulating layer 312, a first gate metal layer 313, and a second gate layer which are sequentially disposed on one side of the substrate 30.
  • the first crack detection line and the source and drain metal layers 317 are provided in the same layer.
  • the first insulating structure layer 61 may include a first gate insulating layer 312, a second gate insulating layer 314, and an interlayer insulating layer 316 that are sequentially stacked in the peripheral region 200.
  • the first crack detection line may be provided in the same layer as the second gate metal layer 315, and the first insulating structure layer 61 may include first gate insulating layers sequentially stacked in the peripheral region 200. Layer 312, the second gate insulating layer 314.
  • a part of the first crack detection line may be provided in the same layer as the source and drain metal layer 317, and a part may be provided in the same layer as the second gate metal layer 315.
  • the first insulating structure layer may be included in the peripheral region 200 sequentially.
  • the first gate insulating layer 312 and the second gate insulating layer 314 are stacked.
  • the touch structure layer 34 includes a transfer metal layer 341, a touch insulation layer 342, and a touch electrode layer 343 that are sequentially stacked.
  • the second crack detection line may be provided in the same layer as the touch electrode layer 343, and the second insulation structure layer 62 may include an encapsulation layer 33 and a touch insulation layer 342 that are sequentially stacked in the peripheral region 200.
  • the second crack detection line may be provided in the same layer as the transit metal layer 341, and the second insulating structure layer 62 may include the encapsulation layer 33 located in the peripheral region 200.
  • the peripheral area 200 includes a first area 201 provided with a binding area, and a third area 203 and a fourth area 204 oppositely provided on both sides of the first area 201.
  • a central axis OO located between the third area 203 and the fourth area 204 may be provided on the display panel.
  • the opposite sides of the central axis OO are the first side close to the third area 203 and the The second side of the four area 204, in FIG. 2, the first side is the left side, and the second side is the right side.
  • the first crack detection line includes a first series line 11 and a second series line 12.
  • the first series line 11 includes a first end point M1 and a second end point M3 located in the first area 201, and the first series line 11 is located in the first area 201 and the third area 203.
  • the second series line 12 includes a second end M2 and a fourth end M4 located in the first area 201, and the second series line 12 is located in the first area 201 and the fourth area 204.
  • one of the first endpoint M1 and the third endpoint M3 is configured to receive the detection signal, and the other is configured to output the first output signal.
  • One of the second terminal M2 and the fourth terminal M4 is configured to receive a detection signal, and the other is configured to output a third output signal.
  • the first output signal can be used to determine whether a crack occurs at the location where the first series circuit 11 is located, and the third output signal can be used to determine whether a crack occurs at the location where the second series circuit 12 is located.
  • the peripheral area 200 further includes a second area 202 disposed opposite to the first area 201, and the first crack detection line further includes a fifth end point M5 and M5 located in the second area 202.
  • the sixth terminal M6 The first end point M1 and the third end point M3 are located on the left side of the central axis O-O, and the second end point M2 and the fourth end point M4 are located on the right side of the central axis O-O.
  • the fifth end point M5 is located on the left side of the central axis O-O, and the sixth end point M6 is located on the right side of the central axis O-O.
  • the first crack detection line includes a first series line 11 and a second series line 12.
  • the first series line 11 includes a first line segment 111 connecting from the first end point M1 to the fifth end point M5 through the third area 203 and a second line segment connecting from the fifth end point M5 to the third end point M3 through the third area 203 112, the first line segment 111 and the second line segment 112 are connected in series to form the first series line 11.
  • the second series line 12 includes a third line segment 121 connecting from the second end point M2 to the sixth end point M6 through the fourth area 204, and a fourth line segment 122 connecting from the sixth end point M6 to the fourth end point M4 through the fourth area 204,
  • the third line segment 121 and the fourth line segment 122 are connected in series to form the second series line 12.
  • the first terminal M1 and the second terminal M2 may be infinitely close to each other but electrically insulated from each other
  • the third terminal M3 and the fourth terminal M4 may be infinitely close to each other but electrically insulated from each other
  • the fifth terminal M5 and the sixth terminal M5 are electrically insulated from each other.
  • the terminals M6 can be infinitely close but are electrically insulated from each other. Therefore, the first crack detection line can cover the peripheral area as much as possible to ensure a more comprehensive crack detection.
  • the first line segment, the second line segment, the third line segment, and the fourth line segment described herein may be straight lines or bent lines, which are not limited here.
  • the serial connection of line segments means that the line segments are connected end to end in sequence.
  • the first series line 11 and the second series line 12 are insulated from each other, as shown in FIG. 2.
  • the third terminal M3 may be configured to receive the detection signal, and the first terminal M1 may be configured to generate the first output signal.
  • the first output signal generated by the first terminal M1 it can be determined whether a crack occurs at the location of the first series circuit 11 (that is, the peripheral area of the display substrate on the left side of the central axis O-O).
  • the first output signal can be compared with the first standard output signal. If the deviation between the first output signal generated by the first terminal M1 and the first standard output signal is within a threshold range, it indicates that the first series circuit 11 is located. There is no crack at the position; if the deviation between the output signal generated by the first end point M1 and the first standard output signal exceeds the threshold range, it indicates that a crack occurs at the position where the first series circuit 11 is located.
  • the fourth terminal M4 may be configured to receive a detection signal, and the second terminal M2 may be configured to generate a third output signal. According to the third output signal generated by the second terminal M2, it can be determined whether a crack occurs at the position of the second series circuit 12 (that is, the peripheral area of the display substrate on the right side of the central axis O-O). For example, the third output signal can be compared with the third standard output signal.
  • the deviation between the third output signal generated by the second terminal M2 and the third standard output signal is within the threshold range, it indicates the position of the second series circuit 12 There is no crack; if the deviation between the output signal generated by the second terminal M2 and the third standard output signal exceeds the threshold range, it indicates that a crack has occurred at the position where the second series circuit 12 is located.
  • the first output signal may be the resistance value of the corresponding series circuit, that is, the resistance value of the first series circuit can be detected by the first terminal M1 and the third terminal M3 to determine the first series circuit. Whether there is a crack at the location of the line. Similarly, the second terminal M2 and the fourth terminal M4 can detect the resistance value of the second series circuit to determine whether a crack occurs at the location of the second series circuit.
  • the detection signal may be a voltage signal
  • the first output signal may be a first output voltage
  • the third output signal may be a third output voltage.
  • the detection signal and the output signal may also be other types of electrical signals, as long as the output signal can be used to determine whether a crack is generated at the location of the corresponding series circuit.
  • the first crack detection line includes a first end point M1 and a second end point M2 located in the first area 201, and the first crack detection line is disposed around the display area 100 at the first end point M1 and the second end point M2.
  • One of the first terminal M1 and the second terminal M2 is configured to receive a detection signal, and the other is configured to output a first output signal. Therefore, it can be determined whether a crack is generated at the position where the first crack detection line is located by the first output signal.
  • the first crack detection line may further include a fifth line segment 13 connecting the third end point M3 and the fourth end point M4, so that the first series line 11 and the fifth line segment 13 It is connected to the second series line 12 as one line.
  • the first terminal M1 may be configured to receive a detection signal
  • the second terminal M2 may be configured to generate a first output signal. According to the output signal generated by the second terminal M2, it can be determined whether a crack is generated at the location of the first crack detection line. For example, the first output signal is compared with the first standard output signal.
  • the deviation between the first output signal generated by the second terminal M2 and the first standard output signal is within a threshold range, it indicates that the position of the first crack detection line is not Cracks are generated; if the deviation between the first output signal generated by the second end M2 and the first standard output signal exceeds the threshold range, it indicates that a crack is generated at the location of the first crack detection line.
  • the first terminal M1 When the first terminal M1 is configured to receive the detection signal and the second terminal M2 is configured to generate the first output signal, it can detect whether a crack occurs in the peripheral area of the display substrate, but the location of the crack in the peripheral area of the display substrate cannot be detected.
  • the third terminal M3 When the third terminal M3 is configured to receive a detection signal, the first terminal M1 is configured to generate a first output signal, the fourth terminal M4 is configured to receive a detection signal, and the second terminal M2 is configured to generate a third output signal, which can detect the display substrate Whether cracks are generated in the peripheral area, and it can be detected which side (left or/and right) of the peripheral area of the display substrate is cracked.
  • the second crack detection line includes a third series line 21 and a fourth series line 22.
  • the third series line 21 includes a seventh end point M7 and a ninth end point M9 located in the first area 201, and the third series line 21 is located in the first area 201 and the third area 203.
  • the fourth series line 22 includes an eighth end point M8 and a tenth end point M10 located in the first area 201, and the fourth series line 22 is located in the first area 201 and the fourth area 204.
  • one of the seventh terminal M7 and the ninth terminal M9 is configured to receive the detection signal, and the other is configured to output the second output signal.
  • One of the eighth endpoint M8 and the tenth endpoint M10 is configured to receive a detection signal, and the other is configured to output a fourth output signal.
  • the second output signal can be used to determine whether a crack occurs at the location of the third series line 21, and the fourth output signal can be used to determine whether a crack occurs at the location where the fourth series line 22 is located.
  • the second crack detection line 10 further includes an eleventh end point M11 and a twelfth end point M12.
  • the seventh end point M7 and the ninth end point M9 are located on the left side of the central axis O-O, and the eighth end point M8 and the tenth end point M10 are located on the right side of the central axis O-O.
  • the eleventh end point M11 and the twelfth end point M12 are located in the second area 202, the eleventh end point M11 is located on the left side of the central axis O-O, and the twelfth end point M12 is located on the right side of the central axis O-O.
  • the second crack detection line includes a third series line 21 and a fourth series line 22.
  • the third series line 21 includes a sixth line segment 211 connected from the seventh terminal M7 to the eleventh terminal M11 through the third region 203, and a second line segment 211 connected from the eleventh terminal M11 to the ninth terminal M9 through the third region 203.
  • the seventh line segment 212, the sixth line segment 211 and the seventh line segment 212 are connected in series to form the third series line 21.
  • the fourth series line 22 includes an eighth line segment 221 connecting from the eighth end point M8 to the twelfth end point M12 through the fourth area 204, and a ninth line segment connecting from the twelfth end point M12 to the tenth end point M10 through the fourth area 204 222, the eighth line segment 221 and the ninth line segment 222 are connected in series to form a fourth series line 22.
  • the seventh terminal M7 and the eighth terminal M8 may be infinitely close to each other but electrically insulated from each other
  • the ninth terminal M9 and the tenth terminal M10 may be infinitely close but electrically insulated from each other
  • the eleventh terminal M11 and the first terminal M11 may be electrically insulated from each other.
  • the twelve terminals M12 can be infinitely close but are electrically insulated from each other. Therefore, the second crack detection line can cover the peripheral area as much as possible to ensure a more comprehensive crack detection.
  • the sixth line segment, the seventh line segment, the eighth line segment, and the ninth line segment described herein may be straight lines or bent lines, which are not limited here.
  • the serial connection of line segments means that the line segments are connected end to end in sequence.
  • the third series line 21 and the fourth series line 22 are insulated from each other, as shown in FIG. 2.
  • the ninth terminal M9 may be configured to receive the detection signal, and the seventh terminal M7 may be configured to generate the second output signal. According to the second output signal generated by the seventh terminal M7, it can be determined whether a crack occurs at the position of the second series circuit 11 (that is, the peripheral area of the touch structure layer on the left side of the central axis O-O). For example, the second output signal can be compared with the second standard output signal.
  • the deviation between the second output signal generated by the seventh terminal M7 and the second standard output signal is within the threshold range, it indicates the position of the second series circuit 21 There is no crack; if the deviation between the second output signal generated by the seventh terminal M7 and the second standard output signal exceeds the threshold range, it indicates that a crack has occurred at the position where the second series circuit 21 is located.
  • the tenth terminal M10 may be configured to receive a detection signal
  • the eighth terminal M8 may be configured to generate a fourth output signal.
  • the fourth output signal generated by the eighth terminal M8 it can be determined whether a crack occurs at the position of the fourth series circuit 22 (that is, the peripheral area of the touch structure layer on the right side of the central axis O-O).
  • the fourth output signal can be compared with the fourth standard output signal. If the deviation between the fourth output signal generated by the eighth terminal M8 and the fourth standard output signal is within the threshold range, it indicates that the fourth series circuit 22 is located. No cracks are generated; if the deviation between the fourth output signal generated by the eighth terminal M8 and the fourth standard output signal exceeds the threshold range, it indicates that a crack is generated at the position where the fourth series circuit 22 is located.
  • the second output signal may be the resistance value of the corresponding series circuit, that is, the resistance value of the third series circuit can be detected by the seventh terminal M7 and the ninth terminal M9 to determine the third series circuit. Whether there are cracks in the location.
  • the resistance value of the fourth series circuit can be detected by the eighth terminal M8 and the tenth terminal M10 to determine whether a crack occurs at the location of the fourth series circuit.
  • the detection signal may be a voltage signal
  • the second output signal may be a second output voltage
  • the fourth output signal may be a fourth output voltage.
  • the detection signal and the output signal may also be other types of electrical signals, as long as the output signal can be used to determine whether a crack is generated at the location of the corresponding series circuit.
  • the second crack detection line includes a seventh end point M7 and an eighth end point M8 located in the first area 201, and the second crack detection line is disposed in the first area around the display area 100. 201, the second area 202, the third area 203, and the fourth area 204.
  • One of the seventh endpoint M7 and the eighth endpoint M8 is configured to receive the detection signal, and the other is configured to output the second output signal. Therefore, it can be judged whether a crack is generated at the position where the second crack detection line is located by the second output signal.
  • the second crack detection line may further include a tenth line segment 23 connecting the ninth end point M9 and the tenth end point M10, so that the third series line 21 and the tenth line segment 23 It is connected to the fourth series line 22 as one line.
  • the seventh terminal M7 may be configured to receive the detection signal
  • the eighth terminal M8 may be configured to generate the second output signal. According to the second output signal generated by the eighth terminal M8, it can be determined whether a crack is generated at the position of the second crack detection line. For example, the second output signal is compared with the second standard output signal.
  • the deviation between the second output signal generated by the eighth terminal M8 and the second standard output signal is within the threshold range, it indicates that the position of the second crack detection line is not Cracks are generated; if the deviation between the second output signal generated by the eighth end point M8 and the second standard output signal exceeds the threshold range, it indicates that a crack is generated at the location of the second crack detection line.
  • the seventh terminal M7 When the seventh terminal M7 is configured to receive the detection signal, and the eighth terminal M8 is configured to generate the second output signal, it can detect whether a crack occurs in the peripheral area of the touch structure layer, but the location of the crack in the peripheral area of the touch structure layer cannot be detected .
  • the ninth terminal M9 When the ninth terminal M9 is configured to receive a detection signal, the seventh terminal M7 is configured to generate a second output signal, the tenth terminal M10 is configured to receive a detection signal, and the eighth terminal M8 is configured to generate a fourth output signal, which can detect the touch structure Whether cracks are generated in the peripheral area of the layer, and which side (left or/and right) of the peripheral area of the touch structure layer can be detected.
  • FIG. 4 is a schematic diagram of a plan structure of a display panel in an exemplary embodiment of the present disclosure
  • FIG. 5 is an enlarged schematic diagram of part D in FIG. 4.
  • the display panel includes a first pad P1 located in the first region 201, and the first terminal M1 is connected to the first pad P1.
  • the first terminal M1 may receive or output a signal through the first bonding pad P1.
  • the display panel further includes a second pad P2 located in the first area 201.
  • the second terminal M2 is connected to the second bonding pad P2.
  • the second terminal M2 can output or receive a signal through the second bonding pad P2.
  • the first terminal M1 receives the detection signal through the first bonding pad P1, and the second terminal M2 outputs the first output signal through the second bonding pad P2.
  • the second terminal M2 receives the detection signal through the second bonding pad P2, and the first terminal M1 outputs the first output signal through the first bonding pad P1.
  • the display panel includes n columns of sub-pixels and n data lines 300 located in the display area 100, and the n data lines 300 are connected to the n columns of sub-pixels.
  • n data lines 300 are connected to n columns of sub-pixels in a one-to-one correspondence.
  • the display panel further includes a third bonding pad P3 located in the first area 201, a first control unit 51, and a test control terminal P5.
  • the ninth terminal M9 is connected to the third bonding pad P3, and the ninth terminal M9 receives the detection signal through the third bonding pad P3.
  • the first control unit 51 is electrically connected to the test control terminal P5, the seventh terminal M7 and the i-th data line.
  • the first control unit 51 is configured to provide the signal of the seventh terminal M7 to the i-th data line under the control of the test control terminal P5 to control the light-emitting state of the i-th column sub-pixels corresponding to the i-th data line. It is determined whether there is a crack at the position where the third series line 21 is located according to the light-emitting state of the sub-pixel in the i-th column.
  • the ninth terminal M9 receives the first level signal through the third bonding pad P3.
  • the first level signal is transmitted to the seventh terminal M7 through the third series line 21,
  • the first control unit 51 provides the signal of the seventh terminal M7 to the i-th data line under the control of the test control terminal P5, and the sub-pixels in the i-th column are in the first light-emitting state under the action of the i-th data line.
  • the first level signal cannot be transmitted to the seventh terminal M7 through the third series line 21.
  • the sub-pixels in the i-th column are in the i-th data line under the action of the i-th data line. Two luminous state. Therefore, when the i-th column of sub-pixels is in the second light-emitting state, it is determined that a crack occurs at the position where the third series line 21 is located.
  • the first light-emitting state may be a dark state
  • the second light-emitting state may be a bright state, that is, when the sub-pixel in the i-th column is a bright line, it indicates that a crack occurs at the position of the third series line 21. .
  • the display panel further includes a fourth pad P4 located in the first area 201 and a second control unit 52.
  • the tenth terminal M10 is connected to the fourth bonding pad P4, and the tenth terminal M10 receives the detection signal through the fourth bonding pad P4.
  • the second control unit 52 is electrically connected to the test control terminal P5, the eighth terminal M8 and the j-th data line.
  • the second control unit 52 is configured to provide the signal of the eighth terminal M8 to the j-th data line under the control of the test control terminal P5 to control the light-emitting state of the j-th column sub-pixels corresponding to the j-th data line. According to the light-emitting state of the sub-pixels in the j-th column, it is determined whether a crack occurs at the position where the fourth series circuit 22 is located.
  • the tenth terminal M10 receives the first level signal (for example +2.5V) through the fourth pad P4.
  • the first level signal is transmitted through the fourth series line 22
  • the second control unit 52 provides the signal of the eighth terminal M8 to the j-th data line under the control of the test control terminal P5.
  • the sub-pixels in the j-th column are under the action of the j-th data line.
  • the first light-emitting state When a crack occurs at the position of the fourth series line 22, the first level signal cannot be transmitted to the eighth terminal M8 through the fourth series line 22.
  • the sub-pixels in the jth column are in the th position under the action of the jth data line. Two luminous state. Therefore, when the sub-pixels in the j-th column are in the second light-emitting state, it is determined that a crack occurs at the position where the fourth series line 22 is located.
  • the first light-emitting state may be a dark state
  • the second light-emitting state may be a bright state, that is, when the sub-pixels in the j-th column are bright lines, it indicates that a crack occurs at the position of the fourth series circuit 22. .
  • first control unit 51 and one second control unit 52 are shown in FIG. 4.
  • the number of the first control unit 51 and the second control unit 52 is not limited to one.
  • the number of the first control unit 51 can be multiple.
  • the number of the second control unit 52 may be multiple.
  • data lines of multiple columns of sub-pixels are respectively connected to the multiple second control units 51 in a one-to-one correspondence. In this way, when a crack occurs at the position of the third series circuit, multiple columns of sub-pixels will appear in the second light-emitting state, and there will be multiple corresponding bright lines in the display area, which is easier to identify.
  • the sub-pixel column corresponding to the first control unit 51 may be located on the same side of the central axis O-O of the display panel as the third series line 21.
  • the third series line 21 is located on the left side of the central axis O-O of the display panel, and the sub-pixel row corresponding to the first control unit 51 is also located on the left side of the central axis O-O.
  • the sub-pixel column corresponding to the second control unit 52 may be located on the same side of the central axis O-O of the display panel as the fourth series line 22.
  • the fourth series line 22 is located on the right side of the central axis O-O, and the sub-pixel row corresponding to the second control unit 52 is also located on the right side of the central axis O-O.
  • the series line and the corresponding sub-pixel column are respectively arranged on opposite sides of the central axis OO, for example, the third series line 21 is located on the left side of the central axis OO and corresponds to the first control unit 51
  • the sub-pixel row of is located on the right side of the central axis OO; the fourth series line 22 is located on the right side of the central axis OO, and the sub-pixel row corresponding to the second control unit 52 is located on the left side of the central axis OO.
  • the first control unit 51 may include a first thin film transistor, the control electrode of the first thin film transistor is connected to the test control terminal P5, and the first electrode of the first thin film transistor is connected to the test control terminal P5.
  • the seven terminal M7 is connected, and the second electrode of the first thin film transistor is connected to the i-th data line.
  • the second control unit 52 may include a second thin film transistor, the control electrode of the second thin film transistor is connected to the test control terminal P5, the first electrode of the second thin film transistor is connected to the eighth terminal M8, and the second electrode of the second thin film transistor is connected to the test control terminal P5.
  • the jth data line is connected.
  • the display panel further includes a plurality of third control units 53 located in the first area 201 and a test data terminal D (D1 or D2).
  • Each third control unit 53 is electrically connected to the test control terminal P5, the test data terminal D, and a data line.
  • the third control unit 53 is configured to provide the signal of the test data terminal D to the corresponding data line under the control of the test control terminal P5, so that the corresponding sub-pixel column is in the first light-emitting state (the first light-emitting state may be a dark state) .
  • the display area of the display panel is in a dark state.
  • the third series line 21 or the fourth series line 22 is broken, the display area appears Bright lines, the bright lines in the dark state picture are easier to identify.
  • test control terminal P5 applies a corresponding control signal (turn-on signal) to the test control terminal P5, so that the first control unit 51, the second control unit 52, and the third control unit 53 are all turned on
  • the test data terminal D applies the first level signal, and applies the first level signal to the third pad P3 and the fourth pad P4.
  • the display area is in the first light-emitting state (dark state).
  • the first level signal may be a high level signal (VGH). In other embodiments, the first level signal may also be a low level signal (VGL).
  • the third control unit 53 may include a third thin film transistor, the control electrode of the third thin film transistor is connected to the test control terminal P5, and the first electrode of the third thin film transistor is connected to the test data line D1 or D2. , The data line of the second pole sub-pixel column of the third thin film transistor is connected.
  • the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, and the test control terminal P5 are all located in the driver integrated circuit (drive IC ) Binding area IC.
  • the driving IC provides the detection signal to the first pad P1 and receives the first output signal output by the second pad P2.
  • the driving IC provides a test control signal to the test control terminal P5 to control the turn-on or turn-off of the first control unit 51, the second control unit 52, and the third control unit 53.
  • the driving IC provides detection signals to the third pad P3 and the fourth pad P4.
  • test data terminals D1 and D2 are located in the flexible circuit board binding area.
  • the flexible circuit board provides test data signals to the test data terminals D1 and D2.
  • the first solder pad P1, the second solder pad P2, the third solder pad P3, the fourth solder joint P4 and the test control terminal P5 are all located in the flexible circuit board binding area FOP.
  • the flexible circuit board provides the detection signal to the first pad P1 and receives the first output signal output by the second pad P2.
  • the flexible circuit board provides a test control signal to the test control terminal P5 to control the on or off of the first control unit 51, the second control unit 52, and the third control unit 53.
  • the flexible circuit board provides detection signals to the third solder pad P3 and the fourth solder joint P4.
  • test data terminals D1 and D2, the third solder pad P3, the fourth solder joint P4, and the test control terminal P5 are all located in the lighting test area ET, so that the test data terminal D1 passes through the lighting test area ET. And D2, the third solder pad P3, the fourth solder joint P4 and the test control terminal P5 provide corresponding electrical signals.
  • the sub-pixel driving circuit may adopt a known driving circuit, as long as it can satisfy that the sub-pixel is in the first light-emitting state when the data line is the first level signal.
  • the first crack detection line and the second crack detection line may be detected at the same time.
  • a detection signal is applied to the first terminal M1 through the first bonding pad P1
  • a detection signal is applied to the ninth terminal M9 through the third bonding pad P3
  • a detection signal is applied to the tenth terminal M10 through the fourth bonding pad P4, Realize the simultaneous detection of the first crack detection line and the second crack detection line.
  • the first crack detection line and the second crack detection line may be detected in a time-sharing manner.
  • the first crack detection line is detected first, and then the second crack detection line is detected, or the second crack detection line is first detected, and then the first crack detection line is detected.
  • a detection signal is applied to the first terminal M1 through the first bonding pad P1, and the second output signal output by the second terminal M2 is received, and the second output signal is used to determine whether a crack occurs at the location of the first crack detection line; then, pass
  • the third bonding pad P3 applies a detection signal to the ninth terminal M9
  • the fourth bonding pad P4 applies a detection signal to the tenth terminal M10 to detect the second crack detection line.
  • the display panel may further include a plurality of sixth thin film transistors 56 and a plurality of seventh thin film transistors 57.
  • the second electrode of each sixth thin film transistor 56 is connected to an odd column data line, and the second electrode of each seventh thin film transistor 57 is connected to an even column data line.
  • the control electrode of the sixth thin film transistor 56 is connected to the first display control line MUX1, and the control electrode of the seventh thin film transistor 57 is connected to the second display control line MUX2.
  • the first electrodes of the thin film transistors corresponding to two adjacent data lines are connected to a display data line source.
  • the wirings located on both sides of the center line O-O are symmetrical.
  • the wiring located on both sides of the neutral line O-O may also be asymmetrical.
  • an off signal is applied to the first display control line MUX1 and the second display control line MUX2, so that the sixth thin film transistor 56 and the seventh thin film transistor 57 are both turned off;
  • a conduction signal is applied to the test control terminal P5, so that the first control unit 51, the second control unit 52, and the third control unit 53 are all turned on, and the signal of the data line is controlled by the corresponding first control unit, second control unit or second control unit.
  • VGH high-level signals
  • a cut-off signal is applied to the test control terminal P5, the first control unit, the second control unit, and the third control unit are all cut off; to the first pad P1, the second pad P2, and the third pad P3
  • the fourth pad P4 applies a high-impedance signal, so that both the first crack detection line and the second crack detection line are in a high-impedance state; a high-level signal (VGH) is applied to the test data terminals D1 and D2; to the first display
  • the control line MUX1 and the second display control line MUX2 apply a turn-on signal, and the signal of the data line is provided by the corresponding sixth thin film transistor 56 or the seventh thin film transistor 57, and the display panel realizes normal display.
  • FIG. 6 is a schematic diagram of a plan structure of a display panel in an exemplary embodiment of the present disclosure
  • FIG. 7 is an enlarged schematic diagram of part E in FIG. 6.
  • the display panel may further include a fourth control unit 54 and a fifth control unit 55 located in the first area 201.
  • the third terminal M3 is connected to the third bonding pad P3, and the third terminal M3 receives the detection signal through the third bonding pad P3.
  • the fourth terminal M4 is connected to the fourth bonding pad P4, and the fourth terminal M4 receives the detection signal through the fourth bonding pad P4.
  • the fourth control unit 54 is electrically connected to the test control terminal P5, the first terminal M1 and the xth data line.
  • the fourth control unit 54 is configured to provide the signal of the first terminal M1 to the xth data line under the control of the test control terminal P5 to control the light emitting state of the xth column sub-pixels corresponding to the xth data line. It is determined whether there is a crack at the position where the first series line 11 is located according to the light-emitting state of the sub-pixels in the x-th column.
  • the third terminal M3 receives the first level signal through the third bonding pad P3, and when there is no crack at the position where the first series line 11 is located, the first level signal is transmitted to the first terminal M1 through the first series line 11 ,
  • the fourth control unit 54 provides the signal of the first terminal M1 to the x-th data line under the control of the test control terminal P5, and the sub-pixels in the x-th column are in the first light-emitting state under the action of the x-th data line .
  • the first level signal cannot be transmitted to the first terminal M1 through the first series line 11.
  • the sub-pixel in the xth column is under the action of the xth data line The second light-emitting state. Therefore, when the sub-pixels in the x-th column are in the second light-emitting state, it is determined that a crack is generated at the position where the first series line 11 is located. In other words, when the x-th column of sub-pixels is a bright line, it means that a crack occurs at the position where the first series circuit 11 is located.
  • the fourth terminal M4 is connected to the fourth bonding pad P4, and the fourth terminal M4 receives the detection signal through the fourth bonding pad P4.
  • the fourth terminal M4 is connected to the fourth bonding pad P4, and the fourth terminal M4 receives the detection signal through the fourth bonding pad P4.
  • the fifth control unit 55 is electrically connected to the test control terminal P5, the second terminal M2, and the y-th data line.
  • the fifth control unit 55 is configured to provide a signal of the second terminal M2 to the y-th data line under the control of the test control terminal P5 to control the light-emitting state of the y-th column sub-pixels corresponding to the y-th data line. According to the light-emitting state of the sub-pixels in the y-th column, it is determined whether a crack occurs at the position where the second series circuit 12 is located.
  • the fourth terminal M4 receives the first level signal through the fourth bonding pad P4.
  • the first level signal is transmitted to the second terminal M2 through the second series line 12.
  • the fifth control unit 55 provides the signal of the second terminal M2 to the y-th data line under the control of the test control terminal P5, and the sub-pixels in the y-th column are in the first light-emitting state under the action of the y-th data line.
  • the first level signal cannot be transmitted to the second terminal M2 through the second series line 12.
  • the sub-pixel in the yth column is in the th Two luminous state.
  • the number of the fourth control unit 54 and the fifth control unit 55 is not limited to one.
  • the number of the fourth control unit 54 can be multiple.
  • the number of the fifth control unit 55 may be multiple.
  • data lines of multiple columns of sub-pixels are respectively connected to the multiple fifth control units 55 in a one-to-one correspondence.
  • the sub-pixel column corresponding to the fourth control unit 54 may be located on the same side of the central axis of the display panel as the first series line 11.
  • the first series circuit 11 is located on the left side of the central axis O-O of the display panel
  • the sub-pixel row corresponding to the fourth control unit 54 is also located on the left side of the central axis O-O.
  • the sub-pixel column corresponding to the fifth control unit 55 may be located on the same side of the central axis O-O of the display panel as the second series line 12.
  • the second series line 12 is located on the right side of the central axis O-O
  • the sub-pixel row corresponding to the fifth control unit 55 is also located on the right side of the central axis O-O.
  • the series line and the corresponding sub-pixel column are respectively arranged on opposite sides of the central axis OO, for example, the first series line 11 is located on the left side of the central axis OO, corresponding to the fourth control unit 54
  • the sub-pixel row of is located on the right side of the central axis OO; the second series line 12 is located on the right side of the central axis OO, and the sub-pixel row corresponding to the fifth control unit 55 is located on the left side of the central axis OO.
  • the fourth control unit 54 may include a fourth thin film transistor, the control electrode of the fourth thin film transistor is connected to the test control terminal P5, and the first electrode of the fourth thin film transistor is connected to the test control terminal P5.
  • One terminal M1 is connected, and the second electrode of the fourth thin film transistor is connected to the xth data line.
  • the fifth control unit 55 may include a fifth thin film transistor, the control electrode of the fifth thin film transistor is connected to the test control terminal P5, the first electrode of the fifth thin film transistor is connected to the second terminal M2, and the second electrode of the fifth thin film transistor is connected to The yth data line is connected.
  • the sub-pixel columns corresponding to the first control unit 51 and the second control unit 52 are all first-color sub-pixel columns, which correspond to the fourth control unit 54 and the fifth control unit 55.
  • the sub-pixel columns are all sub-pixel columns of the second color.
  • the first color and the second color are two different colors. Therefore, the cracked series line can be judged by the color of the bright line. For example, in the crack detection process, when the first color bright line appears on the left side of the central axis OO in the display area, it indicates that a crack has occurred at the position where the third series line 21 is located, and when the second color bright line appears, it indicates that the first series line appears. A crack occurs at the position where the line 11 is located.
  • the colors of the sub-pixel columns corresponding to the first control unit 51, the second control unit 52, the fourth control unit 54 and the fifth control unit 55 can be set as required, as long as they are easy to identify and judge. It is not limited here.
  • the wirings located on both sides of the center line O-O are symmetrical.
  • the wiring located on both sides of the neutral line O-O may also be asymmetrical.
  • the display panel includes n columns of sub-pixels, and i, j, x, and y are all natural numbers between 1 and n and are different from each other.
  • the first thin film transistor, the second thin film transistor, the third thin film transistor, the fourth thin film transistor, the fifth thin film transistor, the sixth thin film transistor, and the seventh thin film transistor can all be P-type thin film transistors, or Both N-type thin film transistors can be used.
  • the turn-on signal of the thin film transistor may be a low-level signal, such as -7V
  • the turn-off signal may be a high-level signal, such as +7V.
  • the turn-on signal of the thin film transistor may be a high-level signal, such as +7V
  • the turn-off signal may be a low-level signal, such as -7V.
  • FIG. 8 is a schematic diagram of a crack detection method of a display panel in an exemplary embodiment of the present disclosure.
  • the display panel includes a display area 100 and a peripheral area 200 located at the periphery of the display area 100, and the display panel includes a substrate and a first insulating layer located on one side of the substrate. Structure layer, a first crack detection line on the side of the first insulation structure layer away from the substrate, a second insulation structure layer on the side of the first crack detection line away from the substrate, and a second insulation structure layer on the side of the first insulation structure layer away from the substrate. The second crack detection line on the side of the insulating structure layer away from the substrate.
  • the peripheral area includes a first area provided with a binding area, a second area disposed opposite to the first area, and a third area and a second area connected to the first area and the second area and disposed oppositely. Four areas.
  • the first crack detection line includes a first end point and a second end point located in a first area, and the first crack detection line is disposed in the first area, the second area, the third area, and the display area around the display area.
  • the fourth area is a first end point and a second end point located in a first area, and the first crack detection line is disposed in the first area, the second area, the third area, and the display area around the display area.
  • the second crack detection line includes a third series line and a fourth series line
  • the third series line includes a seventh end point and a ninth end point located in the first area
  • the third series line is located in the first area
  • the fourth series line includes an eighth end point and a tenth end point located in the first area
  • the fourth series line is located in the first area and the fourth area.
  • the crack detection method includes:
  • the display panel includes n columns of sub-pixels and n data lines located in the display area, and the n columns of sub-pixels and the n data lines are connected in a one-to-one correspondence, so
  • the display panel further includes a first control unit, a second control unit, and a test control terminal located in the first area, the first control unit and the test control terminal, the seventh terminal, and the i-th data line Connected, the second control unit is connected with the test control terminal, the eighth terminal and the j-th data line.
  • Applying a detection signal to the ninth terminal, receiving a second output signal output by the seventh terminal, and judging whether a crack occurs at the position where the third series line is located according to the second output signal includes:
  • the nine terminals apply a first level signal, and a conduction signal is applied to the test control terminal.
  • the i-th data line receives the second output signal output by the seventh terminal.
  • Applying a detection signal to the tenth end point, receiving a fourth output signal output by the eighth end point, and judging whether a crack occurs at the position where the fourth series line is located according to the fourth output signal includes:
  • the tenth terminal applies a first level signal, and a conduction signal is applied to the test control terminal.
  • the j-th data line receives the fourth output signal output by the eighth terminal.
  • FIG. 9 is a schematic diagram of a crack detection method of a display panel in an exemplary embodiment of the present disclosure.
  • the display panel includes a display area and a peripheral area located at the periphery of the display area.
  • the display panel includes a substrate, a first insulating structure layer located on one side of the substrate, and a first insulating structure layer located on the first insulating structure layer.
  • the first crack detection line on the side away from the substrate, the second insulation structure layer on the side of the first crack detection line away from the substrate, and the second insulation structure layer on the side of the second insulation structure layer away from the substrate 2. Crack detection line.
  • the peripheral area includes a first area provided with a binding area, and a third area and a fourth area oppositely provided on both sides of the first area.
  • the first crack detection line includes a first series circuit and a second series connection.
  • the second crack detection line includes a third series line and a fourth series line
  • the first series line includes a first end and a third end located in a first area
  • the first series line is located in the In the first area and the third area
  • the second series line includes a second end and a fourth end located in the first area
  • the second series line is located in the first area and the fourth area
  • the third series line includes a seventh end point and a ninth end point located in the first area
  • the third series line is located in the first area and the third area
  • the fourth series line includes a seventh end point located in the first area.
  • the eighth end point and the tenth end point, the fourth series line is located in the first area and the fourth area.
  • the crack detection method includes:
  • the display panel includes n columns of sub-pixels and n data lines located in the display area, and the n columns of sub-pixels and the n data lines are connected in a one-to-one correspondence.
  • the display panel also includes a first control unit, a second control unit, a fourth control unit, a fifth control unit, and a test control terminal located in the first area.
  • the first control unit and the test control terminal The seventh terminal is connected to the i-th data line, the second control unit is connected to the test control terminal, the eighth terminal, and the j-th data line, and the fourth control unit is connected to the test control
  • the terminal, the first terminal and the xth data line are connected, and the fifth control unit is connected with the test control terminal, the second terminal, and the yth data line.
  • the xth data line receives the first output signal output by the first terminal, when the xth data line When the column of sub-pixels is in the first light-emitting state, no crack occurs at the position where the first series line is located, and when the x-th column of sub-pixels is in the second light-emitting state, a crack occurs at the position where the first series line is located.
  • the yth data line receives the third output signal output by the second end point, when the yth column sub-pixel When in the first light-emitting state, no crack occurs at the position where the second series circuit is located, and when the sub-pixels in the y-th column are in the second light-emitting state, a crack occurs at the position where the second series circuit is located.
  • the i-th data line receives the second output signal output by the seventh terminal, when the i-th column of sub-pixels When in the first light-emitting state, no crack occurs at the position where the third series circuit is located, and when the sub-pixels in the i-th column are in the second light-emitting state, a crack occurs at the position where the third series circuit is located.
  • Receiving the fourth output signal of the eighth terminal, and judging whether a crack occurs at the position of the fourth series line according to the fourth output signal includes: the jth data line receives the fourth output signal output by the eighth terminal, when the jth column of sub-pixels When in the first light-emitting state, no crack occurs at the position where the fourth series circuit is located, and when the sub-pixels in the j-th column are in the second light-emitting state, a crack occurs at the position where the fourth series circuit is located.
  • the embodiments of the present disclosure also provide a display device, which includes the display panel adopting the foregoing embodiments.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

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Abstract

一种显示面板，包括依次设置在基底上的第一绝缘结构层、第一裂纹检测线、第二绝缘结构层和第二裂纹检测线，所述第一裂纹检测线和所述第二裂纹检测线均位于所述周边区且围绕所述显示区设置，第一裂纹检测线的一端配置为接收检测信号，另一端配置为输出第一输出信号，所述第二裂纹检测线的一端配置为接收检测信号，另一端配置为输出第二输出信号。

Description

显示面板及其裂纹检测方法、显示装置
本申请要求于2020年5月27日提交中国专利局、申请号为202010463955.6、发明名称为“显示面板及其裂纹检测方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开实施例涉及但不限于显示技术领域，具体涉及一种显示面板及其裂纹检测方法、显示装置。
背景技术
随着显示装置的发展，有机发光二极体(Organic Light-emitted Diode，OLED)显示技术展现出了巨大的潜力。OLED优良的显示性能使得其具有广泛的应用空间，但技术的发展对屏幕的集成化提出了更高的要求，柔性多层一体化集成触控(Flexible Multi-Layer On Cell，FMLOC)技术将屏幕与触控集成为一体，使得显示装置的集成度大幅提高，FMLOC技术已经成为显示行业的发展趋势。
基板裂纹检测(Panel Crack Detection，PCD)技术已经广泛应用于显示面板检测中。对于采用FMLOC技术的显示面板，如果裂纹检测技术无法区分裂纹发生的位置，将不利于在产品生产和相关不良解析过程中对裂纹的准确定位，将会降低产能和产品性能。
发明概述
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开实施例提供一种显示面板，所述显示面板包括显示区和位于显示区外围的周边区，所述显示面板包括：
基底；
第一绝缘结构层，位于所述基底的一侧；
第一裂纹检测线，位于所述第一绝缘结构层背离所述基底的一侧，所述第一裂纹检测线位于所述周边区且围绕所述显示区设置；
第二绝缘结构层，位于所述第一裂纹检测线背离所述基底的一侧；
第二裂纹检测线，位于所述第二绝缘结构层背离所述基底的一侧，所述第二裂纹检测线位于所述周边区且围绕所述显示区设置，
所述第一裂纹检测线的一端配置为接收检测信号，另一端配置为输出第一输出信号，所述第二裂纹检测线的一端配置为接收检测信号，另一端配置为输出第二输出信号。
在一些可能的实现方式中，所述周边区包括设置有绑定区的第一区域、与所述第一区域相对设置的第二区域，以及连接所述第一区域和所述第二区域且相对设置的第三区域和第四区域，
所述第一裂纹检测线包括位于第一区域的第一端点和第二端点，所述第一裂纹检测线围绕所述显示区设置在所述第一区域、第二区域、第三区域和第四区域，所述第一端点和所述第二端点中的一个配置为接收检测信号，另一个配置为输出第一输出信号。
在一些可能的实现方式中，所述周边区包括设置有绑定区的第一区域以及相对设置在所述第一区域两侧的第三区域和第四区域，所述第一裂纹检测线包括第一串联线路和第二串联线路，所述第一串联线路包括位于第一区域的第一端点和第三端点，所述第一串联线路位于所述第一区域和所述第三区域，所述第二串联线路包括位于第一区域的第二端点和第四端点，所述第二串联线路位于所述第一区域和所述第四区域，
所述第一端点和所述第三端点中的一个配置为接收检测信号，另一个配置为输出第一输出信号，
所述第二端点和所述第四端点中的一个配置为接收检测信号，另一个配置为输出第三输出信号。
在一些可能的实现方式中，所述显示面板包括位于显示区的n列子像素 和n条数据线，所述n列子像素和所述n条数据线连接，
所述显示面板还包括位于所述第一区域的第四控制单元和测试控制端，所述第三端点配置为接收检测信号，所述第四控制单元与所述测试控制端、所述第一端点和第x条数据线连接，所述第四控制单元配置为在所述测试控制端信号的控制下，向第x条数据线提供所述第一端点的信号，以控制第x列子像素的发光状态，其中，x为自然数，1≤x≤n。
在一些可能的实现方式中，所述显示面板还包括位于所述第一区域的第五控制单元，所述第四端点配置为接收检测信号，所述第五控制单元与所述测试控制端、所述第二端点和第y条数据线连接，所述第五控制单元配置为在所述测试控制端信号的控制下，向第y条数据线提供所述第二端点的信号，以控制第y列子像素的发光状态，其中，y为自然数，1≤y≤n。
在一些可能的实现方式中，所述周边区包括设置有绑定区的第一区域、与所述第一区域相对设置的第二区域，以及连接所述第一区域和所述第二区域且相对设置的第三区域和第四区域，
所述第二裂纹检测线包括位于第一区域的第七端点和第八端点，所述第二裂纹检测线围绕所述显示区设置在所述第一区域、第二区域、第三区域和第四区域，所述第七端点和所述第八端点中的一个配置为接收检测信号，另一个配置为输出第二输出信号。
在一些可能的实现方式中，所述周边区包括设置有绑定区的第一区域以及相对设置在所述第一区域两侧的第三区域和第四区域，所述第二裂纹检测线包括第三串联线路和第四串联线路，所述第三串联线路包括位于第一区域的第七端点和第九端点，所述第三串联线路位于所述第一区域和所述第三区域，所述第四串联线路包括位于第一区域的第八端点和第十端点，所述第四串联线路位于所述第一区域和所述第四区域，
所述第七端点和所述第九端点中的一个配置为接收检测信号，另一个配置为输出第二输出信号，
所述第八端点和所述第十端点中的一个配置为接收检测信号，另一个配置为输出第四输出信号。
在一些可能的实现方式中，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线连接，
所述显示面板还包括位于所述第一区域的第一控制单元和测试控制端，所述第九端点配置为接收检测信号，所述第一控制单元与所述测试控制端、所述第七端点和第i条数据线连接，所述第一控制单元配置为在所述测试控制端信号的控制下，向第i条数据线提供所述第七端点的信号，以控制第i列子像素的发光状态，其中，i为自然数，1≤i≤n。
在一些可能的实现方式中，所述显示面板还包括位于所述第一区域的第二控制单元，所述第十端点配置为接收检测信号，所述第二控制单元与所述测试控制端、所述第八端点和第j条数据线连接，所述第二控制单元配置为在所述测试控制端信号的控制下，向第j条数据线提供所述第八端点的信号，以控制第j列子像素的发光状态，其中，j为自然数，1≤j≤n。
在一些可能的实现方式中，所述显示面板还包括位于所述第一区域的多个第三控制单元和测试数据端，每个所述第三控制单元与所述测试控制端、测试数据端和一条数据线连接，所述第三控制单元配置为在所述测试控制端信号的控制下，向对应的数据线提供所述测试数据端的信号，以控制对应子像素列处于第一发光状态。
在一些可能的实现方式中，所述显示面板包括位于所述基底一侧的驱动结构层，所述驱动结构层包括薄膜晶体管，所述第一裂纹检测线与所述薄膜晶体管的源漏金属层同层设置，所述第一绝缘结构层包括设置在所述薄膜晶体管相邻层之间的绝缘层；或者，
所述显示面板包括位于所述基底一侧的驱动结构层，所述驱动结构层包括有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层、层间绝缘层和源漏金属层，所述第一裂纹检测线与所述源漏金属层同层设置，所述第一绝缘结构层包括第一栅绝缘层、第二栅绝缘层和层间绝缘层；或者，
所述显示面板包括位于所述基底一侧的驱动结构层，所述驱动结构层包括有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层、层间绝缘层和源漏金属层，所述第一裂纹检测线与所述第二栅金属层同层设置，所述第一绝缘结构层包括第一栅绝缘层和第二栅绝缘层；或者，
所述显示面板包括位于所述基底一侧的驱动结构层，所述驱动结构层包括有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层、层间绝缘层和源漏金属层，所述第一裂纹检测线的一部分与所述源漏金属层同层设置，一部分与所述第二栅金属层同层设置，所述第一绝缘结构层包括第一栅绝缘层和第二栅绝缘层。
在一些可能的实现方式中，所述显示面板包括位于所述第二绝缘结构层背离所述基底一侧的触控结构层，所述触控结构层包括层叠设置的转接金属层、触控绝缘层和触控电极层，所述第二裂纹检测线与所述触控电极层同层设置，或者，所述第二裂纹检测线与所述转接金属层同层设置。
另一方面，本公开还提供了一种显示面板的裂纹检测方法，所述显示面板包括显示区和位于显示区外围的周边区，所述显示面板包括基底、位于所述基底一侧的第一绝缘结构层、位于所述第一绝缘结构层背离所述基底一侧的第一裂纹检测线、位于所述第一裂纹检测线背离所述基底一侧的第二绝缘结构层以及位于所述第二绝缘结构层背离所述基底一侧的第二裂纹检测线，
所述周边区包括设置有绑定区的第一区域、与所述第一区域相对设置的第二区域，以及连接所述第一区域和所述第二区域且相对设置的第三区域和第四区域，
所述第一裂纹检测线包括位于第一区域的第一端点和第二端点，所述第一裂纹检测线围绕所述显示区设置在所述第一区域、第二区域、第三区域和第四区域，
所述第二裂纹检测线包括第三串联线路和第四串联线路，所述第三串联线路包括位于第一区域的第七端点和第九端点，所述第三串联线路位于所述第一区域和所述第三区域，所述第四串联线路包括位于第一区域的第八端点和第十端点，所述第四串联线路位于所述第一区域和所述第四区域，
所述裂纹检测方法，包括：
向所述第一端点施加检测信号，接收所述第二端点输出的第一输出信号，根据所述第一输出信号判断所述第一裂纹检测线所在的位置是否产生裂纹；
向所述第九端点、所述第十端点施加检测信号，接收所述第七端点输出 的第二输出信号、所述第八端点输出的第四输出信号，根据所述第二输出信号判断所述第三串联线路所在的位置是否产生裂纹，根据所述第四输出信号判断所述第四串联线路所在的位置是否产生裂纹。
在一些可能的实现方式中，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线连接，所述显示面板还包括位于所述第一区域的第一控制单元、第二控制单元和测试控制端，所述第一控制单元与所述测试控制端、所述第七端点和第i条数据线连接，所述第二控制单元与所述测试控制端、所述第八端点和第j条数据线连接，其中，i、j均为自然数，1≤i≤n，1≤j≤n，i、j互不相同，
向所述第九端点施加检测信号，接收所述第七端点输出的第二输出信号，根据所述第二输出信号判断所述第三串联线路所在的位置是否产生裂纹，包括：向所述第九端点施加第一电平信号，向所述测试控制端施加导通信号，第i条数据线接收第七端点输出的第二输出信号，当第i列子像素处于第一发光状态时，第三串联线路所在的位置未产生裂纹，当第i列子像素处于第二发光状态时，第三串联线路所在位置产生裂纹，
向所述第十端点施加检测信号，接收所述第八端点输出的第四输出信号，根据所述第四输出信号判断所述第四串联线路所在的位置是否产生裂纹，包括：向所述第十端点施加第一电平信号，向所述测试控制端施加导通信号，第j条数据线接收第八端点输出的第四输出信号，当第j列子像素处于第一发光状态时，第四串联线路所在的位置未产生裂纹，当第j列子像素处于第二发光状态时，第四串联线路所在位置产生裂纹。
又一方面，本公开还提供了一种显示面板的裂纹检测方法，所述显示面板包括显示区和位于显示区外围的周边区，所述显示面板包括基底、位于所述基底一侧的第一绝缘结构层、位于所述第一绝缘结构层背离所述基底一侧的第一裂纹检测线、位于所述第一裂纹检测线背离所述基底一侧的第二绝缘结构层以及位于所述第二绝缘结构层背离所述基底一侧的第二裂纹检测线，
所述周边区包括设置有绑定区的第一区域以及相对设置在所述第一区域两侧的第三区域和第四区域，所述第一裂纹检测线包括第一串联线路和第二串联线路，所述第二裂纹检测线包括第三串联线路和第四串联线路，所述第 一串联线路包括位于第一区域的第一端点和第三端点，所述第一串联线路位于所述第一区域和所述第三区域，所述第二串联线路包括位于第一区域的第二端点和第四端点，所述第二串联线路位于所述第一区域和所述第四区域，所述第三串联线路包括位于第一区域的第七端点和第九端点，所述第三串联线路位于所述第一区域和所述第三区域，所述第四串联线路包括位于第一区域的第八端点和第十端点，所述第四串联线路位于所述第一区域和所述第四区域，
所述裂纹检测方法，包括：
向第三端点、第四端点、第九端点和第十端点施加检测信号；
接收第一端点的第一输出信号、第二端点的第三输出信号、第七端点的第二输出信号和第八端点的第四输出信号，根据第一输出信号判断第一串联线路所在的位置是否产生裂纹，根据第三输出信号判断第二串联线路所在的位置是否产生裂纹，根据第二输出信号判断第三串联线路所在的位置是否产生裂纹，根据第四输出信号判断第四串联线路是否产生裂纹。
在一些可能的实现方式中，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线连接，
所述显示面板还包括位于所述第一区域的第一控制单元、第二控制单元、第四控制单元、第五控制单元和测试控制端，所述第一控制单元与所述测试控制端、所述第七端点和第i条数据线连接，所述第二控制单元与所述测试控制端、所述第八端点和第j条数据线连接，所述第四控制单元与所述测试控制端、所述第一端点和第x条数据线连接，所述第五控制单元与所述测试控制端、所述第二端点和第y条数据线连接，其中，i、j、x、y均为自然数，1≤i≤n，1≤j≤n，1≤x≤n，1≤y≤n，且i、j、x、y互不相同，
接收第一端点的第一输出信号，根据第一输出信号判断第一串联线路所在的位置是否产生裂纹，包括：第x条数据线接收第一端点输出的第一输出信号，当第x列子像素处于第一发光状态时，第一串联线路所在的位置未产生裂纹，当第x列子像素处于第二发光状态时，第一串联线路所在位置产生裂纹，
接收第二端点的第三输出信号，根据第三输出信号判断第二串联线路所在的位置是否产生裂纹，包括：第y条数据线接收第二端点输出的第三输出信号，当第y列子像素处于第一发光状态时，第二串联线路所在的位置未产生裂纹，当第y列子像素处于第二发光状态时，第二串联线路所在位置产生裂纹，
接收第七端点的第二输出信号，根据第二输出信号判断第三串联线路所在的位置是否产生裂纹，包括：第i条数据线接收第七端点输出的第二输出信号，当第i列子像素处于第一发光状态时，第三串联线路所在的位置未产生裂纹，当第i列子像素处于第二发光状态时，第三串联线路所在位置产生裂纹，
接收第八端点的第四输出信号，根据第四输出信号判断第四串联线路所在的位置是否产生裂纹，包括：第j条数据线接收第八端点输出的第四输出信号，当第j列子像素处于第一发光状态时，第四串联线路所在的位置未产生裂纹，当第j列子像素处于第二发光状态时，第四串联线路所在位置产生裂纹。
再一方面，本公开还提供了一种显示装置，包括以上所述的显示面板。
本公开技术方案的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开技术方案而了解。本公开技术方案的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示面板的平面结构示意图；
图2为本公开一个示例性实施例中显示面板的平面结构示意图；
图3为图2中的C-C截面结构示意图；
图4为本公开一个示例性实施例中显示面板的平面结构示意图；
图5为图4中D部分的放大示意图；
图6为本公开一个示例性实施例中显示面板的平面结构示意图；
图7为图6中E部分的放大示意图；
图8为本公开一个示例性实施例中显示面板的裂纹检测方法的示意图；
图9为本公开一个示例性实施例中显示面板的裂纹检测方法的示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本文中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本文中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据 情况可以适当地更换。
在本文中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开中的含义。
在本文中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本说明书中，沟道区域是指电流主要流过的区域。
在本文中，可以是第一极为漏电极、第二极为源电极，或者可以是第一极为源电极、第二极为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本文中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本文中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
图1为一种显示面板的平面结构示意图，该显示面板为采用FMLOC技术的显示面板。显示面板可以包括显示基板和位于显示基板上的触控结构层。显示基板可以包括基底、位于基底上的驱动结构层、位于驱动结构层背离基底一侧的发光结构层、位于发光结构层背离基底一侧的封装层。触控结构层位于封装层背离基底的一侧。驱动结构层可以包括有源层、第一栅绝缘层、 第一栅电极层、第二栅绝缘层、第二栅电极层、层间绝缘层和源漏电极层。触控结构层可以包括依次层叠的转接金属层、触控绝缘层和触控电极层。如图1所示，显示面板包括显示区100和位于显示区100外围的周边区200。显示面板还包括第一裂纹检测线，第一裂纹检测线位于周边区200且围绕显示区100设置。第一裂纹检测线可以包括第一串联线路11、第二串联线路12和第五线段13。第一裂纹检测线可以与源漏电极层或第二栅电极层同层设置。显示面板还包括第二裂纹检测线，第二裂纹检测线位于周边区200且围绕显示区100设置。第二裂纹检测线可以包括第三串联线路21、第四串联线路22。第二裂纹检测线可以与触控电极层同层设置。
如图1所示，第一串联线路11的第三端点M3与第三串联线路21的第七端点M7通过周边区200的过孔连接，第三串联线路21的第九端点M9与第五线段13的一个端点M3’通过周边区200的过孔连接，第五线段13的另一个端点M4’与第四串联线路22第十端点M10通过周边区200的过孔连接，第四串联线路22的第八端点M8与第二串联线路12的第四端点M4通过周边区200的过孔连接。从而，第一裂纹检测线和第二裂纹检测线串联为一个整体回路。
在进行裂纹检测时，可以通过第一焊垫P1向第一端点M1施加检测信号，通过第二焊垫P2接收第二端点M2的输出信号，根据输出信号的状态可以判断显示面板是否产生裂纹。当判断出显示面板的周边区200产生裂纹时，由于第二裂纹检测线和第一裂纹检测线串联为一个整体回路，无法判断出裂纹产生在第一裂纹检测线所在的位置(显示基板)还是第二裂纹检测线所在的位置(触控结构层)。
在进行裂纹检测时，还可以通过第三焊垫P3和第四焊点P4施加检测信号，当显示面板显示区域出现亮线时，判断显示面板产生裂纹。但由于第一串联线路11和第三串联线路21串联为一个整体，第二串联线路12和第三串联线路22串联为一个整体，虽然可以判断出显示面板的左侧、右侧是否产生裂纹，但仍旧无法判断出裂纹产生在显示基板还是触控结构层。
因此，采用图1所示的显示面板，虽然第一裂纹检测线和第二裂纹检测线的走线简单，可以判断显示面板周边区是否产生裂纹，但只能进行显示基 板与触控结构层一体的裂纹检测，不能进行单一项的裂纹检测，无法判断出裂纹产生的位置，不利于在对产品生产和相关不良解析过程中对裂纹的准确定位，降低了产能和产品性能。
图2为本公开一个示例性实施例中显示面板的平面结构示意图，图3为图2中的C-C截面结构示意图。在一个示例性实施例中，如图2和图3所示，显示面板包括显示区100和位于显示区100外围的周边区200。在垂直于显示面板的方向上，显示面板可以包括基底30、位于基底30一侧的第一绝缘结构层61、位于第一绝缘结构层61背离基底30一侧的第一裂纹检测线、位于第一裂纹检测线背离基底30一侧的第二绝缘结构层62，以及位于第二绝缘结构层62背离基底30一侧的第二裂纹检测线。第一裂纹检测线位于周边区200且围绕显示区100设置，第二裂纹检测线位于周边区200且围绕显示区100设置。第一裂纹检测线的一端配置为接收检测信号，另一端配置为输出第一输出信号。第二裂纹检测线的一端配置为接收检测信号，另一端配置为输出第二输出信号。
本实施例提出的显示面板，第一裂纹检测线和第二裂纹检测线位于不同层，并且，第一裂纹检测线配置为一端接收检测信号，另一端产生第一输出信号；第二裂纹检测线配置为一端接收检测信号，另一端产生第二输出信号，从而可以根据第一输出信号判断第一裂纹检测线所在位置是否产生裂纹，根据第二输出信号判断第二裂纹检测线所在位置是否产生裂纹，实现了第一裂纹检测线所在位置和第二裂纹检测线所在位置的裂纹的单独检测，从而可以检测出裂纹产生的位置，有利于在对产品生产和相关不良解析过程中对裂纹的准确定位，提高了产能和产品性能。
在一个示例性实施例中，如图3所示，显示面板包括位于基底30一侧的驱动结构层31、位于驱动结构层31背离基底30一侧的发光结构层32、位于发光结构层32背离基底30一侧的封装层33、位于封装层33背离基底一侧的触控结构层34。
在一个示例性实施例中，如图3所示，驱动结构层31包括薄膜晶体管，第一裂纹检测线与薄膜晶体管的源漏金属层同层设置，第一绝缘结构层可以包括设置在所述薄膜晶体管相邻层之间的绝缘层。例如，驱动结构层可以包 括位于基底上的有源层、位于有源层上的栅绝缘层、位于栅绝缘层上的栅金属层、位于栅金属层上的层间绝缘层以及位于层间绝缘层上的源漏金属层，第一裂纹检测线位于层间绝缘层上。第一绝缘结构层包括在周边区依次层叠的栅绝缘层和层间绝缘层。
在一个示例性实施例中，如图3所示，驱动结构层31可以包括依次设置在基底30一侧的有源层311、第一栅绝缘层312、第一栅金属层313、第二栅绝缘层314、第二栅金属层315、层间绝缘层316和源漏金属层317。第一裂纹检测线与源漏金属层317同层设置，第一绝缘结构层61可以包括在周边区200依次层叠的第一栅绝缘层312、第二栅绝缘层314和层间绝缘层316。
在一个示例性实施例中，如图3所示，第一裂纹检测线可以与第二栅金属层315同层设置，第一绝缘结构层61可以包括在周边区200依次层叠的第一栅绝缘层312、第二栅绝缘层314。
在一个示例性实施例中，第一裂纹检测线的一部分可以与源漏金属层317同层设置，一部分与第二栅金属层315同层设置，第一绝缘结构层可以包括在周边区200依次层叠的第一栅绝缘层312、第二栅绝缘层314。
在一个示例性实施例中，如图3所示，触控结构层34包括依次层叠设置的转接金属层341、触控绝缘层342和触控电极层343。第二裂纹检测线可以与触控电极层343同层设置，第二绝缘结构层62可以包括在周边区200依次层叠的封装层33和触控绝缘层342。在一个示例性实施例中，第二裂纹检测线可以与转接金属层341同层设置，第二绝缘结构层62可以包括位于周边区200的封装层33。
在一个示例性实施例中，如图2所示，周边区200包括设置有绑定区的第一区域201，以及相对设置在第一区域201两侧的第三区域203和第四区域204。为了更好地说明，可以在显示面板上设置位于第三区域203和第四区域204之间的中轴线O-O，中轴线O-O的相对两侧分别为靠近第三区域203的第一侧和靠近第四区域204的第二侧，在图2中，第一侧为左侧，第二侧为右侧。
在一个示例性实施例中，如图2所示，第一裂纹检测线包括第一串联线路11和第二串联线路12。第一串联线路11包括位于第一区域201的第一端 点M1和第二端点M3，第一串联线路11位于第一区域201和第三区域203。第二串联线路12包括位于第一区域201的第二端点M2和第四端点M4，第二串联线路12位于第一区域201和第四区域204。
在一个示例性实施例中，第一端点M1和第三端点M3中的一个配置为接收检测信号，另一个配置为输出第一输出信号。第二端点M2和第四端点M4中的一个配置为接收检测信号，另一个配置为输出第三输出信号。通过第一输出信号可以判断第一串联线路11所在的位置是否产生裂纹，通过第三输出信号可以判断第二串联线路12所在的位置是否产生裂纹。
在一个示例性实施例中，如图2所示，周边区200还包括与第一区域201相对设置的第二区域202，第一裂纹检测线还包括位于第二区域202的第五端点M5和第六端点M6。第一端点M1、第三端点M3位于中轴线O-O左侧，第二端点M2、第四端点M4位于中轴线O-O右侧。第五端点M5位于中轴线O-O左侧，第六端点M6位于中轴线O-O右侧。
在一个示例性实施例中，如图2所示，第一裂纹检测线包括第一串联线路11和第二串联线路12。第一串联线路11包括自第一端点M1经过第三区域203连接至第五端点M5的第一线段111和自第五端点M5经过第三区域203连接至第三端点M3的第二线段112，第一线段111和第二线段112串联连接为第一串联线路11。第二串联线路12包括自第二端点M2经过第四区域204连接至第六端点M6的第三线段121和自第六端点M6经过第四区域204连接至第四端点M4的第四线段122，第三线段121和第四线段122串联连接为第二串联线路12。
在一个示例性实施例中，第一端点M1和第二端点M2可以无限接近但彼此电气绝缘，第三端点M3和第四端点M4可以无限接近但彼此电气绝缘，第五端点M5和第六端点M6可以无限接近但彼此电气绝缘。从而，第一裂纹检测线可以尽可能布满周边区，保证裂纹检测更加全面。
本文所述第一线段、第二线段、第三线段和第四线段可以是直线也可以是弯折线，在此不作限定。线段串联连接指的是，线段依次首尾相连。
在一个示例性实施例中，第一串联线路11和第二串联线路12相互绝缘，如图2所示。第三端点M3可以配置为接收检测信号，第一端点M1可以配 置为产生第一输出信号。根据第一端点M1产生的第一输出信号，可以判断第一串联线路11所在位置(即显示基板位于中轴线O-O左侧的周边区)是否产生裂纹。例如，可以将第一输出信号与第一标准输出信号进行比较，如果第一端点M1产生的第一输出信号与第一标准输出信号的偏差在阈值范围内，则表明第一串联线路11所在位置没有产生裂纹；如果第一端点M1产生的输出信号与第一标准输出信号的偏差超出阈值范围，则表明第一串联线路11所在位置产生裂纹。
同样地，第四端点M4可以配置为接收检测信号，第二端点M2可以配置为产生第三输出信号。根据第二端点M2产生的第三输出信号，可以判断第二串联线路12所在位置(即显示基板位于中轴线O-O右侧的周边区)是否产生裂纹。例如，可以将第三输出信号与第三标准输出信号进行比较，如果第二端点M2产生的第三输出信号与第三标准输出信号的偏差在阈值范围内，则表明第二串联线路12所在位置没有产生裂纹；如果第二端点M2产生的输出信号与第三标准输出信号的偏差超出阈值范围，则表明第二串联线路12所在位置产生裂纹。
本领域技术人员可以理解，当串联线路所在位置没有产生裂纹时，串联线路的电阻较小，串联线路为导通状态，串联线路的一端接收检测信号后，另一端产生的输出信号与标准输出信号的偏差很小，偏差位于阈值范围。当串联线路所在位置产生裂纹后，串联线路在裂纹处断开，串联线路电阻较大，串联线路产生的输出信号与标准输出信号的偏差较大，偏差大于阈值范围。本领域技术人员可以理解，标准输出信号和阈值范围可以通过试验或测试的方式获得。
在一个示例性实施例中，第一输出信号可以为对应串联线路的电阻值，也就是说，可以通过第一端点M1和第三端点M3检测第一串联线路的电阻值来判断第一串联线路所在位置是否产生裂纹。同样地，可以通过第二端点M2和第四端点M4检测第二串联线路的电阻值来判断第二串联线路所在位置是否产生裂纹。
在一个示例性实施例中，检测信号可以为电压信号，第一输出信号可以为第一输出电压，第三输出信号可以为第三输出电压。本领域技术人员可以 理解，检测信号和输出信号还可以为其他类型的电信号，只要可以通过输出信号判断对应串联线路所在的位置是否产生裂纹即可。
在一个示例性实施例中，如图2所示，第一裂纹检测线包括位于第一区域201的第一端点M1和第二端点M2，第一裂纹检测线围绕显示区100设置在第一区域201、第二区域202、第三区域203和第四区域204。第一端点M1和第二端点M2中的一个配置为接收检测信号，另一个配置为输出第一输出信号。从而，可以通过第一输出信号判断第一裂纹检测线所在的位置是否产生裂纹。
在一个示例性实施例中，如图2所示，第一裂纹检测线还可以包括连接第三端点M3和第四端点M4的第五线段13，从而，第一串联线路11、第五线段13和第二串联线路12连接为一个线路。第一端点M1可以配置为接收检测信号，第二端点M2可以配置为产生第一输出信号。根据第二端点M2产生的输出信号，可以判断第一裂纹检测线所在位置是否产生裂纹。例如，将第一输出信号与第一标准输出信号进行比较，如果第二端点M2产生的第一输出信号与第一标准输出信号的偏差在阈值范围内，则表明第一裂纹检测线所在位置没有产生裂纹；如果第二端点M2产生的第一输出信号与第一标准输出信号的偏差超出阈值范围，则表明第一裂纹检测线所在位置产生裂纹。
当第一端点M1配置为接收检测信号，第二端点M2配置为产生第一输出信号时，可以检测显示基板周边区是否产生裂纹，但无法检测出显示基板周边区产生裂纹的位置。当第三端点M3配置为接收检测信号，第一端点M1配置为产生第一输出信号，第四端点M4配置为接收检测信号，第二端点M2配置为产生第三输出信号，可以检测显示基板周边区是否产生裂纹，而且，可以检测出显示基板周边区的哪一侧(左侧或/和右侧)产生裂纹。
在一个示例性实施例中，如图2所示，第二裂纹检测线包括第三串联线路21和第四串联线路22。第三串联线路21包括位于第一区域201的第七端点M7和第九端点M9，第三串联线路21位于第一区域201和第三区域203。第四串联线路22包括位于第一区域201的第八端点M8和第十端点M10，第四串联线路22位于第一区域201和第四区域204。
在一个示例性实施例中，第七端点M7和第九端点M9中的一个配置为 接收检测信号，另一个配置为输出第二输出信号。第八端点M8和第十端点M10中的一个配置为接收检测信号，另一个配置为输出第四输出信号。通过第二输出信号可以判断第三串联线路21所在的位置是否产生裂纹，通过第四输出信号可以判断第四串联线路22所在的位置是否产生裂纹。
在一个示例性实施例中，如图2所示，第二裂纹检测线10还包括第十一端点M11和第十二端点M12。第七端点M7、第九端点M9位于中轴线O-O左侧，第八端点M8、第十端点M10位于中轴线O-O右侧。第十一端点M11和第十二端点M12位于第二区域202，第十一端点M11位于中轴线O-O左侧，第十二端点M12位于中轴线O-O右侧。
在一个示例性实施例中，如图2所示，第二裂纹检测线包括第三串联线路21和第四串联线路22。第三串联线路21包括自第七端点M7经过第三区域203连接至第十一端点M11的第六线段211、自第十一端点M11经过第三区域203连接至第九端点M9的第七线段212，第六线段211和第七线段212串联连接为第三串联线路21。第四串联线路22包括自第八端点M8经过第四区域204连接至第十二端点M12的第八线段221、自第十二端点M12经过第四区域204连接至第十端点M10的第九线段222，第八线段221和第九线段222串联连接为第四串联线路22。
在一个示例性实施例中，第七端点M7和第八端点M8可以无限接近但彼此电气绝缘，第九端点M9和第十端点M10可以无限接近但彼此电气绝缘，第十一端点M11和第十二端点M12可以无限接近但彼此电气绝缘。从而，第二裂纹检测线可以尽可能布满周边区，保证裂纹检测更加全面。
本文所述第六线段、第七线段、第八线段和第九线段可以是直线也可以是弯折线，在此不作限定。线段串联连接指的是，线段依次首尾相连。
在一个示例性实施例中，第三串联线路21和第四串联线路22相互绝缘，如图2所示。第九端点M9可以配置为接收检测信号，第七端点M7可以配置为产生第二输出信号。根据第七端点M7产生的第二输出信号，可以判断第二串联线路11所在位置(即触摸结构层位于中轴线O-O左侧的周边区)是否产生裂纹。例如，可以将第二输出信号与第二标准输出信号进行比较，如果第七端点M7产生的第二输出信号与第二标准输出信号的偏差在阈值范 围内，则表明第二串联线路21所在位置没有产生裂纹；如果第七端点M7产生的第二输出信号与第二标准输出信号的偏差超出阈值范围，则表明第二串联线路21所在位置产生裂纹。
同样地，第十端点M10可以配置为接收检测信号，第八端点M8可以配置为产生第四输出信号。根据第八端点M8产生的第四输出信号，可以判断第四串联线路22所在位置(即触摸结构层位于中轴线O-O右侧的周边区)是否产生裂纹。例如，可以将第四输出信号与第四标准输出信号进行比较，如果第八端点M8产生的第四输出信号与第四标准输出信号的偏差在阈值范围内，则表明第四串联线路22所在位置没有产生裂纹；如果第八端点M8产生的第四输出信号与第四标准输出信号的偏差超出阈值范围，则表明第四串联线路22所在位置产生裂纹。
本领域技术人员可以理解，当串联线路所在位置没有产生裂纹时，串联线路的电阻较小，串联线路为导通状态，串联线路的一端接收检测信号后，另一端产生的输出信号与第二标准输出信号的偏差很小，偏差位于阈值范围。当串联线路所在位置产生裂纹后，串联线路在裂纹处断开，串联线路电阻较大，串联线路产生的输出信号与标准输出信号的偏差较大，偏差大于阈值范围。本领域技术人员可以理解，标准输出信号和阈值范围可以通过实现或测试的方式获得。
在一个示例性实施例中，第二输出信号可以为对应串联线路的电阻值，也就是说，可以通过第七端点M7和第九端点M9检测第三串联线路的电阻值来判断第三串联线路所在位置是否产生裂纹。同样地，可以通过第八端点M8和第十端点M10检测第四串联线路的电阻值来判断第四串联线路所在位置是否产生裂纹。
在一个示例性实施例中，检测信号可以为电压信号，第二输出信号可以为第二输出电压，第四输出信号可以为第四输出电压。本领域技术人员可以理解，检测信号和输出信号还可以为其他类型的电信号，只要可以通过输出信号判断对应串联线路所在的位置是否产生裂纹即可。
在一个示例性实施例中，如图2所示，第二裂纹检测线包括位于第一区域201的第七端点M7和第八端点M8，第二裂纹检测线围绕显示区100设 置在第一区域201、第二区域202、第三区域203和第四区域204。第七端点M7和第八端点M8中的一个配置为接收检测信号，另一个配置为输出第二输出信号。从而，可以通过第二输出信号判断第二裂纹检测线所在的位置是否产生裂纹。
在一个示例性实施例中，如图2所示，第二裂纹检测线还可以包括连接第九端点M9和第十端点M10的第十线段23，从而，第三串联线路21、第十线段23和第四串联线路22连接为一个线路。第七端点M7可以配置为接收检测信号，第八端点M8可以配置为产生第二输出信号。根据第八端点M8产生的第二输出信号，可以判断第二裂纹检测线所在位置是否产生裂纹。例如，将第二输出信号与第二标准输出信号进行比较，如果第八端点M8产生的第二输出信号与第二标准输出信号的偏差在阈值范围内，则表明第二裂纹检测线所在位置没有产生裂纹；如果第八端点M8产生的第二输出信号与第二标准输出信号的偏差超出阈值范围，则表明第二裂纹检测线所在位置产生裂纹。
当第七端点M7配置为接收检测信号，第八端点M8配置为产生第二输出信号时，可以检测触控结构层周边区是否产生裂纹，但无法检测出触控结构层周边区产生裂纹的位置。当第九端点M9配置为接收检测信号，第七端点M7配置为产生第二输出信号，第十端点M10配置为接收检测信号，第八端点M8配置为产生第四输出信号，可以检测触控结构层周边区是否产生裂纹，而且，可以检测出触控结构层周边区的哪一侧(左侧或/和右侧)产生裂纹。
图4为本公开一个示例性实施例中显示面板的平面结构示意图，图5为图4中D部分的放大示意图。在一个示例性实施例中，如图4和图5所示，显示面板包括位于第一区域201的第一焊垫P1，第一端点M1与第一焊垫P1连接。第一端点M1可以通过第一焊垫P1接收或输出信号。在一个示例性实施例中，如图4和图5所示，显示面板还包括位于第一区域201的第二焊垫P2。第二端点M2与第二焊垫P2连接。第二端点M2可以通过第二焊垫P2输出或接收信号。在一个示例性实施例中，第一端点M1通过第一焊垫P1接收检测信号，第二端点M2通过第二焊垫P2输出第一输出信号。在一个示 例性实施例中，第二端点M2通过第二焊垫P2接收检测信号，第一端点M1通过第一焊垫P1输出第一输出信号。
在一个示例性实施例中，显示面板包括位于显示区100的n列子像素和n条数据线300，n条数据线300与n列子像素连接。在一个示例性实施例中，n条数据线300与n列子像素一一对应连接。
在一个示例性实施例中，显示面板还包括位于第一区域201的第三焊垫P3、第一控制单元51和测试控制端P5。第九端点M9与第三焊垫P3连接，第九端点M9通过第三焊垫P3接收检测信号。第一控制单元51与测试控制端P5、第七端点M7和第i条数据线电连接。第一控制单元51配置为在测试控制端P5的控制下，向第i条数据线提供第七端点M7的信号，来控制与第i条数据线相对应的第i列子像素的发光状态。通过第i列子像素的发光状态判断第三串联线路21所在的位置是否产生裂纹。
例如，第九端点M9通过第三焊垫P3接收第一电平信号，当第三串联线路21所在位置没有产生裂纹时，第一电平信号通过第三串联线路21传输到第七端点M7，第一控制单元51在测试控制端P5的控制下，将第七端点M7的信号提供给第i条数据线，第i列子像素在第i条数据线的作用下，处于第一发光状态。当第三串联线路21所在位置产生裂纹时，第一电平信号无法通过第三串联线路21传输到第七端点M7，此时，第i列子像素在第i条数据线的作用下，处于第二发光状态。从而，当第i列子像素处于第二发光状态时，判断第三串联线路21所在位置产生裂纹。
在一个示例性实施例中，第一发光状态可以为暗态，第二发光状态可以为亮态，也就是说，当第i列子像素为亮线时，说明第三串联线路21所在位置产生裂纹。
在一个示例性实施例中，显示面板还包括位于第一区域201的第四焊垫P4和第二控制单元52。第十端点M10与第四焊垫P4连接，第十端点M10通过第四焊垫P4接收检测信号。第二控制单元52与测试控制端P5、第八端点M8和第j条数据线电连接。第二控制单元52配置为在测试控制端P5的控制下，向第j条数据线提供第八端点M8的信号，来控制与第j条数据线相对应的第j列子像素的发光状态。通过第j列子像素的发光状态判断第四串 联线路22所在的位置是否产生裂纹。
例如，第十端点M10通过第四焊垫P4接收第一电平信号(例如+2.5V)，当第四串联线路22所在位置没有产生裂纹时，第一电平信号通过第四串联线路22传输到第八端点M8，第二控制单元52在测试控制端P5的控制下，将第八端点M8的信号提供给第j条数据线，第j列子像素在第j条数据线的作用下，处于第一发光状态。当第四串联线路22所在位置产生裂纹时，第一电平信号无法通过第四串联线路22传输到第八端点M8，此时，第j列子像素在第j条数据线的作用下，处于第二发光状态。从而，当第j列子像素处于第二发光状态时，判断第四串联线路22所在位置产生裂纹。
在一个示例性实施例中，第一发光状态可以为暗态，第二发光状态可以为亮态，也就是说，当第j列子像素为亮线时，说明第四串联线路22所在位置产生裂纹。
本领域技术人员可以理解，图4中只示出了一个第一控制单元51和一个第二控制单元52。但第一控制单元51和第二控制单元52的数量并不仅限于一个，第一控制单元51的数量可以为多个，对应地，有多列子像素的数据线分别与多个第一控制单元51一一对应连接。第二控制单元52的数量可以为多个，对应地，有多列子像素的数据线分别与多个第二控制单元51一一对应连接。这样，当第三串联线路所在位置产生裂纹时，便会出现多列子像素处于第二发光状态，显示区域便会有多条对应的亮线，更加容易识别。
在一个示例性实施例中，与第一控制单元51相对应的子像素列可以与第三串联线路21位于显示面板中轴线O-O的同一侧。例如，第三串联线路21位于显示面板中轴线O-O的左侧，与第一控制单元51相对应的子像素列也位于中轴线O-O的左侧。与第二控制单元52相对应的子像素列可以与第四串联线路22位于显示面板中轴线O-O的同一侧。例如，第四串联线路22位于中轴线O-O的右侧，与第二控制单元52相对应的子像素列也位于中轴线O-O的右侧。
在一个示例性实施例中，串联线路与对应的子像素列分别设置在中轴线O-O的相对两侧，例如，第三串联线路21位于中轴线O-O的左侧，与第一控制单元51相对应的子像素列位于中轴线O-O的右侧；第四串联线路22位 于中轴线O-O的右侧，与第二控制单元52相对应的子像素列位于中轴线O-O的左侧。
在一个示例性实施例中，如图4所示，第一控制单元51可以包括第一薄膜晶体管，第一薄膜晶体管的控制极与测试控制端P5连接，第一薄膜晶体管的第一极与第七端点M7连接，第一薄膜晶体管的第二极与第i条数据线连接。第二控制单元52可以包括第二薄膜晶体管，第二薄膜晶体管的控制极与测试控制端P5连接，第二薄膜晶体管的第一极与第八端点M8连接，第二薄膜晶体管的第二极与第j条数据线连接。
在一个示例性实施例中，如图4所示，显示面板还包括多个位于第一区域201的第三控制单元53和测试数据端D(D1或D2)。每个第三控制单元53与测试控制端P5、测试数据端D和一条数据线电连接。第三控制单元53配置为在测试控制端P5的控制下，向对应的数据线提供测试数据端D的信号，使得对应的子像素列处于第一发光状态(第一发光状态可以为暗态)。这样的显示面板，在裂纹检测时，当第二裂纹检测线所在位置没有产生裂纹时，显示面板的显示区处于暗态，当第三串联线路21或第四串联线路22断裂时，显示区域出现亮线，暗态画面中的亮线更容易识别。
例如，对第二裂纹检测线进行检测，向测试控制端P5施加对应的控制信号(导通信号)，使得第一控制单元51、第二控制单元52和第三控制单元53均导通，向测试数据端D(D1或D2)施加第一电平信号，向第三焊垫P3和第四焊点P4施加第一电平信号。当第三串联线路21和第四串联线路22所在位置均未产生裂纹时(即第三串联线路21和第四串联线路22均导通)，显示区域为第一发光状态(暗态)。当中轴线O-O左侧存在亮线时，表明第三串联线路21断开，第三串联线路21所在的位置产生裂纹。当中轴线O-O右侧存在亮线时，表明第四串联线路22断开，第四串联线路22所在的位置产生裂纹。在一个示例性实施例中，第一电平信号可以为高电平信号(VGH)。在其它实施例中，第一电平信号也可以为低电平信号(VGL)。
在一个示例性实施例中，第三控制单元53可以包括第三薄膜晶体管，第三薄膜晶体管的控制极与测试控制端P5连接，第三薄膜晶体管的第一极与测试数据线D1或D2连接，第三薄膜晶体管的第二极子像素列的数据线连接。
在一个示例性实施例中，如图4所示，第一焊垫P1、第二焊垫P2、第三焊垫P3、第四焊点P4和测试控制端P5均位于驱动集成电路(驱动IC)绑定区IC。从而，驱动IC向第一焊垫P1提供检测信号，并接收第二焊垫P2输出的第一输出信号。驱动IC向测试控制端P5提供测试控制信号，来控制第一控制单元51、第二控制单元52和第三控制单元53的导通或截止。驱动IC向第三焊垫P3和第四焊点P4提供检测信号。
在一个示例性实施例中，测试数据端D1和D2位于柔性线路板绑定区。从而，柔性线路板向测试数据端D1和D2提供测试数据信号。
在一个示例性实施例中，第一焊垫P1、第二焊垫P2、第三焊垫P3、第四焊点P4和测试控制端P5均位于柔性线路板绑定区FOP。从而，柔性线路板向第一焊垫P1提供检测信号，并接收第二焊垫P2输出的第一输出信号。柔性线路板向测试控制端P5提供测试控制信号，来控制第一控制单元51、第二控制单元52和第三控制单元53的导通或截止。柔性线路板向第三焊垫P3和第四焊点P4提供检测信号。
在一个示例性实施例中，测试数据端D1和D2、第三焊垫P3、第四焊点P4和测试控制端P5均位于点灯测试区ET，从而，通过点灯测试区ET向测试数据端D1和D2、第三焊垫P3、第四焊点P4和测试控制端P5提供对应的电信号。
本领域技术人员可以理解，子像素驱动电路可以采用已知的驱动电路，只要可以满足当数据线为第一电平信号时，子像素为第一发光状态即可。
在一个示例性实施例中，第一裂纹检测线和第二裂纹检测线可以同时检测。例如，通过第一焊垫P1向第一端点M1施加检测信号，同时，通过第三焊垫P3向第九端点M9施加检测信号，通过第四焊垫P4向第十端点M10施加检测信号，实现第一裂纹检测线和第二裂纹检测线的同时检测。
在一个示例性实施例中，第一裂纹检测线和第二裂纹检测线可以分时检测。例如，先检测第一裂纹检测线，后检测第二裂纹检测线，或者，先检测第二裂纹检测线，后检测第一裂纹检测线。例如，通过第一焊垫P1向第一端点M1施加检测信号，接收第二端点M2输出的第二输出信号，通过第二输出信号判断第一裂纹检测线所在位置是否产生裂纹；然后，通过第三焊垫 P3向第九端点M9施加检测信号，通过第四焊垫P4向第十端点M10施加检测信号，来检测第二裂纹检测线。
在一个示例性实施例中，如图4所述，显示面板还可以包括多个第六薄膜晶体管56和多个第七薄膜晶体管57。每个第六薄膜晶体管56的第二极与一个奇数列数据线连接，每个第七薄膜晶体管57的第二极与一个偶数列数据线连接。第六薄膜晶体管56的控制极与第一显示控制线MUX1连接，第七薄膜晶体管57的控制极与第二显示控制线MUX2连接。相邻两条数据线对应的薄膜晶体管的第一极连接一个显示数据线source。
在一个示例性实施例中，如图4所示，在显示面板中，位于中线O-O两侧的布线对称。本领域技术人员可以理解，在其它实施例中，位于中线O-O两侧的布线也可以不对称。
在一个示例性实施例中，当对显示面板进行裂纹检测时，向第一显示控制线MUX1和第二显示控制线MUX2施加截止信号，使得第六薄膜晶体管56和第七薄膜晶体管57均截止；向测试控制端P5施加导通信号，使得第一控制单元51、第二控制单元52和第三控制单元53均导通，数据线的信号由对应的第一控制单元、第二控制单元或第三控制单元提供；向测试数据端D1和D2施加高电平信号(VGH)，可以进行裂纹检测。
当显示面板正常显示时，向测试控制端P5施加截止信号，第一控制单元、第二控制单元和第三控制单元均截止；向第一焊垫P1、第二焊垫P2、第三焊垫P3第四焊垫P4施加高阻态信号，使得第一裂纹检测线和第二裂纹检测线均处于高阻态；向测试数据端D1和D2施加高电平信号(VGH)；向第一显示控制线MUX1和第二显示控制线MUX2施加导通信号，数据线的信号由对应的第六薄膜晶体管56或第七薄膜晶体管57提供，显示面板实现正常显示。
图6为本公开一个示例性实施例中显示面板的平面结构示意图，图7为图6中E部分的放大示意图。在一个示例性实施例中，如图6和图7所示，显示面板还可以包括位于第一区域201的第四控制单元54和第五控制单元55。第三端点M3与第三焊垫P3连接，第三端点M3通过第三焊垫P3接收检测信号。第四端点M4与第四焊垫P4连接，第四端点M4通过第四焊垫 P4接收检测信号。第四控制单元54与测试控制端P5、第一端点M1和第x条数据线电连接。第四控制单元54配置为在测试控制端P5的控制下，向第x条数据线提供第一端点M1的信号，来控制与第x条数据线相对应的第x列子像素的发光状态。通过第x列子像素的发光状态判断第一串联线路11所在的位置是否产生裂纹。
例如，第三端点M3通过第三焊垫P3接收第一电平信号，当第一串联线路11所在位置没有产生裂纹时，第一电平信号通过第一串联线路11传输到第一端点M1，第四控制单元54在测试控制端P5的控制下，将第一端点M1的信号提供给第x条数据线，第x列子像素在第x条数据线的作用下，处于第一发光状态。当第一串联线路11所在位置产生裂纹时，第一电平信号无法通过第一串联线路11传输到第一端点M1，此时，第x列子像素在第x条数据线的作用下，处于第二发光状态。从而，当第x列子像素处于第二发光状态时，判断第一串联线路11所在位置产生裂纹。也就是说，当第x列子像素为亮线时，说明第一串联线路11所在位置产生裂纹。
如图6和图7所示，第四端点M4与第四焊垫P4连接，第四端点M4通过第四焊垫P4接收检测信号。第四端点M4与第四焊垫P4连接，第四端点M4通过第四焊垫P4接收检测信号。第五控制单元55与测试控制端P5、第二端点M2和第y条数据线电连接。第五控制单元55配置为在测试控制端P5的控制下，向第y条数据线提供第二端点M2的信号，来控制与第y条数据线相对应的第y列子像素的发光状态。通过第y列子像素的发光状态判断第二串联线路12所在的位置是否产生裂纹。
例如，第四端点M4通过第四焊垫P4接收第一电平信号，当第二串联线路12所在位置没有产生裂纹时，第一电平信号通过第二串联线路12传输到第二端点M2，第五控制单元55在测试控制端P5的控制下，将第二端点M2的信号提供给第y条数据线，第y列子像素在第y条数据线的作用下，处于第一发光状态。当第二串联线路12所在位置产生裂纹时，第一电平信号无法通过第二串联线路12传输到第二端点M2，此时，第y列子像素在第y条数据线的作用下，处于第二发光状态。从而，当第y列子像素处于第二发光状态时，判断第二串联线路12所在位置产生裂纹。也就是说，当第y列子像素 为亮线时，说明第二串联线路12所在位置产生裂纹。
本领域技术人员可以理解，图6中只示出了一个第四控制单元54和一个第五控制单元55。但第四控制单元54和第五控制单元55的数量并不仅限于一个，第四控制单元54的数量可以为多个，对应地，有多列子像素的数据线分别与多个第四控制单元54一一对应连接。第五控制单元55的数量可以为多个，对应地，有多列子像素的数据线分别与多个第五控制单元55一一对应连接。
在一个示例性实施例中，与第四控制单元54相对应的子像素列可以与第一串联线路11位于显示面板中轴线的同一侧。例如，第一串联线路11位于显示面板中轴线O-O的左侧，与第四控制单元54相对应的子像素列也位于中轴线O-O的左侧。与第五控制单元55相对应的子像素列可以与第二串联线路12位于显示面板中轴线O-O的同一侧。例如，第二串联线路12位于中轴线O-O的右侧，与第五控制单元55相对应的子像素列也位于中轴线O-O的右侧。
在一个示例性实施例中，串联线路与对应的子像素列分别设置在中轴线O-O的相对两侧，例如，第一串联线路11位于中轴线O-O的左侧，与第四控制单元54相对应的子像素列位于中轴线O-O的右侧；第二串联线路12位于中轴线O-O的右侧，与第五控制单元55相对应的子像素列位于中轴线O-O的左侧。
在一个示例性实施例中，如图6所示，第四控制单元54可以包括第四薄膜晶体管，第四薄膜晶体管的控制极与测试控制端P5连接，第四薄膜晶体管的第一极与第一端点M1连接，第四薄膜晶体管的第二极与第x条数据线连接。第五控制单元55可以包括第五薄膜晶体管，第五薄膜晶体管的控制极与测试控制端P5连接，第五薄膜晶体管的第一极与第二端点M2连接，第五薄膜晶体管的第二极与第y条数据线连接。
在一个示例性实施例中，与第一控制单元51和第二控制单元52相对应的子像素列均为第一颜色子像素列，与第四控制单元54和第五控制单元55相对应的子像素列均为第二颜色子像素列。第一颜色和第二颜色为两种不同的颜色。从而，可以通过亮线的颜色判断产生裂纹的串联线路。例如，在裂 纹检测过程中，当显示区域位于中轴线O-O左侧出现第一颜色亮线时，表明第三串联线路21所在的位置产生裂纹，当出现第二颜色亮线时，表明第一串联线路11所在的位置产生裂纹。
本领域技术人员可以理解，第一控制单元51、第二控制单元52、第四控制单元54和第五控制单元55所对应的子像素列的颜色可以根据需要设置，只要容易识别判断即可，在此不作限定。
在一个示例性实施例中，如图6所示，在显示面板中，位于中线O-O两侧的布线对称。本领域技术人员可以理解，在其它实施例中，位于中线O-O两侧的布线也可以不对称。
本领域技术人员可以理解，上文中的i、j、x和y均为自然数，且互不相同。显示面板包括n列子像素，i、j、x和y均为1至n之间的自然数，且互不相同。
本领域技术人员可以理解，第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管、第六薄膜晶体管和第七薄膜晶体管可以均采用P型薄膜晶体管，也可以均采用N型薄膜晶体管。当采用P性薄膜晶体管时，薄膜晶体管的导通信号可以为低电平信号，例如-7V，截止信号可以为高电平信号，例如+7V。当采用N性薄膜晶体管时，薄膜晶体管的导通信号可以为高电平信号，例如+7V，截止信号可以为低电平信号，例如-7V。
图8为本公开一个示例性实施例中显示面板的裂纹检测方法的示意图。在一个示例性实施例中，如图4所示，所述显示面板包括显示区100和位于显示区100外围的周边区200，所述显示面板包括基底、位于所述基底一侧的第一绝缘结构层、位于所述第一绝缘结构层背离所述基底一侧的第一裂纹检测线、位于所述第一裂纹检测线背离所述基底一侧的第二绝缘结构层以及位于所述第二绝缘结构层背离所述基底一侧的第二裂纹检测线。
所述周边区包括设置有绑定区的第一区域、与所述第一区域相对设置的第二区域，以及连接所述第一区域和所述第二区域且相对设置的第三区域和第四区域。
所述第一裂纹检测线包括位于第一区域的第一端点和第二端点，所述第一裂纹检测线围绕所述显示区设置在所述第一区域、第二区域、第三区域和第四区域。
所述第二裂纹检测线包括第三串联线路和第四串联线路，所述第三串联线路包括位于第一区域的第七端点和第九端点，所述第三串联线路位于所述第一区域和所述第三区域，所述第四串联线路包括位于第一区域的第八端点和第十端点，所述第四串联线路位于所述第一区域和所述第四区域。
如图8所示，所述裂纹检测方法，包括：
向所述第一端点施加检测信号，接收所述第二端点输出的第一输出信号，根据所述第一输出信号判断所述第一裂纹检测线所在的位置是否产生裂纹；
向所述第九端点、所述第十端点施加检测信号，接收所述第七端点输出的第二输出信号、所述第八端点输出的第四输出信号，根据所述第二输出信号判断所述第三串联线路所在的位置是否产生裂纹，根据所述第四输出信号判断所述第四串联线路所在的位置是否产生裂纹。
如图4所示，在一个示例性实施例中，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线一一对应连接，所述显示面板还包括位于所述第一区域的第一控制单元、第二控制单元和测试控制端，所述第一控制单元与所述测试控制端、所述第七端点和第i条数据线连接，所述第二控制单元与所述测试控制端、所述第八端点和第j条数据线连接。
向所述第九端点施加检测信号，接收所述第七端点输出的第二输出信号，根据所述第二输出信号判断所述第三串联线路所在的位置是否产生裂纹，包括：向所述第九端点施加第一电平信号，向所述测试控制端施加导通信号，第i条数据线接收第七端点输出的第二输出信号，当第i列子像素处于第一发光状态时，第三串联线路所在的位置未产生裂纹，当第i列子像素处于第二发光状态时，第三串联线路所在位置产生裂纹。
向所述第十端点施加检测信号，接收所述第八端点输出的第四输出信号，根据所述第四输出信号判断所述第四串联线路所在的位置是否产生裂纹，包 括：向所述第十端点施加第一电平信号，向所述测试控制端施加导通信号，第j条数据线接收第八端点输出的第四输出信号，当第j列子像素处于第一发光状态时，第四串联线路所在的位置未产生裂纹，当第j列子像素处于第二发光状态时，第四串联线路所在位置产生裂纹。
图9为本公开一个示例性实施例中显示面板的裂纹检测方法的示意图。如图6所示，所述显示面板包括显示区和位于显示区外围的周边区，所述显示面板包括基底、位于所述基底一侧的第一绝缘结构层、位于所述第一绝缘结构层背离所述基底一侧的第一裂纹检测线、位于所述第一裂纹检测线背离所述基底一侧的第二绝缘结构层以及位于所述第二绝缘结构层背离所述基底一侧的第二裂纹检测线。
所述周边区包括设置有绑定区的第一区域以及相对设置在所述第一区域两侧的第三区域和第四区域，所述第一裂纹检测线包括第一串联线路和第二串联线路，所述第二裂纹检测线包括第三串联线路和第四串联线路，所述第一串联线路包括位于第一区域的第一端点和第三端点，所述第一串联线路位于所述第一区域和所述第三区域，所述第二串联线路包括位于第一区域的第二端点和第四端点，所述第二串联线路位于所述第一区域和所述第四区域，所述第三串联线路包括位于第一区域的第七端点和第九端点，所述第三串联线路位于所述第一区域和所述第三区域，所述第四串联线路包括位于第一区域的第八端点和第十端点，所述第四串联线路位于所述第一区域和所述第四区域。
如图9所示，所述裂纹检测方法，包括：
向第三端点、第四端点、第九端点和第十端点施加检测信号；
接收第一端点的第一输出信号、第二端点的第三输出信号、第七端点的第二输出信号和第八端点的第四输出信号，根据第一输出信号判断第一串联线路所在的位置是否产生裂纹，根据第三输出信号判断第二串联线路所在的位置是否产生裂纹，根据第二输出信号判断第三串联线路所在的位置是否产生裂纹，根据第四输出信号判断第四串联线路是否产生裂纹。
在一个示例性实施例中，如图6所示，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线一一对应连接。
所述显示面板还包括位于所述第一区域的第一控制单元、第二控制单元、第四控制单元、第五控制单元和测试控制端，所述第一控制单元与所述测试控制端、所述第七端点和第i条数据线连接，所述第二控制单元与所述测试控制端、所述第八端点和第j条数据线连接，所述第四控制单元与所述测试控制端、所述第一端点和第x条数据线连接，所述第五控制单元与所述测试控制端、所述第二端点和第y条数据线连接。
接收第一端点的第一输出信号，根据第一输出信号判断第一串联线路所在的位置是否产生裂纹，包括：第x条数据线接收第一端点输出的第一输出信号，当第x列子像素处于第一发光状态时，第一串联线路所在的位置未产生裂纹，当第x列子像素处于第二发光状态时，第一串联线路所在位置产生裂纹。
接收第二端点的第三输出信号，根据第三输出信号判断第二串联线路所在的位置是否产生裂纹，包括：第y条数据线接收第二端点输出的第三输出信号，当第y列子像素处于第一发光状态时，第二串联线路所在的位置未产生裂纹，当第y列子像素处于第二发光状态时，第二串联线路所在位置产生裂纹。
接收第七端点的第二输出信号，根据第二输出信号判断第三串联线路所在的位置是否产生裂纹，包括：第i条数据线接收第七端点输出的第二输出信号，当第i列子像素处于第一发光状态时，第三串联线路所在的位置未产生裂纹，当第i列子像素处于第二发光状态时，第三串联线路所在位置产生裂纹。
接收第八端点的第四输出信号，根据第四输出信号判断第四串联线路所在的位置是否产生裂纹，包括：第j条数据线接收第八端点输出的第四输出信号，当第j列子像素处于第一发光状态时，第四串联线路所在的位置未产生裂纹，当第j列子像素处于第二发光状态时，第四串联线路所在位置产生裂纹。
本公开实施例还提供了一种显示装置，该显示装置包括采用前述实施例的显示面板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (17)

  1. 一种显示面板，所述显示面板包括显示区和位于显示区外围的周边区，所述显示面板包括：
    基底；
    第一绝缘结构层，位于所述基底的一侧；
    第一裂纹检测线，位于所述第一绝缘结构层背离所述基底的一侧，所述第一裂纹检测线位于所述周边区且围绕所述显示区设置；
    第二绝缘结构层，位于所述第一裂纹检测线背离所述基底的一侧；
    第二裂纹检测线，位于所述第二绝缘结构层背离所述基底的一侧，所述第二裂纹检测线位于所述周边区且围绕所述显示区设置，
    所述第一裂纹检测线的一端配置为接收检测信号，另一端配置为输出第一输出信号，所述第二裂纹检测线的一端配置为接收检测信号，另一端配置为输出第二输出信号。
  2. 根据权利要求1所述的显示面板，其中，所述周边区包括设置有绑定区的第一区域、与所述第一区域相对设置的第二区域，以及连接所述第一区域和所述第二区域且相对设置的第三区域和第四区域，
    所述第一裂纹检测线包括位于第一区域的第一端点和第二端点，所述第一裂纹检测线围绕所述显示区设置在所述第一区域、第二区域、第三区域和第四区域，所述第一端点和所述第二端点中的一个配置为接收检测信号，另一个配置为输出第一输出信号。
  3. 根据权利要求1所述的显示面板，其中，所述周边区包括设置有绑定区的第一区域以及相对设置在所述第一区域两侧的第三区域和第四区域，所述第一裂纹检测线包括第一串联线路和第二串联线路，所述第一串联线路包括位于第一区域的第一端点和第三端点，所述第一串联线路位于所述第一区域和所述第三区域，所述第二串联线路包括位于第一区域的第二端点和第四端点，所述第二串联线路位于所述第一区域和所述第四区域，
    所述第一端点和所述第三端点中的一个配置为接收检测信号，另一个配 置为输出第一输出信号，
    所述第二端点和所述第四端点中的一个配置为接收检测信号，另一个配置为输出第三输出信号。
  4. 根据权利要求3所述的显示面板，其中，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线连接，
    所述显示面板还包括位于所述第一区域的第四控制单元和测试控制端，所述第三端点配置为接收检测信号，所述第四控制单元与所述测试控制端、所述第一端点和第x条数据线连接，所述第四控制单元配置为在所述测试控制端信号的控制下，向第x条数据线提供所述第一端点的信号，以控制第x列子像素的发光状态，其中，x为自然数，1≤x≤n。
  5. 根据权利要求4所述的显示面板，其中，所述显示面板还包括位于所述第一区域的第五控制单元，所述第四端点配置为接收检测信号，所述第五控制单元与所述测试控制端、所述第二端点和第y条数据线连接，所述第五控制单元配置为在所述测试控制端信号的控制下，向第y条数据线提供所述第二端点的信号，以控制第y列子像素的发光状态，其中，y为自然数，1≤y≤n。
  6. 根据权利要求1至5中任意一项所述的显示面板，其中，所述周边区包括设置有绑定区的第一区域、与所述第一区域相对设置的第二区域，以及连接所述第一区域和所述第二区域且相对设置的第三区域和第四区域，
    所述第二裂纹检测线包括位于第一区域的第七端点和第八端点，所述第二裂纹检测线围绕所述显示区设置在所述第一区域、第二区域、第三区域和第四区域，所述第七端点和所述第八端点中的一个配置为接收检测信号，另一个配置为输出第二输出信号。
  7. 根据权利要求1至5中任意一项所述的显示面板，其中，所述周边区包括设置有绑定区的第一区域以及相对设置在所述第一区域两侧的第三区域和第四区域，所述第二裂纹检测线包括第三串联线路和第四串联线路，所述第三串联线路包括位于第一区域的第七端点和第九端点，所述第三串联线路位于所述第一区域和所述第三区域，所述第四串联线路包括位于第一区域的 第八端点和第十端点，所述第四串联线路位于所述第一区域和所述第四区域，
    所述第七端点和所述第九端点中的一个配置为接收检测信号，另一个配置为输出第二输出信号，
    所述第八端点和所述第十端点中的一个配置为接收检测信号，另一个配置为输出第四输出信号。
  8. 根据权利要求7所述的显示面板，其中，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线连接，
    所述显示面板还包括位于所述第一区域的第一控制单元和测试控制端，所述第九端点配置为接收检测信号，所述第一控制单元与所述测试控制端、所述第七端点和第i条数据线连接，所述第一控制单元配置为在所述测试控制端信号的控制下，向第i条数据线提供所述第七端点的信号，以控制第i列子像素的发光状态，其中，i为自然数，1≤i≤n。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括位于所述第一区域的第二控制单元，所述第十端点配置为接收检测信号，所述第二控制单元与所述测试控制端、所述第八端点和第j条数据线连接，所述第二控制单元配置为在所述测试控制端信号的控制下，向第j条数据线提供所述第八端点的信号，以控制第j列子像素的发光状态，其中，j为自然数，1≤j≤n。
  10. 根据权利要求7所述的显示面板，其中，所述显示面板还包括位于所述第一区域的多个第三控制单元和测试数据端，每个所述第三控制单元与所述测试控制端、测试数据端和一条数据线连接，所述第三控制单元配置为在所述测试控制端信号的控制下，向对应的数据线提供所述测试数据端的信号，以控制对应子像素列处于第一发光状态。
  11. 根据权利要求1所述的显示面板，其中，
    所述显示面板包括位于所述基底一侧的驱动结构层，所述驱动结构层包括薄膜晶体管，所述第一裂纹检测线与所述薄膜晶体管的源漏金属层同层设置，所述第一绝缘结构层包括设置在所述薄膜晶体管相邻层之间的绝缘层；或者，
    所述显示面板包括位于所述基底一侧的驱动结构层，所述驱动结构层包括有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层、层间绝缘层和源漏金属层，所述第一裂纹检测线与所述源漏金属层同层设置，所述第一绝缘结构层包括第一栅绝缘层、第二栅绝缘层和层间绝缘层；或者，
    所述显示面板包括位于所述基底一侧的驱动结构层，所述驱动结构层包括有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层、层间绝缘层和源漏金属层，所述第一裂纹检测线与所述第二栅金属层同层设置，所述第一绝缘结构层包括第一栅绝缘层和第二栅绝缘层；或者，
    所述显示面板包括位于所述基底一侧的驱动结构层，所述驱动结构层包括有源层、第一栅绝缘层、第一栅金属层、第二栅绝缘层、第二栅金属层、层间绝缘层和源漏金属层，所述第一裂纹检测线的一部分与所述源漏金属层同层设置，一部分与所述第二栅金属层同层设置，所述第一绝缘结构层包括第一栅绝缘层和第二栅绝缘层。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板包括位于所述第二绝缘结构层背离所述基底一侧的触控结构层，所述触控结构层包括层叠设置的转接金属层、触控绝缘层和触控电极层，所述第二裂纹检测线与所述触控电极层同层设置，或者，所述第二裂纹检测线与所述转接金属层同层设置。
  13. 一种显示面板的裂纹检测方法，所述显示面板包括显示区和位于显示区外围的周边区，所述显示面板包括基底、位于所述基底一侧的第一绝缘结构层、位于所述第一绝缘结构层背离所述基底一侧的第一裂纹检测线、位于所述第一裂纹检测线背离所述基底一侧的第二绝缘结构层以及位于所述第二绝缘结构层背离所述基底一侧的第二裂纹检测线，
    所述周边区包括设置有绑定区的第一区域、与所述第一区域相对设置的第二区域，以及连接所述第一区域和所述第二区域且相对设置的第三区域和第四区域，
    所述第一裂纹检测线包括位于第一区域的第一端点和第二端点，所述第一裂纹检测线围绕所述显示区设置在所述第一区域、第二区域、第三区域和第四区域，
    所述第二裂纹检测线包括第三串联线路和第四串联线路，所述第三串联线路包括位于第一区域的第七端点和第九端点，所述第三串联线路位于所述第一区域和所述第三区域，所述第四串联线路包括位于第一区域的第八端点和第十端点，所述第四串联线路位于所述第一区域和所述第四区域，
    所述裂纹检测方法，包括：
    向所述第一端点施加检测信号，接收所述第二端点输出的第一输出信号，根据所述第一输出信号判断所述第一裂纹检测线所在的位置是否产生裂纹；
    向所述第九端点、所述第十端点施加检测信号，接收所述第七端点输出的第二输出信号、所述第八端点输出的第四输出信号，根据所述第二输出信号判断所述第三串联线路所在的位置是否产生裂纹，根据所述第四输出信号判断所述第四串联线路所在的位置是否产生裂纹。
  14. 根据权利要求13所述的裂纹检测方法，其中，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线连接，所述显示面板还包括位于所述第一区域的第一控制单元、第二控制单元和测试控制端，所述第一控制单元与所述测试控制端、所述第七端点和第i条数据线连接，所述第二控制单元与所述测试控制端、所述第八端点和第j条数据线连接，其中，i、j均为自然数，1≤i≤n，1≤j≤n，i、j互不相同，
    向所述第九端点施加检测信号，接收所述第七端点输出的第二输出信号，根据所述第二输出信号判断所述第三串联线路所在的位置是否产生裂纹，包括：向所述第九端点施加第一电平信号，向所述测试控制端施加导通信号，第i条数据线接收第七端点输出的第二输出信号，当第i列子像素处于第一发光状态时，第三串联线路所在的位置未产生裂纹，当第i列子像素处于第二发光状态时，第三串联线路所在位置产生裂纹，
    向所述第十端点施加检测信号，接收所述第八端点输出的第四输出信号，根据所述第四输出信号判断所述第四串联线路所在的位置是否产生裂纹，包括：向所述第十端点施加第一电平信号，向所述测试控制端施加导通信号，第j条数据线接收第八端点输出的第四输出信号，当第j列子像素处于第一发光状态时，第四串联线路所在的位置未产生裂纹，当第j列子像素处于第二发光状态时，第四串联线路所在位置产生裂纹。
  15. 一种显示面板的裂纹检测方法，所述显示面板包括显示区和位于显示区外围的周边区，所述显示面板包括基底、位于所述基底一侧的第一绝缘结构层、位于所述第一绝缘结构层背离所述基底一侧的第一裂纹检测线、位于所述第一裂纹检测线背离所述基底一侧的第二绝缘结构层以及位于所述第二绝缘结构层背离所述基底一侧的第二裂纹检测线，
    所述周边区包括设置有绑定区的第一区域以及相对设置在所述第一区域两侧的第三区域和第四区域，所述第一裂纹检测线包括第一串联线路和第二串联线路，所述第二裂纹检测线包括第三串联线路和第四串联线路，所述第一串联线路包括位于第一区域的第一端点和第三端点，所述第一串联线路位于所述第一区域和所述第三区域，所述第二串联线路包括位于第一区域的第二端点和第四端点，所述第二串联线路位于所述第一区域和所述第四区域，所述第三串联线路包括位于第一区域的第七端点和第九端点，所述第三串联线路位于所述第一区域和所述第三区域，所述第四串联线路包括位于第一区域的第八端点和第十端点，所述第四串联线路位于所述第一区域和所述第四区域，
    所述裂纹检测方法，包括：
    向第三端点、第四端点、第九端点和第十端点施加检测信号；
    接收第一端点的第一输出信号、第二端点的第三输出信号、第七端点的第二输出信号和第八端点的第四输出信号，根据第一输出信号判断第一串联线路所在的位置是否产生裂纹，根据第三输出信号判断第二串联线路所在的位置是否产生裂纹，根据第二输出信号判断第三串联线路所在的位置是否产生裂纹，根据第四输出信号判断第四串联线路是否产生裂纹。
  16. 根据权利要求15所述的裂纹检测方法，其中，所述显示面板包括位于显示区的n列子像素和n条数据线，所述n列子像素和所述n条数据线连接，
    所述显示面板还包括位于所述第一区域的第一控制单元、第二控制单元、第四控制单元、第五控制单元和测试控制端，所述第一控制单元与所述测试控制端、所述第七端点和第i条数据线连接，所述第二控制单元与所述测试控制端、所述第八端点和第j条数据线连接，所述第四控制单元与所述测试 控制端、所述第一端点和第x条数据线连接，所述第五控制单元与所述测试控制端、所述第二端点和第y条数据线连接，其中，i、j、x、y均为自然数，1≤i≤n，1≤j≤n，1≤x≤n，1≤y≤n，且i、j、x、y互不相同，
    接收第一端点的第一输出信号，根据第一输出信号判断第一串联线路所在的位置是否产生裂纹，包括：第x条数据线接收第一端点输出的第一输出信号，当第x列子像素处于第一发光状态时，第一串联线路所在的位置未产生裂纹，当第x列子像素处于第二发光状态时，第一串联线路所在位置产生裂纹，
    接收第二端点的第三输出信号，根据第三输出信号判断第二串联线路所在的位置是否产生裂纹，包括：第y条数据线接收第二端点输出的第三输出信号，当第y列子像素处于第一发光状态时，第二串联线路所在的位置未产生裂纹，当第y列子像素处于第二发光状态时，第二串联线路所在位置产生裂纹，
    接收第七端点的第二输出信号，根据第二输出信号判断第三串联线路所在的位置是否产生裂纹，包括：第i条数据线接收第七端点输出的第二输出信号，当第i列子像素处于第一发光状态时，第三串联线路所在的位置未产生裂纹，当第i列子像素处于第二发光状态时，第三串联线路所在位置产生裂纹，
    接收第八端点的第四输出信号，根据第四输出信号判断第四串联线路所在的位置是否产生裂纹，包括：第j条数据线接收第八端点输出的第四输出信号，当第j列子像素处于第一发光状态时，第四串联线路所在的位置未产生裂纹，当第j列子像素处于第二发光状态时，第四串联线路所在位置产生裂纹。
  17. 一种显示装置，包括权利要求1至12中任意一项所述的显示面板。
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KR102601650B1 (ko) * 2016-07-26 2023-11-13 삼성디스플레이 주식회사 표시 장치
CN111509026B (zh) 2020-05-27 2023-02-07 京东方科技集团股份有限公司 显示面板及其裂纹检测方法、显示装置
CN112289778B (zh) * 2020-10-28 2023-02-07 京东方科技集团股份有限公司 显示基板、显示装置和用于显示基板的检测方法
CN112419947B (zh) * 2020-11-20 2023-05-26 武汉天马微电子有限公司 一种显示面板及其裂纹检测方法、显示装置
CN117037650A (zh) * 2020-11-27 2023-11-10 武汉天马微电子有限公司 一种显示面板及其检测方法和显示装置
CN112863410A (zh) * 2021-01-11 2021-05-28 京东方科技集团股份有限公司 显示基板、其裂纹检测方法及显示装置
CN113205758A (zh) 2021-04-29 2021-08-03 京东方科技集团股份有限公司 显示模组、裂纹检测方法及显示装置
CN113284443B (zh) * 2021-05-31 2023-03-21 云谷（固安）科技有限公司 显示面板及其测试方法和显示装置
CN116195380A (zh) * 2021-07-19 2023-05-30 京东方科技集团股份有限公司 显示基板、显示装置
CN113552177B (zh) * 2021-07-30 2023-05-12 武汉天马微电子有限公司 显示面板的测试方法、显示面板和显示装置
GB2622336A (en) * 2021-11-29 2024-03-13 Boe Technology Group Co Ltd Display panel and display device
KR20230099264A (ko) * 2021-12-27 2023-07-04 엘지디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치
CN115763431A (zh) * 2022-11-17 2023-03-07 武汉天马微电子有限公司 显示面板及其裂纹检测方法、显示装置
KR20240126487A (ko) * 2023-02-13 2024-08-21 삼성디스플레이 주식회사 표시 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206654A (zh) * 2015-05-26 2016-12-07 三星显示有限公司 显示装置
CN110136618A (zh) * 2019-05-31 2019-08-16 京东方科技集团股份有限公司 一种显示面板检测电路、显示装置和显示面板检测方法
CN111189618A (zh) * 2018-11-15 2020-05-22 三星显示有限公司 显示设备以及该显示设备的检查方法
CN111509026A (zh) * 2020-05-27 2020-08-07 京东方科技集团股份有限公司 显示面板及其裂纹检测方法、显示装置

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6138480B2 (ja) 2012-12-20 2017-05-31 株式会社ジャパンディスプレイ 表示装置
KR102246365B1 (ko) 2014-08-06 2021-04-30 삼성디스플레이 주식회사 표시장치와 그의 제조방법
KR102400302B1 (ko) 2015-09-08 2022-05-23 삼성디스플레이 주식회사 표시 패널 및 이의 점등 검사선 형성 방법
KR102601650B1 (ko) * 2016-07-26 2023-11-13 삼성디스플레이 주식회사 표시 장치
US10522608B2 (en) * 2016-12-06 2019-12-31 Samsung Display Co., Ltd. Display device
KR102056678B1 (ko) * 2017-11-23 2019-12-17 엘지디스플레이 주식회사 유기 발광 표시 장치
CN108417561B (zh) 2018-03-06 2020-05-05 京东方科技集团股份有限公司 一种显示面板以及显示装置
CN110415631B (zh) 2018-04-26 2021-01-15 京东方科技集团股份有限公司 显示面板、显示装置及检测方法
CN110503907B (zh) * 2018-05-17 2024-04-05 京东方科技集团股份有限公司 显示面板及其裂纹检测方法、显示装置
CN109192072A (zh) 2018-10-24 2019-01-11 昆山国显光电有限公司 显示面板和显示装置
CN209199078U (zh) 2019-02-19 2019-08-02 京东方科技集团股份有限公司 触控基板、触控装置及显示装置
CN110673766A (zh) 2019-09-26 2020-01-10 京东方科技集团股份有限公司 一种触控显示面板及其检测方法
CN110634411A (zh) * 2019-11-07 2019-12-31 京东方科技集团股份有限公司 一种显示模组及其封装检测方法
CN111048022A (zh) * 2020-01-06 2020-04-21 京东方科技集团股份有限公司 显示面板、驱动电路板、显示装置及其裂纹检测方法
KR20220007799A (ko) * 2020-07-10 2022-01-19 삼성디스플레이 주식회사 표시장치 및 이의 제조방법
EP4128203A4 (en) * 2021-01-15 2023-05-31 BOE Technology Group Co., Ltd. DISPLAY PANEL, DISPLAY APPARATUS AND METHOD FOR DETECTING CRACKS IN A DISPLAY PANEL
KR20220119222A (ko) * 2021-02-19 2022-08-29 삼성디스플레이 주식회사 표시 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106206654A (zh) * 2015-05-26 2016-12-07 三星显示有限公司 显示装置
CN111189618A (zh) * 2018-11-15 2020-05-22 三星显示有限公司 显示设备以及该显示设备的检查方法
CN110136618A (zh) * 2019-05-31 2019-08-16 京东方科技集团股份有限公司 一种显示面板检测电路、显示装置和显示面板检测方法
CN111509026A (zh) * 2020-05-27 2020-08-07 京东方科技集团股份有限公司 显示面板及其裂纹检测方法、显示装置

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