WO2021233280A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021233280A1
WO2021233280A1 PCT/CN2021/094326 CN2021094326W WO2021233280A1 WO 2021233280 A1 WO2021233280 A1 WO 2021233280A1 CN 2021094326 W CN2021094326 W CN 2021094326W WO 2021233280 A1 WO2021233280 A1 WO 2021233280A1
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WO
WIPO (PCT)
Prior art keywords
conductive
conductive member
sublayer
layer
display panel
Prior art date
Application number
PCT/CN2021/094326
Other languages
English (en)
French (fr)
Inventor
许晨
乔勇
吴新银
马永达
Original Assignee
京东方科技集团股份有限公司
北京京东方技术开发有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方技术开发有限公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020227017324A priority Critical patent/KR20230015871A/ko
Priority to EP21798254.5A priority patent/EP3996146A4/en
Priority to US17/437,142 priority patent/US20230180563A1/en
Priority to JP2022515898A priority patent/JP2023527598A/ja
Publication of WO2021233280A1 publication Critical patent/WO2021233280A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/17—Passive-matrix OLED displays
    • H10K59/179—Interconnections, e.g. wiring lines or terminals
    • H10K59/1795—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED

Definitions

  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • Micro-LED Micro-LED
  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • At least one embodiment of the present disclosure provides a display panel, including: a display area having a plurality of pixel units; a peripheral area located on at least one side of the display area; a barrier layer located on a base substrate; On the side of the barrier layer facing away from the base substrate, the length of the conductive member in its extension direction is greater than the width of the conductive member in the direction intersecting the extension direction, and the conductive member includes a first layer stacked in sequence.
  • the thickness of the layer is smaller than the thickness of the second conductive sublayer, the melting point of the third conductive sublayer is greater than the melting point of the second conductive sublayer, and the second conductive sublayer includes a layer close to the first conductive sublayer.
  • the third conductive sublayer is not in contact with the first conductive sublayer.
  • the second conductive sublayer further includes side edges on the same side of the second conductive sublayer that connect the first surface and the second surface In a cross section taken perpendicular to the extending direction of the conductive member, the intersection of the side and the first conductive sublayer is the first intersection, and the intersection of the side and the third conductive sublayer is At the second intersection, at least a part of the side surface is located on the side of the line between the first intersection and the second intersection that is close to the second conductive sub-layer.
  • the side surface includes at least two sub-side surfaces, and the at least two sub-side surfaces include a first sub-side surface close to the first conductive sub-layer and a third sub-side surface close to the third conductive sub-layer.
  • the second sub-side surface of the electronic layer, the angle formed by the first sub-side surface and the first conductive sub-layer is smaller than the angle formed by the second sub-side surface and the first conductive sub-layer.
  • the intersection of the extension line of the second sub-side surface and the first conductive sub-layer is d1
  • the distance of the first conductive sub-layer beyond the first surface is ⁇ w1, d1 ⁇ w1.
  • the distance of the third conductive sub-layer beyond the second surface is ⁇ w2, d1 ⁇ w2.
  • the angle formed by the second sub-side surface and the first conductive sub-layer is greater than 90 degrees.
  • the side surface includes three sub-side surfaces arranged in sequence, and the three sub-side surfaces include a first sub-side surface, a second sub-side surface, and a third sub-side surface.
  • the sub-side surface is closer to the first conductive sub-layer than the third sub-side surface.
  • the angle formed by the first sub-side surface and the first conductive sub-layer is a first angle.
  • the angle formed by the first conductive sub-layer is a second angle
  • the angle formed by the third sub-side surface and the first conductive sub-layer is a third angle
  • the third angle is greater than the second angle
  • the second angle is greater than the first angle.
  • the second conductive sublayer includes two side surfaces, the two side surfaces are disposed oppositely, and the two side surfaces are symmetrically disposed along the thickness direction of the conductive member .
  • At least one of the first surface, the second surface, and the side surface of the second conductive sublayer includes N element, S element, P element, and At least one of Cl elements.
  • the barrier layer has at least one of an F element and a Cl element.
  • the content of at least one of the F element and the Cl element in the barrier layer is 1 ⁇ 10 18 to 5 ⁇ 10 20 atoms per cubic centimeter.
  • the first surface is in contact with the first conductive sublayer, and the second surface is in contact with the third conductive sublayer.
  • the third conductive sublayer covers the second conductive sublayer and is in contact with the first conductive sublayer.
  • the width of the first surface is smaller than the width of the first conductive sublayer, and the width of the second surface is smaller than the width of the third conductive sublayer, The width difference between the third conductive sublayer and the second surface is greater than the thickness of the third conductive sublayer.
  • two adjacent conductive members are provided, the two adjacent conductive members are insulated from each other, the two adjacent conductive members are located on the same layer, the Two adjacent conductive members include a first conductive member and a second conductive member.
  • the third conductive sublayer of the first conductive member and the third conductive sublayer of the second conductive member are between The pitch is smaller than the pitch between the second surface of the second conductive sublayer of the first conductive member and the second surface of the second conductive sublayer of the second conductive member.
  • the second surface of the first conductive member and the second surface of the second conductive member have different distances at different positions.
  • w1 is the maximum width in the cross section of the first conductive member in the width direction thereof
  • w2 is the maximum width in the cross section of the second conductive member in the width direction thereof
  • ⁇ w11 is the distance of the third conductive sublayer beyond the second surface in the first conductive member
  • ⁇ w12 is the third conductive sublayer beyond the second surface in the second conductive member
  • the distance between the surfaces, dmin is the minimum distance between the first conductive member and the second conductive member, and satisfies the following relationship:
  • two conductive members are provided, the two conductive members are insulated from each other, the distances between the two conductive members and the base substrate are different, and the two conductive members are
  • the member includes a first conductive member and a second conductive member, the thickness of the first conductive member is T3, the thickness of the second conductive member is T4, T4 is greater than T3, and the third conductive member in the first conductive member
  • the distance of the electronic layer beyond the second surface is ⁇ w3
  • the distance of the third conductive sublayer beyond the second surface in the second conductive member is ⁇ w4, which satisfies the following relationship:
  • two conductive members are provided, the two conductive members are insulated from each other, the two conductive members include a first conductive member and a second conductive member, the first The conductive member is closer to the display area than the second conductive member, and the size of the third conductive sublayer protruding from the second surface in the first conductive member is larger than that of the first conductive member in the second conductive member. The size of the three conductive sub-layers protruding from the second surface.
  • the display panel further includes a second conductive portion, wherein the second conductive portion and the conductive member are disposed on different layers, and the conductive member has a first end Portion, the second conductive portion has a second end portion, an insulating layer is provided between the first end portion and the second end portion, and the insulating layer has the first end portion or the first end portion exposed.
  • the first via hole at the two ends, the conductive member is connected to the second conductive portion through the first via hole.
  • the display panel further includes a second conductive portion, and the second conductive portion and the conductive member are located on the same layer.
  • the display panel further includes a third conductive portion, wherein the first conductive portion is electrically connected to the third conductive portion, and the third conductive portion has a third conductive portion.
  • An end portion, the first conductive portion has a fourth end portion, an insulating layer is provided between the third end portion and the fourth end portion, and the insulating layer has an exposed third end portion or the The second via hole of the fourth end portion, the first conductive portion is electrically connected to the third conductive portion through the second via hole.
  • the conductive member includes a first portion and a second portion, the width of the first portion is greater than the width of the second portion, and the third conductive member of the first portion
  • the layer protrudes from the second surface along the width direction of the conductive member, the third conductive sublayer of the second part is flush with the second surface along the width direction of the conductive member, or the first part and
  • the third conductive sublayers of the second part all protrude from the second surface along the width direction of the conductive member, and the protruding width of the first part is greater than the protruding width of the second part.
  • the conductive member and the first conductive portion are electrically connected to provide a plurality of first conductive portions, and there is a first interval between adjacent conductive members, and the adjacent first conductive members There is a second interval between one conductive part, and the first interval is different from the second interval.
  • the first interval is smaller than the second interval.
  • the length of the conductive member is less than the length of the first conductive portion, the first conductive portion includes a data line, and the data line is a pixel unit connected thereto Provide data voltage.
  • each pixel unit includes a pixel circuit layer disposed on the barrier layer, an organic electroluminescent device electrically connected to the pixel circuit layer, and On the touch electrode on the light emitting side of the organic electroluminescence device, the first conductive portion is any one of the pixel circuit layer, the organic electroluminescence element or the touch electrode.
  • At least one embodiment of the present disclosure further provides a display panel, including: a display area having a plurality of pixel units, including a foldable area, and a first display area and a second display area located on opposite sides of the foldable area
  • the peripheral area is located on at least one side of the display area;
  • the barrier layer is located on the base substrate;
  • the conductive member is provided on the side of the barrier layer away from the base substrate, and the conductive member is in its extending direction
  • the length of the conductive member is greater than the width of the conductive member in a direction intersecting the extending direction, and the conductive member includes a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer that are sequentially stacked.
  • the electronic layer is closer to the base substrate than the third conductive sublayer; and a first conductive portion is located in the display area, and the first conductive portion and the conductive member are provided in the same layer and have the same material, wherein,
  • the conductivity of the first conductive sublayer is smaller than the conductivity of the second conductive sublayer and the thickness of the first conductive sublayer is smaller than the thickness of the second conductive sublayer.
  • the melting point is greater than the melting point of the second conductive sublayer.
  • the second conductive sublayer includes a first surface close to the first conductive sublayer and a second surface close to the third conductive sublayer. The surface and the second surface are arranged opposite to each other, the third conductive sub-layer protrudes from the second surface along the width direction of the conductive member, and the width direction intersects the extension direction of the conductive member.
  • two conductive members are provided, the two conductive members are insulated from each other, the two conductive members include a first conductive member and a second conductive member, the first The conductive member is closer to the foldable area than the second conductive member, and the size of the third conductive sublayer in the first conductive member protruding from the second surface is larger than that in the second conductive member The third conductive sublayer protrudes by the size of the second surface.
  • At least one embodiment of the present disclosure further provides a display panel, including: a display area having a plurality of pixel units; a peripheral area located on at least one side of the display area; a light-transmitting area located far from the display area of the peripheral area
  • the barrier layer is located on the base substrate; the conductive member is arranged on the side of the barrier layer away from the base substrate, and the conductive member is in the direction of its extension.
  • the length is greater than the width of the conductive member in a direction intersecting the extension direction, and the conductive member includes a first conductive sublayer, a second conductive sublayer, and a third conductive sublayer that are sequentially stacked.
  • the layer is closer to the base substrate than the third conductive sub-layer; and a first conductive portion is located in the display area, and the first conductive portion and the conductive member are arranged in the same layer and have the same material;
  • the conductivity of a conductive sublayer is smaller than the conductivity of the second conductive sublayer, the thickness of the first conductive sublayer is smaller than the thickness of the second conductive sublayer, and the melting point of the third conductive sublayer is greater than that of the second conductive sublayer.
  • the melting point of the second conductive sublayer, the second conductive sublayer includes a first surface close to the first conductive sublayer and a second surface close to the third conductive sublayer, the first surface and the The second surface is arranged opposite to each other, the third conductive sublayer protrudes from the second surface along the width direction of the conductive member, and the width direction intersects the extension direction of the conductive member.
  • two conductive members are provided, the two conductive members are insulated from each other, the two conductive members include a first conductive member and a second conductive member, the first The conductive member is closer to the light-transmitting area than the second conductive member, and the size of the third conductive sublayer protruding from the second surface in the first conductive member is larger than that in the second conductive member The third conductive sublayer protrudes by the size of the second surface.
  • At least one embodiment of the present disclosure further provides a display device including any of the above-mentioned display panels.
  • FIG. 1 is a schematic diagram of a plurality of conductive members in a display panel
  • Figure 2 is a cross-sectional view along line A-B of Figure 1;
  • FIG. 3 is a plan view of a display panel provided by an embodiment of the present disclosure.
  • Figure 4 is a cross-sectional view along line A1-A2 of Figure 3;
  • Fig. 5A is another cross-sectional view taken along line A1-A2 of Fig. 3;
  • Fig. 5B is another cross-sectional view taken along line A1-A2 of Fig. 3;
  • Fig. 6A is another cross-sectional view taken along line A1-A2 of Fig. 3;
  • 6B is a partial cross-sectional view of a conductive member on a display panel provided by an embodiment of the present disclosure
  • FIG. 7 is a partial cross-sectional view of a conductive member on a display panel provided by an embodiment of the disclosure.
  • Figure 8 is another cross-sectional view taken along line A1-A2 of Figure 3;
  • FIG. 9 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a plan view of the first conductive member and the third conductive member in the display panel shown in FIG. 9;
  • FIG. 11 is a cross-sectional view of the first conductive member and the third conductive member in the display panel shown in FIG. 9;
  • FIG. 12 is a cross-sectional view of adjacent conductive members in a display panel provided by an embodiment of the present disclosure
  • FIG. 13 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a plan view of a display panel provided by an embodiment of the present disclosure.
  • 15A is a plan view of a display panel provided by an embodiment of the present disclosure.
  • 15B is a plan view of a display panel provided by another embodiment of the present disclosure.
  • FIG. 16A is a plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 16B is a plan view of a display panel provided by another embodiment of the present disclosure.
  • FIG. 17A is a plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 17B is a plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 17C is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 18 is a perspective view of a display device including the display panel provided by the embodiment of the present disclosure according to an embodiment of the present disclosure
  • FIG. 19 is a plan view of the display device shown in FIG. 18;
  • FIG. 20 is a plan view of a foldable display device including a display panel provided by an embodiment of the present disclosure according to an embodiment of the present disclosure
  • FIG. 21 is a schematic diagram of part of the GOA circuit in the foldable display device shown in FIG. 20;
  • Fig. 22A is a top view of the horizontally arranged connecting line in Fig. 21;
  • FIG. 22B is a top view of two adjacent connecting lines horizontally arranged in FIG. 21; FIG.
  • FIG. 23 is a plan view of a foldable display device including a display panel provided by an embodiment of the present disclosure according to another embodiment of the present disclosure.
  • FIG. 24 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • 25 is a circuit diagram of a pixel driving circuit in a pixel of a display panel provided by an embodiment of the present disclosure
  • FIG. 26 is a working timing diagram of the pixel driving circuit shown in FIG. 25;
  • FIG. 27 is a schematic diagram of a second source and drain metal layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 28 is a layout diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 29 is a layout diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 30 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 31 is a cross-sectional view of a display panel provided by another embodiment of the present disclosure.
  • FIG. 32 is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • Fig. 33 is an enlarged schematic diagram of the data selector in Fig. 32;
  • FIG. 34A is a partial cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 34B is a partial cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 35 is a partial top view of a display panel provided by an embodiment of the disclosure.
  • the increase in the display resolution of the display device leads to increased load and signal delay.
  • the introduction of a low-resistance conductive structure is one of the means to solve the signal delay, and the spacing between low-resistance conductive structures shrinks with the increase in resolution, which is easy Causes defects such as electrostatic discharge and electrostatic breakdown due to process and other reasons or subsequent use.
  • FIG. 1 is a schematic diagram of a plurality of conductive members in a display panel. As shown in FIG. 1, the distance between adjacent conductive members 11 is small, and electrostatic discharge is prone to cause electrostatic breakdown. FIG. 1 only schematically shows four conductive members, and the number of conductive members and the arrangement of the conductive members are not limited to those shown in the figure.
  • the conductive member 11 is located on a base substrate. The base substrate is not shown in FIG. 1, and it can be referred to as shown in FIG.
  • Fig. 2 is a cross-sectional view taken along line A-B of Fig. 1.
  • the conductive members 11 are located on the base substrate 10, and each conductive member 11 includes a first conductive sublayer 11a, a second conductive sublayer 11b, and a third conductive sublayer 11c.
  • the cross section of each conductive member 11 may be a regular trapezoid, but is not limited thereto.
  • a first conductive film, a second conductive film, and a third conductive film can be sequentially formed on the base substrate 10, and then the first conductive film, the second conductive film, and the third conductive film are etched , To form the conductive member 11 shown in FIG. 2.
  • the conductive member 11 can be formed by dry etching or wet etching. As shown in FIG. 2, the distance between adjacent third conductive sublayers 11c is greater than the distance between adjacent second conductive sublayers 11b.
  • the distance between two adjacent conductive members 11 is relatively small, which results in that the two adjacent conductive members 11 shown in FIG. 2 are prone to defects such as electrostatic breakdown.
  • FIG. 3 is a plan view of a display panel provided by an embodiment of the disclosure.
  • the display panel includes: a base substrate 100 (not shown in FIG. 3, refer to FIG. 4) and a conductive member CL.
  • Fig. 4 is a cross-sectional view along line A1-A2 of Fig. 3. 3 and 4, the length of the conductive member CL in the extension direction thereof is greater than the width of the conductive member CL in the direction intersecting the extension direction.
  • the direction intersecting the extending direction may guide the width direction of the electric member CL.
  • the conductive member CL includes a first conductive sublayer 101, a second conductive sublayer 102, and a third conductive sublayer 103 that are sequentially stacked, the first conductive sublayer 101 being closer to the third conductive sublayer 103 Base substrate 100.
  • the electrical conductivity of the first conductive sub-layer 101 is lower than the electrical conductivity of the second conductive sub-layer 102, and the melting point of the third conductive sub-layer 103 is greater than the melting point of the second conductive sub-layer 102.
  • the conductivity of the third conductive sublayer 103 is lower than the conductivity of the second conductive sublayer 102, and the melting point of the first conductive sublayer 101 is greater than the melting point of the second conductive sublayer 102.
  • FIG. 3 shows two adjacent conductive members CL.
  • the base substrate 100 may be a rigid base substrate or a flexible base substrate.
  • the rigid base substrate includes a glass substrate, and the material of the flexible base substrate includes polyimide, but is not limited thereto.
  • the base substrate may be a flexible substrate or a glass substrate
  • the flexible substrate may be selected from among polyimide (PI), polysilane, polysiloxane, polysilazane, polycarbosilane, and polyacrylate.
  • PI polyimide
  • polysilane polysilane
  • polysiloxane polysiloxane
  • polysilazane polysilazane
  • polycarbosilane polyacrylate.
  • laminated layers One kind or several kinds of laminated layers.
  • the first conductive sublayer 101, the second conductive sublayer 102, and the third conductive sublayer 103 can all be made of metal materials or alloys.
  • the material of the first conductive sub-layer 101 may be at least one of molybdenum (Mo), titanium (Ti), neodymium (Nd), chromium (Cr), and nickel (Ni)
  • the material of the second conductive sub-layer 102 may be At least one of aluminum (Al), copper (Cu), and silver (Ag).
  • the material of the third conductive sub-layer 103 can be at least one of molybdenum, titanium, neodymium, chromium, nickel, and tungsten (W), but is not limited to this .
  • the first conductive sublayer 101 and the third conductive sublayer 10 can be made of the same material, but are not limited thereto.
  • the conductive member CL may adopt a form in which three conductive sub-layers such as Mo/Al/Mo, Ti/Al/Ti, Mo/Cu/Mo, and Ti/Cu/Ti are stacked.
  • the display panel further includes a barrier layer BRL on the base substrate.
  • a barrier layer BRL is provided between the conductive member CL and the base substrate 100.
  • the barrier layer BRL may use an inorganic insulating film, for example, it may be a single layer of silicon nitride (SiNx), a single layer of silicon oxide (SiOx), or a multiple layer including silicon nitride (SiNx) and silicon oxide (SiOx) stacked on each other. Layer formation, the barrier layer BRL can effectively cover the impurities or particles on the base substrate, and has a protective effect on the conductive components.
  • the barrier layer BRL may use silicon oxide, but it is not limited thereto.
  • the display panel provided by the embodiment of the present disclosure includes: a display area R1 and a peripheral area R2.
  • the display area R1 has a plurality of pixel units SP; the peripheral area R2 is located on at least one side of the display area R1.
  • the display panel further includes a first conductive portion 61 on the base substrate; the first conductive portion is located in the display area R1, and the first conductive portion 61 and the conductive member CL are arranged in the same layer and have the same material.
  • the conductive member CL is located on the base substrate 100.
  • the second conductive sublayer 102 includes a first surface S1 close to the first conductive sublayer 101 and a second surface S2 close to the third conductive sublayer 103.
  • the one surface S1 and the second surface S2 are arranged opposite to each other.
  • the third conductive sub-layer 103 protrudes from the second surface S2 along the width direction (first direction) DR1 of the conductive member CL, the width direction DR1 and the extension direction (second direction) DR2 of the conductive member CL intersect.
  • the boundary of the second conductive sub-layer 102 is shown by the second surface S2 in FIG. 3.
  • the third conductive sublayer 103 covers the edge of the second conductive sublayer 102.
  • the thickness of the second conductive sublayer 102 is greater than the thickness of the first conductive sublayer 101. Because the thickness of the second conductive sub-layer 102 is large and the conductivity is large, the second conductive sub-layer 102 has a higher risk of poor process such as etching residue. If there is etching residue, it will increase the lateral conduction or electrostatic breakdown. risks of.
  • the second conductive sublayer 102 and the third conductive sublayer 103 can be adjusted so that the third conductive sublayer protrudes from the second surface along the width direction of the conductive member to reduce the risk of lateral conduction and electrostatic breakdown.
  • the sources of static electricity usually include static electricity generated during the manufacturing process of the display panel and static electricity generated during the use of the device containing the display panel.
  • the thickness of the second conductive sub-layer 102 is in the range of The thickness of the first conductive sublayer 101 is in the range of The thickness of the third conductive sublayer 103 is in the range of But it is not limited to this.
  • the thickness of the second conductive sublayer 102 is greater than the thickness of the first conductive sublayer 101, and the thickness of the second conductive sublayer 102 is greater than the thickness of the third conductive sublayer 103.
  • the area of the orthographic projection of the third conductive sublayer 103 on the base substrate 100 is larger than the area of the orthographic projection of the first surface S1 of the second conductive sublayer 102 on the base substrate 100, but Not limited to this. In other embodiments, the area of the orthographic projection of the third conductive sublayer 103 on the base substrate 100 may also be equal to or smaller than that of the orthographic projection of the first surface S1 of the second conductive sublayer 102 on the base substrate 100. area.
  • the second conductive sublayer 102 further includes a side surface S3 connecting the first surface S1 and the second surface S2 on the same side of the second conductive sublayer 102.
  • the side surface S3 located on the left side connects the left side edge of the first surface S1 and the left side edge of the second surface S2, and the side surface S3 located on the right side is connected The right side of the first surface S1 and the right side of the second surface S2.
  • the side surface S3 is an inclined surface.
  • the second conductive sublayer 102 may have a trapezoidal structure, but is not limited thereto.
  • the side surface S3 is arranged obliquely with respect to the first conductive sub-layer 101.
  • the width direction DR1 of the conductive member CL is the horizontal direction.
  • the extension direction DR2 of the conductive member CL is the vertical direction.
  • the thickness direction of the conductive member CL ( The third direction) DR3 is perpendicular to the width direction DR1 of the conductive member CL, and perpendicular to the extension direction DR2 of the conductive member CL.
  • the conductive member CL is a straight line as an example for description. In other embodiments, the conductive member CL may not be a straight line.
  • the conductive member CL may be in other forms such as a broken line or a curve.
  • the extension direction DR2 of the conductive member CL may be the extension direction of the line between the two end points of the conductive member CL
  • the width direction DR1 of the conductive member CL may be a direction perpendicular to the extension direction DR2 of the conductive member CL.
  • the distance between the conductive sublayers and the width of the conductive sublayers may be determined based on the geometric dimensions between substantially the same positions of different conductive sublayers.
  • the second conductive sublayer it may be determined based on the first conductive sublayer.
  • the top position (for example, the second surface S2) of the two conductive sublayers may also be determined based on the bottom position (for example, the first surface S1) of the second conductive sublayer, or based on the middle position of the second conductive sublayer.
  • two adjacent conductive members CL are insulated from each other, two adjacent conductive members CL are located on the same layer, and two adjacent conductive members CL include a first conductive member CL1 and a second conductive member CL1.
  • the member CL2 the spacing spcl between the third conductive sublayer 103 of the first conductive member CL1 and the third conductive sublayer 103 of the second conductive member CL2 is smaller than the second surface of the second conductive sublayer 102 of the first conductive member CL1
  • the spacing spc2 between S2 and the second surface S2 of the second conductive sublayer 102 of the second conductive member CL2 is beneficial to reduce the risk of electrostatic breakdown of adjacent conductive members.
  • the first conductive member CL1 and the second conductive member CL2 may have the same structure, but are not limited thereto.
  • that two elements are located on the same layer means that the two elements are formed by the same film layer using the same patterning process.
  • that two elements are located on the same layer means that the base material directly in contact with the two elements is the same.
  • the materials of the elements formed by the same film layer are the same.
  • the third conductive sublayer 103 is not in contact with the first conductive sublayer 101.
  • the width of the third conductive sublayer 103 is greater than the width of the second surface S2.
  • the area of the orthographic projection of the third conductive sublayer 103 on the base substrate 100 is larger than the area of the orthographic projection of the second surface S2 on the base substrate 100.
  • the width of the third conductive sublayer 103 is greater than the width of the second surface S2
  • the distance between adjacent second conductive sublayers 102 is increased, so that the distance between adjacent second conductive sublayers The risk of electrostatic breakdown is reduced, which is beneficial to improve the stability of the device containing the display panel and improve the yield.
  • the inventor of the present application found that if the width of the third conductive sublayer exceeds the width of the second conductive sublayer too much, the width of the second conductive sublayer becomes smaller, resulting in an increase in the resistance of the conductive member, which is not conducive to high resolution. Show; if the width of the third conductive sublayer beyond the second conductive sublayer is too small, the risk of electrostatic discharge between adjacent second conductive sublayers increases, and the third conductive sublayer exceeds the width of the second conductive sublayer to satisfy Under certain conditions, a conductive member structure with both resistance and stability can be obtained.
  • a display panel that satisfies the following relational expression takes into account resistance and stability:
  • w1 is the maximum width in the cross section of the first conductive member CL1 in the width direction
  • w2 is the maximum width in the cross section of the second conductive member CL2 in the width direction
  • ⁇ w11 is the third width in the first conductive member CL1.
  • the distance of the conductive sublayer 103 beyond the second surface S2 ⁇ w12 is the distance of the third conductive sublayer 103 in the second conductive member CL2 beyond the second surface S2
  • dmin is the distance between the first conductive member CL1 and the second conductive member CL2 Minimum spacing.
  • a method of manufacturing the display panel shown in FIG. 4 may include: forming a first conductive film, patterning the first conductive film to form a first conductive sublayer 101, forming a second conductive film, and performing processing on the second conductive film. Patterning to form a second conductive sublayer 102; forming an insulating layer between adjacent second conductive sublayers 102; forming a third conductive film on the insulating layer and the second conductive sublayer 102, the third conductive film and the second conductive The electronic layer 102 contacts, and the third conductive film is patterned to form a third conductive sublayer 103.
  • the manufacturing method of the display panel shown in FIG. 4 is not limited to the above-exemplified method, and those skilled in the art can select a suitable method to manufacture according to the description of the structure of the display panel in the embodiments of the present disclosure.
  • FIG. 5A is a schematic diagram of a plurality of conductive members provided by an embodiment of the disclosure.
  • the display panel includes a plurality of conductive members CL, the plurality of conductive members CL are located on the same layer, the plurality of conductive members CL includes a first conductive member CL1, a second conductive member CL2, a third conductive member CL3, and a fourth conductive member CL3.
  • the conductive member CL4, the interval SPC01 between the first conductive member CL1 and the second conductive member CL2 is different from the interval SPC02 between the third conductive member CL3 and the fourth conductive member CL4, the third of the two conductive members CL on the left
  • the size of the second surface S2 of the conductive sub-layer 103 protruding from the second conductive sub-layer 102 is different from that of the third conductive sub-layer 103 protruding from the second conductive sub-layer 102 in the two conductive members CL on the right.
  • the interval SPC01 between the first conductive member CL1 and the second conductive member CL2 is smaller than the interval SPC02 between the third conductive member CL3 and the fourth conductive member CL4.
  • the third conductive sublayer 103 of the first conductive member CL1 protrudes from the second surface S2 of the second conductive sublayer 102 along the width direction of the first conductive member CL1.
  • the size of the second surface S2 of the second conductive sublayer 102 is D01.
  • the size of the third conductive sublayer 103 in CL2 protruding from the second surface S2 of the second conductive sublayer 102 along the width direction of the second conductive member CL2 is D02, and the third conductive sublayer 103 in the third conductive member CL3 extends along the first surface S2.
  • the dimension of the third conductive member CL3 protruding from the second surface S2 of the second conductive sublayer 102 in the width direction is D03, and the third conductive sublayer 103 of the fourth conductive member CL4 protrudes from the fourth conductive member CL4 in the width direction.
  • the size of the second surface S2 of the second conductive sub-layer 102 is D04.
  • D01 is greater than D03 and greater than D04;
  • D02 is greater than D03 and greater than D04.
  • D01 is equal to D02, and D03 is equal to D04, but it is not limited thereto.
  • the first conductive member CL1, the second conductive member CL2, the third conductive member CL3, and the fourth conductive member CL4 are parallel to each other. In other embodiments, the adjacent conductive members may not be parallel.
  • FIG. 5B is a schematic diagram of a plurality of conductive members provided by an embodiment of the disclosure.
  • the first conductive member CL1 is not parallel to the second conductive member CL2, and the spacing SPC01 between the first conductive member CL1 and the second conductive member CL2 gradually increases from the first end to the second end, so that for the same conductive member CL At different positions, the third conductive sub-layer 103 protrudes from the second surface S2 of the second conductive sub-layer 102 in different sizes.
  • the size of the second surface S2 of the third conductive sublayer 103 protruding from the second conductive sublayer 102 at a position with a small spacing SPC01 is smaller than that of the third conductive sublayer 103. This is due to the size of the second surface S2 of the second conductive sublayer 102 at a position where the distance SPC01 is large, but it is not limited thereto.
  • FIG. 6A is another cross-sectional view taken along the line A1-A2 of FIG. 3.
  • the side S3 includes at least two sub-sides S3, and the at least two sub-sides S3 include a first sub-side S31 close to the first conductive sub-layer 101 and a second sub-side S32 close to the third conductive sub-layer 103.
  • the angle ⁇ 1 formed by the first sub-side surface S31 and the first conductive sub-layer 101 is smaller than the angle ⁇ 2 formed by the second sub-side surface S32 and the first conductive sub-layer 101.
  • the second conductive sublayer 102 usually forms a side with a certain inclination angle, showing a trend of being larger in the lower part and smaller in the upper part. As a result, the distance between adjacent second conductive sub-layers will naturally become larger from bottom to top.
  • the embodiments of the present disclosure mainly On the basis that the width of the second conductive sub-layer is reduced to reduce the risk of electrostatic discharge, the distance between adjacent second conductive sub-layers may not always increase.
  • the angle ⁇ 2 slows down the tendency to increase, and can form a greater angle.
  • the gentle slope structurally increases the width of the second conductive sublayer at the bottom surface and reduces the resistance of the conductive member.
  • FIG. 6B is a partial cross-sectional view of a conductive member on a display panel provided by an embodiment of the disclosure.
  • the intersection point of the side surface S3 and the first conductive sublayer 101 is the first intersection point P1
  • the intersection point of the side surface S3 and the third conductive sublayer 103 is At the second intersection P2
  • at least a part of the side surface S3 is located on the side of the line LN0 between the first intersection P1 and the second intersection P2, which is close to the second conductive sub-layer 102.
  • the cross section taken perpendicular to the extension direction DR2 of the conductive member CL is a plane formed by the thickness direction DR3 of the conductive member CL and the width direction DR1 of the conductive member CL.
  • the intersection P4 of the extension line LN2 of the first sub-side surface S31 and the third conductive sub-layer 103 and the second sub-side surface S32 and the first sub-side surface S32 The distance between the intersection P2 of the three conductive sublayers 103 is d2, and the distance of the third conductive sublayer 103 beyond the second surface S2 is ⁇ w2.
  • the distance of the third conductive sublayer 103 beyond the second surface S2 refers to the dimension of the portion of the third conductive sublayer 103 beyond the second surface S2 in the width direction of the conductive member.
  • the width direction of the conductive member intersects the length direction of the conductive member.
  • the width direction of the conductive member is perpendicular to the length direction of the conductive member.
  • d1 ⁇ w1 in order to both reduce the risk of electrostatic breakdown and reduce the resistance of the conductive member, d1 ⁇ w1, and further, for example, d1 ⁇ w2.
  • d2 ⁇ w1 in order to both reduce the risk of electrostatic breakdown and reduce the resistance of the conductive member, d2 ⁇ w1, and further, for example, d2 ⁇ w2.
  • the first sub-side surface S31 and the second sub-side surface S32 are both inclined surfaces. 6A and 6B, the first sub-side surface S31 and the second sub-side surface S32 may be inclined surfaces with respect to the base substrate 100, respectively.
  • FIG. 7 is a partial cross-sectional view of a conductive member on a display panel provided by an embodiment of the disclosure.
  • the angle ⁇ 2 formed by the second sub-side surface S32 and the first conductive sub-layer 101 is greater than 90 degrees.
  • Fig. 8 is another cross-sectional view taken along line A1-A2 of Fig. 3.
  • the side surface S3 includes three sub-side surfaces S3 arranged in sequence.
  • the three sub-side surfaces S3 include a first sub-side surface S31, a second sub-side surface S32, and a third sub-side surface S33.
  • the sub-side surface S33 is closer to the first conductive sub-layer 101, the angle formed by the first sub-side surface S31 and the first conductive sub-layer 101 is a first angle ⁇ 1, and the angle formed by the second sub-side surface S32 and the first conductive sub-layer 101 Is the second angle ⁇ 2, and the angle formed by the third sub-side surface S33 and the first conductive sub-layer 101 is the third angle ⁇ 3.
  • the third angle ⁇ 3 is greater than the first angle ⁇ 3.
  • Two angles ⁇ 2, the second angle ⁇ 2 is greater than the first angle ⁇ 1.
  • the second conductive sublayer 102 includes two side surfaces S3, the two side surfaces S3 are disposed oppositely, and the two side surfaces S3 are symmetrically disposed along the thickness direction of the conductive member CL.
  • 6B and FIG. 7 only show one side surface S3 of the conductive member CL, and the other side surface S3 of the conductive member CL may also be symmetrically arranged with the illustrated side surface S3 with respect to the thickness direction of the conductive member CL.
  • the two opposite sides of the same conductive member may also be arranged asymmetrically, which is not limited in the embodiment of the present disclosure.
  • two adjacent conductive members CL are insulated from each other, two adjacent conductive members CL are located on the same layer and have the same structure, and two adjacent conductive members CL include first conductive members CL1 and The spacing spc1 between the second conductive member CL2, the third conductive sublayer 103 of the first conductive member CL1 and the third conductive sublayer 103 of the second conductive member CL2 is smaller than that of the second conductive sublayer 102 of the first conductive member CL1 The distance spc2 between the second surface S2 and the second surface S2 of the second conductive sublayer 102 of the second conductive member CL2.
  • the interval between the first conductive member CL1 and the second conductive member CL2 is relatively small.
  • the distance between the first conductive member CL1 and the second conductive member CL2 may be 5-19 ⁇ m, but it is not limited to this. The value is not specifically limited.
  • the distance from the first conductive member CL1 to the base substrate 100 and the distance from the second conductive member CL2 to the base substrate 100 may be equal, but not limited thereto.
  • FIG. 9 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes: a base substrate 100 and a first conductive member layer 21, an insulating layer 22, and a second conductive member layer 23 on the base substrate 100.
  • the first conductive member layer 21 includes a first conductive member layer 21;
  • the second conductive member layer 23 includes the third conductive member CL3 and the fourth conductive member CL4.
  • the first conductive member CL1 and the second conductive member CL2 may use the first conductive member as described above, respectively.
  • CL1 and the second conductive member CL2, the third conductive member CL3 and the fourth conductive member CL4 may use the first conductive member CL1 and the second conductive member CL2 as described above, respectively.
  • the first conductive member layer 21 and the second conductive member layer 23 are located in different layers, and the distance from the first conductive member layer 21 to the base substrate 100 is different from the distance from the second conductive member layer 23 to the base substrate 100.
  • the distances from the one conductive member CL1 and the third conductive member CL3 to the base substrate 100 are different.
  • FIG. 10 is a plan view of the first conductive member and the third conductive member in the display panel shown in FIG. 9. Both the first conductive member CL1 and the third conductive member CL3 adopt a structure in which the third conductive sub-layer protrudes from the second surface along the width direction of the conductive member.
  • FIG. 11 is a cross-sectional view of the first conductive member and the third conductive member in the display panel shown in FIG. 9.
  • the thickness of the second conductive sublayer 102 of the first conductive member CL1 is T3, the thickness of the second conductive sublayer 102 of the third conductive member CL3 is T4, T4 is greater than T3, and the third conductive sublayer 103 in the first conductive member CL1
  • the distance beyond the second surface S2 is ⁇ w3
  • the distance of the third conductive sublayer 103 beyond the second surface S2 in the third conductive member CL3 is ⁇ w4, which satisfies the following relationship:
  • the thickness of the second conductive sub-layer can be determined according to the thickness of the second conductive sub-layer.
  • the thickness of the conductive member closer to the base substrate is small, and the thickness of the conductive member farther from the base substrate is large.
  • the thickness of the conductive member closer to the base substrate may be larger, and the thickness of the conductive member farther from the base substrate is smaller.
  • FIG. 12 is a cross-sectional view of adjacent conductive members in a display panel provided by an embodiment of the present disclosure.
  • the spacing spc1 between the third conductive sublayer 103 of the first conductive member CL1 and the third conductive sublayer 103 of the second conductive member CL2 is smaller than that of the second conductive sublayer 102 of the first conductive member CL1.
  • the distance spc2 between the second surface S2 and the second surface S2 of the second conductive sublayer 102 of the second conductive member CL2 is beneficial to reduce the risk of electrostatic breakdown.
  • the third conductive sublayer 103 covers the second conductive sublayer 102 and is in contact with the first conductive sublayer 101. Since the side surface S33 of the third conductive sub-layer 103 covers the second conductive sub-layer 102, the risk of electrostatic breakdown of the second conductive sub-layer 102 is reduced.
  • At least one of the first surface S1, the second surface S2, and the side surface S3 of the second conductive sublayer 102 is doped with N, S, and P elements. And at least one of Cl elements.
  • the above-mentioned doping may be performed on the second conductive sublayer 102 of the conductive member CL in the display panel shown in FIGS. 3 to 12 provided by the embodiment of the present disclosure.
  • FIG. 13 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a base substrate 100, a barrier layer 42, and a conductive member layer 43.
  • the conductive member layer 43 includes a conductive member CL, and the conductive member CL is located on an inorganic insulating film 42.
  • the conductive member CL is in contact with the barrier layer 42, but is not limited thereto.
  • the conductive member layer 43 includes the first conductive member CL1 and the second conductive member CL2 as described above.
  • the barrier layer 42 includes an inorganic insulating film, and has at least one of an F element and a Cl element.
  • the barrier layer 42 has at least one of the F element and the Cl element, which can effectively adsorb the metal ions in the conductive member and reduce the risk of electrostatic discharge.
  • the content of at least one of the F element and the Cl element in the barrier layer 42 is 1 ⁇ 10 18 to 5 ⁇ 10 20 atoms per cubic centimeter.
  • the first surface S1 is in contact with the first conductive sublayer 101
  • the second surface S2 is in contact with the third conductive sublayer 103.
  • the width of the first surface S1 is smaller than the width of the first conductive sublayer 101
  • the width of the second surface S2 is smaller than the width of the third conductive sublayer 103
  • the width difference between the third conductive sublayer 103 and the second surface S2 is greater than the thickness of the third conductive sublayer 103.
  • whether the third conductive sublayer 103 exceeds the first surface S1 is not limited.
  • the third conductive sublayer 103 may exceed the first surface S1, that is, the area of the orthographic projection of the third conductive sublayer 103 on the base substrate is larger than the area of the orthographic projection of the first surface S1 on the base substrate.
  • the third conductive sub-layer 103 may not exceed the first surface S1, that is, the orthographic projection of the third conductive sub-layer 103 on the base substrate falls within the first surface S1 on the base substrate.
  • the orthographic projection of the third conductive sublayer 103 on the base substrate may also coincide with the orthographic projection of the first surface S1 on the base substrate.
  • FIG. 14 is a plan view of a display panel provided by an embodiment of the disclosure.
  • the display panel includes a display area R1 and a peripheral area R2 located on at least one side of the display area R1.
  • a plurality of sub-pixels SP are located in the display area R1.
  • a plurality of gate lines GL and a plurality of data lines DL are located in the display area R1.
  • the plurality of gate lines GL and the plurality of data lines DL cross and are insulated from each other.
  • each data line DL is connected to the pad PD located in the peripheral area R2.
  • FIG. 14 shows that the display panel includes a display area R1 and a peripheral area R2 located on at least one side of the display area R1.
  • a plurality of sub-pixels SP are located in the display area R1.
  • a plurality of gate lines GL and a plurality of data lines DL are located in the display area R1.
  • the plurality of gate lines GL and the plurality of data lines DL cross and are
  • FIG. 14 shows a plurality of pixel units SP.
  • the plurality of pixel units SP may be arranged in an array, but is not limited thereto.
  • FIG. 14 takes a plurality of pixel units SP arranged in a matrix as an example for illustration, but it is not limited to this.
  • each data line DL is connected to one pad PD as an example for description.
  • multiple data lines DL may be connected to one pad PD, for example, two or more The data line DL is connected to a pad PD.
  • a data selection unit such as a mux unit can be provided to connect two or more data lines DL to one pad PD.
  • FIG. 15A is a plan view of a display panel provided by an embodiment of the present disclosure.
  • the first conductive member CL1 and the second conductive member CL2 are respectively connected to the pins PN of the external circuit CC through the anisotropic conductive adhesive ADH, and the anisotropic conductive adhesive ADH is in the third direction DR3 (vertical direction).
  • the third conductive sub-layer 103 in the conductive member CL protrudes from the second surface S2 to facilitate its binding with external circuits.
  • FIG. 15A uses the second conductive sub-layer 102 to have two slopes as an example for schematic illustration, but it is not limited to this.
  • the conductive member CL in FIG. 15A may adopt any conductive member CL described in the embodiments of the present disclosure.
  • FIG. 15A shows the conductive portion ADH1 of the anisotropic conductive adhesive ADH.
  • the part of the anisotropic conductive adhesive ADH except for the conductive part ADH1 is an insulating part. That is, the part of the anisotropic conductive adhesive ADH located between two adjacent conductive parts ADH1 is an insulating part to achieve vertical connection and lateral insulation of conductive elements.
  • FIG. 15B is a plan view of a display panel provided by another embodiment of the present disclosure.
  • the conductive member CL of the display panel shown in FIG. 15A is stacked with the first stack element ST1 and the second stack element ST2, and the first stack element ST1 and the second stack element ST2 are respectively provided On both sides of the conductive member CL, the first stack element ST1 is closer to the base substrate than the second stack element ST2.
  • the second stack element ST2 is connected to the pin PN through the conductive part of the anisotropic conductive adhesive ADH.
  • FIG. 15B takes the conductive member CL in contact with the first stack element ST1 and in contact with the second stack element ST2 as an example for illustration, but it is not limited to this.
  • the conductive member CL and the first stack element ST1 can pass through The via hole penetrating the insulating layer is connected, and the conductive member CL and the second stack element ST2 may also be connected via the via hole penetrating the insulating layer.
  • the barrier layer between the base substrate 100 and the conductive member CL is omitted in FIGS. 15A and 15B.
  • FIG. 16A is a plan view of a display panel provided by an embodiment of the present disclosure.
  • the display panel has a light-transmitting area HL. Because the base substrate is hollowed out at the light-transmitting area HL, the distance d21 between two adjacent gate lines GT close to the light-transmitting area HL is smaller than the two gate lines GT far away from the light-transmitting area HL near the light-transmitting area HL. The distance d22 between adjacent gate lines GT.
  • 16A near the light-transmitting area HL and having a homeopathically bent/bent portion may be a conductive layer having a third conductive sub-layer protruding from the second surface structure along the width direction of the conductive member provided by an embodiment of the present disclosure.
  • the first conductive member CL1 is closer to the light-transmitting area HL than the second conductive member CL2.
  • the distance of the third conductive sublayer 103 in the first conductive member CL1 beyond the second surface S2 is greater than the distance of the third conductive sublayer 103 in the second conductive member CL2 beyond the second surface S2.
  • the conductive member CL can also be other signal lines in the display panel.
  • FIG. 16B is a plan view of a display panel provided by another embodiment of the present disclosure.
  • the light-transmitting area HL is located at the edge of the base substrate to form a notch.
  • the light-transmitting area HL can be used to place components such as a camera to facilitate the realization of various functions of the display device.
  • the shape of the light-transmitting area HL is not limited to those shown in FIGS. 16A and 16B, and can be determined according to needs.
  • FIG. 17A is a plan view of a display panel provided by an embodiment of the disclosure.
  • 17A shows a plurality of data lines DL and a plurality of first power lines PL1, the data line DL and the first power line PL1 are adjacent, the data line DL and the first power line PL1 in the vicinity of the light transmission area HL may be These are the first conductive member CL1 and the second conductive member CL2 as described above, respectively.
  • the distance d21 between the adjacent data line DL and the first power line PL1 near the light-transmitting area HL is smaller than the adjacent data line DL and the first power line PL1 far away from the light-transmitting area HL The distance between d22.
  • FIG. 17A shows a plurality of data lines DL and a plurality of first power lines PL1, the data line DL and the first power line PL1 are adjacent, the data line DL and the first power line PL1 in the vicinity of the light transmission area HL may be These are the first
  • the distance d21 between the adjacent data line DL1 and the first power line PL11 near the light-transmitting area HL is smaller than the adjacent data line DL2 far from the light-transmitting area HL And the distance d22 between the first power line PL12.
  • FIG. 17B is a plan view of a display panel provided by an embodiment of the present disclosure.
  • the display panel shown in FIG. 17B includes spacers SEP.
  • the arrangement of the isolation column SEP is beneficial to block the invasion of water and oxygen to the light-emitting layer of the light-emitting diode.
  • the isolation pillar SEP may adopt the structure of the conductive member CL as described above.
  • the isolation pillar SEP is disposed around the light-transmitting area HL, and the isolation pillar SEP and the first power line PL1 adjacent thereto may be the first conductive member CL1 and the second conductive member CL2 as described above, respectively.
  • the data line DL may be adjacent to the isolation pillar SEP, that is, the isolation pillar SEP and the adjacent data line DL may be the first conductive member CL1 and the second conductive member CL1 as described above, respectively.
  • the data line DL and the first power line PL1 are provided in the same layer. It should be noted that there is no data line between the isolation pillar SEP and the adjacent first power line PL1, and there is no first power line PL1 between the isolation pillar SEP and the adjacent data line DL.
  • FIG. 17C is a partial plan view of a display panel provided by an embodiment of the present disclosure.
  • the isolation pillar SEP includes a plurality of sub-isolation pillars SEP0, and the distance d32 between the sub-isolation pillar SEP0 close to the signal line SL and the adjacent sub-isolation pillar SEP0 is greater than the distance between adjacent sub-isolation pillars SEP0 d31.
  • the signal line SL may be the data line DL or the first power line PL1 shown in FIG. 17B.
  • the adjacent sub-isolation pillars SEPO may be the first conductive member CL1 and the second conductive member CL2 as described above.
  • FIG. 18 is a perspective view of a display device including a display panel provided by an embodiment of the present disclosure provided by an embodiment of the present disclosure.
  • the display device is a foldable display device.
  • the display device may be an OLED display device.
  • the display device includes a foldable area R13 and a first display area R11 and a second display area R12 that are separately provided on both sides of the foldable area R13.
  • FIG. 18 shows the foldable line FL.
  • the foldable area R13, the first display area R11, and the second display area R12 constitute a display area R1.
  • Fig. 19 is a plan view of the display device shown in Fig. 18.
  • a first peripheral area R21 is provided on one side of the first display area R11
  • a first pad area PDR1 is provided in the first peripheral area R21
  • a plurality of first pads PD1 are located in the first pad area PDR1
  • the plurality of first pads PD1 includes two adjacent first pads PD1: a first pad PD11 close to the foldable line FL and a first pad PD12 far from the foldable line FL.
  • the first pad PD11 and the first pad PD12 may be the first conductive member CL1 and the second conductive member CL2 as described above, respectively.
  • the distance of the third conductive sublayer 103 in the first conductive member CL1 beyond the second surface S2 is greater than the distance of the third conductive sublayer 103 in the second conductive member CL2 beyond the second surface S2. That is, the first conductive member CL1 is closer to the foldable line FL than the second conductive member CL2, and the third conductive sublayer 103 in the first conductive member CL1 extends beyond the second surface S2 than the third conductive member CL2 in the second conductive member CL2.
  • the distance of the layer 103 beyond the second surface S2 is large.
  • FIG. 19 takes the first pad PD11 as the first pad closest to the foldable line FL as an example for illustration, but it is not limited to this, and the first pad PD11 may not be the first pad closest to the foldable line FL. .
  • the distance of the adjacent second conductive sublayers of two adjacent conductive members close to the foldable line FL is greater than the distance of the adjacent second conductive sublayers of two adjacent conductive members away from the foldable line FL.
  • a second peripheral area R22 is provided on one side of the second display area R12, a second pad area PDR2 is provided in the second peripheral area R22, and a plurality of second pads PD2 are located in the second pad area PDR2, the plurality of second pads PD2 includes two adjacent second pads PD2: a second pad PD21 close to the foldable line FL and a second pad PD22 far from the foldable line FL.
  • the second pad PD21 and the second pad PD22 may be the first conductive member CL1 and the second conductive member CL2 as described above, respectively.
  • the distance of the third conductive sublayer 103 in the first conductive member CL1 beyond the second surface S2 is greater than the distance of the third conductive sublayer 103 in the second conductive member CL2 beyond the second surface S2. That is, the closer to the foldable line FL, the larger the size of the third conductive sublayer in the conductive member protruding from the second surface in the width direction of the conductive member.
  • first pads PD1 and second pads PD are shown in FIG. 19.
  • the number of first pads PD1 and the number of second pads PD can be determined according to needs, and is not limited to the figure. Shown in.
  • FIG. 19 illustrates an example in which the spacing between adjacent conductive members CL is equal throughout.
  • the embodiment of the present disclosure is not limited to this.
  • the spacing between adjacent conductive members CL may also be gradually changed. For example, from a direction closer to the display area R1 to a direction away from the display area R1, the spacing between adjacent conductive members CL gradually increases.
  • FIG. 19 takes as an example that the adjacent conductive members CL are parallel to each other, but in other embodiments, the adjacent conductive members CL may not be parallel to each other.
  • FIG. 20 is a plan view of a foldable display device including a display panel provided by an embodiment of the present disclosure provided by an embodiment of the present disclosure.
  • the foldable display device is an OLED display device.
  • a foldable display device includes a foldable area R13 and a first display area R11 and a second display area R12 located on both sides thereof, and the foldable area R13, the first display area R11, and the second display area R12 constitute the display area R1 Outside the display area R1 is a peripheral area R2.
  • the peripheral area R2 includes a first peripheral area R21 located on at least one side of the first display area R11 and a second peripheral area R21 located on at least one side of the second display area R21.
  • the display area includes multiple rows of pixel units.
  • the first display area R11 and the second display area R12 are non-folding areas.
  • FIG. 21 is a schematic diagram of part of the GOA circuit in the foldable display device shown in FIG. 20.
  • the first peripheral region R21 includes a plurality of signal lines 46 and multi-level GOA unit circuits 45.
  • the GOA unit circuits 45 of each level are electrically connected to the pixel units of the corresponding row through the signal lines 46, and each The GOA unit circuit 45 is used to drive the pixel unit of the corresponding row.
  • the GOA unit circuit 45 of each stage is connected to a signal line 46 through a scan data line (not shown).
  • the signal line 46 includes a GOA signal line, a pixel unit signal line, and a power signal line.
  • the GOA signal line includes a first clock signal line CK1, a second clock signal line CK2, a low-level signal line VGL, and a high-level signal line VGH for the normal operation of the GOA unit circuit 45.
  • the input signal IN in the N-th stage GOA unit circuit 45 is provided by the output signal OUT of the N-1th stage GOA unit circuit, and the output signal OUT of the N-th stage GOA unit circuit provides pixels in the Nth row.
  • the switch signal of the unit and the input signal of the N+1th GOA unit circuit is provided by the input signal IN in the N-th stage GOA unit circuit.
  • the first clock signal line CK1 is configured to provide a first clock signal
  • the second clock signal line CK2 is configured to provide a second clock signal
  • the low-level signal line VGL is configured to provide a low-level signal
  • the second clock signal line CK2 is configured to provide a low-level signal.
  • the signal line VGH is configured to provide a high-level signal.
  • the conductive member CL in the display panel provided by the embodiment of the present disclosure may be the first clock signal line CK1, the second clock signal line CK2, the low level signal line VGL, and the high level signal line VGH shown in FIG. 21. Any two adjacent to each other. That is, the first conductive member CL1 and the second conductive member CL2 may be any of the first clock signal line CK1, the second clock signal line CK2, the low-level signal line VGL, and the high-level signal line VGH shown in FIG. 21. Two adjacent.
  • the third conductive sublayer 103 in the first conductive member CL1 exceeds the second surface S2 by a distance
  • the third conductive sub-layer 103 in the second conductive member CL2 has a large distance beyond the second surface S2.
  • the first conductive member CL1 is the high-level signal line VGH
  • the second conductive member CL2 is the low-level signal line VGL as an example for description.
  • FIG. 21 also shows the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, and the fourth connection line CNL4.
  • the high-level signal line VGH, the low-level signal line VGL, the first clock signal line CK1, and the second clock signal line CK2 are respectively connected through the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, and the fourth connection line.
  • the line CNL4 is connected to the GOA unit circuit 45 of the Nth stage.
  • a clock signal line CK1 and a second clock signal line CK2 are vertically arranged as an example for description.
  • first conductive member CL1 and the second conductive member CL2 may be any adjacent two of the first connecting line CNL1, the second connecting line CNL2, the third connecting line CNL3, and the fourth connecting line CNL4 shown in FIG. 21. indivual.
  • Fig. 22A is a plan view of the horizontally arranged connecting wires in Fig. 21.
  • the conductive member shown in FIG. 22A may be any one of the first connection line CNL1, the second connection line CNL2, the third connection line CNL3, and the fourth connection line CNL4 shown in FIG. 21.
  • the distance d1 of the third conductive sublayer 103 of the portion of the conductive member CL close to the foldable line FL beyond the second surface S2 is greater than the second surface of the portion of the conductive member CL away from the foldable line FL.
  • FIG. 22B is a top view of the two adjacent connecting lines horizontally arranged in FIG. 21. As shown in FIG. 22B, the distance d0 between the second surface S2 between the first conductive member CL1 and the second conductive member CL2 gradually decreases from the direction close to the foldable line FL to away from the foldable line FL.
  • FIG. 23 is a plan view of a foldable display device including a display panel provided by an embodiment of the present disclosure according to another embodiment of the present disclosure.
  • the signal line 46 and the GOA unit circuit 45 are located on the left and right sides of the display device.
  • the foldable display device shown in FIG. 23 is In the device, the signal line 46 and the GOA unit circuit 45 are located on the upper and lower sides of the display device.
  • FIG. 24 is a schematic plan view of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a base substrate 100, and the base substrate 100 is divided into two regions.
  • the base substrate 100 includes a display area R1 and a peripheral area R2 located on at least one side of the display area R1.
  • the peripheral region R2 may be located at at least one of the upper side, the lower side, the left side, and the right side of the display region R1. It is shown in FIG. 24 that the peripheral area R2 is located on the upper, lower, left, and right sides of the display area R1, that is, the peripheral area R2 surrounds the display area R1.
  • the peripheral area R2 may also be located only on one side of the display area R1, for example, only located on the upper side, lower side, left side, or right side of the display area R1.
  • the gray-filled area in FIG. 24 is the display area R1
  • the rest of the base substrate 100 is the peripheral area R2.
  • the display area R1 is a screen display area, which is a light emitting area.
  • the peripheral area R2 is an area where no picture is displayed, and is a non-light emitting area.
  • a crack stop line 51 is provided to prevent edge cracks from propagating to the display region R1.
  • the crack stop line 51 includes a first crack stop line 511 and a second crack stop line 512.
  • a crack detection line 52 configured to detect cracks is also provided.
  • the crack detection line 52 includes a first crack detection line 521 and a second crack detection line 522. The crack detection line 52 is closer to the display area R1 than the crack stop line 51. If cracks are detected through the crack detection line 52, products with edge cracks can be prevented from flowing into the client.
  • cracks may be generated on the edge of the layer on the base substrate 100, such as the inorganic layer.
  • the first conductive member CL1 and the second conductive member CL2 in the display panel provided by the embodiment of the present disclosure may be the first crack blocking line 511 and the second crack blocking line 512, respectively, or the display panel provided by the embodiment of the present disclosure
  • the first conductive member CL1 and the second conductive member CL2 in may be a first crack detection line 521 and a second crack detection line 522, respectively.
  • the third conductive sub-layer 103 in the first conductive member CL1 close to the display area R1 extends beyond the second surface S2 less than in the second conductive member CL2 far away from the display area R1. The distance of the third conductive sub-layer 103 beyond the second surface S2.
  • the display panel has a feature area, two conductive members CL are provided, and the two conductive members CL are insulated from each other.
  • the two conductive members CL include a first conductive member CL1 and a second conductive member CL2.
  • the first conductive member CL1 is more conductive than the second conductive member CL1.
  • the member CL2 is closer to the feature area, and the size of the third conductive sublayer 103 in the first conductive member CL1 protruding from the second surface S2 is greater than the size of the third conductive sublayer 103 in the second conductive member CL2 protruding from the second surface S2.
  • the characteristic area includes at least one of a light-transmitting area, a foldable area, and a display area.
  • first conductive member CL1 and the second conductive member CL2 as the first power line (power supply voltage line) ELVDD and the data line, respectively, as an example.
  • the transistors used in FIGS. 25 and 28 can all be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is referred to as the first pole, and the other pole is referred to as the second pole.
  • the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the emitter.
  • the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate and the first electrode can be The source electrode and the second electrode may be the drain electrode.
  • the display panel shown in FIG. 28 includes an array layer on a base substrate and a light-shielding layer on the side of the array layer away from the base substrate.
  • a plurality of imaging holes are formed on the light-shielding layer, and the imaging holes are on the base substrate.
  • the first orthographic projection of and the second orthographic projection of the active layer pattern of the switching transistor in the array layer on the base substrate do not overlap.
  • the switching transistor is a transistor connected to the gate of the driving transistor in the array layer.
  • the imaging pinholes formed on the light shielding layer are set to the active layer patterns that do not correspond to the switching transistors in the array layer, so that the light passing through the imaging pinholes will not interfere with the switching transistors.
  • the active layer pattern affects, so that the switching transistor will not have photo-generated leakage current in the off state due to the irradiation of light, thereby not affecting the potential of the gate of the driving transistor, and avoiding the problem of inaccurate gray scale display.
  • the non-overlapping of the first orthographic projection and the second orthographic projection means that there is no overlap between the first orthographic projection and the second orthographic projection, but it is not limited to this.
  • the array layer may be a thin film transistor array layer, but is not limited thereto.
  • the thin film transistor array layer may include an array layer and a second source/drain metal layer, and the second source/drain metal layer is multiplexed as a light-shielding layer, but is not limited thereto.
  • the orthographic projection of the channel region in the active layer pattern of the control transistor in the array layer on the base substrate is the third orthographic projection, and the channel region in the active layer pattern of the drive transistor is on the base substrate.
  • the orthographic projection is the fourth orthographic projection.
  • the orthographic projection of the channel region in the active layer pattern of the switching transistor on the base substrate is the fifth orthographic projection.
  • the shortest distance between the edge of the first orthographic projection and the fifth orthographic projection is greater than the distance between the edge of the first orthographic projection and the third orthographic projection.
  • the shortest distance between the edge of the first orthographic projection and the fifth orthographic projection is greater than the distance between the edge of the first orthographic projection and the fourth orthographic projection.
  • control transistor is a transistor other than the switching transistor and the driving transistor in the array layer.
  • the shortest distance between the edge of the first orthographic projection and the fifth orthographic projection is greater than the distance between the edge of the first orthographic projection and the third orthographic projection, and the shortest distance between the edge of the first orthographic projection and the fifth orthographic projection The distance is greater than the distance between the edge of the first orthographic projection and the fourth orthographic projection, and the imaging aperture is farther from the channel region of the active layer pattern of the switching transistor to prevent the channel region of the active layer pattern of the switching transistor from being penetrated Light shining through the imaging aperture.
  • the display panel may include a first pixel area provided with imaging apertures and a second pixel area not provided with imaging apertures.
  • the area of the first pixel area is larger than the area of the second pixel area.
  • the aspect ratio of the switching transistor in the first pixel area may be smaller than the aspect ratio of the switching transistor in the second pixel area, so as to reduce the current value of the photo-generated leakage current, thereby improving the accuracy of the display gray scale, but it is not limited to this. .
  • the first orthographic projection does not overlap with the orthographic projection of the metal pattern included in the array layer on the base substrate.
  • the imaging aperture needs to not be blocked by the metal pattern, so as to improve the accuracy of the imaging fingerprint recognition of the aperture.
  • the diameter of the imaging aperture may be greater than or equal to 2 ⁇ m and less than or equal to 20 ⁇ m, but is not limited thereto.
  • the diameter of the imaging aperture may be greater than or equal to 4 ⁇ m and less than or equal to 7 ⁇ m, but is not limited thereto.
  • the density of the imaging apertures can be flexibly adjusted according to actual conditions, and one imaging aperture can be set in the area of N pixels, where N is a positive integer.
  • N may be greater than or equal to 3 and less than or equal to 10, but is not limited thereto.
  • the array layer may include an active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, and a first gate insulating layer, which are sequentially arranged between the base substrate and the light shielding layer.
  • the source-drain metal layer and the second insulating layer; the display panel further includes a flat layer and an anode layer sequentially arranged on the side of the light shielding layer away from the second insulating layer.
  • the light-shielding layer includes light-shielding patterns and connection patterns; the light-shielding patterns have imaging apertures.
  • the first source/drain metal layer is electrically connected to the anode layer through a first via hole penetrating the second insulating layer, a connection pattern, and a second via hole penetrating the flat layer; there is a light leakage gap between the connection pattern and the light shielding pattern.
  • the orthographic projection of the light leakage gap on the base substrate is covered by the orthographic projection of the metal electrode included in the thin film transistor array layer on the base substrate.
  • the light-shielding pattern and the connection pattern are separated from each other, and the light-shielding pattern and the connection pattern are insulated from each other.
  • the display panel may include a base substrate, an array layer, a light-shielding layer, a flat layer, and an anode layer that are sequentially arranged from bottom to top.
  • the array layer may include an active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source/drain metal layer, and a second Insulation.
  • the anode layer needs to be electrically connected to the first source-drain metal layer. Therefore, a connection pattern separate from the light-shielding pattern is provided in the light-shielding layer, so that the first source-drain metal layer passes through the first via hole penetrating the second insulating layer. The connection pattern and the second via hole penetrating the planarization layer are electrically connected to the anode layer.
  • the orthographic projection of the light leakage gap on the base substrate is set as the metal electrode included in the array layer.
  • the front projection on the base substrate is covered to prevent the light exposed through the light leakage gap from affecting the fingerprint recognition of the small hole imaging.
  • the metal electrode may be, for example, the upper plate of the storage capacitor, but it is not limited thereto.
  • FIG. 25 is a circuit diagram of a pixel driving circuit in a pixel of a display panel provided by an embodiment of the present disclosure.
  • the pixel driving circuit may include a driving transistor T1, a first switching transistor T3, a second switching transistor T6, a first control transistor T2, a second control transistor T4, a third control transistor T5, and a fourth control transistor T7. And storage capacitor Cst.
  • the source T3s of the first switching transistor T3 is electrically connected to the gate T1g of the driving transistor T1, and the drain T3d of the first switching transistor T3 is electrically connected to the drain T1d of the driving transistor T1.
  • the gate T3g of the first switching transistor T3 is electrically connected to the gate line G(n) in the nth row.
  • the gate T6g of the second switching transistor T6 is electrically connected to the reset line Reset(n) in the nth row, the drain T6d of the second switching transistor T6 is electrically connected to the gate T1g of the driving transistor T1, and the source of the second switching transistor T6 is T6s is electrically connected to the initial voltage line Vint.
  • the gate T2g of the first control transistor T2 is electrically connected to the gate line G(n) of the nth row
  • the source T2s of the first control transistor T2 is electrically connected to the data line D(m) of the mth column
  • the first control transistor T2 The drain T2d is electrically connected to the source T1s of the driving transistor T1.
  • the gate T4g of the second control transistor T4 is electrically connected to the n-th row of light-emitting control line EM(n), the source T4s of the second control transistor T4 is electrically connected to the first power line ELVDD, and the drain T4d of the second control transistor T4 It is electrically connected to the source T1s of the driving transistor T1.
  • the gate T5g of the third control transistor T5 is electrically connected to the n-th row of light-emitting control line EM(n), the source T5s of the third control transistor T5 is electrically connected to the drain T1d of the driving transistor T1, and the drain of the third control transistor T5 is electrically connected.
  • the electrode T5d is electrically connected to the anode of the organic light emitting diode OLED; the cathode of the organic light emitting diode OLED is electrically connected to the second power line ELVSS.
  • the gate T7g of the fourth control transistor T7 is electrically connected to the reset line Reset (n+1) in the n+1th row, the drain T7d of the fourth control transistor T7 is electrically connected to the anode of the organic light emitting diode OLED, and the fourth control transistor T7
  • the source T7s is electrically connected to the initial voltage line Vint.
  • the first plate Csa of the storage capacitor Cst is electrically connected to the first power line ELVDD, and the gate T1g of the driving transistor T1 can be multiplexed as the second plate Csb of the storage capacitor Cst.
  • n is a positive integer and m is a positive integer.
  • the pixel driving circuit shown in FIG. 25 may be the pixel driving circuit in the pixel area of the nth row and the mth column, but is not limited to this.
  • all transistors are p-type thin film transistors, but they are not limited to this.
  • the first node N1 is a node electrically connected to the gate of the driving transistor T1.
  • the pixel drive circuit shown in FIG. 25 is only an embodiment of the pixel drive circuit in the pixel, and does not limit the structure of the pixel drive circuit.
  • the second switching transistor T6 may be a double-gate transistor to reduce its leakage current and maintain the potential of the gate of the driving transistor T1, but it is not limited to this.
  • Fig. 26 is an operation timing chart of the pixel driving circuit shown in Fig. 25.
  • t1 is the first stage
  • t2 is the second stage
  • t3 is the third stage.
  • the data voltage labeled Vdata is the data voltage provided by the data line D(n).
  • the pixel driving circuit shown in FIG. 26 is described as follows during operation.
  • Reset(n) inputs a low level
  • G(n) inputs a high level
  • EM(n) inputs a high level
  • the second switching transistor T6 is turned on, and the driving transistor T1 The potential of the gate is reset to the initial voltage.
  • the second switch transistor T6 is turned off, the second control transistor T4 and the third control transistor T5 are turned off, the first control transistor T2, the first switch transistor T3, the driving transistor T1 and the fourth control transistor T7 are turned on, and Vdata passes through the A control transistor T2, a driving transistor T1, and a first switching transistor T3 charge Cst to increase the potential of the gate of the driving transistor T1 until the potential of the gate of the driving transistor T1 becomes Vdata+Vth (Vth is the voltage of the driving transistor T1 Threshold voltage), the first switching transistor T3 is turned off, the potential of N1 is stored by Cst, and the fourth control transistor T7 is turned on to reset the potential of the anode of the OLED to the initial voltage.
  • Vth is the voltage of the driving transistor T1 Threshold voltage
  • the third stage t3 (that is, the light-emitting stage), Reset(n) inputs a high level, G(n) inputs a high level, EM(n) inputs a low level, the driving transistor T1, the first control transistor T2, and the second A switching transistor T3, a second switching transistor T6, and a fourth control transistor T7 are turned off, the second control transistor T4 and the third control transistor T5 are turned on, the OLED emits light, and the driving current I of the driving transistor T1 to drive the OLED to emit light is equal to (1/2 ) K(Vdata-Vdd) 2 ; where K is the current coefficient, and Vdd is the power supply value of the power supply voltage input by ELVDD.
  • the source T3s of the first switching transistor T3 is electrically connected to the gate T1g of the driving transistor T1
  • the drain T6d of the second switching transistor T6 is electrically connected to the gate T1g of the driving transistor T1.
  • the display panel can be individually set with a specific fingerprint recognition area, or the entire screen can be a fingerprint recognition area.
  • the display panel may include a base substrate, a buffer layer, an array layer, a second source/drain metal layer, a flat layer, an anode layer, a pixel defining layer, a light emitting layer, and a cathode layer arranged from bottom to top.
  • the array layer includes an active layer, a gate insulating layer, a first gate metal layer, a first insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source/drain metal layer, and a second insulating layer arranged in sequence from bottom to top .
  • the first gate metal layer is used to form structures such as gate lines, light-emitting control lines, and gates of transistors in the pixel driving circuit.
  • the second gate metal layer is used to form the plate of the storage capacitor and the initial voltage line.
  • the first source-drain metal layer is used to form the data line, the first power line, the source of each transistor in the pixel driving circuit, and the drain of each transistor in the pixel driving circuit.
  • the second source-drain metal layer is multiplexed as a light shielding layer, and imaging small holes are formed on the light shielding layer.
  • the anode layer needs to be electrically connected to the first source-drain metal layer to complete the circuit structure, it is necessary to set the second source-drain metal layer (that is, the light shielding layer) to also include a connection pattern, and the first source-drain metal layer
  • the anode layer is electrically connected through a first via hole penetrating the second insulating layer, a connection pattern, and a second via hole penetrating the planarization layer.
  • the active layer pattern may include a channel region, a source region, and a drain region.
  • the channel region may not be doped with impurities, so it has semiconductor characteristics.
  • the source region is arranged on the first side of the channel region, and the drain region is arranged on the second side of the channel region.
  • the first side and the second side are opposite sides, and are doped with impurities, and therefore have conductivity sex. Impurities may vary depending on whether the transistor is an n-type transistor or a p-type transistor.
  • the doped source region may correspond to the source electrode of the transistor
  • the doped drain region may correspond to the drain electrode of the transistor
  • FIG. 27 is a schematic diagram of a second source and drain metal layer in a display panel provided by an embodiment of the present disclosure.
  • L0 is the connection pattern included in the second source-drain metal layer
  • SE is the light-shielding pattern included in the second source-drain metal layer
  • H0 is the imaging aperture
  • F1 is the connection pattern. Is a light leakage gap
  • the connection pattern L1 included in the first source-drain metal layer is used for electrical connection between the drain of the third control transistor T5 and the connection pattern L0 included in the second source-drain metal layer
  • the second source-drain metal layer includes The connection pattern L0 is used for electrical connection between the connection pattern L1 included in the second source-drain metal layer and the anode layer.
  • FIG. 28 is a layout diagram of a display panel provided by an embodiment of the present disclosure.
  • the data line labeled Data(m) is the mth column data line
  • the data line labeled Data(m+1) is the m+1th column data line
  • the one labeled ELVDD is the first power line
  • the label is Vint Is the initial voltage line
  • labeled Reset(n) is the reset line of the nth row
  • labeled Reset(n+1) is the reset line of the n+1th row
  • labeled EM(n) is the nth row of light-emitting Control line
  • the light-emitting control line labeled EM(n+1) is the n+1th row
  • the gate line labeled G(n) is the nth row
  • the one labeled G(n+1) is the n+1th row Line gate line.
  • 16g is the channel region of the active layer pattern of the second switching transistor T6, 16s is the source region of the active layer pattern of the second switching transistor T6, and 16d is The drain region of the active layer pattern of the second switching transistor T6, the channel region of the active layer pattern of the first switching transistor T3, labeled 13g, and the channel region of the active layer pattern of the driving transistor T1, labeled 11g
  • the road area, marked 11d is the drain area of the active layer pattern of the driving transistor T1, marked 11s is the source area of the active layer pattern of the driving transistor T1; marked 12g is the first control transistor T2
  • the channel region of the active layer pattern, marked 12s is the source region of the active layer pattern of the first control transistor T2
  • marked 14g is the channel region of the active layer pattern of the second control transistor T4, marked The 14s is the source region of the active layer pattern of the second control transistor T4, the 15g is the channel region of the active layer pattern of the third control transistor T5, and the 15d is the third control transistor T5
  • H0 is the imaging aperture.
  • the orthographic projection of H0 on the base substrate does not overlap with the orthographic projection of the active layer pattern of the first switching transistor T3 on the base substrate.
  • H0 is on the base substrate.
  • the orthographic projection on the above does not overlap with the orthographic projection of the active layer pattern of the second switching transistor T6 on the base substrate, and the orthographic projection of H0 on the base substrate does not overlap with the orthographic projection of H0 on the n+1th row and mth column of the pixel area.
  • the active layer patterns of the two switching transistors overlap, so that the active layer pattern of the first switching transistor T3, the active layer pattern of the second switching transistor T6, and the second switching transistor in the pixel region of the n+1th row and mth column
  • the active layer pattern is not irradiated by the light passing through the imaging hole H0, so as to avoid the light-generated leakage current of the switching transistors in the off state due to the light irradiation, which will not affect the potential of the gate of the driving transistor T1. Avoid the problem of inaccurate grayscale display.
  • the distance d1 between the edge of the orthographic projection of H0 on the base substrate and 16g' is greater than the distance d2 between the edge of the orthographic projection of H0 on the base substrate and 15g.
  • the shortest distance between the edge of the orthographic projection of H0 on the base substrate and the active layer of the first switching transistor T3 is greater than the edge distance of the orthographic projection of H0 on the base substrate, except for the first switching transistor T3 and the first switching transistor T3 and the first switching transistor T3.
  • the distance between the active layer of any transistor other than the two switching transistors T6, the shortest distance between the edge of the orthographic projection of H0 on the base substrate and the active layer of the second switching transistor T6 is greater than that of H0 on the base substrate
  • the edge distance of the orthographic projection is the distance between the active layer of any transistor except the first switching transistor T3 and the second switching transistor T6.
  • 11d is connected to the source region in the active layer pattern of the third control transistor T5, 15d is connected to the drain region in the active layer pattern of the fourth control transistor T7, and 16d It is connected to the source region of the active layer pattern of the first switching transistor T3, 11s is connected to the drain region of the active layer pattern of the second control transistor T4, and 11d is connected to the drain region of the active layer pattern of the third control transistor T5 Area is connected, 11s is connected with the drain area of the active layer pattern of the first control transistor T2.
  • T6g' is the gate of the second switching transistor in the pixel area of the n+1th row and the mth column.
  • T1g is the gate of the driving transistor T1
  • T2g is the gate of the first control transistor T2
  • T3g is the gate of the first switching transistor T3, which is labeled T4g is the gate of the second control transistor T4, labeled T5g is the gate of the third control transistor T5, labeled T6g is the gate of the second switching transistor T6, labeled T7g is the fourth control transistor T7 ⁇ Grid.
  • the vertical vertical lines except the data line and the first power line are connecting lines.
  • the display panel provided by the embodiment of the present disclosure shown in FIG. 28 has designed the design position of the imaging aperture, which reduces the influence of the aperture imaging system on the display quality, especially the display accuracy, while maintaining the accuracy of the imaging recognition of the aperture. Improved display quality.
  • the first anode included in the anode layer is labeled An1
  • the second anode included in the anode layer is labeled An2
  • the third anode included in the anode layer is labeled An3
  • the third anode included in the anode layer is labeled An4.
  • the anode layer includes a fourth anode.
  • the first anode An1 included in the anode layer is electrically connected to the drain of the third control transistor T5 through the connection pattern L0 included in the second source/drain metal layer and the connection pattern L1 included in the first source/drain metal layer.
  • FIG. 28 shows the data line Data(m+2) in the m+2th column, the data line Data(m+3) in the m+3th column, and the first power supply lines in two columns, and also shows the fifth column of the anode layer.
  • An1 may be an anode of a blue organic light emitting diode
  • An5 may be an anode of a red organic light emitting diode
  • An7 may be an anode of a green organic light emitting diode, but it is not limited thereto.
  • the imaging pinhole H0 is provided in the pixel area surrounded by Reset(n), Reset(n+1), D(m), and D(m+1), but it is not limited to this.
  • the imaging hole H0 and the connection pattern L0 need to be separated by a certain distance, and the orthographic projection of the light leakage gap F1 between the connection pattern L0 and the light shielding pattern SE on the base substrate needs to be covered by the metal electrode (such as storage).
  • the metal electrode such as storage
  • the width of the light leakage gap F1 cannot be infinitely narrow, the radius of the imaging hole H0, the size of the connection pattern L0 and the imaging hole
  • the distance between H0 and the connecting figure L0 is also limited by the production accuracy and cannot be infinitely small. Therefore, the area of each figure in the pixel area with the imaging hole can be compared with that of the pixel area without the imaging hole.
  • each pattern is appropriately enlarged to ensure that the orthographic projection of the light leakage gap F1 between the connection pattern L0 and the light-shielding pattern SE on the base substrate needs to be lined by the metal electrode (such as the plate of the storage capacitor) included in the array layer Orthographic coverage on the base substrate.
  • the metal electrode such as the plate of the storage capacitor
  • the manufacturing method of the display panel provided by the embodiment of the present disclosure shown in FIG. 28 may include: forming an array layer on a base substrate; forming a light-shielding layer on the side of the array layer away from the base substrate; and forming a plurality of layers on the light-shielding layer
  • the imaging aperture; the first orthographic projection of the imaging aperture on the base substrate and the second orthographic projection of the active layer pattern of the switching transistor in the array layer on the base substrate do not overlap; the switching transistor is the same as that in the array layer A transistor connected to the gate of the driving transistor.
  • the light-shielding layer and the imaging apertures in the light-shielding layer may not be provided.
  • the structure of the display panel provided by the embodiment of the present disclosure is not limited to that shown in FIG. 28.
  • FIG. 29 is a layout diagram of a display panel provided by another embodiment of the present disclosure. Compared with the display panel shown in FIG. 28, the display panel shown in FIG. 29 does not have imaging apertures.
  • the first anode An1 is electrically connected to the drain of the third control transistor T5 through the connection pattern L01 included in the second source-drain metal layer and the connection pattern L11 included in the first source-drain metal layer.
  • the second source/drain metal layer may not be provided, and the first anode An1 is electrically connected to the drain of the third control transistor T5 through the connection pattern L11 included in the first source/drain metal layer.
  • other suitable setting methods can also be used.
  • FIG. 30 is a cross-sectional view of a display panel provided by an embodiment of the disclosure.
  • the display panel includes a first base substrate BS1, a first barrier layer BR1, and a second base substrate BS2.
  • the first transistor 01 and the second transistor 02 are provided on the second base substrate BS2.
  • the first transistor 01 is connected to the anode AN.
  • the first transistor 01 includes an active layer ACT1, a first gate insulating layer GI1, a first gate GT1, a first source SE1, and a first drain DE1.
  • the first source SE1 includes two layers: a source SE11 and a source SE12.
  • the first drain electrode DE1 includes two layers: a drain electrode DE11 and a drain electrode DE12.
  • the second transistor 02 includes an active layer ACT2, a second gate insulating layer GI2, a second gate GT2, a second source SE2, and a second drain DE2.
  • the second source SE2 includes two layers: a source SE21 and a source SE22.
  • the second drain electrode DE2 includes two layers: a drain electrode DE21 and a drain electrode DE22.
  • the display panel further includes a first interlayer dielectric layer ILD1, a second buffer layer BF2, a second interlayer dielectric layer ILD2, a passivation layer PVX, a first planarization layer PLN1, and a second planarization layer PLN2 , Pixel definition layer PDL and support layer PS.
  • the pixel definition layer PDL and the support layer PS can be formed by the same film layer using the same patterning process, but are not limited thereto.
  • the drain electrode DE11 and the drain electrode DE12 in FIG. 30 may be the connection pattern L11 and the connection pattern L01 in FIG. 29, respectively.
  • the first active layer ACT1 is a polysilicon semiconductor layer
  • the second active layer ACT2 is an oxide semiconductor layer
  • the polysilicon semiconductor layer is closer to the base substrate.
  • the base substrate adopts a flexible substrate
  • the first base substrate BS1 and the second base substrate BS2 are both flexible base substrates.
  • polyimide may be used, but is not limited thereto.
  • the material of the first barrier layer BR1 may be SiOx or SiNx or a stacked layer thereof, and the thickness is between 400 nm and 800 nm.
  • the base substrate may also adopt other flexible plastic substrates.
  • the base substrate may also be a base substrate made of glass or quartz material.
  • a second barrier layer BR2 and a first buffer layer BF1 are further provided between the second base substrate BS2 and the first transistor 01.
  • the second barrier layer BR2 may use silicon oxide, but is not limited thereto.
  • the first buffer layer BF1 may include a buffer layer BF11 and a buffer layer BF12.
  • the buffer layer BF11 can be SiNx, and the buffer layer BF12 can be SiOx.
  • the thickness of the first buffer layer BF1 is 600-1000 nm.
  • the thickness of the buffer layer BF11 is between 400-600 nm.
  • the first buffer layer BF1 may also take the form of a single layer instead of a stacked layer.
  • the function of the buffer layer BF11 is to prevent impurity particles in the substrate from entering the semiconductor region and affecting the characteristics of the transistor.
  • At least one of the buffer layer BF11, the buffer layer BF12, the first barrier layer BR1, and the second barrier layer BR2 may be the barrier layer described previously.
  • the thickness of the first active layer ACT1 is 30-70 nm, and a polysilicon semiconductor layer can be used.
  • the polysilicon semiconductor layer can be used as the channel of the driving transistor.
  • a light shielding layer can be formed before the polysilicon is formed.
  • Polysilicon is formed after SiOx is formed on the layer.
  • the first gate insulating layer GI may be SiOx, and the thickness may be 80-180 nm.
  • the first gate GT1 may be Mo, Ti, Cu or alloys thereof, and the thickness is 15-350 nm.
  • a conductive pattern is formed in the same layer as the oxide semiconductor region.
  • the conductive pattern can be used as a shielding layer for subsequent oxides to prevent light from irradiating the oxide semiconductor layer to cause characteristic degradation.
  • the first interlayer insulating layer ILD1 may adopt a three-layer structure of SiOx, SiNx and SiOx.
  • the thickness of the first interlayer insulating layer ILD1 is 100-350 nm
  • the oxide semiconductor layer is SiOx, which is thicker than SiNx. In order to ensure the characteristics of the oxide.
  • the second buffer layer BF2 may use SiOx.
  • the thickness of the second active layer ACT2 is 30-60 nm, and IGZO can be used, but is not limited thereto.
  • the second gate insulating layer GI2 may be SiOx, and the thickness may be 100-300 nm.
  • the second gate GT2 may be Mo, Ti, Cu or alloys thereof, and the thickness may be 15-350 nm.
  • the first interlayer dielectric layer ILD1 and the second interlayer dielectric layer ILD2 may use at least one of SiOx and SiNx.
  • the first interlayer dielectric layer ILD1 may be in the form of a double-layered SiNx/SiOx layer, and the second interlayer dielectric layer ILD2 may be SiOx.
  • the first gate insulating layer GI1 and the second gate insulating layer GI2 may use at least one of SiOx and SiNx.
  • the passivation layer PVX can be SiOX, and the thickness can be 200-500 nm.
  • the first flat layer PLN1, the second flat layer PLN2, the pixel definition layer PDL, and the support layer PS can all be polyimide, but it is not limited thereto.
  • the arrangement of the source electrode SE21 and the source electrode SE22 can protect the second active layer ACT2, thereby improving the stability of the second transistor 02.
  • An organic functional layer and a cathode are formed on the structure shown in FIG. 30, and then encapsulated to form an OLED display device. It is also possible to form a touch structure on the packaging layer, and the touch structure may adopt a metal mesh, but is not limited to this.
  • FIG. 30 also shows the conductive member 03 and the conductive member 04.
  • the conductive member 03 and the conductive member 04 may be conductive members CL provided by embodiments of the present disclosure, respectively.
  • the conductive member 03, the source electrode SE21, the drain electrode DE22, the source electrode SE11, and the drain electrode DE12 are formed from the same film layer using the same patterning process.
  • the conductive member 04, the source electrode SE12, and the drain electrode DE12 are formed from the same film layer using the same patterning process.
  • both the source electrode and the drain electrode are formed of metal or alloy materials.
  • FIG. 31 is a cross-sectional view of a display panel provided by another embodiment of the present disclosure. Compared with the display panel shown in FIG. 30, the display panel shown in FIG. 31 is not provided with the source electrode SE21 and the source electrode SE22.
  • the first conductive member CL1 and the second conductive member CL2 in the display panel provided by the embodiments of the present disclosure may be located in areas with high static electricity generation, such as the pad area, and areas with low static electricity generation, such as the pixel area.
  • the arrangement of the three conductive sub-layers protruding from the second surface, that is, the usual conductive members are arranged.
  • the conductive member with the third conductive sublayer protruding from the second surface has a boundary with the usual conductive member, and the boundary is located outside the display area to prevent static electricity from affecting the pixel area.
  • the pad area includes at least one of the pad area for connecting an external circuit, the pad area for array testing, and the pad area for binding the touch circuit, but it is not limited thereto.
  • first conductive sublayer 101, the second conductive sublayer 102, and the third conductive sublayer 103 in the figure form a plane structure completely parallel to the base substrate 100, they are not limited to this. According to the characteristics of the shape of the film layer under the conductive member, it can naturally be formed on an uneven surface and thus it also has an incompletely flat plane. In such an example, the above-mentioned angle can also be understood as conforming to the conductive sub-layer The corresponding angle formed by the surface, but not limited to this.
  • FIG. 32 is a partial plan view of a display panel provided by an embodiment of the disclosure.
  • Fig. 33 is an enlarged schematic diagram of the data selector in Fig. 32. The display panel will be described below with reference to FIGS. 32 and 33.
  • the conductive member CL is electrically connected to the first conductive portion 61, and the display panel shown in FIG. 32 uses the first conductive portion 61 as the data line DL and the conductive member CL as the pad PD as an example for description.
  • the data line DL provides a data voltage for each pixel unit SP.
  • the pad PD is used to connect to an external circuit.
  • the external circuit includes an integrated circuit (IC), but is not limited to this.
  • the conductive member CL and the first conductive portion 61 are formed from the same film layer using the same patterning process.
  • the conductive member CL and the first conductive portion 61 are located on the first source-drain metal layer LY3.
  • the insulating layer between adjacent conductive members includes a first organic material (such as epoxy resin), and the insulating layer between adjacent first conductive parts is made of a second organic material (such as polyamide) that is different from the first organic material.
  • a first organic material such as epoxy resin
  • the insulating layer between adjacent first conductive parts is made of a second organic material (such as polyamide) that is different from the first organic material.
  • Imine or inorganic materials (such as SiOX or silicon oxide or their laminates).
  • the dielectric constant of the first organic material is smaller than that of the second organic material or inorganic material.
  • the display panel further includes a second conductive portion 62, and the second conductive portion 62 and the conductive member CL are disposed on different layers.
  • the second conductive portion 62 and the conductive member CL are located in the same layer, but it is not limited thereto.
  • first conductive portions 61 and a plurality of second conductive portions 62 are provided, and there is a first interval IN1 between adjacent conductive members CL, and between adjacent first conductive portions 61 There is a second interval IN2, and the first interval IN1 is different from the second interval IN2. For example, the first interval IN1 is smaller than the second interval IN2.
  • the length of the conductive member CL is smaller than the length of the first conductive portion 61.
  • the length of an element refers to the dimension along the extension direction of the element.
  • the conductive member CL is connected to the expansion line FL, and the expansion line FL is connected to the data line DL.
  • the expansion line FL and the data line DL are connected through a via hole penetrating the insulating layer.
  • the expansion line FL includes the expansion line FL1 and the expansion line FL2.
  • one of the expansion line FL1 and the expansion line FL2 is located in the first gate metal layer LY1, and the other of the expansion line FL1 and the expansion line FL2 is located in the second gate metal layer LY2.
  • FIG. 32 also shows a first power line PL1 and a second power line PL2, a plurality of second power lines PL2 are connected to the bus 311, and the first power line PL1 and the second power line PL2 are also located on the first source drain metal layer LY2 .
  • FIG. 32 also shows a plurality of gate lines GL and a plurality of pixel cells SP.
  • the gate line GL extends in the first direction DR1
  • the data line DL extends in the second direction DR2
  • the plurality of gate lines GL and the plurality of data lines DL are insulated from each other, and the plurality of gate lines GL and the plurality of data lines DL cross each other to define Multiple pixel units SP.
  • the first power line PL1 is configured to provide a first power voltage to the pixel unit SP
  • the second power line PL2 is configured to provide a second power voltage to the pixel unit SP.
  • the first power line PL1 is a VDD line
  • the second power line PL2 is a VSS line.
  • the second power line PL2 is connected to the cathode of the light emitting diode.
  • each pad PD is respectively connected to two expansion lines FL1 through a data selector MUX, and then is electrically connected to two data lines DL, respectively.
  • the first signal line L1 and the second signal line L2 are controlled to be turned on at different time periods, so that the data signal is transmitted to the two data lines DL connected to the data selector MUX.
  • the setting method of the data selector MUX can refer to the usual design.
  • the data selector MUX is not limited to connecting two data lines DL, and the number of data lines DL connected to the data selector MUX can be determined according to needs.
  • each data selector MUX includes an active layer ACTL.
  • the portion of the active layer ACTL covered by the first signal line L1 and the second signal line L2 is a channel region.
  • the part covered by the first signal line L1 and the second signal line L2 is a conductor.
  • the first end of the active layer ACTL is connected to a data line DL
  • the second end of the active layer ACTL is connected to another data line DL
  • the third end of the active layer ACTL is connected to the pad PD through the second conductive portion 62 .
  • the first end, the second end, and the third end of the active layer ACTL are all located in the conductor part of the active layer ACTL, and can be connected to the active layer ACTL through an adapter (which can be located in the first source/drain metal layer).
  • the first conductive portion 61 is not limited to the data line.
  • each pixel unit includes a pixel circuit layer provided on the barrier layer, an organic electroluminescent device electrically connected to the pixel circuit layer, and a touch electrode provided on the light emitting side of the organic electroluminescent device.
  • the first conductive portion 61 It is any one of pixel circuit layer, organic electroluminescence element or touch electrode.
  • FIG. 34A is a partial cross-sectional view of a display panel provided by an embodiment of the disclosure.
  • FIG. 34A is a partial cross-sectional view of the dotted circle B1 in FIG. 32.
  • the base substrate 100 is provided with a barrier layer BR and an insulating layer ISL1, and the second conductive portion 62 is located on the insulating layer ISL1.
  • the conductive member CL has a first end E1, the second conductive portion 62 has a second end E2, an insulating layer ISL2 is provided between the first end E1 and the second end E2, and the insulating layer ISL2 has an exposed second end In the first via hole V1 of E2, the conductive member CL is connected to the second conductive portion 62 through the first via hole V1.
  • the insulating layer ISL2 has a first via hole exposing the first end E1.
  • the second conductive portion 62 may be located between the barrier layer BR and the insulating layer ISL1, so that the first via hole V1 penetrates the insulating layer ISL1 and the insulating layer ISL2.
  • FIG. 34B is a partial cross-sectional view of a display panel provided by an embodiment of the disclosure.
  • FIG. 34B is a partial cross-sectional view of the dotted circle B2 in FIG. 32.
  • the display panel further includes a third conductive portion 63, the conductive member CL is electrically connected to the third conductive portion 63, the third conductive portion 63 has a third end E3, and the first conductive portion 61 has a third conductive portion E3.
  • An insulating layer ISL2 is provided between the four ends E4, the third end E3 and the fourth end E4.
  • the insulating layer ISL2 has a second via V2 exposing the third end E3, and the first conductive portion 61 passes through the second via
  • the hole V2 is electrically connected to the third conductive portion 63.
  • the insulating layer ISL2 has a second via V2 exposing the fourth end portion.
  • the third conductive portion 63 may be located between the barrier layer BR and the insulating layer ISL1, so that the first via hole V1 penetrates the insulating layer ISL1 and the insulating layer ISL2.
  • FIG. 35 is a partial top view of a display panel provided by an embodiment of the disclosure.
  • the conductive member CL includes a first portion PT1 and a second portion PT2.
  • the width of the first portion PT1 is greater than the width of the second portion PT2.
  • the third conductive sublayer 103 of the first portion PT1 extends along the width of the conductive member CL.
  • the direction protrudes from the second surface S2, and the third conductive sublayer 103 of the second portion PT2 is flush with the second surface S2 along the width direction of the conductive member CL.
  • the third conductive sublayer 103 of the first portion PT1 and the second portion PT2 may both protrude from the second surface S2 along the width direction of the conductive member CL, and the third conductive sublayer 103 of the first portion PT1
  • the third conductive sublayer 103 of the layer 103 protruding from the second surface S2 in the width direction of the conductive member CL is greater than the width of the second portion PT2 protruding from the width of the second surface S2 in the width direction of the conductive member CL.
  • the conductive member having a structure in which the third conductive sublayer protrudes from the second surface of the second conductive sublayer in the width direction of the conductive member is not covered by the flat layer.
  • the first conductive portion 61 provided in the same layer as the conductive member CL shown in FIG. 32 is covered by the flat layer, and the conductive member CL is not covered by the flat layer.
  • At least one embodiment of the present disclosure provides a display device including any of the above-mentioned display panels.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an Organic Light-Emitting Diode (OLED) display, and a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, and a navigation device including these display devices. Any product or component with display function such as instrument.
  • a display device such as a liquid crystal display, an electronic paper, an Organic Light-Emitting Diode (OLED) display, and a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, and a navigation device including these display devices.
  • Any product or component with display function such as instrument.
  • the conductive member may be a part or all of the conductive structure, and the conductive member may be a pattern formed by a continuous metal structure or a stacked structure of a plurality of metal conductive patterns.
  • each element is only a schematic description, and is not limited to what is shown in the figure, and can be determined according to needs.

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Abstract

提供一种显示面板和显示装置。显示面板包括：衬底基板以及导电构件，导电构件位于所述衬底基板上，所述导电构件包括依次层叠的第一导电子层、第二导电子层和第三导电子层，所述第一导电子层比所述第三导电子层更靠近所述衬底基板，所述第一导电子层的电导率小于所述第二导电子层的电导率，所述第三导电子层的熔点大于所述第二导电子层的熔点，所述第二导电子层包括靠近所述第一导电子层的第一表面和靠近所述第三导电子层的第二表面，所述第一表面和所述第二表面相对设置，所述第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述宽度方向与所述导电构件的延伸方向相交。包含该显示面板的显示装置可降低静电击穿的风险。

Description

显示面板和显示装置
相关申请的交叉引用
本专利申请要求于2020年05月21日递交的中国专利申请第202010435328.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一实施例涉及一种显示面板和显示装置。
背景技术
显示装置例如液晶显示(Liquid Crystal Display，LCD)装置、有源矩阵有机发光二极管(Active Matrix Organic Light-Emitting Diode，AMOLED)装置、微发光二极管(Micro-LED)装置等的日益发展极大地丰富了人们的生活，消费者对显示品质的追求也越来越高，如更高分辨率(8K)，更高刷新频率(90HZ、120HZ)以及更多的产品形态(折叠、卷曲)的显示面板被开发出来，随着显示品质的提升，对显示面板的制造工艺也带来了新的挑战。
发明内容
本公开的至少一实施例涉及一种显示面板和显示装置。
本公开至少一实施例提供一种显示面板，包括：显示区，具有多个像素单元；周边区，位于显示区的至少一侧；阻隔层，位于衬底基板上；导电构件，设置在所述阻隔层的背离所述衬底基板的一侧，所述导电构件在其延伸方向上的长度大于所述导电构件在与延伸方向相交的方向上的宽度，且所述导电构件包括依次层叠的第一导电子层、第二导电子层和第三导电子层，所述第一导电子层比所述第三导电子层更靠近所述衬底基板；以及第一导电部，位于所述显示区，所述第一导电部与所述导电构件同层设置且材料相同，其中，所述第一导电子层的电导率小于所述第二导电子层的电导率且所述第一导电子层的厚度小于所述第二导电子层的厚度，所述第三导电子层的熔点大于所述第二导电子层的熔点，所述第二导电子层包括靠近所述第一导电子层的第一表面和靠近所述第三导电子层的第二表面，所述第一表面和所述第二表面相对设置，所述第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述宽度方向与所述导电构件的延伸方向相交。
根据本公开一个或多个实施例提供的显示面板，所述第三导电子层不与所述第一导电子层接触。
根据本公开一个或多个实施例提供的显示面板，所述第二导电子层还包括连接所述第一表面和所述第二表面的位于所述第二导电子层的同一侧的侧边的侧面，在垂直于所述导电构件的延伸方向截取的截面中，所述侧面与所述第一导电子层的交点为第一交点，所述侧面与所述第三导电子层的交点为第二交点，所述侧面的至少一部分位于所述第一交点和所述第二交点的连线的靠近所述第二导电子层的一侧。
根据本公开一个或多个实施例提供的显示面板，所述侧面包括至少两个子侧面，所述至少两个子 侧面包括靠近所述第一导电子层的第一子侧面和靠近所述第三导电子层的第二子侧面，所述第一子侧面与所述第一导电子层所成的角度小于所述第二子侧面与所述第一导电子层所成的角度。
根据本公开一个或多个实施例提供的显示面板，在垂直于所述导电构件的延伸方向截取的所述截面中，所述第二子侧面的延长线与所述第一导电子层的交点与所述第一子侧面与所述第一导电子层的交点之间的距离为d1，所述第一导电子层超出所述第一表面的距离为Δw1，d1<Δw1。
根据本公开一个或多个实施例提供的显示面板，所述第三导电子层超出所述第二表面的距离为Δw2，d1<Δw2。
根据本公开一个或多个实施例提供的显示面板，所述第二子侧面与所述第一导电子层所成的角度大于90度。
根据本公开一个或多个实施例提供的显示面板，所述侧面包括依次设置的三个子侧面，所述三个子侧面包括第一子侧面、第二子侧面和第三子侧面，所述第一子侧面比所述第三子侧面更靠近所述第一导电子层，所述第一子侧面与所述第一导电子层所成的角度为第一角度，所述第二子侧面与所述第一导电子层所成的角度为第二角度，所述第三子侧面与所述第一导电子层所成的角度为第三角度，所述第三角度大于所述第二角度，所述第二角度大于所述第一角度。
根据本公开一个或多个实施例提供的显示面板，所述第二导电子层包括两个侧面，所述两个侧面相对设置，所述两个侧面沿所述导电构件的厚度方向呈对称设置。
根据本公开一个或多个实施例提供的显示面板，所述第二导电子层的所述第一表面、所述第二表面和所述侧面至少之一包含N元素、S元素、P元素和Cl元素至少之一。
根据本公开一个或多个实施例提供的显示面板，所述阻隔层具有F元素和Cl元素至少之一。
根据本公开一个或多个实施例提供的显示面板，所述阻隔层中的所述F元素和Cl元素至少之一的含量在每立方厘米1×10 18至5×10 20个原子。
根据本公开一个或多个实施例提供的显示面板，所述第一表面与所述第一导电子层接触，所述第二表面与所述第三导电子层接触。
根据本公开一个或多个实施例提供的显示面板，所述第三导电子层覆盖所述第二导电子层，并与所述第一导电子层接触。
根据本公开一个或多个实施例提供的显示面板，所述第一表面的宽度小于所述第一导电子层的宽度，所述第二表面的宽度小于所述第三导电子层的宽度，所述第三导电子层和所述第二表面的宽度差大于所述第三导电子层的厚度。
根据本公开一个或多个实施例提供的显示面板，提供两个相邻的导电构件，所述两个相邻的导电构件彼此绝缘，所述两个相邻的导电构件位于同一层，所述两个相邻的导电构件包括第一导电构件和第二导电构件，所述第一导电构件的所述第三导电子层和所述第二导电构件的所述第三导电子层之间的间距小于所述第一导电构件的所述第二导电子层的所述第二表面和所述第二导电构件的所述第二导电子层的所述第二表面之间的间距。
根据本公开一个或多个实施例提供的显示面板，所述第一导电构件的所述第二表面和所述第二导电构件的所述第二表面在不同位置处的距离不同。
根据本公开一个或多个实施例提供的显示面板，w1为所述第一导电构件在其宽度方向上的截面中的最大宽度，w2为所述第二导电构件在其宽度方向上的截面中的最大宽度，Δw11为所述第一导电构件中所述第三导电子层超出所述第二表面的距离，Δw12为所述第二导电构件中所述第三导电子层超出所述第二表面的距离，dmin为所述第一导电构件和所述第二导电构件之间的最小间距，满足以下关系式：
Figure PCTCN2021094326-appb-000001
根据本公开一个或多个实施例提供的显示面板，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件到所述衬底基板的距离不同，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件的厚度为T3，所述第二导电构件的厚度为T4，T4大于T3，所述第一导电构件中所述第三导电子层超出所述第二表面的距离为Δw3，所述第二导电构件中所述第三导电子层超出所述第二表面的距离为Δw4，满足如下关系式：
Figure PCTCN2021094326-appb-000002
根据本公开一个或多个实施例提供的显示面板，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件比所述第二导电构件更靠近所述显示区，所述第一导电构件中所述第三导电子层凸出所述第二表面的尺寸大于所述第二导电构件中所述第三导电子层凸出所述第二表面的尺寸。
根据本公开一个或多个实施例提供的显示面板，显示面板还包括第二导电部，其中，所述第二导电部与所述导电构件设置在不同层，且所述导电构件具有第一端部，所述第二导电部具有第二端部，所述第一端部和所述第二端部之间设有绝缘层，所述绝缘层具有暴露所述第一端部或所述第二端部的第一过孔，所述导电构件通过所述第一过孔与所述第二导电部相连。
根据本公开一个或多个实施例提供的显示面板，显示面板还包括第二导电部，所述第二导电部与所述导电构件位于同一层。
根据本公开一个或多个实施例提供的显示面板，显示面板还包括第三导电部，其中，所述第一导电部电连接至所述第三导电部，所述第三导电部具有第三端部，所述第一导电部具有第四端部，所述第三端部和所述第四端部之间设有绝缘层，所述绝缘层具有暴露所述第三端部或所述第四端部的第二过孔，所述第一导电部通过所述第二过孔与所述第三导电部电连接。
根据本公开一个或多个实施例提供的显示面板，所述导电构件包括第一部分和第二部分，所述第一部分的宽度大于所述第二部分的宽度，所述第一部分的第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述第二部分的第三导电子层沿所述导电构件的宽度方向与第二表面平齐，或者所述第一部分和所述第二部分的第三导电子层均沿所述导电构件的宽度方向凸出于所述第二表面，所述第一部分凸出的宽度大于所述第二部分凸出的宽度。
根据本公开一个或多个实施例提供的显示面板，所述导电构件和所述第一导电部电连接，提供多个第一导电部，相邻导电构件之间具有第一间隔，相邻第一导电部之间具有第二间隔，所述第一间隔与所述第二间隔不同。
根据本公开一个或多个实施例提供的显示面板，所述第一间隔小于所述第二间隔。
根据本公开一个或多个实施例提供的显示面板，所述导电构件的长度小于所述第一导电部的长度，所述第一导电部包括数据线，所述数据线为与其相连的像素单元提供数据电压。
根据本公开一个或多个实施例提供的显示面板，所述每个像素单元包括设置在所述阻隔层上的像素电路层、与所述像素电路层电连接的有机电致发光器件，以及设置在所述有机电致发光器件出光侧的触控电极，所述第一导电部为所述像素电路层，所述有机电致发光元件或所述触控电极中的任意一种。
本公开至少一实施例还提供一种显示面板，包括：显示区，具有多个像素单元，包括可折叠区和位于所述可折叠区的相对的两侧的第一显示区和第二显示区；周边区，位于显示区的至少一侧；阻隔层，位于衬底基板上；导电构件，设置在所述阻隔层的背离所述衬底基板的一侧，所述导电构件在其延伸方向上的长度大于所述导电构件在与延伸方向相交的方向上的宽度，且所述导电构件包括依次层叠的第一导电子层、第二导电子层和第三导电子层，所述第一导电子层比所述第三导电子层更靠近所述衬底基板；以及第一导电部，位于所述显示区，所述第一导电部与所述导电构件同层设置且材料相同，其中，所述第一导电子层的电导率小于所述第二导电子层的电导率且所述第一导电子层的厚度小于所述第二导电子层的厚度，所述第三导电子层的熔点大于所述第二导电子层的熔点，所述第二导电子层包括靠近所述第一导电子层的第一表面和靠近所述第三导电子层的第二表面，所述第一表面和所述第二表面相对设置，所述第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述宽度方向与所述导电构件的延伸方向相交。
根据本公开一个或多个实施例提供的显示面板，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件比所述第二导电构件更靠近所述可折叠区，所述第一导电构件中所述第三导电子层凸出所述第二表面的尺寸大于所述第二导电构件中所述第三导电子层凸出所述第二表面的尺寸。
本公开至少一实施例还提供一种显示面板，包括：显示区，具有多个像素单元；周边区，位于显示区的至少一侧；透光区，位于所述周边区的远离所述显示区的一侧或被所述显示区包围；阻隔层，位于衬底基板上；导电构件，设置在所述阻隔层的背离所述衬底基板的一侧，所述导电构件在其延伸方向上的长度大于所述导电构件在与延伸方向相交的方向上的宽度，且所述导电构件包括依次层叠的第一导电子层、第二导电子层和第三导电子层，所述第一导电子层比所述第三导电子层更靠近所述衬底基板；以及第一导电部，位于所述显示区，所述第一导电部与所述导电构件同层设置且材料相同；所述第一导电子层的电导率小于所述第二导电子层的电导率且所述第一导电子层的厚度小于所述第二导电子层的厚度，所述第三导电子层的熔点大于所述第二导电子层的熔点，所述第二导电子层包括靠近所述第一导电子层的第一表面和靠近所述第三导电子层的第二表面，所述第一表面和所述第二表面相对设置，所述第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述宽度方向与所述导电构件的延伸方向相交。
根据本公开一个或多个实施例提供的显示面板，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件比所述第二导电构件更靠近所述透光区，所述第一导电构件中所述第三导电子层凸出所述第二表面的尺寸大于所述第二导电构件 中所述第三导电子层凸出所述第二表面的尺寸。
本公开至少一实施例还提供一种显示装置，包括上述任一显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示面板中的多个导电构件的示意图；
图2为图1的沿A-B线的剖视图；
图3为本公开一实施例提供的一种显示面板的平面图；
图4为图3的沿A1-A2线的一种剖视图；
图5A为图3的沿A1-A2线的另一种剖视图；
图5B为图3的沿A1-A2线的另一种剖视图；
图6A为图3的沿A1-A2线的另一种剖视图；
图6B为本公开一实施例提供的显示面板上的导电构件的部分剖视图；
图7为本公开一实施例提供的显示面板上的导电构件的部分剖视图；
图8为图3的沿A1-A2线的另一种剖视图；
图9为本公开一实施例提供的一种显示面板的剖视图；
图10为图9所示的显示面板中第一导电构件和第三导电构件的平面图；
图11为图9所示的显示面板中第一导电构件和第三导电构件的剖视图；
图12为本公开一实施例提供的一种显示面板中的相邻导电构件的剖视图；
图13为本公开一实施例提供的一种显示面板的剖视图；
图14为本公开一实施例提供的一种显示面板的平面图；
图15A为本公开一实施例提供的一种显示面板的平面图；
图15B为本公开另一实施例提供的一种显示面板的平面图；
图16A为本公开一实施例提供的一种显示面板的平面图；
图16B为本公开另一实施例提供的一种显示面板的平面图；
图17A为本公开一实施例提供的一种显示面板的平面图；
图17B为本公开一实施例提供的一种显示面板的平面图；
图17C为本公开一实施例提供的显示面板的局部平面图；
图18为本公开一实施例提供的一种含有本公开的实施例提供的显示面板的显示装置的立体图；
图19为图18所示的显示装置的平面图；
图20为本公开一实施例提供的一种含有本公开的实施例提供的显示面板的可折叠显示装置的平面图；
图21为图20所示的可折叠显示装置中的部分GOA电路的示意图；
图22A为图21中的水平设置的连接线的俯视图；
图22B为图21中的水平设置的两条相邻的连接线的俯视图；
图23为本公开另一实施例提供的一种含有本公开的实施例提供的显示面板的可折叠显示装置的平面图；
图24为本公开一实施例提供的一种显示面板的平面示意图；
图25是本公开一实施例提供的显示面板的像素中的像素驱动电路的电路图；
图26是图25所示的像素驱动电路的工作时序图；
图27是本公开一实施例提供的显示面板中的第二源漏金属层的示意图；
图28是本公开一实施例提供的显示面板的布局图；
图29是本公开一实施例提供的显示面板的布局图；
图30为本公开一实施例提供的显示面板的剖视图；
图31为本公开另一实施例提供的显示面板的剖视图；
图32为本公开的实施例提供的一种显示面板的局部平面图；
图33为图32中数据选择器的放大示意图；
图34A为本公开一实施例提供的显示面板的局部剖视图；
图34B为本公开一实施例提供的显示面板的局部剖视图；以及
图35为本公开一实施例提供的显示面板的局部俯视图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
显示装置的显示分辨率的提升导致负载加大，信号延迟加重，引入低电阻导电结构是解决信号延迟的手段之一，而低电阻导电结构之间的间距随着分辨率的增加而缩小，容易产生由于工艺等原因或者后续使用过程引起的不良如静电放电和静电击穿现象。
图1为一种显示面板中的多个导电构件的示意图。如图1所示，相邻导电构件11之间的距离较小，容易产生静电放电导致静电击穿。图1仅示意性地示出了四个导电构件，导电构件的个数以及导电构件的排布方式不限于图中所示。导电构件11位于衬底基板上，图1中未示出衬底基板，可参 照图2所示。
图2为图1的沿A-B线的剖视图。如图2所示，导电构件11位于衬底基板10上，每个导电构件11包括第一导电子层11a、第二导电子层11b和第三导电子层11c。每个导电构件11的截面可以呈正梯形，但不限于此。在形成导电构件11时，可在衬底基板10上依次形成第一导电薄膜、第二导电薄膜和第三导电薄膜，再对第一导电薄膜、第二导电薄膜和第三导电薄膜进行刻蚀，以形成图2所示的导电构件11。可采用干法刻蚀或湿法刻蚀形成导电构件11。如图2所示，相邻第三导电子层11c之间的间距大于相邻第二导电子层11b之间的间距。
如图2所示，两个相邻导电构件11之间的间距较小，导致图2所示的两个相邻导电构件11容易产生不良如静电击穿现象。
图3为本公开一实施例提供的一种显示面板的平面图。如图3所示，该显示面板包括：衬底基板100(图3未示出，参照图4)以及导电构件CL。
图4为图3的沿A1-A2线的一种剖视图。参考图3和图4，导电构件CL在其延伸方向上的长度大于导电构件CL在与延伸方向相交的方向上的宽度。与延伸方向相交的方向可指导电构件CL的宽度方向。参考图3和图4，导电构件CL包括依次层叠的第一导电子层101、第二导电子层102和第三导电子层103，第一导电子层101比第三导电子层103更靠近衬底基板100。例如，第一导电子层101的电导率小于第二导电子层102的电导率，第三导电子层103的熔点大于第二导电子层102的熔点。例如，第三导电子层103的电导率小于第二导电子层102的电导率，第一导电子层101的熔点大于第二导电子层102的熔点。图3示出了两个相邻的导电构件CL。衬底基板100可采用刚性衬底基板，也可以采用柔性衬底基板。刚性衬底基板包括玻璃基板，柔性衬底基板的材料包括聚酰亚胺，但不限于此。
例如，衬底基板可以为柔性衬底或者玻璃衬底，柔性衬底可以是聚酰亚胺(PI)、聚硅烷、聚硅氧烷、聚硅氮烷、聚碳硅烷、聚丙烯酸酯中的一种或其中几种的叠层。
例如，第一导电子层101、第二导电子层102和第三导电子层103均可采用金属材料或合金来制作。例如，第一导电子层101的材料可采用钼(Mo)、钛(Ti)、钕(Nd)、铬(Cr)、镍(Ni)至少之一，第二导电子层102的材料可采用铝(Al)、铜(Cu)、银(Ag)至少之一，第三导电子层103的材料可采用钼、钛、钕、铬、镍、钨(W)至少之一，但不限于此。例如，第一导电子层101和第三导电子层10可采用相同的材料制作，但不限于此。例如，导电构件CL可采用Mo/Al/Mo、Ti/Al/Ti、Mo/Cu/Mo以及Ti/Cu/Ti等三个导电子层层叠设置的形式。
例如，如图4所示，显示面板还包括位于衬底基板上的阻隔层BRL。导电构件CL和衬底基板100之间设有阻隔层BRL。阻隔层BRL可采用无机绝缘膜，例如，可以为氮化硅(SiNx)的单层、氧化硅的单层(SiOx)或包括彼此堆叠的氮化硅(SiNx)和氧化硅(SiOx)的多层形成，阻隔层BRL可以有效覆盖衬底基板上的杂质或微粒，对导电构件具有保护作用。例如，阻隔层BRL可采用氧化硅，但不限于此。
例如，参考图14和图32，本公开的实施例提供的显示面板包括：显示区R1和周边区R2，显示区R1具有多个像素单元SP；周边区R2位于显示区R1的至少一侧。显示面板还包括位于衬底基板 上的第一导电部61；第一导电部位于显示区R1，第一导电部61与导电构件CL同层设置且材料相同。
如图4所示，导电构件CL位于衬底基板100上，第二导电子层102包括靠近第一导电子层101的第一表面S1和靠近第三导电子层103的第二表面S2，第一表面S1和第二表面S2相对设置。参考图3和图4，第三导电子层103沿导电构件CL的宽度方向(第一方向)DR1凸出于第二表面S2，宽度方向DR1与导电构件CL的延伸方向(第二方向)DR2相交。图3中以第二表面S2示出第二导电子层102的边界。如图4所示，第三导电子层103覆盖第二导电子层102的边缘。
例如，如图4所示，第二导电子层102的厚度大于第一导电子层101的厚度。因第二导电子层102的厚度较大且电导率较大，第二导电子层102出现工艺不良如刻蚀残留风险较大，若出现刻蚀残留，会加大横向导通或者静电击穿的风险。可以调整第二导电子层102和第三导电子层103以使得第三导电子层沿导电构件的宽度方向凸出于第二表面来减小横向导通和静电击穿的风险。静电的来源通常包括显示面板制作过程中产生的静电和含有该显示面板的装置使用过程中产生的静电。
例如，第二导电子层102的厚度范围在
Figure PCTCN2021094326-appb-000003
第一导电子层101的厚度范围在
Figure PCTCN2021094326-appb-000004
Figure PCTCN2021094326-appb-000005
第三导电子层103的厚度范围在
Figure PCTCN2021094326-appb-000006
但不限于此。例如，第二导电子层102的厚度大于第一导电子层101的厚度，并且第二导电子层102的厚度大于第三导电子层103的厚度。
例如，如图4所示，第三导电子层103在衬底基板100上的正投影的面积大于第二导电子层102的第一表面S1在衬底基板100上的正投影的面积，但不限于此。在其他的实施例中，第三导电子层103在衬底基板100上的正投影的面积也可以等于或者小于第二导电子层102的第一表面S1在衬底基板100上的正投影的面积。
例如，如图4所示，第二导电子层102还包括连接第一表面S1和第二表面S2的位于第二导电子层102的同一侧的侧边的侧面S3。如图4所示，在第二导电构件CL2中，位于左侧的侧面S3连接第一表面S1的左侧的侧边和第二表面S2的左侧的侧边，位于右侧的侧面S3连接第一表面S1的右侧的侧边和第二表面S2的右侧的侧边。如图4所示，侧面S3为斜面。第二导电子层102可呈梯形结构，但不限于此。侧面S3相对于第一导电子层101倾斜设置。
参考图3和图4，导电构件CL的宽度方向DR1为水平方向，如图3所示，导电构件CL的延伸方向DR2为竖直方向，参考图3和图4，导电构件CL的厚度方向(第三方向)DR3垂直于导电构件CL的宽度方向DR1，并且垂直于导电构件CL的延伸方向DR2。图3中以导电构件CL为直线为例进行说明，在其他的实施例中，导电构件CL也可以不为直线，例如，导电构件CL可以为折线或者曲线等其他形式。
例如，导电构件CL的延伸方向DR2可为导电构件CL的两个端点之间的连线的延伸方向，导电构件CL的宽度方向DR1可为垂直于导电构件CL的延伸方向DR2的方向。
例如，在本公开的实施例中，导电子层之间的距离和导电子层的宽度可基于不同导电子层的大致相同的位置间的几何尺寸确定，对于第二导电子层，可以基于第二导电子层的顶部位置(例如，第二表面S2)确定，也可以基于第二导电子层的底部位置(例如，第一表面S1)确定，或者基于第二导电子层的中部位置确定。
例如，参考图3和图4，两个相邻的导电构件CL彼此绝缘，两个相邻的导电构件CL位于同一层，两个相邻的导电构件CL包括第一导电构件CL1和第二导电构件CL2，第一导电构件CL1的第三导电子层103和第二导电构件CL2的第三导电子层103之间的间距spc1小于第一导电构件CL1的第二导电子层102的第二表面S2和第二导电构件CL2的第二导电子层102的第二表面S2之间的间距spc2，以利于减小相邻导电构件的静电击穿的风险。第一导电构件CL1和第二导电构件CL2可具有相同的结构，但不限于此。例如，在本公开的实施例中，两个元件位于同一层是指该两个元件由同一膜层采用同一构图工艺形成。或者，两个元件位于同一层是指与两个元件直接接触的基底材料相同。例如，由同一膜层形成的元件材料相同。例如，如图4所示，第三导电子层103不与第一导电子层101接触。第三导电子层103的宽度大于第二表面S2的宽度。例如，参考图3和图4，第三导电子层103在衬底基板100上的正投影的面积大于第二表面S2在衬底基板100上的正投影的面积。参考图3和图4，由于第三导电子层103的宽度大于第二表面S2的宽度，加大相邻第二导电子层102之间的距离，使得相邻第二导电子层之间的静电击穿的风险降低，有利于提升含有该显示面板的装置的稳定性，提升良率。
本申请的发明人发现，若第三导电子层超出第二导电子层的宽度太大，则第二导电子层的宽度变得更小，导致导电构件的电阻增大，不利于高分辨率显示；若第三导电子层超出第二导电子层的宽度太小，相邻第二导电子层之间的静电放电风险加大，则第三导电子层超出第二导电子层的宽度满足一定条件时，可得到电阻和稳定性兼顾的导电构件结构。
例如，如图4所示，满足以下关系式的显示面板，兼顾了电阻和稳定性：
Figure PCTCN2021094326-appb-000007
其中，w1为第一导电构件CL1在其宽度方向上的截面中的最大宽度，w2为第二导电构件CL2在其宽度方向上的截面中的最大宽度，Δw11为第一导电构件CL1中第三导电子层103超出第二表面S2的距离，Δw12为第二导电构件CL2中第三导电子层103超出第二表面S2的距离，dmin为第一导电构件CL1和第二导电构件CL2之间的最小间距。满足上述关系式的显示面板，使得第三导电子层超出第二导电子层的宽度对电阻的影响降到最小，同时兼顾降低静电击穿的风险。
例如，制作图4所示的显示面板的方法可包括：形成第一导电薄膜，并对第一导电薄膜进行构图形成第一导电子层101，形成第二导电薄膜，并对第二导电薄膜进行构图形成第二导电子层102；在相邻的第二导电子层102之间形成绝缘层；在绝缘层和第二导电子层102上形成第三导电薄膜，第三导电薄膜与第二导电子层102接触，对第三导电薄膜进行构图形成第三导电子层103。需要说明的是，图4所示的显示面板的制作方法不限于以上例举的方法，本领域技术人员根据本公开的实施例对显示面板的结构的描述可以选择适合的方法来制作。
图5A为本公开一实施例提供的多个导电构件的示意图。如图5A所示，显示面板包括多个导电构件CL，多个导电构件CL位于同一层，多个导电构件CL包括第一导电构件CL1、第二导电构件CL2、第三导电构件CL3和第四导电构件CL4，第一导电构件CL1和第二导电构件CL2之间的间隔SPC01不同于第三导电构件CL3和第四导电构件CL4之间的间隔SPC02，左侧的两个导电构件CL中第三导电子层103的凸出于第二导电子层102的第二表面S2的尺寸不同于右侧的两个导电 构件CL中第三导电子层103的凸出于第二导电子层102的第二表面S2的尺寸。
如图5A所示，第一导电构件CL1和第二导电构件CL2之间的间隔SPC01小于第三导电构件CL3和第四导电构件CL4之间的间隔SPC02。
如图5A所示，第一导电构件CL1中第三导电子层103沿第一导电构件CL1的宽度方向凸出于第二导电子层102的第二表面S2的尺寸为D01，第二导电构件CL2中第三导电子层103沿第二导电构件CL2的宽度方向凸出于第二导电子层102的第二表面S2的尺寸为D02，第三导电构件CL3中第三导电子层103沿第三导电构件CL3的宽度方向凸出于第二导电子层102的第二表面S2的尺寸为D03，第四导电构件CL4中第三导电子层103沿第四导电构件CL4的宽度方向凸出于第二导电子层102的第二表面S2的尺寸为D04。D01大于D03，并且大于D04；D02大于D03，并且大于D04。例如，在一些实施例中，D01等于D02，D03等于D04，但不限于此。
如图5A所示，第一导电构件CL1、第二导电构件CL2、第三导电构件CL3、第四导电构件CL4彼此平行，在其他的实施例中，相邻的导电构件也可以不平行。
图5B为本公开一实施例提供的多个导电构件的示意图。第一导电构件CL1不平行于第二导电构件CL2，第一导电构件CL1和第二导电构件CL2之间的间距SPC01从第一端至第二端逐渐增大，从而，对于同一条导电构件CL，在不同位置处，第三导电子层103凸出于第二导电子层102的第二表面S2的尺寸不同。
例如，如图5B所示，对于同一导电构件，第三导电子层103凸出于第二导电子层102的第二表面S2在间距SPC01小的位置处的尺寸小于第三导电子层103凸出于第二导电子层102的第二表面S2在间距SPC01大的位置处的尺寸，但不限于此。
图6A为图3的沿A1-A2线的另一种剖视图。例如，如图6A所示，侧面S3包括至少两个子侧面S3，至少两个子侧面S3包括靠近第一导电子层101的第一子侧面S31和靠近第三导电子层103的第二子侧面S32，第一子侧面S31与第一导电子层101所成的角度θ1小于第二子侧面S32与第一导电子层101所成的角度θ2。
第二导电子层102通常会形成具有一定倾斜角度的侧面，呈现下大上小的趋势，导致相邻的第二导电子层的间距自然会从下到上变大，本公开的实施例主要在第二导电子层的宽度减小的方式降低静电放电风险的基础上，相邻的第二导电子层的间距可以不是一直变大，角度θ2使得变大的趋势放缓，可以形成角度更缓的斜坡，结构上增大了底面处第二导电子层的宽度，降低导电构件的电阻。
图6B为本公开一实施例提供的显示面板上的导电构件的部分剖视图。如图6B所示，在垂直于导电构件CL的延伸方向DR2截取的截面中，侧面S3与第一导电子层101的交点为第一交点P1，侧面S3与第三导电子层103的交点为第二交点P2，侧面S3的至少一部分位于第一交点P1和第二交点P2的连线LN0的靠近第二导电子层102的一侧。垂直于导电构件CL的延伸方向DR2截取的截面为导电构件CL的厚度方向DR3和导电构件CL的宽度方向DR1所成的平面。
例如，如图6B所示，在垂直于导电构件CL的延伸方向DR2截取的截面中，第二子侧面S32的延长线LN1与第一导电子层101的交点P3与第一子侧面S31与第一导电子层101的交点P1之间的距离为d1，第一导电子层101超出第一表面S1的距离为Δw1。
例如，如图6B所示，在垂直于导电构件CL的延伸方向DR2截取的截面中，第一子侧面S31的延长线LN2与第三导电子层103的交点P4与第二子侧面S32与第三导电子层103的交点P2之间的距离为d2，第三导电子层103超出第二表面S2的距离为Δw2。例如，本公开的实施例中，第三导电子层103超出第二表面S2的距离是指第三导电子层103超出第二表面S2的部分在导电构件的宽度方向上的尺寸。导电构件的宽度方向与导电构件的长度方向相交。例如，导电构件的宽度方向与导电构件的长度方向垂直。
例如，如图6B所示，为了兼顾降低静电击穿的风险以及减小导电构件的电阻，d1<Δw1，进一步例如，d1<Δw2。
例如，如图6B所示，为了兼顾降低静电击穿的风险以及减小导电构件的电阻，d2<Δw1，进一步例如，d2<Δw2。
例如，如图6B所示，为了兼顾降低静电击穿的风险以及减小导电构件的电阻，Δw2<Δw1。
例如，如图6B所示，第一子侧面S31和第二子侧面S32均为斜面。参考图6A和图6B，第一子侧面S31和第二子侧面S32可分别为相对于衬底基板100的斜面。
图7为本公开一实施例提供的显示面板上的导电构件的部分剖视图。例如，如图7所示，为了兼顾降低静电击穿的风险以及减小导电构件的电阻，第二子侧面S32与第一导电子层101所成的角度θ2大于90度。
图8为图3的沿A1-A2线的另一种剖视图。例如，如图8所示，侧面S3包括依次设置的三个子侧面S3，三个子侧面S3包括第一子侧面S31、第二子侧面S32和第三子侧面S33，第一子侧面S31比第三子侧面S33更靠近第一导电子层101，第一子侧面S31与第一导电子层101所成的角度为第一角度θ1，第二子侧面S32与第一导电子层101所成的角度为第二角度θ2，第三子侧面S33与第一导电子层101所成的角度为第三角度θ3，为了兼顾降低静电击穿的风险以及减小导电构件的电阻，第三角度θ3大于第二角度θ2，第二角度θ2大于第一角度θ1。
例如，参考图4、图6A和图8，第二导电子层102包括两个侧面S3，两个侧面S3相对设置，两个侧面S3沿导电构件CL的厚度方向呈对称设置。图6B和图7中仅示出了导电构件CL的一个侧面S3，导电构件CL的另一个侧面S3也可以相对于该导电构件CL的厚度方向与示出的侧面S3呈对称设置。需要说明的是，同一导电构件的两个相对的侧面也可不对称设置，本公开的实施例对此不作限定。
参考图6A和图8，两个相邻的导电构件CL彼此绝缘，两个相邻的导电构件CL位于同一层并具有相同的结构，两个相邻的导电构件CL包括第一导电构件CL1和第二导电构件CL2，第一导电构件CL1的第三导电子层103和第二导电构件CL2的第三导电子层103之间的间距spc1小于第一导电构件CL1的第二导电子层102的第二表面S2和第二导电构件CL2的第二导电子层102的第二表面S2之间的间距spc2。
参考图3至图6A以及图8，第一导电构件CL1和第二导电构件CL2之间的间距较小。例如，第一导电构件CL1和第二导电构件CL2之间的间距可为5-19μm，但不限于此，本公开的实施例对第一导电构件CL1和第二导电构件CL2之间的间距的数值不做具体限定。
参考图4、图6A和图8，第一导电构件CL1到衬底基板100的距离与第二导电构件CL2到衬底基板100的距离可相等，但不限于此。
图9为本公开一实施例提供的一种显示面板的剖视图。如图9所示，显示面板包括：衬底基板100以及位于衬底基板100上的第一导电构件层21、绝缘层22和第二导电构件层23，第一导电构件层21包括第一导电构件CL1和第二导电构件CL2，第二导电构件层23包括第三导电构件CL3和第四导电构件CL4，第一导电构件CL1和第二导电构件CL2可分别采用如上所述的第一导电构件CL1和第二导电构件CL2，第三导电构件CL3和第四导电构件CL4可分别采用如上所述的第一导电构件CL1和第二导电构件CL2。
例如，第一导电构件层21和第二导电构件层23位于不同的层，第一导电构件层21到衬底基板100的距离与第二导电构件层23到衬底基板100的距离不同，第一导电构件CL1和第三导电构件CL3到衬底基板100的距离不同。
图10为图9所示的显示面板中第一导电构件和第三导电构件的平面图。第一导电构件CL1和第三导电构件CL3均采用第三导电子层沿导电构件的宽度方向凸出于第二表面的结构。
图11为图9所示的显示面板中第一导电构件和第三导电构件的剖视图。第一导电构件CL1的第二导电子层102的厚度为T3，第三导电构件CL3的第二导电子层102的厚度为T4，T4大于T3，第一导电构件CL1中第三导电子层103超出第二表面S2的距离为Δw3，第三导电构件CL3中第三导电子层103超出第二表面S2的距离为Δw4，满足如下关系式：
Figure PCTCN2021094326-appb-000008
从而，当显示面板中具有需要设置成第三导电子层沿导电构件的宽度方向凸出于第二表面的结构的多个导电构件的情况下，可根据第二导电子层的厚度来确定与衬底基板具有不同距离的导电构件中第三导电子层103超出第二表面S2的距离。
需要说明的是，本公开的实施例以距离衬底基板较近的导电构件的厚度小，距离衬底基板较远的导电构件的厚度大为例进行说明。在其他的实施例中，也可以距离衬底基板较近的导电构件的厚度大，而距离衬底基板较远的导电构件的厚度小。
图12为本公开一实施例提供的一种显示面板中的相邻导电构件的剖视图。如图12所示，第一导电构件CL1的第三导电子层103和第二导电构件CL2的第三导电子层103之间的间距spc1小于第一导电构件CL1的第二导电子层102的第二表面S2和第二导电构件CL2的第二导电子层102的第二表面S2之间的间距spc2，以利于减小静电击穿的风险。
例如，如图12所示，第三导电子层103覆盖第二导电子层102，并与第一导电子层101接触。因第三导电子层103的侧面S33覆盖第二导电子层102，降低了第二导电子层102的静电击穿的风险。
例如，为进一步降低静电放电影响，以显著降低风险发生频率，在第二导电子层102的第一表面S1、第二表面S2和侧面S3至少之一中掺入N元素、S元素、P元素和Cl元素至少之一。例如，可以在本公开的实施例提供的图3至图12所示的显示面板中的导电构件CL的第二导电子层102进行上述掺杂。
图13为本公开一实施例提供的一种显示面板的剖视图。如图13所示，显示面板包括衬底基板 100、阻隔层42和导电构件层43，导电构件层43包括导电构件CL，导电构件CL位于无机绝缘膜42上。例如，导电构件CL与阻隔层42接触，但不限于此。例如，导电构件层43包括如上所述的第一导电构件CL1和第二导电构件CL2。
例如，阻隔层42包括无机绝缘膜，具有F元素和Cl元素至少之一。阻隔层42具有F元素和Cl元素至少之一，能有效吸附导电构件中的金属离子，降低静电放电风险。
例如，为了显著降低静电放电发生的频率，阻隔层42中的F元素和Cl元素至少之一的含量在每立方厘米1×10 18至5×10 20个原子。
例如，参考图4、图6A至图8、图11以及图12，第一表面S1与第一导电子层101接触，第二表面S2与第三导电子层103接触。
例如，参考图4、图6A至图8、图11以及图12，第一表面S1的宽度小于第一导电子层101的宽度，第二表面S2的宽度小于第三导电子层103的宽度，为了得到电阻和稳定性兼顾的导电构件，第三导电子层103和第二表面S2的宽度差大于第三导电子层103的厚度。
在本公开的实施例中，对于第三导电子层103是否超出第一表面S1不做限定。例如，第三导电子层103可超出第一表面S1，即，第三导电子层103在衬底基板上的正投影的面积大于第一表面S1在衬底基板上的正投影的面积。当然，在其他的实施例中，第三导电子层103可不超出第一表面S1，即，第三导电子层103在衬底基板上的正投影落入第一表面S1在衬底基板上的正投影内。在一些实施例中，第三导电子层103在衬底基板上的正投影也可与第一表面S1在衬底基板上的正投影重合。
以下对于本公开的实施例提供的图3至图13所示的显示面板中的导电构件的适用情况进行描述，需要说明的是，本公开的实施例提供的显示面板中的导电构件的适用情况不限于下述描述。
图14为本公开一实施例提供的显示面板的平面图。如图14所示，显示面板包括显示区R1和位于显示区R1至少一侧的周边区R2。多个子像素SP位于显示区R1。多条栅线GL和多条数据线DL位于显示区R1。多条栅线GL和多条数据线DL交叉并彼此绝缘。如图14所示，每条数据线DL与位于周边区R2的接垫PD相连。如图14所示，多个接垫PD位于周边区R2，多个接垫PD可被配置为与其他元件或与外部电路例如柔性电路板相连。图14中两个相邻的接垫PD可为如上所述的第一导电构件CL1和第二导电构件CL2。图14还示出了多个像素单元SP。多个像素单元SP可呈阵列排布，但不限于此。图14以多个像素单元SP呈矩阵排布为例进行说明，但不限于此。图14中以每条数据线DL与一个接垫PD相连为例进行说明，在其他的实施例中，还可以多条数据线DL与一个接垫PD相连，例如，两条或更多条的数据线DL与一个接垫PD相连。例如，可通过设置数据选择单元例如mux单元来使得两条或更多条的数据线DL与一个接垫PD相连。
图15A为本公开一实施例提供的显示面板的平面图。如图15A所示，第一导电构件CL1和第二导电构件CL2通过各向异性导电胶ADH分别与外部电路CC的引脚PN相连，各向异性导电胶ADH在第三方向DR3(竖直方向)导电以电连接外部电路CC的第一引脚PN1和第一导电构件CL1以及电连接外部电路CC的第二引脚PN2和第二导电构件CL2。导电构件CL中的第三导电子层103凸出于第二表面S2可利于其与外部电路的绑定。图15A以第二导电子层102具有两个斜面为例进行示意性的说明，但不限于此。图15A中的导电构件CL可采用本公开实施例所述的任一导电构件CL。
图15A示出了各向异性导电胶ADH的导电部分ADH1。各向异性导电胶ADH的除了导电部分ADH1之外的部分为绝缘部分。即，各向异性导电胶ADH的位于两个相邻导电部分ADH1之间的部分为绝缘部分以实现导电元件的竖向相连和横向绝缘。
图15B为本公开另一实施例提供的显示面板的平面图。与图15A所示的显示面板相比，图15A所示的显示面板的导电构件CL与第一堆叠元件ST1和第二堆叠元件ST2堆叠设置，第一堆叠元件ST1和第二堆叠元件ST2分别设置在导电构件CL的两侧，第一堆叠元件ST1比第二堆叠元件ST2更靠近衬底基板。第二堆叠元件ST2通过各向异性导电胶ADH的导电部分与引脚PN相连。图15B以导电构件CL与第一堆叠元件ST1接触，且与第二堆叠元件ST2接触为例进行说明，但不限于此，在其他的实施例中，导电构件CL与第一堆叠元件ST1可以通过贯穿绝缘层的过孔相连，导电构件CL与第二堆叠元件ST2也可以通过贯穿绝缘层的过孔相连。图15A和图15B中省略了衬底基板100于导电构件CL之间的阻隔层。
图16A为本公开一实施例提供的显示面板的平面图。如图16A所示，显示面板具有透光区HL。因衬底基板在透光区HL处被挖空，在靠近透光区HL处，靠近透光区HL的两条相邻的栅线GT之间的距离d21小于远离透光区HL的两条相邻的栅线GT之间的距离d22。图16A靠近透光区HL的并具有顺势弯曲/弯折的部分的栅线GT可为本公开实施例提供的具有第三导电子层沿导电构件的宽度方向凸出于第二表面结构的导电构件CL。如图16A所示，第一导电构件CL1比第二导电构件CL2更靠近透光区HL。为了降低静电击穿的风险，第一导电构件CL1中第三导电子层103超出第二表面S2的距离比第二导电构件CL2中第三导电子层103超出第二表面S2的距离大。当然，导电构件CL也可以为显示面板中的其他信号线。
图16B为本公开另一实施例提供的显示面板的平面图。图16B中的所示的显示面板与图16A中的所示的显示面板相比，透光区HL位于衬底基板的边缘形成缺口。透光区HL可用来放置摄像头等部件以利于实现显示装置的多种功能。透光区HL的形状不限于图16A和图16B所示，可根据需要而定。
图17A为本公开一实施例提供的显示面板的平面图。图17A示出了多条数据线DL和多条第一电源线PL1，数据线DL和第一电源线PL1相邻，数据线DL和第一电源线PL1的在透光区HL附近的部分可分别为如上所述的第一导电构件CL1和第二导电构件CL2。在靠近透光区HL处，靠近透光区HL的相邻的数据线DL和第一电源线PL1之间的距离d21小于远离透光区HL的相邻的数据线DL和第一电源线PL1的之间的距离d22。如图17A所示，在靠近透光区HL处，靠近透光区HL的相邻的数据线DL1和第一电源线PL11之间的距离d21小于远离透光区HL的相邻的数据线DL2和第一电源线PL12的之间的距离d22。
图17B为本公开一实施例提供的显示面板的平面图。与图17A所示的显示面板相比，图17B所的显示面板包括隔离柱SEP。隔离柱SEP的设置利于阻断水氧对发光二极管的发光层的侵袭。隔离柱SEP可采用如上所述的导电构件CL的结构。隔离柱SEP围绕透光区HL设置，隔离柱SEP和与其相邻的第一电源线PL1可分别为如上所述的第一导电构件CL1和第二导电构件CL2。当然，在其他的实施例中，也可以是数据线DL与隔离柱SEP相邻，即，隔离柱SEP和与其相邻的数据线DL可分别 为如上所述的第一导电构件CL1和第二导电构件CL2。例如，数据线DL和第一电源线PL1同层设置。需要说明的是，隔离柱SEP和与其相邻的第一电源线PL1之间不具有数据线，隔离柱SEP和与其相邻的数据线DL之间不具有第一电源线PL1。
图17C为本公开一实施例提供的显示面板的局部平面图。如图17所示，隔离柱SEP包括多个子隔离柱SEP0，靠近信号线SL的子隔离柱SEP0和与其相邻的子隔离柱SEP0之间的距离d32大于相邻子隔离柱SEP0之间的间距d31。信号线SL可为图17B中所示的数据线DL或者第一电源线PL1。相邻子隔离柱SEP0之间具有间隔。相邻子隔离柱SEP0可为如上所述的第一导电构件CL1和第二导电构件CL2。
图18为本公开一实施例提供的含有本公开的实施例提供的显示面板的显示装置的立体图。如图18所示，显示装置为可折叠的显示装置。显示装置可为OLED显示装置。显示装置包括可折叠区R13和分设在可折叠区R13两侧的第一显示区R11和第二显示区R12。图18示出了可折叠线FL。可折叠区R13、第一显示区R11和第二显示区R12构成显示区R1。
图19为图18所示的显示装置的平面图。如图19所示，在第一显示区R11的一侧设置第一周边区R21，第一周边区R21内设有第一接垫区PDR1，多个第一接垫PD1位于第一接垫区PDR1，多个第一接垫PD1包括两个相邻的第一接垫PD1：靠近可折叠线FL的第一接垫PD11和远离可折叠线FL的第一接垫PD12。第一接垫PD11和第一接垫PD12可分别为如上所述的第一导电构件CL1和第二导电构件CL2。为了降低静电击穿的风险，第一导电构件CL1中第三导电子层103超出第二表面S2的距离比第二导电构件CL2中第三导电子层103超出第二表面S2的距离大。即，第一导电构件CL1比第二导电构件CL2更靠近可折叠线FL，第一导电构件CL1中第三导电子层103超出第二表面S2的距离比第二导电构件CL2中第三导电子层103超出第二表面S2的距离大。图19以第一接垫PD11为最靠近可折叠线FL的第一接垫为例进行说明，但不限于此，第一接垫PD11也可以不为最靠近可折叠线FL的第一接垫。
例如，靠近可折叠线FL处的两个相邻导电构件的相邻第二导电子层的距离大于远离可折叠线FL处的两个相邻导电构件的相邻第二导电子层的距离。
如图19所示，在第二显示区R12的一侧设置第二周边区R22，第二周边区R22内设有第二接垫区PDR2，多个第二接垫PD2位于第二接垫区PDR2，多个第二接垫PD2包括两个相邻的第二接垫PD2：靠近可折叠线FL的第二接垫PD21和远离可折叠线FL的第二接垫PD22。第二接垫PD21和第二接垫PD22可分别为如上所述的第一导电构件CL1和第二导电构件CL2。为了降低静电击穿的风险，第一导电构件CL1中第三导电子层103超出第二表面S2的距离比第二导电构件CL2中第三导电子层103超出第二表面S2的距离大。即，越靠近可折叠线FL，导电构件中第三导电子层沿导电构件的宽度方向凸出于第二表面的尺寸越大。
图19中只示出了四个第一接垫PD1和四个第二接垫PD，第一接垫PD1的个数和第二接垫PD的个数均可根据需要而定，不限于图中所示。
图19以相邻的导电构件CL之间的间距各处相等为例进行说明，然而，本公开的实施例并不限于此。在其他的实施例中，相邻的导电构件CL之间的间距也可以逐渐变化。例如，从靠近显示区R1 到远离显示区R1的方向上，相邻的导电构件CL之间的间距逐渐增大。图19以相邻的导电构件CL彼此平行为例，但在其他的实施例中，相邻的导电构件CL也可以不彼此平行。
图20为本公开一实施例提供的含有本公开的实施例提供的显示面板的可折叠显示装置的平面图。如图20所示，可折叠显示装置为OLED显示装置。例如，可折叠显示装置包括可折叠区R13和位于其两侧的第一显示区R11和第二显示区R12，并且可折叠区R13、第一显示区R11和第二显示区R12构成显示区R1，显示区R1外为周边区R2，周边区R2包括位于第一显示区R11至少一侧的第一周边区R21和位于第二显示区R21至少一侧的第二周边区R21。显示区包括多行像素单元。第一显示区R11和第二显示区R12为非折叠区。
图21为图20所示的可折叠显示装置中的部分GOA电路的示意图。
参考图20和图21，第一周边区R21包括多条信号线46和多级GOA单元电路45，每一级的GOA单元电路45通过信号线46电性连接于对应行的像素单元，每一级的GOA单元电路45用于驱动对应行的像素单元。
如图20和图21所示，每一级的GOA单元电路45通过扫描数据线(未示出)与信号线46相连接，信号线46包括GOA信号线、像素单元信号线以及电源信号线。GOA信号线包括供GOA单元电路45正常工作的第一时钟信号线CK1、第二时钟信号线CK2、低电平信号线VGL以及高电平信号线VGH。
例如，如图21所示，第N级GOA单元电路45中的输入信号IN由第N-1级GOA单元电路的输出信号OUT提供，第N级GOA单元电路的输出信号OUT提供第N行像素单元的开关信号以及第N+1级GOA单元电路的输入信号。
例如，第一时钟信号线CK1被配置为提供第一时钟信号，第二时钟信号线CK2被配置为提供第二时钟信号，低电平信号线VGL被配置为提供低电平信号，高电平信号线VGH被配置为提供高电平信号。
例如，本公开的实施例提供的显示面板中的导电构件CL可以为图21所示的第一时钟信号线CK1、第二时钟信号线CK2、低电平信号线VGL以及高电平信号线VGH中任意相邻的两个。即，第一导电构件CL1和第二导电构件CL2可以为图21中所示的第一时钟信号线CK1、第二时钟信号线CK2、低电平信号线VGL以及高电平信号线VGH中任意相邻的两个。在第一导电构件CL1比第二导电构件CL2更靠近可折叠线FL的情况下，为了降低静电击穿的风险，第一导电构件CL1中第三导电子层103超出第二表面S2的距离比第二导电构件CL2中第三导电子层103超出第二表面S2的距离大。图21中以第一导电构件CL1为高电平信号线VGH，并且第二导电构件CL2为低电平信号线VGL为例进行说明。
图21还示出了第一连接线CNL1、第二连接线CNL2、第三连接线CNL3和第四连接线CNL4。高电平信号线VGH、低电平信号线VGL、第一时钟信号线CK1以及第二时钟信号线CK2分别通过第一连接线CNL1、第二连接线CNL2、第三连接线CNL3和第四连接线CNL4与第N级GOA单元电路45相连。图21所示的显示面板以第一连接线CNL1、第二连接线CNL2、第三连接线CNL3和第四连接线CNL4水平设置，而高电平信号线VGH、低电平信号线VGL、第一时钟信号线CK1以及 第二时钟信号线CK2竖直设置为例进行说明。
例如，第一导电构件CL1和第二导电构件CL2可以为图21中所示的第一连接线CNL1、第二连接线CNL2、第三连接线CNL3和第四连接线CNL4中任意相邻的两个。
图22A为图21中的水平设置的连接线的俯视图。图22A所示的导电构件可为图21所示的第一连接线CNL1、第二连接线CNL2、第三连接线CNL3和第四连接线CNL4中的任一个。例如，为了降低静电击穿的风险，导电构件CL的靠近可折叠线FL的部分的第三导电子层103超出第二表面S2的距离d1大于导电构件CL的远离可折叠线FL的部分的第三导电子层103超出第二表面S2的距离d2。即，同一个导电构件的不同位置处的第三导电子层103超出第二表面S2的距离不同。
图22B为图21中的水平设置的两条相邻的连接线的俯视图。如图22B所示，第一导电构件CL1和第二导电构件CL2之间的第二表面S2之间的距离d0从靠近可折叠线FL到远离可折叠线FL的方向逐渐减小。
图23为本公开另一实施例提供的一种含有本公开的实施例提供的显示面板的可折叠显示装置的平面图。图20所示的可折叠显示装置中，信号线46和GOA单元电路45位于显示装置的左侧和右侧，与图20所示的可折叠显示装置相比，图23所示的可折叠显示装置中，信号线46和GOA单元电路45位于显示装置的上侧和下侧。
图24为本公开一实施例提供的一种显示面板的平面示意图。如图24所示，显示面板包括衬底基板100，衬底基板100被划分为两个区域。例如，衬底基板100包括显示区R1和位于显示区R1至少一侧的周边区R2。例如，周边区R2可位于显示区R1的上侧、下侧、左侧和右侧中的至少一个。图24中示出了周边区R2位于显示区R1的上侧、下侧、左侧和右侧，即，周边区R2围绕显示区R1。例如，周边区R2也可仅位于显示区R1的一侧，例如，仅位于显示区R1的上侧、下侧、左侧或右侧。图24中灰色填充处为显示区R1，衬底基板100的其余位置处为周边区R2。例如，在本公开的实施例中，显示区R1为画面显示区域，为出光区。例如，周边区R2为不显示画面的区域，为非出光区。
如图24所示，在周边区R2，设置有裂纹阻挡线51以阻挡边缘裂纹扩展至显示区R1。裂纹阻挡线51包括第一裂纹阻挡线511和第二裂纹阻挡线512。在周边区R2，还设置有被配置为检测裂纹的裂纹检测线52。裂纹检测线52包括第一裂纹检测线521和第二裂纹检测线522。裂纹检测线52比裂纹阻挡线51更靠近显示区R1。若通过裂纹检测线52检测出有裂纹产生，则可避免有边缘裂纹的产品流入客户端。例如，在显示面板母板切割为多个单个显示面板的过程中、运输过程中、或者在显示面板受到机械冲击或者热冲击时，衬底基板100上的层例如无机层的边缘可产生裂纹。
本公开的实施例提供的显示面板中的第一导电构件CL1和第二导电构件CL2可分别为第一裂纹阻挡线511和第二裂纹阻挡线512，或者，本公开的实施例提供的显示面板中的第一导电构件CL1和第二导电构件CL2可分别为第一裂纹检测线521和第二裂纹检测线522。
如图24所示，为了降低静电击穿的风险，靠近显示区R1的第一导电构件CL1中第三导电子层103超出第二表面S2的距离小于远离显示区R1的第二导电构件CL2中第三导电子层103超出第二表面S2的距离。
例如，显示面板具有特征区，提供两个导电构件CL，两个导电构件CL彼此绝缘，两个导电构件 CL包括第一导电构件CL1和第二导电构件CL2，第一导电构件CL1比第二导电构件CL2更靠近特征区，第一导电构件CL1中第三导电子层103凸出第二表面S2的尺寸大于第二导电构件CL2中第三导电子层103凸出第二表面S2的尺寸。例如，特征区包括透光区、可折叠区和显示区至少之一。
下面结合图25至图28以第一导电构件CL1和第二导电构件CL2分别为第一电源线(电源电压线)ELVDD和数据线为例进行说明。
图25和图28采用的晶体管均可以为三极管、薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
例如，当晶体管为三极管时，控制极可以为基极，第一极可以为集电极，第二极可以发射极；或者，控制极可以为基极，第一极可以为发射极，第二极可以集电极。
例如，当晶体管为薄膜晶体管或场效应管时，控制极可以为栅极，第一极可以为漏极，第二极可以为源极；或者，控制极可以为栅极，第一极可以为源极，第二极可以为漏极。
图28所示的显示面板，包括位于衬底基板上的阵列层以及位于阵列层远离衬底基板一侧的遮光层，遮光层上形成有多个成像小孔，成像小孔在衬底基板上的第一正投影与阵列层中的开关晶体管的有源层图形在衬底基板上的第二正投影不重叠。开关晶体管为与阵列层中的驱动晶体管的栅极连接的晶体管。
本公开实施例的显示面板通过将在遮光层上形成的成像小孔设置为不对应于阵列层中的开关晶体管的有源层图形，以使得穿过成像小孔的光线不会对开关晶体管的有源层图形造成影响，从而不会由于光线的照射造成该开关晶体管在截止状态下也有光生漏电流存在，进而不会影响驱动晶体管的栅极的电位，避免显示灰阶不准确的问题。
例如，第一正投影与第二正投影不重叠指的是：第一正投影和第二正投影之间不存在交叠的部分，但不限于此。
例如，阵列层可以为薄膜晶体管阵列层，但不限于此。
例如，薄膜晶体管阵列层可以包括阵列层和第二源漏金属层，该第二源漏金属层复用为遮光层，但不限于此。
例如，阵列层中的控制晶体管的有源层图形中的沟道区在衬底基板上的正投影为第三正投影，驱动晶体管的有源层图形中的沟道区在衬底基板上的正投影为第四正投影。
开关晶体管的有源层图形中的沟道区在衬底基板上的正投影为第五正投影。
例如，第一正投影的边缘与第五正投影之间的最短距离大于第一正投影的边缘与第三正投影之间的距离。
例如，第一正投影的边缘与第五正投影之间的最短距离大于第一正投影的边缘与第四正投影之间的距离。
例如，控制晶体管为阵列层中的除了开关晶体管和驱动晶体管之外的晶体管。
例如，第一正投影的边缘与第五正投影之间的最短距离大于第一正投影的边缘与第三正投影之间的距离，第一正投影的边缘与第五正投影之间的最短距离大于第一正投影的边缘与第四正投影之间的距离，成像小孔距离开关晶体管的有源层图形的沟道区较远，防止开关晶体管的有源层图形的沟道区 被穿过成像小孔的光线照射。
例如，显示面板可以包括设置有成像小孔的第一像素区域和未设置有成像小孔的第二像素区域。例如，第一像素区域的面积大于第二像素区域的面积。
例如，第一像素区域内的开关晶体管的宽长比可以小于第二像素区域内的开关晶体管的宽长比，以降低光生漏电流的电流值，进而提升显示灰阶准确性，但不限于此。
例如，第一正投影与阵列层包括的金属图形在衬底基板上的正投影不重叠。
进一步的，成像小孔需要不被金属图形遮挡，以提升小孔成像指纹识别精度。
例如，成像小孔的直径可以大于或等于2μm而小于或等于20μm，但不限于此。
例如，成像小孔的直径可以大于或等于4μm而小于或等于7μm，但不限于此。
例如，成像小孔的密度可以根据实际情况灵活调节，可以在N个像素区域内设置一个成像小孔，N为正整数。
例如，N可以大于或等于3而小于或等于10，但不限于此。
例如，阵列层可以包括依次设置于衬底基板与遮光层之间的有源层、栅绝缘层、第一栅金属层、第一绝缘层、第二栅金属层、层间介质层、第一源漏金属层和第二绝缘层；显示面板还包括依次设置于遮光层远离第二绝缘层的一侧的平坦层和阳极层。
例如，遮光层包括遮光图形以及连接图形；遮光图形具有成像小孔。
例如，第一源漏金属层通过贯穿第二绝缘层的第一过孔、连接图形以及贯穿平坦层的第二过孔与阳极层电连接；连接图形和遮光图形之间存在漏光缝隙。
漏光缝隙在衬底基板上的正投影被薄膜晶体管阵列层包括的金属电极在衬底基板上的正投影覆盖。
例如，遮光图形与连接图形相互分立，遮光图形与连接图形相互绝缘。
例如，显示面板可以由下至上依次设置的衬底基板、阵列层、遮光层、平坦层和阳极层。
例如，阵列层可以包括由下至上设置的有源层、栅绝缘层、第一栅金属层、第一绝缘层、第二栅金属层、层间介质层、第一源漏金属层和第二绝缘层。
例如，阳极层需要与第一源漏金属层电连接，因此通过在遮光层中设置与遮光图形分立的连接图形，以使得第一源漏金属层通过贯穿第二绝缘层的第一过孔、连接图形以及贯穿平坦层的第二过孔与阳极层电连接。
由于遮光图形和连接图形之间绝缘，因此遮光图形和连接图形之间存在漏光缝隙，漏光缝隙可能会漏光，因此将漏光缝隙在衬底基板上的正投影设置为被阵列层包括的金属电极在衬底基板上的正投影覆盖，以防止通过漏光缝隙露出的光对小孔成像指纹识别造成影响。
金属电极例如可以为存储电容的上极板，但不限于此。
图25是本公开一实施例提供的显示面板的像素中的像素驱动电路的电路图。
如图25所示，像素驱动电路可以包括驱动晶体管T1、第一开关晶体管T3、第二开关晶体管T6、第一控制晶体管T2、第二控制晶体管T4、第三控制晶体管T5、第四控制晶体管T7和存储电容Cst。
第一开关晶体管T3的源极T3s与驱动晶体管T1的栅极T1g电连接，第一开关晶体管T3的漏极 T3d与驱动晶体管T1的漏极T1d电连接。
第一开关晶体管T3的栅极T3g与第n行栅线G(n)电连接。
第二开关晶体管T6的栅极T6g与第n行复位线Reset(n)电连接，第二开关晶体管T6的漏极T6d与驱动晶体管T1的栅极T1g电连接，第二开关晶体管T6的源极T6s与初始电压线Vint电连接。
第一控制晶体管T2的栅极T2g与第n行栅线G(n)电连接，第一控制晶体管T2的源极T2s与第m列数据线D(m)电连接，第一控制晶体管T2的漏极T2d与驱动晶体管T1的源极T1s电连接。
第二控制晶体管T4的栅极T4g与第n行发光控制线EM(n)电连接，第二控制晶体管T4的源极T4s与第一电源线ELVDD电连接，第二控制晶体管T4的漏极T4d与驱动晶体管T1的源极T1s电连接。
第三控制晶体管T5的栅极T5g与第n行发光控制线EM(n)电连接，第三控制晶体管T5的源极T5s与驱动晶体管T1的漏极T1d电连接，第三控制晶体管T5的漏极T5d与有机发光二极管OLED的阳极电连接；有机发光二极管OLED的阴极与第二电源线ELVSS电连接。
第四控制晶体管T7的栅极T7g与第n+1行复位线Reset(n+1)电连接，第四控制晶体管T7的漏极T7d与有机发光二极管OLED的阳极电连接，第四控制晶体管T7的源极T7s与初始电压线Vint电连接。
存储电容Cst的第一极板Csa与第一电源线ELVDD电连接，驱动晶体管T1的栅极T1g可以复用为存储电容Cst的第二极板Csb。
例如，n为正整数，m为正整数。
图25所示的像素驱动电路可以为第n行第m列像素区域中的像素驱动电路，但不限于此。
在图25所示的像素驱动电路中，所有晶体管都为p型薄膜晶体管，但不限于此。
在图25中，第一节点N1为与驱动晶体管T1的栅极电连接的节点。
图25所示的像素驱动电路仅是像素中的像素驱动电路的一个实施例，并不对像素驱动电路的结构进行限定。
例如，第二开关晶体管T6可以为双栅晶体管，以能够减小其漏电流，能够很好的保持驱动晶体管T1的栅极的电位，但不限于此。
图26是图25所示的像素驱动电路的工作时序图。t1是第一阶段，t2为第二阶段，t3为第三阶段，标号为Vdata的为数据线D(n)提供的数据电压。
如图26所示，图26所示的像素驱动电路在工作时的描述如下。
在第一阶段t1(也即复位阶段)，Reset(n)输入低电平，G(n)输入高电平，EM(n)输入高电平，第二开关晶体管T6打开，驱动晶体管T1的栅极的电位被复位为初始电压。
在第二阶段t2(也即数据写入和阈值电压补偿阶段)，Reset(n)输入高电平，G(n)输入低电平，Data(m)输入数据电压Vdata，EM(n)输入高电平，第二开关晶体管T6截止，第二控制晶体管T4和第三控制晶体管T5截止，第一控制晶体管T2、第一开关晶体管T3、驱动晶体管T1和第四控制晶体管T7开启，Vdata通过第一控制晶体管T2、驱动晶体管T1、第一开关晶体管T3为Cst充电，以提升驱动晶体管T1的栅极的电位，直至驱动晶体管T1的栅极的电位变为Vdata+Vth(Vth为 驱动晶体管T1的阈值电压)时，第一开关晶体管T3关闭，N1的电位被Cst存储，同时第四控制晶体管T7打开，以将OLED的阳极的电位复位为初始电压。
在第三阶段t3(也即发光阶段)，Reset(n)输入高电平，G(n)输入高电平，EM(n)输入低电平，驱动晶体管T1、第一控制晶体管T2、第一开关晶体管T3、第二开关晶体管T6和第四控制晶体管T7截止，第二控制晶体管T4和第三控制晶体管T5导通，OLED发光，驱动晶体管T1驱动OLED发光的驱动电流I等于(1/2)K(Vdata-Vdd) 2；其中，K为电流系数，Vdd为ELVDD输入的电源电压的电源值。
在图25所示的像素驱动电路中，第一开关晶体管T3的源极T3s与驱动晶体管T1的栅极T1g电连接，第二开关晶体管T6的漏极T6d与驱动晶体管T1的栅极T1g电连接，如果有光线照射到第一开关晶体管T3和第二开关晶体管T6，可能会造成第一开关晶体管T3和第二开关晶体管T6在截止状态下也会有光生漏电流存在，进而影响驱动晶体管T1的栅极T1g的电位，造成显示灰阶不准确。本公开实施例提供的一种集成小孔成像功能的显示面板，对成像小孔的设置位置和方式进行了调整，在保证小孔成像指纹识别的精度的同时，降低了成像小孔对显示品质及显示精度的影响。
例如，显示面板可以单独设置特定的指纹识别区域，也可以全屏均为指纹识别区域。
在本公开实施例中，显示面板可以包括从下至上设置的衬底基板、缓冲层、阵列层、第二源漏金属层、平坦层、阳极层、像素界定层、发光层和阴极层。阵列层包括从下至上依次设置的有源层、栅绝缘层、第一栅金属层、第一绝缘层、第二栅金属层、层间介质层、第一源漏金属层和第二绝缘层。
第一栅金属层用来形成栅线、发光控制线和像素驱动电路中的各晶体管的栅极等结构。
第二栅金属层用来形成存储电容的极板和初始电压线。
第一源漏金属层用来形成数据线、第一电源线、像素驱动电路中的各晶体管的源极和像素驱动电路中的各晶体管的漏极等结构。
第二源漏金属层复用为遮光层，遮光层上形成有成像小孔。
例如，由于阳极层需要与第一源漏金属层电连接，以完成电路结构，因此需要通过将第二源漏金属层(也即遮光层)设置为还包括连接图形，第一源漏金属层通过贯穿第二绝缘层的第一过孔、连接图形以及贯穿平坦层的第二过孔与阳极层电连接。
例如，有源层图形可以包括沟道区、源极区和漏极区。沟道区可以不掺杂有杂质，因此具有半导体特性。源极区设置于沟道区的第一侧，漏极区设置于沟道区的第二侧上，第一侧和第二侧为相对的两侧，并且掺杂有杂质，并因此具有导电性。杂质可以根据晶体管是n型晶体管还是p型晶体管而变化。
例如，掺杂源极区可以对应于晶体管的源电极，掺杂漏极区可以对应于晶体管的漏电极。
图27是本公开一实施例提供的显示面板中的第二源漏金属层的示意图。在图27中，标号为L0的为第二源漏金属层包括的连接图形；标号为SE的为第二源漏金属层包括的遮光图形，标号为H0的为成像小孔，标号为F1的为漏光缝隙；第一源漏金属层包括的连接图形L1用于第三控制晶体管T5的漏极与第二源漏金属层包括的连接图形L0之间的电连接；第二源漏金属层包括的连接图形L0用于第二源漏金属层包括的连接图形L1与阳极层之间的电连接。
图28是本公开一实施例提供的显示面板的布局图。在图28中，标号为Data(m)的是第m列数据线，标号为Data(m+1)的为第m+1列数据线，标号为ELVDD的为第一电源线，标号为Vint的为初始电压线，标号为Reset(n)的为第n行复位线，标号为Reset(n+1)的为第n+1行复位线，标号为EM(n)的为第n行发光控制线，标号为EM(n+1)的为第n+1行发光控制线，标号为G(n)的为第n行栅线，标号为G(n+1)的为第n+1行栅线。
在图28中，标号为16g的为第二开关晶体管T6的有源层图形的沟道区，标号为16s的为第二开关晶体管T6的有源层图形的源极区，标号为16d的为第二开关晶体管T6的有源层图形的漏极区，标号为13g的为第一开关晶体管T3的有源层图形的沟道区，标号为11g的为驱动晶体管T1的有源层图形的沟道区，标号为11d的为驱动晶体管T1的有源层图形的漏极区，标号为11s的为驱动晶体管T1的有源层图形的源极区；标号为12g的为第一控制晶体管T2的有源层图形的沟道区，标号为12s的为第一控制晶体管T2的有源层图形的源极区，标号为14g的为第二控制晶体管T4的有源层图形的沟道区，标号为14s的为第二控制晶体管T4的有源层图形的源极区，标号为15g的为第三控制晶体管T5的有源层图形的沟道区，标号为15d的为第三控制晶体管T5的有源层图形的漏极区，标号为17g的为第四控制晶体管T7的有源层图形的沟道区，标号为17s的为第四控制晶体管T7的有源层图形的源极区，标号为Csa的为存储电容Cst的第一极板，标号为16g’的为第n+1行第m列像素区域中的第二开关晶体管的有源层图形的沟道区，标号为16d’的为第n+1行第m列像素区域中的第二开关晶体管的有源层图形的漏极区。
在图28中，标号为H0的为成像小孔，H0在衬底基板上的正投影不与第一开关晶体管T3的有源层图形在衬底基板上的正投影重叠，H0在衬底基板上的正投影不与第二开关晶体管T6的有源层图形在衬底基板上的正投影重叠，H0在衬底基板上的正投影不与第n+1行第m列像素区域中的第二开关晶体管的有源层图形重叠，以使得第一开关晶体管T3的有源层图形、第二开关晶体管T6的有源层图形和第n+1行第m列像素区域中的第二开关晶体管的有源层图形不被透过成像小孔H0的光线照射到，避免由于光线的照射造成各开关晶体管在截止状态下也有光生漏电流存在，进而不会影响驱动晶体管T1的栅极的电位，避免显示灰阶不准确的问题。
在图28中，H0在衬底基板上的正投影的边缘与16g’之间的距离d1大于H0在衬底基板上的正投影的边缘与15g之间的距离d2。
在图28中，H0在衬底基板上的正投影的边缘距离第一开关晶体管T3的有源层的最短距离大于H0在衬底基板上的正投影的边缘距离除了第一开关晶体管T3和第二开关晶体管T6之外的任一晶体管的有源层之间的距离，H0在衬底基板上的正投影的边缘距离第二开关晶体管T6的有源层的最短距离大于H0在衬底基板上的正投影的边缘距离除了第一开关晶体管T3和第二开关晶体管T6之外的任一晶体管的有源层之间的距离。
并在图28所示的显示面板中，11d与第三控制晶体管T5的有源层图形中的源极区连通，15d与第四控制晶体管T7的有源层图形中的漏极区连通，16d与第一开关晶体管T3的有源层图形的源极区连通，11s与第二控制晶体管T4的有源层图形的漏极区连通，11d与第三控制晶体管T5的有源层图形的漏极区连通，11s与第一控制晶体管T2的有源层图形的漏极区连通。
例如，标号为T6g’的为第n+1行第m列像素区域中的第二开关晶体管的栅极。
在图25和图28中，标号为T1g的为驱动晶体管T1的栅极，标号为T2g的为第一控制晶体管T2的栅极，标号为T3g的为第一开关晶体管T3的栅极，标号为T4g的为第二控制晶体管T4的栅极，标号为T5g的为第三控制晶体管T5的栅极，标号为T6g的为第二开关晶体管T6的栅极，标号为T7g的为第四控制晶体管T7的栅极。
在图25和图28中，方框框起来的叉号标示的是过孔。
在图28中，除了数据线和第一电源线之外的纵向的竖线为连接线。
图28所示的本公开实施例提供的显示面板对成像小孔设计位置进行了设计，在保持小孔成像识别精度的同时，降低了小孔成像系统对显示品质，尤其是显示精度的影响，提升了显示品质。
如图28所示，标号为An1的为阳极层包括的第一阳极，标号为An2的为阳极层包括的第二阳极，标号为An3的为阳极层包括的第三阳极，标号为An4的为阳极层包括的第四阳极。
阳极层包括的第一阳极An1通过第二源漏金属层包括的连接图形L0和第一源漏金属层包括的连接图形L1与第三控制晶体管T5的漏极电连接。
图28示出了第m+2列数据线Data(m+2)、第m+3列数据线Data(m+3)和两列第一电源线，还示出了阳极层包括的第五阳极An5、阳极层包括的第六阳极An6和阳极层包括的第七阳极An7。
在图28中，An1可以为蓝色有机发光二极管的阳极，An5可以为红色有机发光二极管的阳极，An7可以为绿色有机发光二极管的阳极，但不限于此。
在图28中，由Reset(n)、Reset(n+1)、D(m)和D(m+1)围成的像素区域内设置有成像小孔H0，但不限于此。
例如，成像小孔H0与连接图形L0之间需要间隔一定距离，并且连接图形L0与遮光图形SE之间的漏光缝隙F1在衬底基板上的正投影需要被阵列层包括的金属电极(例如存储电容的极板)在衬底基板上的正投影覆盖，然而，由于制作精度的限制，漏光缝隙F1的宽度无法做到无限窄，成像小孔H0的半径、连接图形L0的尺寸和成像小孔H0与连接图形L0之间的距离也受到制作精度的限制也不能做到无限小，因此可以将设置有成像小孔的像素区域的各图形的面积相比于未设置有成像小孔的像素区域的各图形的面积适当的放大，以确保连接图形L0与遮光图形SE之间的漏光缝隙F1在衬底基板上的正投影需要被阵列层包括的金属电极(例如存储电容的极板)在衬底基板上的正投影覆盖。
图28所示的本公开实施例提供的显示面板的制作方法可以包括：在衬底基板上形成阵列层；在阵列层远离衬底基板的一侧形成遮光层；以及在遮光层上形成多个成像小孔；成像小孔在衬底基板上的第一正投影与阵列层中的开关晶体管的有源层图形在衬底基板上的第二正投影不重叠；开关晶体管为与阵列层中的驱动晶体管的栅极连接的晶体管。
本公开的另一实施例提供的显示面板中，也可以不设置遮光层以及遮光层中的成像小孔。本公开的实施例提供的显示面板的结构不限于图28所示。
图29是本公开另一实施例提供的一种显示面板的布局图。与图28所示的显示面板相比，图29所示的显示面板不具有成像小孔。第一阳极An1通过第二源漏金属层包括的连接图形L01和第一源漏金属层包括的连接图形L11与第三控制晶体管T5的漏极电连接。或者，也可以不设置第二源漏金 属层，第一阳极An1通过第一源漏金属层包括的连接图形L11与第三控制晶体管T5的漏极电连接。当然，也可以采用其他适合的设置方式。
图30为本公开一实施例提供的显示面板的剖视图。如图30所示，显示面板包括第一衬底基板BS1、第一阻挡层BR1以及第二衬底基板BS2。在第二衬底基板BS2上设置第一晶体管01和第二晶体管02。第一晶体管01与阳极AN相连。
如图30所示，第一晶体管01包括有源层ACT1、第一栅极绝缘层GI1、第一栅极GT1、第一源极SE1和第一漏极DE1。第一源极SE1包括两层：源极SE11和源极SE12。第一漏极DE1包括两层：漏极DE11和漏极DE12。
如图30所示，第二晶体管02包括有源层ACT2、第二栅极绝缘层GI2、第二栅极GT2、第二源极SE2和第二漏极DE2。第二源极SE2包括两层：源极SE21和源极SE22。第二漏极DE2包括两层：漏极DE21和漏极DE22。
如图30所示，显示面板还包括第一层间介电层ILD1、第二缓冲层BF2、第二层间介电层ILD2、钝化层PVX、第一平坦层PLN1、第二平坦层PLN2、像素定义层PDL和支撑层PS。像素定义层PDL和支撑层PS可由同一膜层采用同一构图工艺形成，但不限于此。
例如，参考图30和图29，图30中的漏极DE11和漏极DE12可分别为图29中的连接图形L11和连接图形L01。
例如，第一有源层ACT1为多晶硅半导体层，第二有源层ACT2为氧化物半导体层，多晶硅半导体层更靠近衬底基板。例如，衬底基板采用柔性衬底，第一衬底基板BS1和第二衬底基板BS2均为柔性衬底基板，例如，可采用聚酰亚胺，但不限于此。例如，第一阻挡层BR1的材料可以采用SiOx或SiNx或其叠层，厚度在400nm-800nm之间。例如，衬底基板还可以采用其他柔性塑料衬底。例如，衬底基板还可以采用玻璃、或者石英材料的衬底基板。
例如，第二衬底基板BS2和第一晶体管01之间还设置有第二阻挡层BR2和第一缓冲层BF1。第二阻挡层BR2可采用氧化硅，但不限于此。第一缓冲层BF1可包括缓冲层BF11和缓冲层BF12。缓冲层BF11可采用SiNx，缓冲层BF12可采用SiOx。第一缓冲层BF1的厚度为600-1000nm。缓冲层BF11的厚度在400-600nm之间。第一缓冲层BF1也可以采用单层而非叠层的形式。缓冲层BF11(SiNx)的作用是防止衬底基板中杂质粒子进入半导体区影响晶体管的特性。缓冲层BF11、缓冲层BF12、第一阻挡层BR1、第二阻挡层BR2中至少之一可为之前描述的阻隔层。
例如，第一有源层ACT1的厚度为30-70nm，可采用多晶硅半导体层，多晶硅半导体层可以用来作为驱动晶体管的沟道，例如，在多晶硅形成之前还可以形成光遮挡层，在光遮挡层上形成SiOx后形成多晶硅。
例如，第一栅极绝缘层GI，可采用SiOx，厚度可为80-180nm。
例如，第一栅极GT1可采用Mo、Ti、Cu或其合金，厚度为15-350nm。
例如，在形成第一栅极的同时在对于氧化物半导体区域同层形成导电图形，该导电图形可以作为后续氧化物的遮挡层，防止光线照射氧化物半导体层引起特性劣化。
例如，第一层间绝缘层ILD1可采用SiOx、SiNx和SiOx的三叠层结构，例如，第一层间绝缘层 ILD1的厚度为100-350nm，靠近氧化物半导体层的为SiOx，厚度大于SiNx以保证氧化物特性。
例如，第二缓冲层BF2可采用SiOx。
例如，第二有源层ACT2的厚度为30-60nm，可采用IGZO，但不限于此。
例如，第二栅极绝缘层GI2可采用SiOx，厚度可为100-300nm。
例如，第二栅极GT2可采用Mo、Ti、Cu或其合金，厚度可为15-350nm。
例如，第一层间介电层ILD1和第二层间介电层ILD2可采用SiOx、SiNx至少之一。例如，第一层间介电层ILD1可采用SiNx/SiOx的双层叠层形式，第二层间介电层ILD2可采用SiOx。
例如，第一栅极绝缘层GI1和第二栅极绝缘层GI2可采用SiOx、SiNx至少之一。
例如，钝化层PVX可采用SiOX，厚度可为200-500nm。
例如，第一平坦层PLN1、第二平坦层PLN2、像素定义层PDL和支撑层PS均可采用聚酰亚胺，但不限于此。
如图30所示，源极SE21和源极SE22的设置可对第二有源层ACT2形成保护，从而提高第二晶体管02的稳定性。
在图30所示的结构上形成有机功能层和阴极，再进行封装，即可形成OLED显示装置。也可以在封装层上形成触摸结构，触摸结构可采用金属网格(metal mesh)，但不限于此。
图30还示出了导电构件03和导电构件04。导电构件03和导电构件04可分别为本公开的实施例提供的导电构件CL。如图30所示，导电构件03、源极SE21、漏极DE22、源极SE11以及漏极DE12由同一膜层采用同一构图工艺形成。如图30所示，导电构件04、源极SE12以及漏极DE12由同一膜层采用同一构图工艺形成。例如，源极和漏极均采用金属或合金材料形成。
图31为本公开另一实施例提供的显示面板的剖视图。图31所示的显示面板与图30所示的显示面板相比，没有设置源极SE21和源极SE22。
本公开的实施例提供的显示面板中的第一导电构件CL1和第二导电构件CL2可位于静电高发区，例如接垫区，静电发生少的区域如像素区，为保证电阻降低，不进行第三导电子层凸出于第二表面的设置，即，设置通常的导电构件。例如，具有第三导电子层凸出于第二表面的导电构件与通常导电构件具有边界，该边界位于显示区外，以避免静电影响像素区。接垫区包括外接外部电路的接垫区、阵列测试的接垫区和绑定触摸电路的接垫区至少之一，但不限于此。
需要说明的是，虽然图示中的第一导电子层101、第二导电子层102，第三导电子层103形成完全平行于衬底基板100的平面结构，但不限于此。按照导电构件下方的膜层形状的特点，其可以自然形成在具有凹凸不平的表面上进而其也具有不完全平整的平面，在这样的实例中，上述角度也可被理解为顺应导电子层的表面形成的相应角度，但不限于此。
图32为本公开的实施例提供的一种显示面板的局部平面图。图33为图32中数据选择器的放大示意图。以下参考图32和图33对显示面板进行描述。
例如，如图32所示，导电构件CL和第一导电部61电连接，图32所示的显示面板以第一导电部61为数据线DL，导电构件CL为接垫PD为例进行说明。数据线DL为每个像素单元SP提供数据电压。接垫PD用于与外接电路相连。外接电路包括集成电路(IC)，但不限于此。导电构件 CL和第一导电部61由同一膜层采用同一构图工艺形成。例如，导电构件CL和第一导电部61位于第一源漏金属层LY3。
例如，相邻导电构件之间的绝缘层包括第一有机材料(如环氧树脂)，相邻第一导电部之间的绝缘层为不同于第一有机材料的第二有机材料(如聚酰亚胺)或无机材料(如SiOX或氧化硅或其叠层)。例如，第一有机材料的介电常数小于第二有机材料或无机材料。
例如，如图32和图33所示，显示面板还包括第二导电部62，第二导电部62与导电构件CL设置在不同层。例如，第二导电部62与导电构件CL位于同一层，但不限于此。
例如，如图32和图33所示，提供多个第一导电部61和多个第二导电部62，相邻导电构件CL之间具有第一间隔IN1，相邻第一导电部61之间具有第二间隔IN2，第一间隔IN1与第二间隔IN2不同。例如，第一间隔IN1小于第二间隔IN2。
例如，如图33所示，导电构件CL的长度小于第一导电部61的长度。本公开的实施例中，一个元件的长度是指沿着该元件的延伸方向上的尺寸。
如图32所示，导电构件CL与展开线FL相连，展开线FL与数据线DL相连。展开线FL与数据线DL通过贯穿绝缘层的过孔相连。展开线FL包括展开线FL1和展开线FL2，例如，展开线FL1和展开线FL2之一位于第一栅金属层LY1，展开线FL1和展开线FL2之另一位于第二栅金属层LY2。
图32还示出了第一电源线PL1和第二电源线PL2，多个第二电源线PL2连接至总线311，第一电源线PL1和第二电源线PL2也位于第一源漏金属层LY2。
图32还示出了多条栅线GL和多个像素单元SP。栅线GL沿第一方向DR1延伸，数据线DL沿着第二方向DR2延伸，多条栅线GL与多条数据线DL彼此绝缘，多条栅线GL与多条数据线DL相互交叉以限定多个像素单元SP。第一电源线PL1被配置为向像素单元SP提供第一电源电压，第二电源线PL2被配置为向像素单元SP提供第二电源电压。例如，第一电源线PL1为VDD线，第二电源线PL2为VSS线。例如，第二电源线PL2与发光二极管的阴极相连。
如图32所示，每个接垫PD通过数据选择器MUX分别与两条展开线FL1相连，进而分别与两条数据线DL电连接。例如，数据信号到达数据选择器MUX后，通过在不同时段分别控制第一信号线L1和第二信号线L2打开，使数据信号分别传输到与该数据选择器MUX相连的两条数据线DL上。数据选择器MUX的设置方式可参照通常设计。数据选择器MUX不限于连接两条数据线DL，数据选择器MUX连接的数据线DL的数量可根据需要而定。
参考图32和图33，每个数据选择器MUX包括有源层ACTL，有源层ACTL的被第一信号线L1和第二信号线L2覆盖的部分为沟道区，有源层ACTL的未被第一信号线L1和第二信号线L2覆盖的部分为导体。有源层ACTL的第一端与一条数据线DL相连，有源层ACTL的第二端与另一条数据线DL相连，有源层ACTL的第三端通过第二导电部62与接垫PD相连。有源层ACTL的第一端、第二端和第三端均位于有源层ACTL的导体部分，并可通过转接头(可位于第一源漏金属层)与有源层ACTL相连。
第一导电部61不限于数据线。例如，每个像素单元包括设置在阻隔层上的像素电路层、与像素电路层电连接的有机电致发光器件，以及设置在有机电致发光器件出光侧的触控电极，第一导电部61 为像素电路层，有机电致发光元件或触控电极中的任意一种。
图34A为本公开一实施例提供的显示面板的局部剖视图。图34A为图32中虚线圈B1处的局部剖视图。如图34A所示，衬底基板100上设有阻隔层BR和绝缘层ISL1，第二导电部62位于绝缘层ISL1上。导电构件CL具有第一端部E1，第二导电部62具有第二端部E2，第一端部E1和第二端部E2之间设有绝缘层ISL2，绝缘层ISL2具有暴露第二端部E2的第一过孔V1，导电构件CL通过第一过孔V1与第二导电部62相连。当导电构件CL位于第二导电部62的下方时，绝缘层ISL2具有暴露第一端部E1的第一过孔。在另一些实施例中，第二导电部62可位于阻隔层BR和绝缘层ISL1之间，从而，第一过孔V1贯穿绝缘层ISL1和绝缘层ISL2。
图34B为本公开一实施例提供的显示面板的局部剖视图。图34B为图32中虚线圈B2处的局部剖视图。如图32和图34B所示，显示面板还包括第三导电部63，导电构件CL电连接至第三导电部63，第三导电部63具有第三端部E3，第一导电部61具有第四端部E4，第三端部E3和第四端部E4之间设有绝缘层ISL2，绝缘层ISL2具有暴露第三端部E3的第二过孔V2，第一导电部61通过第二过孔V2与第三导电部63电连接。当导电构件CL位于第三导电部63的下方时，绝缘层ISL2具有暴露第四端部的第二过孔V2。在另一些实施例中，第三导电部63可位于阻隔层BR和绝缘层ISL1之间，从而，第一过孔V1贯穿绝缘层ISL1和绝缘层ISL2。
图35为本公开一实施例提供的显示面板的局部俯视图。例如，如图35所示，导电构件CL包括第一部分PT1和第二部分PT2，第一部分PT1的宽度大于第二部分PT2的宽度，第一部分PT1的第三导电子层103沿导电构件CL的宽度方向凸出于第二表面S2，第二部分PT2的第三导电子层103沿导电构件CL的宽度方向与第二表面S2平齐。当然，在其他的实施例中，也可以第一部分PT1和第二部分PT2的第三导电子层103均沿导电构件CL的宽度方向凸出于第二表面S2，第一部分PT1的第三导电子层103沿导电构件CL的宽度方向凸出于第二表面S2的宽度大于第二部分PT2的第三导电子层103沿导电构件CL的宽度方向凸出于第二表面S2的宽度。
例如，在本公开的实施例中，具有第三导电子层沿导电构件的宽度方向凸出于第二导电子层第二表面的结构的导电构件不被平坦层覆盖。例如，图32中示出的与导电构件CL同层设置的第一导电部61被平坦层覆盖，而导电构件CL不被平坦层覆盖。
本公开的至少一实施例提供一种显示装置，包括上述任一显示面板。
例如，显示装置可以为液晶显示器、电子纸、有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
例如，在本公开的实施例中，导电构件可以是导电结构的一部分或者全部，导电构件可以是连续金属结构形成的图形或者多个金属导电图形的堆叠结构。
需要说明的是，为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在本公开的实施例中，各个元件的形状只是示意性的描述，不限于图中所示，可根据需要而 定。
在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (53)

  1. 一种显示面板，包括：
    显示区，具有多个像素单元；
    周边区，位于所述显示区的至少一侧；
    阻隔层，位于衬底基板上；
    导电构件，设置在所述阻隔层的背离所述衬底基板的一侧，所述导电构件在其延伸方向上的长度大于所述导电构件在与延伸方向相交的方向上的宽度，且所述导电构件包括依次层叠的第一导电子层、第二导电子层和第三导电子层，所述第一导电子层比所述第三导电子层更靠近所述衬底基板；以及
    第一导电部，位于所述显示区，所述第一导电部与所述导电构件同层设置且材料相同，
    其中，所述第一导电子层的电导率小于所述第二导电子层的电导率且所述第一导电子层的厚度小于所述第二导电子层的厚度，所述第三导电子层的熔点大于所述第二导电子层的熔点，
    所述第二导电子层包括靠近所述第一导电子层的第一表面和靠近所述第三导电子层的第二表面，所述第一表面和所述第二表面相对设置，所述第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述宽度方向与所述导电构件的延伸方向相交。
  2. 根据权利要求1所述的显示面板，其中，所述第三导电子层不与所述第一导电子层接触。
  3. 根据权利要求1或2所述的显示面板，其中，所述第二导电子层还包括连接所述第一表面和所述第二表面的位于所述第二导电子层的同一侧的侧边的侧面，在垂直于所述导电构件的延伸方向截取的截面中，所述侧面与所述第一导电子层的交点为第一交点，所述侧面与所述第三导电子层的交点为第二交点，所述侧面的至少一部分位于所述第一交点和所述第二交点的连线的靠近所述第二导电子层的一侧。
  4. 根据权利要求3所述的显示面板，其中，所述侧面包括至少两个子侧面，所述至少两个子侧面包括靠近所述第一导电子层的第一子侧面和靠近所述第三导电子层的第二子侧面，所述第一子侧面与所述第一导电子层所成的角度小于所述第二子侧面与所述第一导电子层所成的角度。
  5. 根据权利要求4所述的显示面板，其中，在垂直于所述导电构件的延伸方向截取的所述截面中，所述第二子侧面的延长线与所述第一导电子层的交点与所述第一子侧面与所述第一导电子层的交点之间的距离为d1，所述第一导电子层超出所述第一表面的距离为Δw1，d1<Δw1。
  6. 根据权利要求5所述的显示面板，其中，所述第三导电子层超出所述第二表面的距离为Δw2，d1<Δw2。
  7. 根据权利要求4-6任一项所述的显示面板，其中，所述第二子侧面与所述第一导电子层所成的角度大于90度。
  8. 根据权利要求3所述的显示面板，其中，所述侧面包括依次设置的三个子侧面，所述三个子侧面包括第一子侧面、第二子侧面和第三子侧面，所述第一子侧面比所述第三子侧面更靠近所述第一导电子层，所述第一子侧面与所述第一导电子层所成的角度为第一角度，所述第二子侧面与所述第一导电子层所成的角度为第二角度，所述第三子侧面与所述第一导电子层所成的角度为第三角度，所述第三角度大于所述第二角度，所述第二角度大于所述第一角度。
  9. 根据权利要求3所述的显示面板，其中，所述第二导电子层包括两个侧面，所述两个侧面相对设置，所述两个侧面沿所述导电构件的厚度方向呈对称设置。
  10. 根据权利要求3所述的显示面板，其中，所述第二导电子层的所述第一表面、所述第二表面和所述侧面至少之一包含N元素、S元素、P元素和Cl元素至少之一。
  11. 根据权利要求1-10任一项所述的显示面板，其中，所述阻隔层具有F元素和Cl元素至少之一。
  12. 根据权利要求11所述的显示面板，其中，所述阻隔层中的所述F元素和Cl元素至少之一的含量在每立方厘米1×10 18至5×10 20个原子。
  13. 根据权利要求1-12任一项所述的显示面板，其中，所述第一表面与所述第一导电子层接触，所述第二表面与所述第三导电子层接触。
  14. 根据权利要求1-13任一项所述的显示面板，其中，所述第三导电子层覆盖所述第二导电子层，并与所述第一导电子层接触。
  15. 根据权利要求1-14任一项所述的显示面板，其中，所述第一表面的宽度小于所述第一导电子层的宽度，所述第二表面的宽度小于所述第三导电子层的宽度，所述第三导电子层和所述第二表面的宽度差大于所述第三导电子层的厚度。
  16. 根据权利要求1-15任一项所述的显示面板，其中，提供两个相邻的导电构件，所述两个相邻的导电构件彼此绝缘，所述两个相邻的导电构件位于同一层，所述两个相邻的导电构件包括第一导电构件和第二导电构件，所述第一导电构件的所述第三导电子层和所述第二导电构件的所述第三导电子层之间的间距小于所述第一导电构件的所述第二导电子层的所述第二表面和所述第二导电构件的所述第二导电子层的所述第二表面之间的间距。
  17. 根据权利要求16所述的显示面板，其中，所述第一导电构件的所述第二表面和所述第二导电构件的所述第二表面在不同位置处的距离不同。
  18. 根据权利要求16或17所述的显示面板，其中，w1为所述第一导电构件在其宽度方向上的截面中的最大宽度，w2为所述第二导电构件在其宽度方向上的截面中的最大宽度，Δw11为所述第一导电构件中所述第三导电子层超出所述第二表面的距离，Δw12为所述第二导电构件中所述第三导电子层超出所述第二表面的距离，dmin为所述第一导电构件和所述第二导电构件之间的最小间距，满足以下关系式：
    Figure PCTCN2021094326-appb-100001
  19. 根据权利要求1-15任一项所述的显示面板，其中，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件到所述衬底基板的距离不同，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件的厚度为T3，所述第二导电构件的厚度为T4，T4大于T3，所述第一导电构件中所述第三导电子层超出所述第二表面的距离为Δw3，所述第二导电构件中所述第三导电子层超出所述第二表面的距离为Δw4，满足如下关系式：
    Figure PCTCN2021094326-appb-100002
  20. 根据权利要求1-15任一项所述的显示面板，其中，提供两个导电构件，所述两个导电构件彼 此绝缘，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件比所述第二导电构件更靠近所述显示区，所述第一导电构件中所述第三导电子层凸出所述第二表面的尺寸大于所述第二导电构件中所述第三导电子层凸出所述第二表面的尺寸。
  21. 根据权利要求1-20任一项所述的显示面板，还包括第二导电部，其中，所述第二导电部与所述导电构件设置在不同层，且所述导电构件具有第一端部，所述第二导电部具有第二端部，所述第一端部和所述第二端部之间设有绝缘层，所述绝缘层具有暴露所述第一端部或所述第二端部的第一过孔，所述导电构件通过所述第一过孔与所述第二导电部相连。
  22. 根据权利要求1-21任一项所述的显示面板，还包括第二导电部，其中，所述第二导电部与所述导电构件位于同一层。
  23. 根据权利要求1-22任一项所述的显示面板，还包括第三导电部，其中，所述第一导电部电连接至所述第三导电部，所述第三导电部具有第三端部，所述第一导电部具有第四端部，所述第三端部和所述第四端部之间设有绝缘层，所述绝缘层具有暴露所述第三端部或所述第四端部的第二过孔，所述第一导电部通过所述第二过孔与所述第三导电部电连接。
  24. 根据权利要求1-23任一项所述的显示面板，其中，所述导电构件包括第一部分和第二部分，所述第一部分的宽度大于所述第二部分的宽度，所述第一部分的第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述第二部分的第三导电子层沿所述导电构件的宽度方向与第二表面平齐，或者所述第一部分和所述第二部分的第三导电子层均沿所述导电构件的宽度方向凸出于所述第二表面，所述第一部分凸出的宽度大于所述第二部分凸出的宽度。
  25. 根据权利要求1-24任一项所述的显示面板，其中，所述导电构件和所述第一导电部电连接，提供多个第一导电部，相邻导电构件之间具有第一间隔，相邻第一导电部之间具有第二间隔，所述第一间隔与所述第二间隔不同。
  26. 根据权利要求25所述的显示面板，其中，所述第一间隔小于所述第二间隔。
  27. 根据权利要求25或26所述的显示面板，其中，所述导电构件的长度小于所述第一导电部的长度，所述第一导电部包括数据线，所述数据线为与其相连的像素单元提供数据电压。
  28. 根据权利要求25-27任一项所述的显示面板，其中，所述每个像素单元包括设置在所述阻隔层上的像素电路层、与所述像素电路层电连接的有机电致发光器件，以及设置在所述有机电致发光器件出光侧的触控电极，所述第一导电部为所述像素电路层，所述有机电致发光元件或所述触控电极中的任意一种。
  29. 一种显示面板，包括：
    显示区，具有多个像素单元，包括可折叠区和位于所述可折叠区的相对的两侧的第一显示区和第二显示区；
    周边区，位于所述显示区的至少一侧；
    阻隔层，位于衬底基板上；
    导电构件，设置在所述阻隔层的背离所述衬底基板的一侧，所述导电构件在其延伸方向上的长度大于所述导电构件在与延伸方向相交的方向上的宽度，且所述导电构件包括依次层叠的第一导电子层、 第二导电子层和第三导电子层，所述第一导电子层比所述第三导电子层更靠近所述衬底基板；以及
    第一导电部，位于所述显示区，所述第一导电部与所述导电构件同层设置且材料相同，
    其中，所述第一导电子层的电导率小于所述第二导电子层的电导率且所述第一导电子层的厚度小于所述第二导电子层的厚度，所述第三导电子层的熔点大于所述第二导电子层的熔点，
    所述第二导电子层包括靠近所述第一导电子层的第一表面和靠近所述第三导电子层的第二表面，所述第一表面和所述第二表面相对设置，所述第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述宽度方向与所述导电构件的延伸方向相交。
  30. 根据权利要求29所述的显示面板，其中，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件比所述第二导电构件更靠近所述可折叠区，所述第一导电构件中所述第三导电子层凸出所述第二表面的尺寸大于所述第二导电构件中所述第三导电子层凸出所述第二表面的尺寸。
  31. 根据权利要求29或30所述的显示面板，其中，提供两个相邻的导电构件，所述两个相邻的导电构件彼此绝缘，所述两个相邻的导电构件位于同一层，所述两个相邻的导电构件包括第一导电构件和第二导电构件，所述第一导电构件的所述第三导电子层和所述第二导电构件的所述第三导电子层之间的间距小于所述第一导电构件的所述第二导电子层的所述第二表面和所述第二导电构件的所述第二导电子层的所述第二表面之间的间距。
  32. 根据权利要求31所述的显示面板，其中，所述第一导电构件的所述第二表面和所述第二导电构件的所述第二表面在不同位置处的距离不同。
  33. 根据权利要求31或32所述的显示面板，其中，w1为所述第一导电构件在其宽度方向上的截面中的最大宽度，w2为所述第二导电构件在其宽度方向上的截面中的最大宽度，Δw11为所述第一导电构件中所述第三导电子层超出所述第二表面的距离，Δw12为所述第二导电构件中所述第三导电子层超出所述第二表面的距离，dmin为所述第一导电构件和所述第二导电构件之间的最小间距，满足以下关系式：
    Figure PCTCN2021094326-appb-100003
  34. 根据权利要求29-33任一项所述的显示面板，其中，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件到所述衬底基板的距离不同，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件的厚度为T3，所述第二导电构件的厚度为T4，T4大于T3，所述第一导电构件中所述第三导电子层超出所述第二表面的距离为Δw3，所述第二导电构件中所述第三导电子层超出所述第二表面的距离为Δw4，满足如下关系式：
    Figure PCTCN2021094326-appb-100004
  35. 根据权利要求29-33任一项所述的显示面板，还包括第二导电部，其中，所述第二导电部与所述导电构件位于同一层；或者，所述第二导电部与所述导电构件设置在不同层，且所述导电构件具有第一端部，所述第二导电部具有第二端部，所述第一端部和所述第二端部之间设有绝缘层，所述绝缘层具有暴露所述第一端部或所述第二端部的第一过孔，所述导电构件通过所述第一过孔与所述第二导电部相连。
  36. 根据权利要求29-35任一项所述的显示面板，还包括第三导电部，其中，所述第一导电部电连接至所述第三导电部，所述第三导电部具有第三端部，所述第一导电部具有第四端部，所述第三端部和所述第四端部之间设有绝缘层，所述绝缘层具有暴露所述第三端部或所述第四端部的第二过孔，所述第一导电部通过所述第二过孔与所述第三导电部电连接。
  37. 根据权利要求29-36任一项所述的显示面板，其中，所述导电构件包括第一部分和第二部分，所述第一部分的宽度大于所述第二部分的宽度，所述第一部分的第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述第二部分的第三导电子层沿所述导电构件的宽度方向与第二表面平齐，或者所述第一部分和所述第二部分的第三导电子层均沿所述导电构件的宽度方向凸出于所述第二表面，所述第一部分凸出的宽度大于所述第二部分凸出的宽度。
  38. 根据权利要求29-37任一项所述的显示面板，其中，所述导电构件和所述第一导电部电连接，提供多个第一导电部，相邻导电构件之间具有第一间隔，相邻第一导电部之间具有第二间隔，所述第一间隔与所述第二间隔不同。
  39. 根据权利要求38所述的显示面板，其中，所述第一间隔小于所述第二间隔。
  40. 根据权利要求38所述的显示面板，其中，所述导电构件的长度小于所述第一导电部的长度，所述第一导电部包括数据线，所述数据线为与其相连的像素单元提供数据电压。
  41. 一种显示面板，包括：
    显示区，具有多个像素单元；
    周边区，位于所述显示区的至少一侧；
    透光区，位于所述周边区的远离所述显示区的一侧或被所述显示区包围；
    阻隔层，位于衬底基板上；
    导电构件，设置在所述阻隔层的背离所述衬底基板的一侧，所述导电构件在其延伸方向上的长度大于所述导电构件在与延伸方向相交的方向上的宽度，且所述导电构件包括依次层叠的第一导电子层、第二导电子层和第三导电子层，所述第一导电子层比所述第三导电子层更靠近所述衬底基板；以及
    第一导电部，位于所述显示区，所述第一导电部与所述导电构件同层设置且材料相同，
    其中，所述第一导电子层的电导率小于所述第二导电子层的电导率且所述第一导电子层的厚度小于所述第二导电子层的厚度，所述第三导电子层的熔点大于所述第二导电子层的熔点，
    所述第二导电子层包括靠近所述第一导电子层的第一表面和靠近所述第三导电子层的第二表面，所述第一表面和所述第二表面相对设置，所述第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述宽度方向与所述导电构件的延伸方向相交。
  42. 根据权利要求41所述的显示面板，其中，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件比所述第二导电构件更靠近所述透光区，所述第一导电构件中所述第三导电子层凸出所述第二表面的尺寸大于所述第二导电构件中所述第三导电子层凸出所述第二表面的尺寸。
  43. 根据权利要求41或42所述的显示面板，其中，提供两个相邻的导电构件，所述两个相邻的导电构件彼此绝缘，所述两个相邻的导电构件位于同一层，所述两个相邻的导电构件包括第一导电构 件和第二导电构件，所述第一导电构件的所述第三导电子层和所述第二导电构件的所述第三导电子层之间的间距小于所述第一导电构件的所述第二导电子层的所述第二表面和所述第二导电构件的所述第二导电子层的所述第二表面之间的间距。
  44. 根据权利要求43所述的显示面板，其中，所述第一导电构件的所述第二表面和所述第二导电构件的所述第二表面在不同位置处的距离不同。
  45. 根据权利要求41-44任一项所述的显示面板，其中，w1为所述第一导电构件在其宽度方向上的截面中的最大宽度，w2为所述第二导电构件在其宽度方向上的截面中的最大宽度，Δw11为所述第一导电构件中所述第三导电子层超出所述第二表面的距离，Δw12为所述第二导电构件中所述第三导电子层超出所述第二表面的距离，dmin为所述第一导电构件和所述第二导电构件之间的最小间距，满足以下关系式：
    Figure PCTCN2021094326-appb-100005
  46. 根据权利要求41-45任一项所述的显示面板，其中，提供两个导电构件，所述两个导电构件彼此绝缘，所述两个导电构件到所述衬底基板的距离不同，所述两个导电构件包括第一导电构件和第二导电构件，所述第一导电构件的厚度为T3，所述第二导电构件的厚度为T4，T4大于T3，所述第一导电构件中所述第三导电子层超出所述第二表面的距离为Δw3，所述第二导电构件中所述第三导电子层超出所述第二表面的距离为Δw4，满足如下关系式：
    Figure PCTCN2021094326-appb-100006
  47. 根据权利要求41-46任一项所述的显示面板，还包括第二导电部，其中，所述第二导电部与所述导电构件位于同一层；或者，所述第二导电部与所述导电构件设置在不同层，且所述导电构件具有第一端部，所述第二导电部具有第二端部，所述第一端部和所述第二端部之间设有绝缘层，所述绝缘层具有暴露所述第一端部或所述第二端部的第一过孔，所述导电构件通过所述第一过孔与所述第二导电部相连。
  48. 根据权利要求41-47任一项所述的显示面板，还包括第三导电部，其中，所述第一导电部电连接至所述第三导电部，所述第三导电部具有第三端部，所述第一导电部具有第四端部，所述第三端部和所述第四端部之间设有绝缘层，所述绝缘层具有暴露所述第三端部或所述第四端部的第二过孔，所述第一导电部通过所述第二过孔与所述第三导电部电连接。
  49. 根据权利要求41-48任一项所述的显示面板，其中，所述导电构件包括第一部分和第二部分，所述第一部分的宽度大于所述第二部分的宽度，所述第一部分的第三导电子层沿所述导电构件的宽度方向凸出于所述第二表面，所述第二部分的第三导电子层沿所述导电构件的宽度方向与第二表面平齐，或者所述第一部分和所述第二部分的第三导电子层均沿所述导电构件的宽度方向凸出于所述第二表面，所述第一部分凸出的宽度大于所述第二部分凸出的宽度。
  50. 根据权利要求41-49任一项所述的显示面板，其中，所述导电构件和所述第一导电部电连接，提供多个第一导电部，相邻导电构件之间具有第一间隔，相邻第一导电部之间具有第二间隔，所述第一间隔与所述第二间隔不同。
  51. 根据权利要求50所述的显示面板，其中，所述第一间隔小于所述第二间隔。
  52. 根据权利要求50所述的显示面板，其中，所述导电构件的长度小于所述第一导电部的长度，所述第一导电部包括数据线，所述数据线为与其相连的像素单元提供数据电压。
  53. 一种显示装置，包括根据权利要求1-52任一项所述的显示面板。
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