WO2021233276A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2021233276A1
WO2021233276A1 PCT/CN2021/094286 CN2021094286W WO2021233276A1 WO 2021233276 A1 WO2021233276 A1 WO 2021233276A1 CN 2021094286 W CN2021094286 W CN 2021094286W WO 2021233276 A1 WO2021233276 A1 WO 2021233276A1
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Prior art keywords
layer
word line
substrate
forming
shallow trench
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PCT/CN2021/094286
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English (en)
French (fr)
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徐正弘
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长鑫存储技术有限公司
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Priority to EP21800975.1A priority Critical patent/EP3958314B1/en
Priority to US17/445,085 priority patent/US20210375879A1/en
Publication of WO2021233276A1 publication Critical patent/WO2021233276A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors
    • H01L2221/1073—Barrier, adhesion or liner layers

Definitions

  • This application relates to the field of integrated circuit technology, in particular to a semiconductor structure and a method of manufacturing the same.
  • Shallow Trench Isolation isolates a number of active areas (AA) arranged at intervals in the substrate; the word line structure that can be used as the gate of the transistor of the memory cell intersects the active area ; The source and drain regions of the transistor are formed in the substrate on both sides of the gate.
  • the word line trench of the word line structure is formed by one-time etching, and the width of the upper part of the conductive layer in the word line structure is not significantly different from the width of the lower part.
  • the channel width of the gate of the semiconductor device with the above word line structure is relatively narrow, and the resistance between the source and the drain is relatively large, resulting in a relatively small current between the source and the drain during operation. , Thereby affecting the performance of the device.
  • the overall width of the active region must be increased, and the increase in the width of the active region will result in too small a spacing between adjacent active regions, which leads to adjacent ones.
  • the source area is short-circuited.
  • a semiconductor structure and a manufacturing method thereof are provided.
  • a method for preparing a semiconductor structure includes:
  • a substrate is provided, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure isolates a plurality of active regions arranged at intervals in the substrate;
  • a word line trench is formed in the substrate, and the depth of the word line trench in the active region portion is smaller than the depth in the shallow trench isolation structure portion, so that the word line trench is located in the A first protrusion structure is formed at the bottom of the active area part;
  • a part of the shallow trench isolation structure is removed to form a second raised structure based on the first raised structure.
  • the upper sidewall and top of the second raised structure are covered with the etching protection layer, the The part of the shallow trench isolation structure where the lower portion of the second protruding structure is removed is exposed;
  • a word line structure is formed in the word line trench.
  • the semiconductor structure prepared by the above-mentioned method for preparing the semiconductor structure has a second protrusion structure at the bottom of the word line trench located in the active region, and the width of the lower part of the second protrusion structure is smaller than the width of the upper part of the second protrusion structure, so it can be Without increasing the width of the upper part of the active region, the channel width of the gate is increased, the resistance between the source and the drain is reduced, and the current between the source and the drain is increased.
  • FIG. 1 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment
  • FIG. 2 is a schematic diagram of a cross-sectional structure of a substrate with an oxide layer, a nitride layer, and a first mask layer formed on the upper surface in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a structure obtained after patterning the first mask layer in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 4 is a schematic cross-sectional structure diagram of a structure obtained after a shallow trench is formed in a substrate in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 5 is a schematic cross-sectional structure diagram of a structure obtained after a shallow trench isolation structure is formed in a substrate in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 6 is a schematic diagram of a cross-sectional structure of a structure obtained after patterning the second mask layer in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 7 is a schematic diagram of a structure obtained after forming a word line trench in a substrate in a method for fabricating a semiconductor structure provided by an embodiment
  • FIG. 8 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 7;
  • FIG. 9 is a schematic cross-sectional structure view along the BB direction in FIG. 7;
  • FIG. 10 is a schematic cross-sectional structure view along the CC direction in FIG. 7;
  • FIG. 11 is a schematic view of the cross-sectional structure of the structure obtained after the etching protection layer is formed in the AA direction in FIG. 7 in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 12 is a schematic view of the cross-sectional structure in the CC direction of FIG. 7 of the structure obtained after the etching protection layer is formed in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 13 is a schematic cross-sectional structure diagram of a structure obtained after forming a second protrusion structure based on the first protrusion structure in a method for manufacturing a semiconductor structure according to an embodiment
  • FIG. 14 is a schematic diagram of a cross-sectional structure of a structure obtained after etching the lower portion of the second protruding structure based on an etching protection layer in a method for manufacturing a semiconductor structure provided by an embodiment
  • 15 is a schematic view of the cross-sectional structure of the structure obtained after the formation of the inter-gate dielectric layer in the manufacturing method of the semiconductor structure provided by an embodiment, taken along the AA direction in FIG. 7;
  • 16 is a schematic view of the cross-sectional structure of the structure obtained after the formation of the inter-gate dielectric layer in a method for manufacturing a semiconductor structure provided by an embodiment, taken along the CC direction in FIG. 7;
  • FIG. 17 is a schematic view of the cross-sectional structure of the structure obtained after forming the first conductive material layer in the direction of AA in FIG. 7 in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 18 is a schematic view of the cross-sectional structure of the structure obtained after forming the first conductive material layer in the direction of CC in FIG. 7 in a method for manufacturing a semiconductor structure provided by an embodiment
  • 19 is a schematic cross-sectional structure view of the structure obtained after forming the second conductive material layer in a method for manufacturing a semiconductor structure provided by an embodiment, taken along the AA direction in FIG. 7;
  • FIG. 20 is a schematic cross-sectional structure diagram of the structure obtained after forming the second conductive material layer in a method for preparing a semiconductor structure according to an embodiment, taken along the CC direction in FIG. 7; FIG.
  • FIG. 21 is a schematic cross-sectional structure view of the structure obtained after forming the first conductive layer and the second conductive layer in a method for manufacturing a semiconductor structure provided by an embodiment, taken along the AA direction in FIG. 7;
  • FIG. 22 is a schematic view of the cross-sectional structure of the structure obtained after forming the first conductive layer and the second conductive layer in the direction of CC in FIG. 7 in a method for manufacturing a semiconductor structure provided by an embodiment
  • FIG. 23 is a schematic cross-sectional structure diagram of the structure obtained after forming the etching protection layer in another semiconductor structure manufacturing method provided by an embodiment, taken along the AA direction in FIG. 7; FIG.
  • FIG. 24 is a schematic cross-sectional structure view of the structure obtained after the etching protection layer is formed in the CC direction in FIG. 7 in another method for preparing a semiconductor structure provided by an embodiment
  • 25 is a schematic cross-sectional structure view of the structure obtained after forming a filling insulating layer in a method for manufacturing a semiconductor structure provided by an embodiment, taken along the AA direction in FIG. 7;
  • FIG. 26 is a schematic cross-sectional structure diagram of the structure obtained after forming a filling insulating layer in a method for manufacturing a semiconductor structure provided by an embodiment, taken along the CC direction in FIG. 7.
  • This application provides a method for manufacturing a semiconductor structure.
  • the manufacturing method of the semiconductor structure may include the following steps:
  • a substrate 10 is provided, a shallow trench isolation structure 20 is formed in the substrate 10, and the shallow trench isolation structure 20 isolates a plurality of active regions 40 arranged at intervals in the substrate 10;
  • a first raised structure 310 is formed at the bottom of the device
  • the word line trench 30 is located at the bottom of the active region 40 and has a second raised structure 340.
  • the width of the lower part of the second raised structure 340 is smaller than that of the second raised structure 340.
  • the width of the upper part can increase the channel width of the gate without increasing the width of the upper part of the active region 40, reduce the resistance between the source and the drain, and increase the current between the source and the drain.
  • the substrate 10 provided in step S10 may include any existing semiconductor substrate.
  • the substrate 10 may include, but is not limited to, a silicon substrate.
  • forming the shallow trench isolation structure 20 in the substrate 10 in step S10 may include the following steps:
  • the first patterned mask layer 220 has a first opening pattern 221, and the first opening pattern 221 defines a shallow groove The position of the slot isolation structure 20;
  • the step S110 may include forming an oxide layer 211 on the upper surface of the substrate 10, and then forming a nitride layer 212 on the upper surface of the oxide layer 211.
  • the first mask layer 210 may be a photoresist layer, and the first mask layer 210 may be formed on the upper surface of the nitride layer 212 by, but not limited to, a spin coating process.
  • the oxide layer 211 may be formed by a physical vapor deposition process, a chemical deposition process, or a thermal oxidation process; when the substrate 10 is a silicon substrate, a thermal oxidation process may be used to form an oxide layer on the surface of the substrate 10 211.
  • the thickness of the oxide layer 211 can be set according to actual needs. In this embodiment, the thickness of the oxide layer 211 can be, but is not limited to, 3 nm to 15 nm.
  • the nitride layer 212 may be formed by a physical vapor deposition process or a chemical vapor deposition process or the like.
  • a Low Pressure Chemical Vapor Deposition (LPCVD) process may be used to form the nitride layer 212; the nitride layer 212 may include but is not limited to silicon nitride.
  • the thickness of the nitride layer 212 can be set according to actual needs. In this embodiment, the thickness of the nitride layer 212 can be, but is not limited to, 100 nm to 200 nm.
  • step S120 may use a photolithography and etching process to pattern the first mask layer 210 to obtain the first patterned mask layer 220.
  • the first patterned mask layer 220 has a first opening pattern 221 in it, and the first opening pattern 221 defines the position of the shallow trench 230.
  • the shallow trench 230 may include a first shallow trench 231 and a second shallow trench (not shown), wherein the first shallow trench 231 may be located in the length direction of the active region 40 (the active region 40 In the substrate 10 between two adjacent active regions 40 in the extension direction), the second shallow trench may be located in the width direction of the active region 40 (perpendicular to the extension direction of the active region 40). 40 between the base 10 inside.
  • a step of removing the first patterned mask layer 220 may be included.
  • the distance between the first shallow trench 231 and the upper surface of the substrate 10 may be 250 nm to 350 nm, and the distance between the second shallow trench and the upper surface of the substrate 10 may be 200 nm to 300 nm.
  • step S140 filling the isolation material 240 in the shallow trench 230 to form the shallow trench isolation structure 20 may include the following steps:
  • S141 Fill the isolation material 240 in the shallow trench 230 and the upper surface of the etched nitride layer 212;
  • the isolation material 240 may include, but is not limited to, silicon oxide.
  • a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process can be used to remove the isolation material 240 located on the upper surface of the etched nitride layer 212, and the patterned nitride layer 212 can be As a polishing stop layer.
  • CMP Chemical Mechanical Polishing
  • step S20 forming the word line trench 30 in the substrate 10 may include the following steps:
  • S220 Perform a patterning process on the second mask layer to form a second patterned mask layer 321.
  • the second patterned mask layer 321 has a second opening pattern 322, and the second opening pattern 322 defines a word line groove The position of slot 30;
  • a photolithography process may be used to pattern the second mask layer to form the second patterned mask layer 321.
  • the second patterned mask layer 321 has a second opening pattern 322 therein, and the second opening pattern 322 defines the position of the word line trench 30.
  • step S220 is based on the second patterned mask layer 321.
  • a dry etching process can be used to etch the substrate 10, the oxide layer 211, and the nitrogen.
  • the compound layer 212 is used to form a word line trench 30 in the substrate 10.
  • a step of removing the second patterned mask layer 321 may be included.
  • the extending direction of the word line trench 30 and the extending direction of the active region 40 may intersect at an angle of less than 90 degrees.
  • the word line trench 30 in the process of forming the word line trench 30, along the extending direction of the word line trench 30, the word line trench 30 is located in the part of the active region 40
  • the depth of the word line trench 30 is different from the depth of the word line trench 30 located in the shallow trench isolation structure 20.
  • the depth of the word line trench 30 located in the active region 40 is smaller than that of the word line trench located in the shallow trench isolation structure 20
  • the depth of the word line trench 30 is located at the bottom of the active region 40 to form the first raised structure 310.
  • a solution containing but not limited to hydrofluoric acid HF, diluted hydrofluoric acid DHF (1:100 ⁇ 1:2000, that is, 49% HF: deionized water) or buffered oxide etching solution (Buffered Oxide Etch) can be used. , BOE), etc., perform wet cleaning and wet etching on the isolation material 240 in the word line trench 30 to form the first raised structure 310.
  • the depth of each part of the word line trench 30 can be set according to actual needs. In this embodiment, the depth of the part of the word line trench 30 in the active region 40 can be, but is not limited to, 90 nm to 160 nm. The depth of the portion 30 located in the shallow trench isolation structure 20 is 100 nm to 180 nm.
  • step S30 forming an etching protection layer 330 on the surface of the first protruding structure 310 may include the following steps:
  • nitrogen gas is introduced into the word line trench 30 at a predetermined temperature to form a nitride layer as the etching protection layer 330 on the sidewall and bottom of the word line trench 30 in the active region 40.
  • nitrogen gas can be introduced into the word line trench 30 at a high temperature above 900°C, and the partial pressure of the nitrogen gas can be about 0.1 MPa, so that the silicon substrate is exposed to the outside.
  • a silicon nitride layer is formed on the sidewalls and bottom of the silicon substrate as an etch protection layer 330 to protect the silicon substrate.
  • the reaction formula can be expressed as:
  • the isolation material 240 may be etched.
  • HF containing but not limited to hydrofluoric acid, diluted hydrofluoric acid DHF (1:100 ⁇ 1:2000, that is, 49% HF: deionized water) or buffered oxide etching solution (Buffered Oxide) can be used. Etch, BOE) etc.
  • the second convex structure 340 is formed based on the first convex structure 310. It should be noted that after the step S40 is completed, the upper sidewall and top of the second raised structure 340 are covered with the etching protection layer 330, and the lower part of the second raised structure 340 is exposed by removing part of the isolation material 240.
  • the height of the lower portion of the second protruding structure 340 can be set according to actual needs.
  • the height of the lower portion of the second raised structure 340 may be, but is not limited to, 3-20 nm, and the width of the lower portion of the second raised structure 340 may be smaller than the width of the upper portion, but is not limited to 2-10 nm.
  • step S50 wet etching may be used, but not limited to, to etch the exposed portion of the lower portion of the second protruding structure 340, so that the second protruding structure
  • the width of the lower part of 340 is smaller than the width of the upper part of the second protruding structure 340.
  • the silicon substrate can be etched with but not limited to alkaline liquids such as diluted potassium hydroxide KOH or ammonium hydroxide NH 4 OH to increase the channel width of the gate and reduce the source and The resistance between the drains increases the current between the source and drain.
  • alkaline liquids such as diluted potassium hydroxide KOH or ammonium hydroxide NH 4 OH
  • step S60 forming the word line structure 50 in the word line trench 30 may include the following steps:
  • wet etching may be used, but not limited to, to remove the oxide layer that is naturally generated on the surface of the inter-gate dielectric layer 510 to be formed.
  • Etch, BOE buffered oxide etching solution perform wet cleaning to remove the sidewalls formed on the word line trench 30, the bottom of the word line trench 30, the upper surface of the etched nitride layer 212, and the upper surface of the shallow trench isolation structure 20 The surface has an oxide layer in its natural state.
  • the inter-gate dielectric layer 510 may include a silicon oxide layer, a silicon nitride layer, or a high-k dielectric layer.
  • the high-k dielectric layer may be, but is not limited to, an aluminum oxide layer, a hafnium oxide layer, a hafnium silicon oxide layer, a hafnium aluminum oxide layer, a tantalum oxide layer, a zirconium oxide layer, or a stack of the foregoing multiple layers.
  • the thickness of the inter-gate dielectric layer 510 may be, but is not limited to, 3 nm-7 nm.
  • the first conductive material layer 520 may be formed by but not limited to a physical vapor deposition process or a chemical vapor deposition process; the first conductive material layer 520 may include, but is not limited to, a titanium nitride layer. The thickness of the first conductive material layer 520 may be, but is not limited to, 2 nm to 5 nm.
  • the second conductive material layer 530 may be formed by a process such as electroplating.
  • the second conductive material layer 530 may be, but is not limited to, a tungsten layer.
  • step S640 a chemical mechanical polishing process may be used to remove the first conductive material layer 520 and the first conductive material layer 520 on the upper surface of the patterned nitride layer 212.
  • Two conductive material layer 530 After engraving, the upper surface of the first conductive layer 540 and the upper surface of the second conductive layer 550 are both lower than the top of the word line trench 30, and the upper surface of the second conductive layer 550 is higher than the upper surface of the first conductive layer 540. surface.
  • forming an etching protection layer 330 on the surface of the first protrusion structure 310 may include the following steps: using an epitaxial growth method where the word line trench 30 is located. Part of the sidewall and bottom of the source region 40 form an epitaxial layer 331, and the material of the epitaxial layer 331 is the same as that of the substrate 10.
  • VPE Vapor Phase Epitaxy
  • MBE Molecular Beam Epitaxy
  • LPE Liquid Phase Epitaxy
  • An epitaxial layer 331 is grown on the sidewall and bottom of the trench 30.
  • the substrate 10 is a silicon substrate
  • the above process and the growth of epitaxial silicon on the sidewall and bottom of the word line trench can be used as the epitaxial layer 331 so that the material of the epitaxial layer 331 is the same as the material of the substrate 10.
  • forming the word line structure 50 in the word line trench 30 may include the following steps:
  • the first conductive material layer 520 and the second conductive material layer 530 are etched back to obtain the first conductive layer 540 and the second conductive layer 550, the upper surface of the first conductive layer 540 and the upper surface of the second conductive layer 550 The surface is lower than the top of the word line trench 30.
  • wet etching may be used, but not limited to, to remove the oxide layer that is naturally generated on the surface of the inter-gate dielectric layer 510 to be formed.
  • Etch, BOE buffered oxide etching solution
  • perform wet cleaning to remove the sidewalls formed on the word line trench 30, the bottom of the word line trench 30, the upper surface of the etched nitride layer 212, and the upper surface of the shallow trench isolation structure 20 The surface has an oxide layer in its natural state.
  • an in-situ steam (ISSG) process may be used to oxidize the substrate to form the inter-gate dielectric layer 510.
  • the inter-gate dielectric layer 510 may be a silicon oxide layer.
  • the thickness of the inter-gate dielectric layer 510 can be set according to actual needs. In this embodiment, the thickness of the inter-gate dielectric layer 510 can be, but is not limited to, 3 nm-7 nm. It should be noted that steps S660 to S680 may be the same as steps S620 to S640.
  • the etch protection layer 330 may include an oxide layer or a nitride layer. In this embodiment, before forming the inter-gate dielectric layer 510, a step of removing the etching protection layer 330 is further included.
  • step S330 when step S330 is used to form an oxide layer and a nitride layer on the sidewall and bottom of the word line trench 30 as the etching protection layer 330, a word is formed in the word line trench 30 in step S60.
  • a step of removing the etching protection layer 330 is further included.
  • the silicon nitride when the substrate 10 is a silicon substrate and silicon nitride is used as the etching protection layer, the silicon nitride can be removed by but not limited to wet etching.
  • a hot phosphoric acid H 3 PO 4 solution with a temperature range of 110° C. to 165° C.
  • the silicon nitride can be used to etch silicon nitride, and the silicon nitride can be removed by precisely controlling the action time of phosphoric acid. It should be noted that at this time, the surface of the silicon nitride as the nitride layer 212 is also lightly etched.
  • step S680 the following steps are further included:
  • the filling insulating layer 570 can be formed by but not limited to a low-pressure chemical vapor deposition process.
  • the filling insulating layer 570 may include, but is not limited to, a silicon nitride layer.
  • step S691 the following steps are further included:
  • drain (not shown) and a source (not shown) in the active region 40.
  • the drain is located between the gate word lines 560 across the same active region 40, and the source is located on the side of the gate word line 560 away from the drain.
  • the etched nitride layer 212, the inter-gate dielectric layer 510, the first conductive material layer 520, and the first conductive material layer 520 on the upper surface of the substrate 10 may be removed.
  • the present application also provides a semiconductor structure 100.
  • the semiconductor structure 100 may include a substrate 10, a shallow trench isolation structure 20, a word line trench 30 opened in the substrate 10, and a gate word line 560.
  • the shallow trench isolation structure 20 isolates a plurality of active regions 40 arranged at intervals in the substrate 10.
  • the word line trench 30 is located in the substrate 10.
  • the word line trench 30 is located at the bottom of the active area 40 and has a raised structure 350.
  • the width of the lower portion of the raised structure 350 is smaller than the width of the upper portion of the raised structure 350.
  • the gate word line 560 is located in the word line trench 30.
  • the word line trench 30 is located at the bottom of the active region 40 and has a raised structure 350.
  • the width of the lower portion of the raised structure 350 is smaller than the width of the upper portion of the second raised structure 350.
  • the channel width of the gate is increased, the resistance between the source and the drain is reduced, and the current between the source and the drain is increased.
  • the substrate 10 may include any existing semiconductor substrate.
  • the substrate 10 may include, but is not limited to, a silicon substrate.
  • a shallow trench 230 is formed in the substrate 10, and the shallow trench 230 is filled with an isolation material 240 to form the shallow trench isolation structure 20.
  • the shallow trench 230 may include a first shallow trench 231 and a second shallow trench, where the first shallow trench 231 may be located adjacent to the length direction of the active region 40 (the extension direction of the active region 40).
  • the second shallow trench may be located in the substrate 10 between two adjacent active regions 40 in the width direction of the active region 40 (perpendicular to the extending direction of the active region 40).
  • the distance between the first shallow trench 231 and the upper surface of the substrate 10 may be 250 nm to 350 nm, and the distance between the second shallow trench and the upper surface of the substrate 10 may be 200 nm to 300 nm.
  • the substrate 10 is provided with a word line trench 30, and the gate word line 560 is located in the word line trench 30, that is, a word line structure 50 is formed.
  • the extending direction of the word line trench 30 and the extending direction of the active region 40 may intersect at an angle of less than 90 degrees.
  • the word line trench 30 is located at the distance between the bottom of the active region 40 and the upper surface of the substrate 10, and the word line trench 30 is located at the bottom of the shallow trench isolation structure 20 and the upper surface of the substrate 10.
  • the distance between can be set according to actual needs. In this embodiment, the distance between the word line trench 30 located at the bottom of the active region 40 and the upper surface of the substrate 10 is 90-160 nm, and the word line trench 30 is located at the bottom of the shallow trench isolation structure 20 and the substrate 10.
  • the distance between the upper surfaces is 100 nm to 180 nm.
  • the height of the lower portion of the raised structure 350 can be set according to actual needs.
  • the height of the lower portion of the raised structure 350 is but not limited to 3-20 nm, and the width of the lower portion of the raised structure 350 may be smaller than the width of the upper portion, but is not limited to 2-10 nm.
  • the gate word line 560 includes an inter-gate dielectric layer 510, a first conductive layer 540, and a second conductive layer 550.
  • the inter-gate dielectric layer 510 may be located on the sidewall and bottom of the word line trench 30, and may include a silicon oxide layer, a silicon nitride layer, or a high-k dielectric layer.
  • the thickness of the inter-gate dielectric layer 510 can be set according to actual needs. In this embodiment, the thickness of the inter-gate dielectric layer 510 can be, but is not limited to, 3 nm-7 nm.
  • the first conductive layer 540 is located in the word line trench 30 and on the surface of the inter-gate dielectric layer 510, and the upper surface of the first conductive layer 540 is lower than the top of the word line trench 30.
  • the first conductive layer 540 may include, but is not limited to, a titanium nitride layer.
  • the thickness of the first conductive layer 540 may be set according to actual needs. In this embodiment, the thickness of the first conductive layer 540 may be, but is not limited to, 2 nm to 5 nm. .
  • the second conductive layer 550 is located in the word line trench 30 and on the surface of the first conductive layer 540, and the upper surface of the second conductive layer 550 is lower than the top of the word line trench 30.
  • the height of the upper surface of the second conductive layer 550 may be equal to the height of the upper surface of the first conductive layer 540.
  • the second conductive layer 550 may be, but is not limited to, a tungsten layer.
  • the semiconductor structure further includes a filling insulating layer 570, the filling insulating layer 570 is located on the gate word line 560, and the filling insulating layer 570 fills the word line trench 30 , And cover the upper surface of the patterned nitride layer 212.
  • the filling insulating layer 570 may include, but is not limited to, a silicon nitride layer.
  • the semiconductor structure 100 further includes a drain (not shown).
  • the drain is located in the active region 40 and between two gate word lines 560 that span the same active region 40; the source is (Not shown), it is located in the active region 40 and located on the side of the gate word line 560 away from the drain.

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Abstract

一种半导体结构及其制备方法，包括：提供基底，于基底内形成浅沟槽隔离结构，浅沟槽隔离结构于基底内隔离出若干个间隔排布的有源区；于基底内形成字线沟槽，字线沟槽位于有源区部分的深度小于位于浅沟槽隔离结构部分的深度，以使字线沟槽位于有源区部分的底部形成第一凸起结构；于第一凸起结构的表面形成刻蚀保护层；去除部分浅沟槽隔离结构，以基于第一凸起结构形成第二凸起结构，第二凸起结构的上部侧壁及顶部覆盖有刻蚀保护层，第二凸起结构的下部被去除的部分浅沟槽隔离结构暴露出来；对第二凸起结构的下部进行刻蚀，以使得第二凸起结构下部的宽度小于第二凸起结构上部的宽度；于字线沟槽内形成字线结构。

Description

半导体结构及其制备方法
相关申请的交叉引用
本申请要求于2020年5月22日提交中国专利局、申请号为2020104414459、发明名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，特别是涉及一种半导体结构及其制备方法。
背景技术
浅沟槽隔离结构(Shallow Trench Isolation，STI)在基底内隔离出若干间隔排布的有源区(Active Area，AA)；可作为存储单元的晶体管的栅极的字线结构与有源区相交；晶体管的源漏区形成于该栅极两侧的衬底中。在传统的半导体工艺中，字线结构的字线沟槽通过一次性刻蚀而形成，且字线结构中的导电层的上部的宽度与下部的宽度没有明显差异。
然而，具有上述字线结构的半导体器件中栅极的沟道宽度(Channel Width)较窄，源极与漏极之间的电阻较大，导致工作时源极与漏极之间的电流较小，从而影响器件的性能。为了将栅极的沟道宽度提高至所需的要求，则必须增加有源区的整体宽度，而有源区宽度的增加会导致相邻有源区之间的间距太小而导致相邻有源区短路。
发明内容
根据各个实施例，提供一种半导体结构及其制备方法。
一种半导体结构的制备方法，包括：
提供基底，于所述基底内形成浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出若干个间隔排布的有源区；
于所述基底内形成字线沟槽，所述字线沟槽位于所述有源区部分的深度小于位于所述浅沟槽隔离结构部分的深度，以使得所述字线沟槽位于所述有源区部分的底部形成第一凸起结构；
于所述第一凸起结构的表面形成刻蚀保护层；
去除部分所述浅沟槽隔离结构，以基于所述第一凸起结构形成第二凸起结构，所述第二凸起结构的上部侧壁及顶部覆盖有所述刻蚀保护层，所述第二凸起结构的下部被去除的部分所述浅沟槽隔离结构暴露出来；
对所述第二凸起结构的下部进行刻蚀，以使得所述第二凸起结构下部的宽度小于所述第二凸起结构上部的宽度；及
于所述字线沟槽内形成字线结构。
上述半导体结构的制备方法制备的半导体结构，其字线沟槽位于有源区部分的底部具有第二凸起结构，第二凸起结构下部的宽度小于第二凸起结构上部的宽度，故可以在不增加有源区上部的宽度的前提下增加栅极的沟道宽度，降低源极与漏极之间的电阻，增大源极与漏极之间的电流。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例提供的一种半导体结构的制备方法流程图；
图2为一实施例提供的一种半导体结构的制备方法中，上表面形成有氧化物层、氮化物层以及第一掩膜层的基底的截面结构示意图；
图3为一实施例提供的一种半导体结构的制备方法中，对第一掩膜层进行图形化处理后所得结构的截面结构示意图；
图4为一实施例提供的一种半导体结构的制备方法中，于基底内形成浅沟槽后所得结构的截面结构示意图；
图5为一实施例提供的一种半导体结构的制备方法中，于基底内形成浅沟槽隔离结构后所得结构的截面结构示意图；
图6为一实施例提供的一种半导体结构的制备方法中，对第二掩膜层进行图形化处理后所得结构的截面结构示意图；
图7为一实施例提供的一种半导体结构的制备方法中，于基底内形成字线沟槽后所得结构示意图；
图8为沿图7中AA方向的截面结构示意图；
图9为沿图7中BB方向的截面结构示意图；
图10为沿图7中CC方向的截面结构示意图；
图11为一实施例提供的一种半导体结构的制备方法中，形成刻蚀保护层后所得结构的同图7中AA方向的截面结构示意图；
图12为一实施例提供的一种半导体结构的制备方法中，形成刻蚀保护层后所得结构的同图7中CC方向的截面结构示意图；
图13为一实施例提供的一种半导体结构的制备方法中，基于第一凸起结构形成第二凸起结构后所得结构的截面结构示意图；
图14为一实施例提供的一种半导体结构的制备方法中，基于刻蚀保护层对第二凸起结构的下部进行刻蚀后所得结构的截面结构示意图；
图15为一实施例提供的一种半导体结构的制备方法中，形成栅间介质层后所得结构的同图7中AA方向的截面结构示意图；
图16为一实施例提供的一种半导体结构的制备方法中，形成栅间介质层后所得结构的同图7中CC方向的截面结构示意图；
图17为一实施例提供的一种半导体结构的制备方法中，形成第一导电材料层后所得结构的同图7中AA方向的截面结构示意图；
图18为一实施例提供的一种半导体结构的制备方法中，形成第一导电材料层后所得结构的同图7中CC方向的截面结构示意图；
图19为一实施例提供的一种半导体结构的制备方法中，形成第二导电材料层后所得结构的同图7中AA方向的截面结构示意图；
图20为一实施例提供的一种半导体结构的制备方法中，形成第二导电材料层后所得结构的同图7中CC方向的截面结构示意图；
图21为一实施例提供的一种半导体结构的制备方法中，形成第一导电层及第二导电层后所得结构的同图7中AA方向的截面结构示意图；
图22为一实施例提供的一种半导体结构的制备方法中，形成第一导电层及第二导电层后所得结构的同图7中CC方向的截面结构示意图；
图23为一实施例提供的另一种半导体结构的制备方法中，形成刻蚀保护层后所得结构的同图7中AA方向的截面结构示意图；
图24为一实施例提供的另一种半导体结构的制备方法中，形成刻蚀保护层后所得结构的同图7中CC方向的截面结构示意图；
图25为一实施例提供的一种半导体结构的制备方法中，形成填充绝缘层后所得结构的同图7中AA方向的截面结构示意图；
图26为一实施例提供的一种半导体结构的制备方法中，形成填充绝缘层后所得结构的同图7中CC方向的截面结构示意图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
请参见图1，本申请提供一种半导体结构的制备方法。半导体结构的制备方法可以包括如下步骤：
S10，提供基底10，于基底10内形成浅沟槽隔离结构20，浅沟槽隔离结构20于基底10内隔离出若干个间隔排布的有源区40；
S20，于基底内形成字线沟槽30，字线沟槽30位于有源区40部分的深度小于位于浅沟槽隔离结构20部分的深度，以使得字线沟槽30位于有源区40部分的底部形成第一凸起结构310；
S30，于第一凸起结构310的表面形成刻蚀保护层330；
S40，去除部分浅沟槽隔离结构20，以基于第一凸起结构310形成第二凸起结构340，第二凸起结构340的上部侧壁及顶部覆盖有刻蚀保护层330，第二凸起结构340的下部被去除的部分浅沟槽隔离结构暴露出来；
S50，对第二凸起结构340的下部进行刻蚀，以使得第二凸起结构340下部的宽度小于第二凸起结构340上部的宽度；
S60，于字线沟槽30内形成字线结构50。
上述半导体结构的制备方法制备的半导体结构100，其字线沟槽30位于有源区40部分的底部具有第二凸起结构340，第二凸起结构340下部的宽度小于第二凸起结构340上部的宽度，故可以在不增加有源区40上部的宽度的前提下增加栅极的沟道宽度，降低源极与漏极之间的电阻，增大源极与漏极之间的电流。
在其中一个实施例中，步骤S10中提供的基底10可以包括任意一种现有的半导体基底。本实施例中，基底10可以包括但不仅限于硅基底。
在其中一个实施例中，步骤S10中于基底10内形成浅沟槽隔离结构20，可以包括如下步骤：
S110，于基底10的上表面形成第一掩膜层210；
S120，对第一掩膜层210进行图形化处理，以得到第一图形化掩膜层220，第一图形化掩膜层220内具有第一开口图形221，第一开口图形221定义出浅沟槽隔离结构20的位置；
S130，基于第一图形化掩膜层220刻蚀基底10，以于基底10内形成浅沟槽230；
S140，于浅沟槽230内填充隔离材料240以形成浅沟槽隔离结构20。
请一并参见图2，在其中一个实施例中，步骤S110之前可以包括：于基底10的上表面形成氧化物层211，再于氧化物层211的上表面形成氮化物层212。
在其中一个实施例中，步骤S110中，第一掩膜层210可以为光刻胶层，可以采用但不仅限于旋涂工艺于氮化物层212的上表面形成第一掩膜层210。
在其中一个实施例中，可以采用物理气相沉积工艺、化学沉积工艺或热氧化工艺等形成氧化物层211；当基底10为硅基底时，可以采用热氧化工艺于基底10的表面形成氧化物层211。氧化物层211的厚度可以根据实际需要进行设定，本实施例中，氧化物层211的厚度可以为但不仅限于3nm～15nm。
在其中一个实施例中，可以采用物理气相沉积工艺或化学气相沉积工艺等形成氮化物层212。本实施例中，可以采用低压化学气相沉积(Low Pressure Chemical Vapor Deposition，LPCVD)工艺形成氮化物层212；氮化物层212可以包括但不仅限于氮化硅。氮化物层212的厚度可以根据实际需要进行设 定，本实施例中，氮化物层212的厚度可以为但不仅限于100nm～200nm。
请一并参见图3，在其中一个实施例中，步骤S120可以采用光刻刻蚀工艺对第一掩膜层210进行图形化处理，以得到第一图形化掩膜层220。第一图形化掩膜层220内具有第一开口图形221，第一开口图形221定义出浅沟槽230的位置。
请一并参见图4，在其中一个实施例中，步骤S130中基于第一图形化掩膜层220，可以同时对氧化物层211、氮化物层212以及基底10进行刻蚀，其中可以采用但不限于干法刻蚀工艺刻蚀基底10，以于基底10内形成浅沟槽230。在本实施例中，浅沟槽230可以包括第一浅沟槽231和第二浅沟槽(未示出)，其中第一浅沟槽231可以位于有源区40长度方向(有源区40延伸方向)上相邻两个有源区40之间的基底10内，第二浅沟槽可以位于有源区40宽度方向(垂直于有源区40延伸方向)上相邻两个有源区40之间的基底10内。在其中一个实施例中，在步骤S130之后，可以包括去除第一图形化掩膜层220的步骤。本实施例中，第一浅沟槽231距离基底10上表面的距离可以为250nm～350nm，第二浅沟槽距离基底10上表面的距离可以为200nm～300nm。
请一并参见图5，步骤S140中，于浅沟槽230内填充隔离材料240以形成浅沟槽隔离结构20可以包括如下步骤：
S141：于浅沟槽230内及刻蚀后的氮化物层212的上表面填充隔离材料240；
S142：去除位于刻蚀后的氮化物层212的上表面的隔离材料240，保留的隔离材料240填满浅沟槽230，且保留的隔离材料240的上表面可以与图形化后的氮化物层212的上表面相平齐。
在其中一个实施例中，可以采用但不仅限于高密度等离子化学气相沉积(High Density Plasma-Chemical Vapor Deposition，HDPCVD)工艺、可流动氧化物化学气相沉积(Flowable oxide CVD)工艺或旋涂介质层(Spin-on Dielectric，SOD)工艺形成隔离材料240。隔离材料240可以包括但不仅限于氧化硅。
在其中一个实施例中，可以采用但不仅限于化学机械抛光(Chemical Mechanical Polishing，CMP)工艺去除位于刻蚀后的氮化物层212的上表面的隔离材料240，图形化后的氮化物层212可以作为研磨停止层。
在其中一个实施例中，步骤S20中，于基底10内形成字线沟槽30，可以包括如下步骤：
S210，于基底10的上表面形成第二掩膜层(未示出)；
S220，对第二掩膜层进行图形化处理，以形成第二图形化掩膜层321，第二图形化掩膜层321内具有第二开口图形322，第二开口图形322定义出字线沟槽30的位置；
S230，基于第二图形化掩膜层321刻蚀基底10，以于基底10内形成字线沟槽30。
请一并参见图6，在其中一个实施例中，步骤S210可以采用光刻工艺对第二掩膜层进行图形化处理，以形成第二图形化掩膜层321。第二图形化掩膜层321内具有第二开口图形322，第二开口图形322定义出字线沟槽30的位置。
请一并参见图7-图8，在其中一个实施例中，步骤S220基于第二图形化掩膜层321，可以采用但不限于干法刻蚀工艺刻蚀基底10、氧化物层211和氮化物层212，以于基底10内形成字线沟槽30。在步骤S220之后，可以包括去除第二图形化掩膜层321的步骤。在其中一个实施例中，字线沟槽30的延伸方向与有源区40的延伸方向可以相交于小于90度的角度。
请一并参见图9-图10，在其中一个实施例中，在形成字线沟槽30的过程中，沿字线沟槽30延伸方向，字线沟槽30位于有源区40内的部分的深度与字线沟槽30位于浅沟槽隔离结构20内的深度不同，一般为字线沟槽30位于有源区40内的部分的深度小于字线沟槽位于浅沟槽隔离结构20内的深度，以使得字线沟槽30位于有源区40部分的底部形成第一凸起结构310。本实施例中，可以采用含有但不仅限于氢氟酸HF、稀释氢氟酸DHF(1：100～1：2000，即49％HF：去离子水)或缓冲氧化物刻蚀液(Buffered Oxide Etch，BOE)等对字线沟槽30内的隔离材料240进行湿法清洁和湿法蚀刻，以形成第一凸起结构310。字线沟槽30各部分的深度可以根据实际需要进行设定，本实施例中，字线沟槽30位于有源区40内的部分的深度可以为但不仅限于90nm～160nm，字线沟槽30位于浅沟槽隔离结构20内的部分的深度为100nm～180nm。
请一并参见图11-图12，在其中一个实施例中，步骤S30中，于第一凸起结构310的表面形成刻蚀保护层330，可以包括如下步骤：
S310，于预设温度下向字线沟槽30内通入氮气，以于字线沟槽30位于有源区40部分的侧壁及底部形成氮化物层作为刻蚀保护层330。
在其中一个实施例中，当基底10为硅基底时，可以在900℃以上的高温下向字线沟槽30内通入氮气，氮气的分压可以约为0.1MPa，以于硅基底裸露在外的侧壁及底部形成氮化硅层作为刻蚀保护层330保护硅基底。其中，反应式可以表示为：
3Si+2N 2(g)→Si 3N 4。
请一并参见图13，在其中一个实施例中，步骤S40中可以采用但不仅限于湿法清洁和湿法蚀刻工艺对隔离材料240进行刻蚀。在本实施例中，可以采用含有但不仅限于氢氟酸HF，稀释氢氟酸DHF(1：100～1：2000，即49％HF：去离子水)或缓冲氧化物刻蚀液(Buffered Oxide Etch，BOE)等对隔离材料240进行湿法清洁和湿法蚀刻，以使字线沟槽30位于有源区40内的上表面与位于浅沟槽隔离结构20内的上表面之间的高度差增大，即基于第一凸起结构310形成第二凸起结构340。需要说明的是，在步骤S40完成后，第二凸起结构340的上部侧壁及顶部覆盖有刻蚀保护层330，第二凸起结构340的下部被去除部分隔离材料240后暴露出来。
在其中一个实施例中，第二凸起结构340的下部高度可以根据实际需要进行设定。本实施例中，第二凸起结构340的下部高度可以为但不仅限于3～20nm，第二凸起结构340的下部的宽度比上部的宽度可以小但不仅限于2～10nm。
请一并参见图14，在其中一个实施例中，步骤S50中可以采用但不仅限于湿法刻蚀对第二凸起结构340的下部暴露出来的部分进行刻蚀，以使第二凸起结构340下部的宽度小于第二凸起结构340上部的宽度。当基底10为硅基底时，可以采用但不限于稀释的氢氧化钾KOH或氢氧化铵NH 4OH等碱性液体对硅基底进行刻蚀，以增加栅极的沟道宽度，降低源极与漏极之间的电阻，增大源极与漏极之间的电流。其中，反应式可以表示为：
Si+4OH -→SiO 2(OH) 2 -2+2H ++4e -；
4e -+4H 2O→4OH -+2H +；
SiO 2(OH) 2 -2+2H +→Si(OH) 4→Si(OH) 3-O-Si(OH) 3+H 2O。
在其中一个实施例中，步骤S60中，于字线沟槽30内形成字线结构50，可以包括如下步骤：
S610，于字线沟槽30的侧壁、字线沟槽30的底部、刻蚀后的氮化物层212的上表面及浅沟槽隔离结构20的上表面形成栅间介质层510；
S620，于栅间介质层510的表面形成第一导电材料层520；
S630，于第一导电材料层520的表面形成第二导电材料层530；
S640，去除位于刻蚀后的氮化物层212上表面及浅沟槽隔离结构20上表面的第一导电材料层520及第二导电材料层530，并回刻去除位于字线沟槽30内的部分第一导电材料层520及部分第二导电材料层530，以得到第一导电层540及第二导电层550，第一导电层540的上表面及第二导电层550的上表面均低于字线沟槽30的顶部。
在其中一个实施例中，在步骤S610之前，可以采用但不仅限于湿法刻蚀去除待形成栅间介质层510的表面上的天然情况下产生氧化层。在本实施例中，可以采用含有但不仅限于氢氟酸HF、稀释氢氟酸DHF(1：100～1：2000，即49％HF：去离子水)或缓冲氧化物刻蚀液(Buffered Oxide Etch，BOE)等进行湿法清洗以去除形成于字线沟槽30的侧壁、字线沟槽30的底部、刻蚀后的氮化物层212的上表面及浅沟槽隔离结构20的上表面的天然情况下产生氧化层。
请一并参见图15-图16，在其中一个实施例中，在步骤S610中，栅间介质层510可以包括氧化硅 层、氮化硅层或高k介电层。在本实施例中，高k介电层可以为但不限于氧化铝层、氧化铪层、氧化铪硅层、氧化铪铝层、氧化钽层、氧化锆层或上述多个层的堆叠。栅间介质层510的厚度可以为但不仅限于3nm～7nm。
请一并参见图17-图18，在其中一个实施例中，在步骤S620中，可以采用但不仅限于物理气相沉积工艺或化学气相沉积工艺等形成第一导电材料层520；第一导电材料层520可以包括但不仅限于氮化钛层。第一导电材料层520的厚度可以为但不仅限于2nm～5nm。
请一并参见图19-图20，在其中一个实施例中，在步骤S630中，可以采用电镀等工艺形成第二导电材料层530，第二导电材料层530可以为但不仅限于钨层。
请一并参见图21-图22，在其中一个实施例中，在步骤S640中，可以采用化学机械抛光工艺去除位于图形化后的氮化物层212上表面上的第一导电材料层520、第二导电材料层530。回刻后，第一导电层540的上表面及第二导电层550的上表面均低于字线沟槽30的顶部，且第二导电层550的上表面高于第一导电层540的上表面。
请一并参见图23-图24，在其中一个实施例中，于第一凸起结构310的表面形成刻蚀保护层330，可以包括如下步骤：使用外延生长法在字线沟槽30位于有源区40的部分的侧壁和底部形成外延层331，外延层331的材料与基底10的材料相同。
在其中一个实施例中，可以采用但不仅限于气相外延(Vapor Phase Epitaxy，VPE)工艺、分子束外延(Molecular Beam Epitaxy，MBE)工艺以及液相外延(Liquid Phase Epitaxy，LPE)工艺于字线沟槽30的侧壁及底部生长外延层331。当基底10为硅基底时，可以采用上述工艺与字线沟槽的侧壁及底部生长外延硅作为外延层331，以使外延层331的材料与基底10的材料相同。
在其中一个实施例中，于字线沟槽30内形成字线结构50，可以包括如下步骤：
S650，于字线沟槽30的侧壁及底部形成栅间介质层510；
S660，于栅间介质层510表面形成第一导电材料层520；
S670，于第一导电材料层520的表面形成第二导电材料层530；
S680，对第一导电材料层520及第二导电材料层530进行回刻，以得到第一导电层540及第二导电层550，第一导电层540的上表面及第二导电层550的上表面均低于字线沟槽30的顶部。
在其中一个实施例中，在步骤S650之前，可以采用但不仅限于湿法刻蚀去除待形成栅间介质层510的表面上的天然情况下产生氧化层。在本实施例中，可以采用含有但不仅限于氢氟酸HF、稀释氢氟酸DHF(1：100～1：2000，即49％HF：去离子水)或缓冲氧化物刻蚀液(Buffered Oxide Etch，BOE)等进行湿法清洗以去除形成于字线沟槽30的侧壁、字线沟槽30的底部、刻蚀后的氮化物层212的上表面及浅沟槽隔离结构20的上表面的天然情况下产生氧化层。
在其中一个实施例中，在步骤S650中，可以采用原位蒸汽(In Situ Steam Generation，ISSG)工艺对基底进行氧化以形成栅间介质层510。本实施例中，栅间介质层510可以为氧化硅层。栅间介质层510的厚度可以根据实际需要进行设定，本实施例中，栅间介质层510的厚度可以为但不仅限于3nm～7nm。需要说明的是，步骤S660～步骤S680可以与步骤S620～步骤S640相同。
在其中一个实施例中，刻蚀保护层330可以包括氧化物层或氮化物层。本实施例中，形成栅间介质层510之前还包括去除刻蚀保护层330的步骤。
在其中一个实施例中，当采用步骤S330于字线沟槽30的侧壁及底部形成氧化物层和氮化物层作为刻蚀保护层330时，在步骤S60于字线沟槽30内形成字线结构50之前，也即在形成栅间介质层510之前，还包括去除刻蚀保护层330的步骤。在其中一个实施例中，当基底10为硅基底，并采用氮化硅作为刻蚀保护层时，氮化硅可以采用但不限于湿法蚀刻进行去除。本实施例中，可以使用温度范围在110℃至165℃之间的热磷酸H 3PO 4溶液对氮化硅进行蚀刻，并通过精确控制磷酸的作用时间实现对氮化硅的去除。需要说明的是，此时作为氮化物层212的氮化硅表面也被轻蚀刻。
在其中一个实施例中，在步骤S680之后还包括如下步骤：
S691，于字线沟槽30内及刻蚀后的氮化物层212的上表面形成填充绝缘层570。
在其中一个实施例中，可以采用但不仅限于低压化学气相沉积工艺形成填充绝缘层570。本实施例 中，填充绝缘层570可以包括但不仅限于氮化硅层。
在其中一个实施例中，步骤S691之后还包括如下步骤：
S692，于所述有源区40内形成漏极(未示出)及源极(未示出)。漏极位于横跨同一有源区40的栅极字线560之间，源极位于栅极字线560远离漏极的一侧。
需要说明的是，形成所述漏极及所述源极之前，可以先去除位于基底10上表面上的刻蚀后的氮化物层212、栅间介质层510、第一导电材料层520及第二导电材料层530。
基于同一发明构思，本申请还提供一种半导体结构100。半导体结构100可以包括基底10、浅沟槽隔离结构20、开设于基底10内的字线沟槽30以及栅极字线560。浅沟槽隔离结构20于基底10内隔离出若干个间隔排布的有源区40。字线沟槽30位于基底10内，字线沟槽30位于有源区40部分的底部具有凸起结构350，凸起结构350下部的宽度小于凸起结构350上部的宽度。栅极字线560位于字线沟槽30内。
上述半导体结构100，其字线沟槽30位于有源区40部分的底部具有凸起结构350，凸起结构350下部的宽度小于第二凸起结构350上部的宽度，故可以在不增加有源区40上部的宽度的前提下增加栅极的沟道宽度，降低源极与漏极之间的电阻，增大源极与漏极之间的电流。
在其中一个实施例中，基底10可以包括任意一种现有的半导体基底。本实施例中，基底10可以包括但不仅限于硅基底。
在其中一个实施例中，基底10内开设有浅沟槽230，于浅沟槽230内填充隔离材料240即可形成浅沟槽隔离结构20。本实施例中，浅沟槽230可以包括第一浅沟槽231和第二浅沟槽，其中第一浅沟槽231可以位于有源区40长度方向(有源区40延伸方向)上相邻两个有源区40之间的基底10内，第二浅沟槽可以位于有源区40宽度方向(垂直于有源区40延伸方向)上相邻两个有源区40之间的基底10内。本实施例中，第一浅沟槽231距离基底10上表面的距离可以为250nm～350nm，第二浅沟槽距离基底10上表面的距离可以为200nm～300nm。
在其中一个实施例中，基底10内开设有字线沟槽30，栅极字线560位于字线沟槽30内，即形成字线结构50。在其中一个实施例中，字线沟槽30的延伸方向与有源区40的延伸方向可以相交于小于90度的角度。
在其中一个实施例中，字线沟槽30位于有源区40部分的底部与基底10上表面之间的距离和字线沟槽30位于浅沟槽隔离结构20部分的底部与基底10上表面之间的距离可以根据实际需要进行设定。本实施例中，字线沟槽30位于有源区40部分的底部与基底10上表面之间的距离为90～160nm，字线沟槽30位于浅沟槽隔离结构20部分的底部与基底10上表面之间的距离为100nm～180nm。
在其中一个实施例中，凸起结构350的下部高度可以根据实际需要进行设定。本实施例中，凸起结构350的下部高度为但不限于3～20nm，凸起结构350的下部的宽度比上部的宽度可以小但不限于2～10nm。
在其中一个实施例中，栅极字线560包括栅间介质层510、第一导电层540以及第二导电层550。其中，栅间介质层510可以位于字线沟槽30的侧壁及底部，可以包括氧化硅层、氮化硅层或高k介电层。栅间介质层510的厚度可以根据实际需要进行设定，本实施例中，栅间介质层510的厚度可以为但不仅限于3nm～7nm。
在其中一个实施例中，第一导电层540位于字线沟槽30内，且位于栅间介质层510的表面，第一导电层540的上表面低于字线沟槽30的顶部。第一导电层540可以包括但不仅限于氮化钛层，第一导电层540的厚度可以根据实际需要进行设定，本实施例中，第一导电层540的厚度可以为但不仅限于2nm～5nm。
在其中一个实施例中，第二导电层550位于字线沟槽30内，且位于第一导电层540的表面，第二导电层550的上表面低于字线沟槽30的顶部。本实施例中，第二导电层550的上表面的高度可以等于第一导电层540的上表面的高度。第二导电层550可以为但不仅限于钨层。
请一并参见图25-图26，在其中一个实施例中，半导体结构还包括填充绝缘层570，填充绝缘层570位于栅极字线560上，且填充绝缘层570填满字线沟槽30，并覆盖图形化后的氮化物层212的上 表面。填充绝缘层570可以包括但不仅限于氮化硅层。
在其中一个实施例中，半导体结构100还包括漏极(未示出)，漏极位于有源区40内，且位于横跨同一有源区40的两栅极字线560之间；源极(未示出)，位于有源区40内，且位于栅极字线560远离漏极的一侧。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种半导体结构的制备方法，包括：
    提供基底，于所述基底内形成浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出若干个间隔排布的有源区；
    于所述基底内形成字线沟槽，所述字线沟槽位于所述有源区部分的深度小于位于所述浅沟槽隔离结构部分的深度，以使得所述字线沟槽位于所述有源区部分的底部形成第一凸起结构；
    于所述第一凸起结构的表面形成刻蚀保护层；
    去除部分所述浅沟槽隔离结构，以基于所述第一凸起结构形成第二凸起结构，所述第二凸起结构的上部侧壁及顶部覆盖有所述刻蚀保护层，所述第二凸起结构的下部被去除的部分所述浅沟槽隔离结构暴露出来；
    对所述第二凸起结构的下部进行刻蚀，以使得所述第二凸起结构下部的宽度小于所述第二凸起结构上部的宽度；及
    于所述字线沟槽内形成字线结构。
  2. 根据权利要求1所述的方法，其中所述于所述第一凸起结构的表面形成刻蚀保护层，包括：
    于预设温度下向所述字线沟槽内通入氮气，以于所述字线沟槽位于所述有源区部分的侧壁及底部形成氮化物层作为所述刻蚀保护层。
  3. 根据权利要求1所述的方法，其中所述于所述基底内形成浅沟槽隔离结构，包括：
    于所述基底的上表面形成第一掩膜层；
    对所述第一掩膜层进行图形化处理，以得到第一图形化掩膜层，所述第一图形化掩膜层内具有第一开口图形，所述第一开口图形定义出所述浅沟槽隔离结构的位置；
    基于所述第一图形化掩膜层刻蚀所述基底，以于所述基底内形成浅沟槽；及
    于所述浅沟槽内填充隔离材料以形成所述浅沟槽隔离结构。
  4. 根据权利要求3所述的方法，其中于所述基底的上表面形成第一掩膜层之前，所述方法还包括：于所述基底的上表面形成氧化物层，再于所述氧化物层的上表面形成氮化物层。
  5. 根据权利要求4所述的方法，其中于所述浅沟槽内填充隔离材料以形成所述浅沟槽隔离结构包括：
    于所述浅沟槽内及刻蚀后的氮化物层的上表面填充隔离材料；
    去除位于刻蚀后的氮化物层的上表面的所述隔离材料，保留的隔离材料填满所述浅沟槽，且保留的隔离材料的上表面与图形化后的氮化物层的上表面相平齐。
  6. 根据权利要求5所述的方法，其中所述于所述字线沟槽内形成字线结构包括：
    于所述字线沟槽的侧壁、所述字线沟槽的底部、刻蚀后的氮化物层的上表面及所述浅沟槽隔离结构的上表面形成栅间介质层；
    于所述栅间介质层的表面形成第一导电材料层；
    于所述第一导电材料层的表面形成第二导电材料层；
    去除位于刻蚀后的氮化物层上表面及所述浅沟槽隔离结构上表面的所述第一导电材料层及所述第二导电材料层，并回刻去除位于所述字线沟槽内的部分第一导电材料层及部分第二导电材料层，以得到第一导电层及第二导电层，所述第一导电层的上表面及所述第二导电层的上表面均低于所述字线沟槽的顶部。
  7. 根据权利要求1所述的方法，其中所述于所述基底内形成所述字线沟槽，包括：
    于所述基底的上表面形成第二掩膜层；及
    对所述第二掩膜层进行图形化处理，以形成第二图形化掩膜层，所述第二图形化掩膜层内具有第二开口图形，所述第二开口图形定义出所述字线沟槽的位置；
    基于所述第二图形化掩膜层刻蚀所述基底，以于所述基底内形成所述字线沟槽。
  8. 根据权利要求1所述的方法，其中所述于所述字线沟槽内形成字线结构包括：
    于所述字线沟槽的侧壁及底部形成栅间介质层；
    于所述栅间介质层表面形成第一导电材料层；
    于所述第一导电材料层的表面形成第二导电材料层；及
    对所述第一导电材料层及所述第二导电材料层进行回刻，以得到第一导电层及第二导电层，所述第一导电层的上表面及所述第二导电层的上表面均低于所述字线沟槽的顶部。
  9. 根据权利要求8所述的方法，其中形成所述栅间介质层之前，所述方法还包括：去除所述刻蚀保护层。
  10. 根据权利要求8所述的方法，其中所述栅间介质层包括氧化硅层、氮化硅层或高k介电层。
  11. 根据权利要求10所述的方法，其中所述高k介电层为氧化铝层、氧化铪层、氧化铪硅层、氧化铪铝层、氧化钽层、氧化锆层或上述多个层的堆叠。
  12. 根据权利要求8所述的方法，其中在对所述第一导电材料层及所述第二导电材料层进行回刻，以得到第一导电层及第二导电层之后，所述方法还包括：
    于所述字线沟槽内及刻蚀后的氮化物层的上表面形成填充绝缘层。
  13. 根据权利要求8所述的方法，还包括：
    于所述有源区内形成漏极及源极，所述漏极位于横跨同一有源区的栅极字线之间，所述源极位于所述栅极字线远离所述漏极的一侧。
  14. 根据权利要求13所述的方法，其中于形成所述漏极及所述源极之前，所述方法包括：去除位于所述基底上表面的刻蚀后的氮化物层、所述栅间介质层、所述第一导电材料层及所述第二导电材料层。
  15. 根据权利要求1所述的方法，其中所述于所述第一凸起结构的表面形成刻蚀保护层，包括：使用外延生长法在所述字线沟槽位于所述有源区的部分的侧壁和底部形成外延层，所述外延层的材料与所述基底的材料相同。
  16. 一种半导体结构，包括：
    基底；
    浅沟槽隔离结构，所述浅沟槽隔离结构于所述基底内隔离出若干个间隔排布的有源区；
    字线沟槽，位于所述基底内，所述字线沟槽位于所述有源区部分的底部具有凸起结构，所述凸起结构下部的宽度小于所述凸起结构上部的宽度；以及
    栅极字线，位于所述字线沟槽内。
  17. 根据权利要求16所述的半导体结构，其中所述凸起结构的下部高度为3～20nm，所述凸起结构的下部的宽度比上部的宽度小2～10nm。
  18. 根据权利要求17所述的半导体结构，其中所述字线沟槽位于所述有源区部分的底部与所述基底上表面之间的距离为90～160nm，所述字线沟槽位于所述浅沟槽隔离结构部分的底部与所述基底上表面之间的距离为100nm～180nm。
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