WO2021232950A1 - 一种通信装置 - Google Patents

一种通信装置 Download PDF

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Publication number
WO2021232950A1
WO2021232950A1 PCT/CN2021/084216 CN2021084216W WO2021232950A1 WO 2021232950 A1 WO2021232950 A1 WO 2021232950A1 CN 2021084216 W CN2021084216 W CN 2021084216W WO 2021232950 A1 WO2021232950 A1 WO 2021232950A1
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Prior art keywords
signal
terminal
state
positive
negative
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PCT/CN2021/084216
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English (en)
French (fr)
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金玮
冀晋
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展讯通信（上海）有限公司
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Publication of WO2021232950A1 publication Critical patent/WO2021232950A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of communication technology, in particular to a communication device.
  • a communication device that can implement multiple applications, it usually has at least two integrated circuit chips, one of which is a modem (modem), which is used to implement cellular communication functions, and can be understood as a communication system; the other chip is application processing Application Processor (AP for short) is used to implement functions such as shooting, display, 2D/3D engine, etc., and can be understood as an application processing system.
  • modem modem
  • AP application processing Application Processor
  • the application processor acts as a master IC (Master IC) to control a slave IC (Slave IC) modem, and a serial bus is used to couple between the two for data transmission.
  • Master IC master IC
  • slave IC slave IC
  • serial bus is used to couple between the two for data transmission.
  • the prior art usually uses differential signal lines to connect the application processor and the modem to achieve efficient data exchange.
  • LP mode Low Power
  • MIPI Mobile Industry Processor Interface
  • HS High Speed
  • the technical problem solved by the present invention is to provide an improved communication device, so that no sideband signal or additional low-power circuit between the main control chip and the controlled chip can wake up or sleep the peer.
  • an embodiment of the present invention provides a communication device, including: a main control chip, the main control chip includes a transmitting end; a controlled chip, the controlled chip includes a receiving end, the transmitting end and the receiving end
  • the terminals are coupled by a differential signal line, the differential signal line includes a positive terminal and a negative terminal; a positive terminal state detection unit, coupled to the positive terminal to detect a single-ended signal of the positive terminal; a negative terminal state detection unit , Coupled to the negative terminal to detect the single-ended signal of the negative terminal; a control unit, respectively coupled to the positive terminal state detection unit, the negative terminal state detection unit and the receiving terminal, the control unit according to the detected signal
  • the state combination wakes up or sleeps the receiving end, wherein the signal state combination is a signal state combination of the single-ended signal at the positive end and the single-ended signal at the negative end.
  • the signal state of the single-ended signal at the positive end is the same as that of the single-ended signal at the negative end.
  • the control unit wakes up or sleeps the receiving end according to the detected signal state combination includes: when the signal state combination is 11, the control unit wakes up the receiving end, and when the signal state combination When it is 00, the control unit sleeps the receiving end; or, when the signal state combination is 00, the control unit wakes up the receiving end, and when the signal state combination is 11, the control unit Sleep the receiving end.
  • the positive end state detection unit and the negative end state detection unit enter a non-working state.
  • the positive-end state detection unit and the negative-end state detection unit are kept in a working state.
  • the receiving terminal receives the signals of the positive terminal and the negative terminal respectively, and determines the start timing and the end timing of the current data transmission according to a combination of the signal states of the positive terminal and the negative terminal.
  • the receiving end determining the start timing and ending timing of this data transmission according to the signal state combination of the positive end and the negative end includes: when the signal state combination of the positive end and the negative end is 10, the receiving end The terminal determines that the current data transmission will start after a preset period of time, and when the signal state of the positive terminal and the negative terminal is combined to be 01, the receiving terminal determines that the current data transmission ends.
  • the swing amplitude of the signal transmitted by the positive terminal and the negative terminal used to wake up or sleep the receiving terminal is greater than the swing amplitude of the signal transmitted by the positive terminal and the negative terminal during data transmission.
  • the positive terminal state detection unit includes a first comparator, and the first comparator is used to detect whether the single-ended signal of the positive terminal is 1 or 0;
  • the negative terminal state detection unit includes a second comparator, The second comparator is used to detect whether the single-ended signal at the negative terminal is 1 or 0.
  • the main control chip further includes: a first control switch for switching the signal state of the positive terminal and/or the signal state of the negative terminal.
  • the controlled chip includes a second control switch for switching the signal state of the positive terminal and/or the negative terminal during reverse transmission;
  • the communication device includes: a reverse positive terminal state detection unit, coupled The positive terminal is connected to detect the single-ended signal when the positive terminal is transmitted in the reverse direction; the reverse negative terminal state detection unit is coupled to the negative terminal to detect the single-ended signal when the negative terminal is transmitted in the reverse direction;
  • the transmitting end is respectively coupled to the reverse positive end state detection unit and the reverse negative end state detection unit to obtain a reverse signal state combination, wherein the reverse signal state combination is the positive end reverse transmission
  • the positive terminal state detection unit monitors the signal state of the positive terminal, and/or the negative terminal state detection unit monitors the signal state of the negative terminal to determine the differential signal line Whether there is a status conflict.
  • the main control chip is an application processor, and the controlled chip is a modem.
  • the communication device further includes: a shared storage module, the application processor is coupled to the shared storage module and can directly access the shared storage module, the modem and the application processor pass through the
  • the differential signal line is coupled to and indirectly accesses the shared memory through the application processor.
  • An embodiment of the present invention provides a communication device, including: a main control chip, the main control chip includes a transmitting end; a controlled chip, the controlled chip includes a receiving end, and a differential signal is passed between the transmitting end and the receiving end Line-phase coupling, the differential signal line includes a positive terminal and a negative terminal; a positive terminal state detection unit coupled to the positive terminal to detect a single-ended signal of the positive terminal; a negative terminal state detection unit coupled to the negative terminal Terminal to detect the single-ended signal of the negative terminal; the control unit is respectively coupled to the positive terminal state detection unit, the negative terminal state detection unit and the receiving terminal, the control unit wakes up or sleeps according to the detected signal state combination
  • the receiving end wherein the signal state combination is a signal state combination of the single-ended signal at the positive end and the single-ended signal at the negative end.
  • the communication device adopting the scheme of this embodiment can wake up or sleep without sideband signals or additional low-power circuits between the master chip and the controlled chip.
  • the edge removal of the differential single-ended voltage amplitude is used as a judgment flag for state switching.
  • both ends of the transceiver are controlled as single-ended, with more signal states, and more messages can be transmitted.
  • the signal state of the single-ended signal at the positive end is the same as that of the single-ended signal at the negative end. Therefore, on the basis of the original differential signal, two signal states of double-ended high and double-ended low are added. That is, the two abnormal states of the high-speed differential signal line are used to transmit the control word to realize the sleep or wake-up control of the receiving end. Furthermore, because the peer control is realized by using the abnormal state of the differential drive, no or only a very small amount of additional circuit support is required in the communication device. Furthermore, more information can be transmitted through the switch of abnormal state.
  • FIG. 1 is a schematic diagram of the principle of a first communication device according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of signal swing when the communication device according to an embodiment of the present invention transmits a signal through a differential signal line;
  • Fig. 3 is a schematic diagram of the principle of a second communication device according to an embodiment of the present invention.
  • an LP circuit needs to be additionally provided in existing communication devices or sideband signals are used to implement wake-up or sleep control between master and slave chips.
  • an embodiment of the present invention provides a communication device, including: a main control chip, the main control chip includes a transmitting end; a controlled chip, the controlled chip includes a receiving end, the transmitting end and the receiving end
  • the terminals are coupled by a differential signal line, the differential signal line includes a positive terminal and a negative terminal; a positive terminal state detection unit, coupled to the positive terminal to detect a single-ended signal of the positive terminal; a negative terminal state detection unit , Coupled to the negative terminal to detect the single-ended signal of the negative terminal; a control unit, respectively coupled to the positive terminal state detection unit, the negative terminal state detection unit and the receiving terminal, the control unit according to the detected signal
  • the state combination wakes up or sleeps the receiving end, wherein the signal state combination is a signal state combination of the single-ended signal at the positive end and the single-ended signal at the negative end.
  • No sideband signal or additional low-power circuit between the main control chip and the controlled chip in the communication device adopting the solution of this embodiment can wake up or sleep the opposite end, which is beneficial to reduce the cost and size of the device, and is simple to implement And can pass more information through the switch of signal state.
  • the edge removal of the differential single-ended voltage amplitude is used as a judgment flag for state switching.
  • both ends of the transceiver are controlled as single-ended, with more signal states, and more messages can be transmitted.
  • Fig. 1 is a schematic diagram of the principle of a first communication device according to an embodiment of the present invention.
  • the communication device may be a user equipment such as a mobile phone.
  • the communication device 1 described in this embodiment may include a main control chip 11, and the main control chip 11 may include a sending end 111.
  • the main control chip 11 may be an application processor.
  • the communication device 1 may further include a controlled chip 12, and the controlled chip 12 may include a receiving terminal 121.
  • the controlled chip 12 may be a modem.
  • main control chip 11 and the controlled chip 12 may be coupled through a serial bus for communication.
  • the transmitting terminal 111 and the receiving terminal 121 are coupled through a differential signal line 13, and the differential signal line 13 may include a positive terminal Vp and a negative terminal Vn.
  • the transmitting terminal 111 may be a high-speed transmitting terminal, such as a D-bus transmitting terminal; the receiving terminal 121 may be a high-speed receiving terminal, such as a D-bus receiving terminal.
  • the main control chip 11 and the controlled chip 12 communicate with each other through the differential signal line 13. For example, a high-speed differential signal is transmitted between the main control chip 11 and the controlled chip 12 through the differential signal line 13 to realize data transmission.
  • the communication device 1 may further include a positive terminal state detection unit 122 coupled to the positive terminal Vp to detect a single-ended signal of the positive terminal Vp.
  • the positive terminal state detection unit 122 may include a first comparator 124 configured to detect whether the single-ended signal of the positive terminal Vp is 1 or 0. That is, it is detected whether the single-ended signal of the positive terminal Vp is high or low.
  • 1 represents high level and 0 represents low level
  • the positive end state detection unit 122 may be arranged on the side of the controlled chip 12.
  • the communication device 1 may further include: a negative terminal state detecting unit 123, coupled to the negative terminal Vn to detect a single-ended signal of the negative terminal Vn.
  • the negative terminal state detection unit 123 may include a second comparator 125 configured to detect whether the single-ended signal of the negative terminal Vn is 1 or 0. That is, it is detected whether the single-ended signal of the negative terminal Vn is high or low.
  • the negative terminal state detection unit 123 may be arranged on the side of the controlled chip 12.
  • the communication device 1 may further include a control unit 126, which is respectively coupled to the positive terminal state detection unit 122, the negative terminal state detection unit 123, and the receiving terminal 121, and the The control unit 126 may wake up or sleep the receiving terminal 121 according to the detected signal state combination, wherein the signal state combination is a signal state combination of the single-ended signal of the positive terminal Vp and the single-ended signal of the negative terminal Vn.
  • the signal state combination is a signal state combination of the single-ended signal of the positive terminal Vp and the single-ended signal of the negative terminal Vn.
  • the signal state combination is a signal state combination of the single-ended signal of the positive terminal Vp and the single-ended signal of the negative terminal Vn.
  • the single-ended signal of the positive terminal Vp can be in a high-level state or a low-level state
  • the single-ended signal of the negative terminal Vn can be in a high-level state or a low-level state.
  • the communication device 1 of this embodiment uses the edge removal of the differential single-ended voltage amplitude as a judgment flag for state switching.
  • the transmitting and receiving ends ie, the transmitting end 111 and the receiving end 121 are controlled as single-ended, and the positive end state detection unit 122 and the negative end state detection unit 123 are added to the side of the controlled chip 12 to detect the differential signal line 13 respectively.
  • the single-ended signal state of the positive terminal Vp and the negative terminal Vn Furthermore, in the case of single-ended control, more signal states can be combined, making it possible to transmit more messages.
  • control unit 126 may be a physical module or a software-level control logic.
  • control unit 126 and the receiving terminal 121 may be integrated as a whole, and the positive terminal state detecting unit 122 and the negative terminal state detecting unit 123 directly send the detection result to the receiving terminal 121, so that when the signal state combination is a wake-up or sleep control word Wake up or sleep the receiving end 121 directly.
  • the two can also be two separate modules.
  • the signal state of the single-ended signal of the positive terminal Vp is the same as the signal state of the single-ended signal of the negative terminal Vn.
  • the signal transmitted on the differential signal line 13 is no longer necessarily limited to the differential signal. That is, the signals transmitted by the positive terminal Vp and the negative terminal Vn no longer have to be inverted.
  • two signal states of double-ended high and double-ended low are added. That is, the two abnormal states of the high-speed differential signal line 13 are used to transmit the control word, and the sleep or wake-up control of the receiving end 121 is realized. Furthermore, since the peer control is realized by the abnormal state of the differential driver, no or only a very small amount of additional circuit support is required in the communication device 1. Furthermore, more information can be transmitted through the switch of abnormal state.
  • the control unit 126 can wake up the The receiving end 121, and when the signal state combination is 00 (that is, the double-ended low level, the positive and negative ends are both in the low state, referred to as the double-ended low), the control unit 126 can sleep the receiving ⁇ 121.
  • the control unit 126 wakes up the receiving end 121, and when the signal state combination is 11, the control unit 126 sleeps the receiving end 121.
  • the receiving terminal 121 may respectively receive the signals of the positive terminal Vp and the negative terminal Vn, and determine the start timing and timing of this data transmission according to the combination of the signal states of the positive terminal Vp and the negative terminal Vn. Timing of the end.
  • the signal transmitted by the differential signal line 13 received by the receiving terminal 121 may be a differential signal in the traditional sense, that is, at this time, the phase of the signal transmitted on the positive terminal Vp and the negative terminal Vn has a phase difference of 180°. .
  • the receiving end 121 determines the start time and end time of this data transmission according to the received signal state combination.
  • the receiving terminal 121 may determine that this data transmission will start after a preset period of time.
  • the signal state combination is 01, the receiving end 121 determines that this data transmission is over.
  • the preset duration may be a value configured by the protocol, such as 200 ns.
  • the controlled chip 12 (or at least the receiving end 121 of the controlled chip 12) is initially in a sleep state (also called a sleep state), and the main control chip 11 needs Data is transmitted to the controlled chip 12.
  • the sending end 111 of the main control chip 11 pulls the signal states of both the positive terminal Vp and the negative terminal Vn of the differential signal line 13 from a low level to a high level.
  • the positive terminal state detection unit 122 and the negative terminal state detection unit 123 on the side of the controlled chip 12 respectively detect that the single-ended signals of the positive terminal Vp and the negative terminal Vn both change from 0 to 1, and then determine that the receiving terminal 121 needs to be awakened.
  • the positive end state detection unit 122 and the negative end state detection unit 123 respectively transmit the detection results to the control unit 126.
  • the control unit 126 wakes up the receiving terminal 121. Specifically, only a partial module in the receiving end 121 may be awakened, such as a module in the receiving end 121 that has a long startup time and a relatively slow response.
  • the positive terminal state detection unit 122 and the negative terminal state detection unit 123 enter a non-working state to save power consumption. After that, the receiving terminal 121 continues to receive the signal transmitted on the differential signal line 13.
  • the main control chip 11 can pull the signal state of the negative terminal Vn from high level to low level.
  • the receiving terminal 121 detects that the signal state combination of the positive terminal Vp and the negative terminal Vn is 10, and determines that the DiFP signal is received.
  • the DiFP signal is used to indicate the start of data transmission after a preset period of time since the signal is received.
  • the receiving end 121 In response to receiving the DiFP signal, the receiving end 121 self-checks and prepares for receiving, and wakes up all internal modules.
  • the main control chip 11 performs normal data transmission to the controlled chip 12 through the differential signal line 13.
  • the transmitting terminal 111 of the main control chip 11 switches the signal state of the positive terminal Vp to 0 and the signal state of the negative terminal Vn to 1.
  • the receiving terminal 121 detects that the signal state combination of the positive terminal Vp and the negative terminal Vn is 01, and determines that the DiFN signal is received. Among them, the DiFN signal is used to indicate that this data transmission has been sent.
  • the receiving end 121 determines that this data transmission has been completed, and wakes up the positive end state detection unit 122 and the negative end state detection unit 123.
  • the main control chip 11 switches the signal state of the negative terminal Vn from a high level to a low level.
  • the single-ended signals of the positive terminal Vp and the negative terminal Vn respectively detected by the positive terminal state detection unit 122 and the negative terminal state detection unit 123 are both 0, and it is determined that the sleep receiving terminal 121 is required.
  • the positive end state detection unit 122 and the negative end state detection unit 123 respectively transmit the detection results to the control unit 126.
  • control unit 126 In response to the received signal state of the positive terminal Vp and the signal state of the negative terminal Vn both being 0, the control unit 126 sleeps the receiving terminal 121.
  • the positive end state detecting unit 122 and the negative end state detecting unit 123 are kept in working state, and the next wake-up signal of the transmitting end 111 is discovered in time.
  • This application scenario can realize the fusion of wake/sleep mechanism and burst mode.
  • the transmission terminal 111 and the receiving terminal 121 may transmit a high-speed signal through the differential signal line 13; and in the wake/sleep state switching stage, the transmitting terminal 111 transmits to the positive terminal state detection
  • the signals of the unit 122 and the negative terminal state detection unit 123 may be low-speed signals.
  • the signal swing amplitude of the signal transmitted by the positive terminal Vp and the negative terminal Vn used to wake up or sleep the receiving terminal 121 is larger than the positive terminal Vp and the negative terminal Vn during data transmission.
  • the swing amplitude of the transmitted signal is larger than the positive terminal Vp and the negative terminal Vn during data transmission.
  • the first comparator 124 and the second comparator 125 only need to compare the voltage value of the single-ended signal to distinguish different signal states.
  • the main control chip 11 may include: a first control switch (not shown) for switching the signal state of the positive terminal Vp and/or the signal state of the negative terminal Vn.
  • the first control switch can switch the signal state of the positive terminal Vp and the negative terminal Vn at the same time.
  • the number of the first control switches may be two and used to switch the signal state of the positive terminal Vp and the negative terminal Vn respectively.
  • the controlled chip 12 may include a second control switch (not shown) for switching the signal state of the positive terminal Vp and/or the negative terminal Vn during reverse transmission.
  • the reverse transmission refers to the data transmission from the controlled chip 12 to the main control chip 11.
  • the single-ended signal state switching of the positive terminal Vp/or the negative terminal Vn is realized through the second control switch.
  • the communication device 1 may include: a reverse positive terminal state detection unit (not shown), coupled to the positive terminal Vp to detect a single-ended signal during the reverse transmission of the positive terminal Vp; and a reverse negative terminal
  • the state detection unit (not shown in the figure) is coupled to the negative terminal Vn to detect a single-ended signal when the negative terminal Vn is transmitted in the reverse direction.
  • a reverse positive terminal state detection unit please refer to the aforementioned description about the positive end state detection unit 122, and for the specific structure of the reverse negative end state detection unit, refer to the foregoing description of the negative end state detection unit. Description of unit 123.
  • the sending end 111 is respectively coupled to the reverse positive end state detection unit and the reverse negative end state detection unit to obtain a reverse signal state combination, wherein the reverse signal state combination is the positive
  • the reverse signal state combination is the positive
  • the reverse signal state combination includes: 00, 01, 10, and 11. That is, the double-ended low level, the positive end low level, the negative end high level, the positive end high level, the negative end low level, and the double-ended high level.
  • the positive terminal state detection unit 122 may monitor the signal state of the positive terminal Vp, and/or the negative terminal state detection unit 123 may monitor the signal state of the negative terminal Vn State to determine whether there is a state conflict on the differential signal line 13.
  • the first comparator 124 and/or the second comparator 125 of the receiving end 121 finds that the signal state of the positive terminal Vp or the signal state of the negative terminal Vn is not changed according to its own requirements on the differential signal line 13 Pull it up, or when it is found that the differential signal line 13 fails to pull the online state down as required by the receiving end 121, it can be determined that there is a conflict in the online state. In this way, reverse transmission collision detection can be realized.
  • the communication device 1 may further include: a shared storage module 14.
  • the application processor ie, the main control chip 11
  • the modem ie, the controlled chip 12
  • the communication device 1 may further include: a shared storage module 14.
  • the application processor executes the aforementioned wake-up mechanism (such as sending a double-ended high control word) to wake up the modem, and the awakened modem accesses the shared memory module 14 through the application processor to read/write data.
  • the read/write data is transmitted at a high speed between the application processor and the modem through the differential signal line 13.
  • the application processor executes the aforementioned sleep mechanism (such as sending a double-ended low control word) to make the modem enter the sleep state.
  • the aforementioned sleep mechanism such as sending a double-ended low control word
  • the main control chip 11 and the controlled chip 12 in the communication device 1 adopting the scheme of this embodiment can wake up or sleep the peer without sideband signals or additional low-power circuits, which is beneficial to reduce the cost and size of the device. And it is simple to implement and can transmit more information by switching the signal state.
  • logic high level ie, high level
  • logic low level ie, low level
  • logic high level refers to the level range that can be recognized as a digital signal "1”
  • logic low level refers to the level range that can be recognized as a digital signal "0”
  • specific level The scope is not specifically limited.

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Abstract

一种通信装置（1），包括：主控芯片（11），包括发送端（111）；被控芯片（12），包括接收端（121），发送端（111）与接收端（121）之间通过差分信号线（13）相耦接，差分信号线（13）包括正端和负端；正端状态检测单元（122），耦接正端以检测正端的单端信号；负端状态检测单元（123），耦接负端以检测负端的单端信号；控制单元（126），分别与正端状态检测单元（122）、负端状态检测单元（123）和接收端（121）耦接，控制单元（126）根据检测到的信号状态组合唤醒或睡眠接收端（121），其中，信号状态组合为正端的单端信号和负端的单端信号的信号状态组合。由于主控芯片（11）和被控芯片（12）之间无需边带信号或额外的低功耗电路即能唤醒或睡眠对端，利于降低器件成本和减小尺寸，且实现简单并能够通过信号状态的切换传递更多信息。

Description

一种通信装置
本申请要求2020年5月22日提交中国专利局、申请号为2020104411855、发明名称为“一种通信装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及通信技术领域，具体地涉及一种通信装置。
背景技术
为满足用户的多样化需求，手机等通信装置除了实现通话功能外，还逐渐扩展出摄像、游戏等多样化功能。这些应用可以是基于独立的系统来控制和实现的。
因此，对于能够实现多种应用的通信装置，通常至少具有两个集成电路芯片，其中一个芯片为调制解调器(modem)，用于实现蜂窝通信功能，可以理解为通信系统；其中另一个芯片为应用处理器(Application Processor，简称AP)，用于实现诸如拍摄、显示、2D/3D引擎等功能，可以理解为应用处理系统。
通常，应用处理器作为主控芯片(Master IC)控制被控芯片(Slave IC)调制解调器，两者之间采用串行总线耦接以进行数据传输。例如，现有技术通常采用差分信号线连接应用处理器和调制解调器，以实现高效数据交互。
但是，目前现有协议中，例如移动产业处理器接口(Mobile Industry Processor Interface，简称MIPI)的低功耗(Low Power，简称LP)模式(LP mode)都是通过区别于高速(High Speed，简称HS)信号的摆动幅度的高电压作为控制字传输来唤醒或睡眠对端接收端的。这需要在通信装置中额外设置LP电路或通过边带(side band)信号实现。
发明内容
本发明解决的技术问题是提供一种改进的通信装置，使得主控芯片和被控芯片之间无需边带信号或额外的低功耗电路既能唤醒或睡眠对端。
为解决上述技术问题，本发明实施例提供一种通信装置，包括：主控芯片，所述主控芯片包括发送端；被控芯片，所述被控芯片包括接收端，所述发送端与接收端之间通过差分信号线相耦接，所述差分信号线包括正端和负端；正端状态检测单元，耦接所述正端以检测所述正端的单端信号；负端状态检测单元，耦接所述负端以检测所述负端的单端信号；控制单元，分别与所述正端状态检测单元、负端状态检测单元和接收端耦接，所述控制单元根据检测到的信号状态组合唤醒或睡眠所述接收端，其中，所述信号状态组合为所述正端的单端信号和负端的单端信号的信号状态组合。
可选的，用于唤醒或睡眠所述接收端的所述信号状态组合中，所述正端的单端信号与负端的单端信号的信号状态相同。
可选的，所述控制单元根据检测到的信号状态组合唤醒或睡眠所述接收端包括：当所述信号状态组合为11时，所述控制单元唤醒所述接收端，当所述信号状态组合为00时，所述控制单元睡眠所述接收端；或者，当所述信号状态组合为00时，所述控制单元唤醒所述接收端，当所述信号状态组合为11时，所述控制单元睡眠所述接收端。
可选的，在所述接收端被唤醒后，所述正端状态检测单元和负端状态检测单元进入非工作状态。
可选的，在所述接收端被睡眠后，所述正端状态检测单元和负端状态检测单元保持在工作状态。
可选的，所述接收端分别接收所述正端和负端的信号，并根据所述正端和负端的信号状态组合确定本次数据传输的开始时机和结束 时机。
可选的，所述接收端根据所述正端和负端的信号状态组合确定本次数据传输的开始时机和结束时机包括：当所述正端和负端的信号状态组合为10时，所述接收端确定本次数据传输将在预设时长后开始，当所述正端和负端的信号状态组合为01时，所述接收端确定本次数据传输结束。
可选的，用于唤醒或睡眠所述接收端的所述正端和负端传输的信号的摆动幅度，大于数据传输时所述正端和负端传输的信号的摆动幅度。
可选的，所述正端状态检测单元包括第一比较器，所述第一比较器用于检测所述正端的单端信号为1还是0；所述负端状态检测单元包括第二比较器，所述第二比较器用于检测所述负端的单端信号为1还是0。
可选的，所述主控芯片还包括：第一控制开关，用于切换所述正端的信号状态和/或所述负端的信号状态。
可选的，所述被控芯片包括第二控制开关，用于切换所述正端和/或负端反向传输时的信号状态；所述通信装置包括：反向正端状态检测单元，耦接所述正端以检测所述正端反向传输时的单端信号；反向负端状态检测单元，耦接所述负端以检测所述负端反向传输时的单端信号；所述发送端分别与所述反向正端状态检测单元和反向负端状态检测单元耦接，以获取反向信号状态组合，其中，所述反向信号状态组合为所述正端反向传输时的单端信号和负端反向传输时的单端信号的信号状态组合。
可选的，反向传输期间，所述正端状态检测单元监控所述正端的信号状态，和/或所述负端状态检测单元监控所述负端的信号状态，以确定所述差分信号线上是否存在状态冲突。
可选的，所述主控芯片为应用处理器，所述被控芯片为调制解调 器。
可选的，所述通信装置还包括：共享存储模块，所述应用处理器与所述共享存储模块耦接并可直接访问所述共享存储模块，所述调制解调器与所述应用处理器通过所述差分信号线耦接并通过所述应用处理器间接访问所述共享存储器。
与现有技术相比，本发明实施例的技术方案具有以下有益效果：
本发明实施例提供一种通信装置，包括：主控芯片，所述主控芯片包括发送端；被控芯片，所述被控芯片包括接收端，所述发送端与接收端之间通过差分信号线相耦接，所述差分信号线包括正端和负端；正端状态检测单元，耦接所述正端以检测所述正端的单端信号；负端状态检测单元，耦接所述负端以检测所述负端的单端信号；控制单元，分别与所述正端状态检测单元、负端状态检测单元和接收端耦接，所述控制单元根据检测到的信号状态组合唤醒或睡眠所述接收端，其中，所述信号状态组合为所述正端的单端信号和负端的单端信号的信号状态组合。
较之现有主从芯片之间的唤醒/睡眠机制，采用本实施例方案的通信装置中的主控芯片和被控芯片之间无需边带信号或额外的低功耗电路既能唤醒或睡眠对端，利于降低器件成本和减小尺寸，且实现简单并能够通过信号状态的切换传递更多信息。具体而言，利用差分单端电压幅度的去边作为状态切换的判断标志。进一步，本实施方案将收发两端都按单端控制，信号状态更多，能传递更多消息。
进一步，用于唤醒或睡眠所述接收端的所述信号状态组合中，所述正端的单端信号与负端的单端信号的信号状态相同。由此，在原本差分信号的基础上，增加双端高/双端低两种信号状态。也即，采用高速差分信号线的两个异常状态来传输控制字，实现对接收端的睡眠或唤醒控制。进一步，由于是利用差分驱动的异常状态实现的对端控制，通信装置内无需或仅需极少量的额外电路支持。进一步，通过异常状态的切换能够传递更多的信息。
附图说明
图1是本发明实施例第一种通信装置的原理示意图；
图2是本发明实施例所述通信装置通过差分信号线传输信号时的信号摆动示意图；
图3是本发明实施例第二种通信装置的原理示意图。
具体实施方式
如背景技术所言，现有的通信装置中需要额外设置LP电路或通过边带(side band)信号实现主从芯片之间的唤醒或睡眠控制。
为解决上述技术问题，本发明实施例提供一种通信装置，包括：主控芯片，所述主控芯片包括发送端；被控芯片，所述被控芯片包括接收端，所述发送端与接收端之间通过差分信号线相耦接，所述差分信号线包括正端和负端；正端状态检测单元，耦接所述正端以检测所述正端的单端信号；负端状态检测单元，耦接所述负端以检测所述负端的单端信号；控制单元，分别与所述正端状态检测单元、负端状态检测单元和接收端耦接，所述控制单元根据检测到的信号状态组合唤醒或睡眠所述接收端，其中，所述信号状态组合为所述正端的单端信号和负端的单端信号的信号状态组合。
采用本实施例方案的通信装置中的主控芯片和被控芯片之间无需边带信号或额外的低功耗电路既能唤醒或睡眠对端，利于降低器件成本和减小尺寸，且实现简单并能够通过信号状态的切换传递更多信息。具体而言，利用差分单端电压幅度的去边作为状态切换的判断标志。进一步，本实施方案将收发两端都按单端控制，信号状态更多，能传递更多消息。
为使本发明的上述目的、特征和有益效果能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明实施例第一种通信装置的原理示意图。
所述通信装置可以为手机等用户设备。
具体地，参考图1，本实施例所述的通信装置1可以包括：主控芯片11，所述主控芯片11可以包括发送端111。例如，主控芯片11可以为应用处理器。
进一步，通信装置1还可以包括被控芯片12，所述被控芯片12可以包括接收端121。例如，所述被控芯片12可以为调制解调器。
进一步，主控芯片11和被控芯片12之间可以通过串行总线耦接以通信。
在一个具体实施中，所述发送端111与接收端121之间通过差分信号线13相耦接，所述差分信号线13可以包括正端Vp和负端Vn。例如，发送端111可以为高速发送端，如D-bus发送端；接收端121可以为高速接收端，如D-bus接收端。
所述主控芯片11与所述被控芯片12之间通过所述差分信号线13相通信。例如，主控芯片11与被控芯片12之间通过所述差分信号线13传输高速差分信号，以实现数据传输。
在一个具体实施中，继续参考图1，所述通信装置1还可以包括：正端状态检测单元122，耦接所述正端Vp以检测所述正端Vp的单端信号。
例如，所述正端状态检测单元122可以包括第一比较器124，所述第一比较器124用于检测所述正端Vp的单端信号为1还是0。也即，检测所述正端Vp的单端信号为高电平还是低电平。本实施例以1表示高电平，0表示低电平
进一步，所述正端状态检测单元122可以设置于所述被控芯片12侧。
在一个具体实施中，继续参考图1，所述通信装置1还可以包括：负端状态检测单元123，耦接所述负端Vn以检测所述负端Vn的单 端信号。
例如，所述负端状态检测单元123可以包括第二比较器125，所述第二比较器125用于检测所述负端Vn的单端信号为1还是0。也即，检测所述负端Vn的单端信号为高电平还是低电平。
进一步，所述负端状态检测单元123可以设置于所述被控芯片12侧。
在一个具体实施中，继续参考图1，所述通信装置1还可以包括：控制单元126，分别与所述正端状态检测单元122、负端状态检测单元123和接收端121耦接，所述控制单元126可以根据检测到的信号状态组合唤醒或睡眠所述接收端121，其中，所述信号状态组合为所述正端Vp的单端信号和负端Vn的单端信号的信号状态组合。进一步而言，所述信号状态组合共有四种情况，也即，所述正端Vp的单端信号可以是高电平状态或低电平状态，所述负端Vn的单端信号可以是高电平状态或低电平状态，二者的组合共计四种情况。
由此，本实施例所述通信装置1利用差分单端电压幅度的去边作为状态切换的判断标志。具体而言，将收发两端(即发送端111和接收端121)都按单端控制，被控芯片12侧增设正端状态检测单元122和负端状态检测单元123以分别检测差分信号线13的正端Vp和负端Vn的单端信号状态。进一步，按单端控制的情形下，能够组合得到的信号状态更多，使得传递更多消息成为可能。
在一个具体实施中，控制单元126可以为实体模块，或者为软件层面的控制逻辑。
进一步，控制单元126与接收端121可以集成为一体，则正端状态检测单元122和负端状态检测单元123将检测结果直接发送至接收端121，以在信号状态组合为唤醒或睡眠控制字时直接唤醒或睡眠接收端121。或者，两者也可以为相分离的两个独立模块。
在一个具体实施中，用于唤醒或睡眠所述接收端121的所述信号 状态组合中，所述正端Vp的单端信号与负端Vn的单端信号的信号状态相同。
具体而言，由于此时差分信号线13的正端Vp和负端Vn是按照相独立的两个单端来控制的，使得在差分信号线13上传输的信号不再必须局限于差分信号。也即，正端Vp和负端Vn各自传输的信号不再必须是反相的。
由此，在原本差分信号的基础上，增加双端高/双端低两种信号状态，。也即，采用高速差分信号线13的两个异常状态来传输控制字，实现对接收端121的睡眠或唤醒控制。进一步，由于是利用差分驱动(driver)的异常状态实现的对端控制，通信装置1内无需或仅需极少量的额外电路支持。进一步，通过异常状态的切换能够传递更多的信息。
在一个具体实施中，当所述信号状态组合为11(即双端高电平，正端和负端都为高电平状态，简称双端高)时，所述控制单元126可以唤醒所述接收端121，而当所述信号状态组合为00(即双端低电平，正端和负端都为低电平状态，简称双端低)时，所述控制单元126可以睡眠所述接收端121。
在一个变化例中，当所述信号状态组合为00时，所述控制单元126唤醒所述接收端121，当所述信号状态组合为11时，所述控制单元126睡眠所述接收端121。
在一个具体实施中，所述接收端121可以分别接收所述正端Vp和负端Vn的信号，并根据所述正端Vp和负端Vn的信号状态组合确定本次数据传输的开始时机和结束时机。
具体而言，所述接收端121接收到的差分信号线13传输的信号可以是传统意义上的差分信号，即此时正端Vp和负端Vn上传输的信号的相位具有180°的相位差。接收端121根据接收到的信号状态组合确定本次数据传输的开始时机和结束时机。
例如，当所述正端Vp和负端Vn的信号状态组合为10时，所述接收端121可以确定本次数据传输将在预设时长后开始，当所述正端Vp和负端Vn的信号状态组合为01时，所述接收端121确定本次数据传输结束。
其中，预设时长可以是协议配置的数值，如200ns。
表1
正端Vp的信号状态 0 1 0 1
负端Vn的信号状态 0 0 1 1
接收端状态 睡眠 DiFP DiFN 唤醒
在一个典型的应用场景中，结合图1和表1，假设被控芯片12(或至少被控芯片12的接收端121)初始处于睡眠状态(也可称为休眠状态)，主控芯片11需要向被控芯片12传输数据。
首先，主控芯片11的发送端111将差分信号线13的正端Vp和负端Vn双端的信号状态均从低电平拉到高电平。
被控芯片12侧的正端状态检测单元122和负端状态检测单元123分别检测到正端Vp和负端Vn的单端信号均从0变为1，进而确定需要唤醒接收端121。正端状态检测单元122和负端状态检测单元123分别将检测结果传输至控制单元126。
响应于接收到的正端Vp的信号状态和负端Vn的信号状态的均为1，控制单元126唤醒接收端121。具体地，可以仅唤醒接收端121内的局部模块，如接收端121内启动时间较长、响应比较慢的模块。
进一步，接收端121被唤醒后，所述正端状态检测单元122和负端状态检测单元123进入非工作状态，以节省功耗。此后，由接收端121继续接收差分信号线13上传输的信号。
进一步，在发送双端高信号后，主控芯片11可以将负端Vn的信 号状态从高电平拉低到低电平。相应的，接收端121检测发现正端Vp和负端Vn的信号状态组合为10，确定接收到DiFP信号。其中，DiFP信号用于指示自接收到该信号起预设时长后开始进行数据传输。
响应于接收到DiFP信号，接收端121自检并做接收准备，唤醒内部所有模块。
进一步，在预设时长后，主控芯片11通过差分信号线13向被控芯片12进行正常数据传输。
数据传输完成后，主控芯片11的发送端111将正端Vp的信号状态切换为0、将负端Vn的信号状态切换为1。相应的，接收端121检测发现正端Vp和负端Vn的信号状态组合为01，确定接收到DiFN信号。其中，DiFN信号用于指示本次数据传输已经发送完毕。
响应于接收到DiFN信号，接收端121确定本次数据传输已经完成，并唤醒正端状态检测单元122和负端状态检测单元123。
进一步，主控芯片11将负端Vn的信号状态由高电平切换至低电平。相应的，正端状态检测单元122和负端状态检测单元123各自检测到的正端Vp和负端Vn的单端信号均为0，确定需要睡眠接收端121。正端状态检测单元122和负端状态检测单元123分别将检测结果传输至控制单元126。
响应于接收到的正端Vp的信号状态和负端Vn的信号状态的均为0，控制单元126睡眠接收端121。
进一步，在所述接收端121被睡眠后，所述正端状态检测单元122和负端状态检测单元123保持在工作状态，以及时发现发送端111的下一次唤醒信号。
本应用场景能够实现唤醒/睡眠机制与突发模式(burst mode)的融合。
在一个具体实施中，在数据传输阶段，发送端111和接收端121之间通过差分信号线13传输的可以是高速信号；而在唤醒/睡眠状态切换阶段，发送端111传输至正端状态检测单元122以及负端状态检测单元123的信号则可以为低速信号。
例如，参考图2，用于唤醒或睡眠所述接收端121的所述正端Vp和负端Vn传输的信号的摆动(Signal Swing)幅度，大于数据传输时所述正端Vp和负端Vn传输的信号的摆动幅度。
由此，第一比较器124和第二比较器125只需比较单端信号的电压值即可区分不同的信号状态。
在一个具体实施中，所述主控芯片11可以包括：第一控制开关(图未示)，用于切换所述正端Vp的信号状态和/或所述负端Vn的信号状态。
例如，所述第一控制开关可以同时切换正端Vp和负端Vn的信号状态。
又例如，所述第一控制开关的数量可以为两个并分别用于切换正端Vp和负端Vn的信号状态。
在一个具体实施中，所述被控芯片12可以包括第二控制开关(图未示)，用于切换所述正端Vp和/或负端Vn反向传输时的信号状态。其中，反向传输是指被控芯片12向主控芯片11进行的数据传输。此时，与第一控制开关类似，通过第二控制开关实现正端Vp/或负端Vn的单端信号状态切换。
进一步，所述通信装置1可以包括：反向正端状态检测单元(图未示)，耦接所述正端Vp以检测所述正端Vp反向传输时的单端信号；反向负端状态检测单元(图未示)，耦接所述负端Vn以检测所述负端Vn反向传输时的单端信号。其中，关于所述反向正端状态检测单元的具体结构可以参考前述关于正端状态检测单元122的相关描述，关于所述反向负端状态检测单元的具体结构可以参考前述关于负端 状态检测单元123的相关描述。
进一步，所述发送端111分别与所述反向正端状态检测单元和反向负端状态检测单元耦接，以获取反向信号状态组合，其中，所述反向信号状态组合为所述正端Vp反向传输时的单端信号和负端Vn反向传输时的单端信号的信号状态组合。
进一步，不同的反向信号状态组合可以用于传递不同的消息。
例如，所述反向信号状态组合包括：00、01、10和11。也即，双端低电平、正端低电平负端高电平、正端高电平负端低电平以及双端高电平。
由此，通过在接收端121增加简易的开关(switcher)，在发送端111增加比较器，可以实现反向信号交互。
在一个具体实施中，反向传输期间，所述正端状态检测单元122可以监控所述正端Vp的信号状态，和/或所述负端状态检测单元123可以监控所述负端Vn的信号状态，以确定所述差分信号线13上是否存在状态冲突。
例如，反向传输的时候，接收端121的第一比较器124和/或第二比较器125发现差分信号线13上没有根据自己的要求把正端Vp的信号状态或者负端Vn的信号状态拉起来，或者，发现差分信号线13未能按接收端121要求把线上状态拉低的时候，可以确定线上状态有冲突。由此，可以实现反向传输冲突检测。
在一个具体实施中，参考图3，所述通信装置1还可以包括：共享存储模块14，所述应用处理器(即主控芯片11)与所述共享存储模块14耦接并可直接访问所述共享存储模块14，所述调制解调器(即被控芯片12)与所述应用处理器通过所述差分信号线13耦接并通过所述应用处理器间接访问所述共享存储器14。
例如，应用处理器执行前述唤醒机制(如发送双端高控制字)唤醒调制解调器，被唤醒的调制解调器通过应用处理器访问共享存储模 块14以读/写数据。读/写的数据通过差分信号线13在应用处理器和调制解调器之间高速传输。
数据读/写完毕后，应用处理器执行前述睡眠机制(如发送双端低控制字)使调制解调器进入睡眠状态。
采用本实施例方案的通信装置1中的主控芯片11和被控芯片12之间无需边带信号或额外的低功耗电路既能唤醒或睡眠对端，利于降低器件成本和减小尺寸，且实现简单并能够通过信号状态的切换传递更多信息。
本实施例所述“逻辑高电平”(即高电平)和“逻辑低电平”(即低电平)是相对的逻辑电平。“逻辑高电平”指的是可被识别为数字信号“1”的电平范围，“逻辑低电平”指的是可被识别为数字信号“0”的电平范围，其具体电平范围并不做具体限制。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (14)

  1. 一种通信装置，其特征在于，包括：
    主控芯片，所述主控芯片包括发送端；
    被控芯片，所述被控芯片包括接收端，所述发送端与接收端之间通过差分信号线相耦接，所述差分信号线包括正端和负端；
    正端状态检测单元，耦接所述正端以检测所述正端的单端信号；
    负端状态检测单元，耦接所述负端以检测所述负端的单端信号；
    控制单元，分别与所述正端状态检测单元、负端状态检测单元和接收端耦接，所述控制单元根据检测到的信号状态组合唤醒或睡眠所述接收端，其中，所述信号状态组合为所述正端的单端信号和负端的单端信号的信号状态组合。
  2. 根据权利要求1所述的通信装置，其特征在于，用于唤醒或睡眠所述接收端的所述信号状态组合中，所述正端的单端信号与负端的单端信号的信号状态相同。
  3. 根据权利要求1或2所述的通信装置，其特征在于，所述控制单元根据检测到的信号状态组合唤醒或睡眠所述接收端包括：
    当所述信号状态组合为11时，所述控制单元唤醒所述接收端，当所述信号状态组合为00时，所述控制单元睡眠所述接收端；或者，
    当所述信号状态组合为00时，所述控制单元唤醒所述接收端，当所述信号状态组合为11时，所述控制单元睡眠所述接收端。
  4. 根据权利要求1所述的通信装置，其特征在于，在所述接收端被唤醒后，所述正端状态检测单元和负端状态检测单元进入非工作状态。
  5. 根据权利要求4所述的通信装置，其特征在于，在所述接收端被睡眠后，所述正端状态检测单元和负端状态检测单元保持在工作 状态。
  6. 根据权利要求1或4所述的通信装置，其特征在于，所述接收端分别接收所述正端和负端的信号，并根据所述正端和负端的信号状态组合确定本次数据传输的开始时机和结束时机。
  7. 根据权利要求6所述的通信装置，其特征在于，所述接收端根据所述正端和负端的信号状态组合确定本次数据传输的开始时机和结束时机包括：
    当所述正端和负端的信号状态组合为10时，所述接收端确定本次数据传输将在预设时长后开始，当所述正端和负端的信号状态组合为01时，所述接收端确定本次数据传输结束。
  8. 根据权利要求1所述的通信装置，其特征在于，用于唤醒或睡眠所述接收端的所述正端和负端传输的信号的摆动幅度，大于数据传输时所述正端和负端传输的信号的摆动幅度。
  9. 根据权利要求1所述的通信装置，其特征在于，所述正端状态检测单元包括第一比较器，所述第一比较器用于检测所述正端的单端信号为1还是0；所述负端状态检测单元包括第二比较器，所述第二比较器用于检测所述负端的单端信号为1还是0。
  10. 根据权利要求1所述的通信装置，其特征在于，所述主控芯片还包括：
    第一控制开关，用于切换所述正端的信号状态和/或所述负端的信号状态。
  11. 根据权利要求1所述的通信装置，其特征在于，所述被控芯片包括第二控制开关，用于切换所述正端和/或负端反向传输时的信号状态；
    所述通信装置包括：反向正端状态检测单元，耦接所述正端以检测所述正端反向传输时的单端信号；反向负端状态检测单元，耦 接所述负端以检测所述负端反向传输时的单端信号；
    所述发送端分别与所述反向正端状态检测单元和反向负端状态检测单元耦接，以获取反向信号状态组合，其中，所述反向信号状态组合为所述正端反向传输时的单端信号和负端反向传输时的单端信号的信号状态组合。
  12. 根据权利要求11所述的通信装置，其特征在于，反向传输期间，所述正端状态检测单元监控所述正端的信号状态，和/或所述负端状态检测单元监控所述负端的信号状态，以确定所述差分信号线上是否存在状态冲突。
  13. 根据权利要求1所述的通信装置，其特征在于，所述主控芯片为应用处理器，所述被控芯片为调制解调器。
  14. 根据权利要求13所述的通信装置，其特征在于，还包括：
    共享存储模块，所述应用处理器与所述共享存储模块耦接并可直接访问所述共享存储模块，所述调制解调器与所述应用处理器通过所述差分信号线耦接并通过所述应用处理器间接访问所述共享存储器。
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