WO2013189292A1 - 基于芯片间高速接口hsic的唤醒、热插拔方法和设备 - Google Patents

基于芯片间高速接口hsic的唤醒、热插拔方法和设备 Download PDF

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Publication number
WO2013189292A1
WO2013189292A1 PCT/CN2013/077539 CN2013077539W WO2013189292A1 WO 2013189292 A1 WO2013189292 A1 WO 2013189292A1 CN 2013077539 W CN2013077539 W CN 2013077539W WO 2013189292 A1 WO2013189292 A1 WO 2013189292A1
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Prior art keywords
host
hsic
external device
state
bus
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Application number
PCT/CN2013/077539
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English (en)
French (fr)
Inventor
桂永林
赵阳
朱光泽
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华为终端有限公司
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Publication of WO2013189292A1 publication Critical patent/WO2013189292A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3253—Power saving in bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate

Definitions

  • the present invention relates to information technology, and in particular, to a wake-up, hot-plug method and device based on an inter-chip high-speed interface HSIC.
  • High Speed Inter-Chip uses Inter-Chip Connectivity (ICC) technology to enable USB 2.0 protocol transmission over short distances, as well as software that is analogous to USB 2.0 connectivity. compatibility.
  • ICC Inter-Chip Connectivity
  • the host chip and the peripheral chip of the HSIC interface are soldered in the same single board, and the two chips are simultaneously powered on and simultaneously powered down, so that the power consumption of the device is large.
  • Embodiments of the present invention provide a wake-up, hot-plug method and device based on an inter-chip high-speed interface HSIC, which saves equipment power.
  • an embodiment of the present invention provides a wake-up method based on an inter-chip high-speed interface HSIC, including:
  • the host obtains an external device connected to the host through the inter-chip high-speed interface HSIC bus in an idle state;
  • the host is in a sleep state
  • the host receives an interrupt signal sent by the external device from a signal line connected to the external device;
  • An embodiment of the present invention further provides a wake-up method based on an inter-chip high-speed interface HSIC, including: receiving an operation instruction of a user from an external device connected to a host through an inter-chip high-speed interface HSIC bus;
  • the external device sends an interrupt signal to the host through a signal line connected to the host to wake the host from a sleep state.
  • an embodiment of the present invention further provides a hot plugging method based on an inter-chip high-speed interface HSIC, including:
  • the host obtains an idle state connected to the host through the inter-chip high-speed interface HSIC bus, or the host needs to control the external device to be powered off according to the needs of the service; the host controls the external device to be powered off;
  • the host controls the HSIC bus to enter an initial state to wait for the external device to be powered on; the host controls the external device to be powered on.
  • an embodiment of the present invention provides a host, including:
  • the inter-chip high-speed interface HSIC interface is connected to the external device through the HSIC bus;
  • the level change interface is connected to the external device through the signal line, and is used for receiving an interrupt signal sent by the external device;
  • a processor configured to obtain that the external device is in an idle state, the host is in a sleep state, and the level change interface receives an interrupt signal sent by the external device from the signal line, according to the interrupt signal Controlling the host to wake up from a sleep state.
  • An embodiment of the present invention provides an external device, including:
  • Inter-chip high-speed interface HSIC interface connected to the host through the HSIC bus;
  • a level change interface connected to the host through a signal line, generating an interrupt signal under the control of the processor, and transmitting the interrupt signal to the external device through the signal line;
  • a processor configured to receive an operation instruction of the user, and control the level change interface to generate the interrupt signal.
  • an embodiment of the present invention further provides a host, including: The inter-chip high-speed interface HSIC interface is connected to the external device through the HSIC bus; the processor is configured to control the external device to be powered off when the external device is in an idle state, or when the external device is powered off according to the needs of the service; Controlling the HSIC bus to enter an initial state to wait for the external device to be powered on; controlling the external device to power on.
  • An embodiment of the present invention provides a terminal, including: a host and an external device, where the host and the external device include an inter-chip high-speed HSIC interface, and an HSIC interface of the host and an HSIC interface of the external device are connected through an HSIC bus.
  • the host and the external device include an interface capable of generating a level change, and the level change interface of the host is connected to a level change interface of the external device through a signal line.
  • the method and device for waking up based on the inter-chip high-speed interface HSIC provided by the embodiment of the present invention, when the host obtains an idle state connected to the host through the HSIC bus, the host receives the signal line connected to the external device in the sleep state. After the interrupt signal sent by the external device, the sleep signal can be awakened according to the interrupt signal, so that the host and the external device wake up based on the HSIC bus to save power of the device.
  • the method and device for hot plugging based on the inter-chip high-speed interface HSIC provided by the embodiment of the present invention can control when the external device connected to the host through the HSIC bus is in an idle state or the host needs to control the external device to be powered off according to service requirements.
  • the external device is powered off, thereby enabling hot plugging of the external device and saving power of the device.
  • 1 is a flow chart of an embodiment of an on-chip high-speed interface HSIC-based wake-up method according to the present invention
  • 2 is a flowchart of still another embodiment of a wake-up method based on an inter-chip high-speed interface HSIC according to the present invention
  • FIG. 3 is a flow chart of still another embodiment of a wake-up method based on an inter-chip high-speed interface HSIC according to the present invention.
  • FIG. 4 is a flow chart of an embodiment of a hot plugging method based on an interchip high speed interface HSIC according to the present invention
  • FIG. 5 is a flowchart of still another embodiment of a hot plugging method based on an interchip high speed interface HSIC according to the present invention.
  • FIG. 6 is a schematic structural diagram of an embodiment of a host provided by the present invention.
  • FIG. 7 is a schematic structural diagram of an embodiment of an external device according to the present invention.
  • FIG. 8 is a schematic structural diagram of another embodiment of a host provided by the present invention.
  • FIG. 9 is a schematic structural diagram of an embodiment of a wireless terminal according to the present invention.
  • the host involved in the embodiment of the present invention may be a central processing unit (CPU) on various terminals such as a personal computer, a mobile phone, a PAD, a routerless router, or a Universal Serial Bus (USB) modem.
  • the external device can be a peripheral chip such as a Wireless Fidelity (WiFi) chip module, a Bluetooth module, or a camera module.
  • WiFi Wireless Fidelity
  • FIG. 1 is an embodiment of a wake-up method based on an inter-chip high-speed interface HSIC provided by the present invention
  • the flow chart, as shown in Figure 1, includes:
  • the host obtains an external device connected to the host through a high speed Inter-Chip (HSIC) bus.
  • HSIC High Speed Inter-Chip
  • the host is in a sleep state.
  • the host receives an interrupt signal sent by the external device from a signal line connected to the external device.
  • the host wakes up from the sleep state according to the interrupt signal.
  • the host and the external device involved in this embodiment may include a High Speed Inter-Chip (HSIC) interface, and the HSIC interface of the host and the HSIC interface of the external device are connected through the HSIC bus, wherein the host and the external device may further include A flat-changing interface (such as a General Purpose Input Output (GPIO) interface or an interrupt interface), the level-changing interface of the host and the level-changing interface of the external device can be connected by a signal line, which can be connected by a host
  • the signal line consists of two-way communication between external devices, and can also be composed of a signal line from the host to the external device and a signal line from the peripheral to the host.
  • the signal line can be a General Purpose Input Output (GPIO) signal line or other signal line that can produce a level change.
  • GPIO General Purpose Input Output
  • the situation in which the external device is in an idle state may be: a scenario in which the external device is not used by the user, waiting for the user, or a scenario in which the usage rate of the external device is lower than a certain threshold.
  • the host can detect that the external device is in the idle state, or the external device is in the idle state.
  • the host After the host obtains that the external device is idle, the host can suspend the HSIC bus.
  • the host can have multiple sleep states. For example, in one implementation scenario, the host can be powered off, all software is not running, and the memory is in a self-refresh state. In another implementation scenario, the host can In a slow clock state. In the embodiment of the present invention, how the host is in a dormant state is not limited. After the external device is in the idle state, it can enter the sleep state. As a feasible implementation manner, after obtaining the idle state of the external device, the host can control the external device to enter the sleep state. For example, the host can control the external device to enter the sleep state through a software command, and can also adopt various existing methods.
  • the external device can enter a sleep state after detecting that the HSIC bus is suspended.
  • the external device may have multiple sleep states.
  • the external device may be in a low power consumption state. In this state, the external device is in a power saving mode, but may respond to user operations.
  • wifi chip such an external device can reduce power in a sleep state, the signaling frame is elongated, and can respond to user access.
  • the external device can send an interrupt signal to the host through a signal line connected to the host.
  • the interrupt signal can be a high level signal or a low level signal.
  • the host After receiving the interrupt signal sent by the external device, the host can wake up from the sleep state. After the host wakes up, it can be in the normal working mode.
  • the HSIC bus can be resumed from the suspend state to the normal working state, so that the HSIC bus can resume data transmission.
  • the HSIC bus resumes data transmission, and the external device can wake up from the sleep state.
  • the resume protocol in the HSIC protocol can be used to enable the external device to wake up from the sleep state.
  • the host can also save the current state of the HSIC controller and then enter the sleep state.
  • the HSIC controller can be restored according to the state of the saved HSIC, and then the suspended HSIC bus is restored to the normal working state.
  • the host can save the current state of the HSIC controller, control the HSIC bus to be powered off, and then the host enters the sleep state.
  • the host wakes up according to the interrupt signal sent by the external device, it can first control the HSIC bus to power up, and then restore the HSIC controller according to the state of the saved HSIC controller. State, then resume the suspended HSIC bus to normal operation.
  • the external device can enter the normal working state from the sleep state.
  • the host when the host obtains an idle state connected to the host through the HSIC bus, the host receives the external device from the signal line connected to the external device in the sleep state. After the interrupt signal, the sleep signal can be awakened according to the interrupt signal, so that the host and the external device wake up based on the HSIC bus to save power of the device.
  • FIG. 2 is a flowchart of still another embodiment of a wake-up method based on an inter-chip high-speed interface HSIC according to the present invention. As shown in FIG. 2, the method includes:
  • the external device connected to the host through the inter-chip high-speed interface HSIC bus receives an operation instruction of the user;
  • the external device sends an interrupt signal to the host through a signal line connected to the host, so that the host wakes up from the sleep state.
  • the external device After receiving the user's operation command, the external device can send an interrupt signal to the host through the signal line connected to the host, thereby enabling the host to sleep in the sleep state based on the HSIC bus.
  • the external device when the external device receives the operation instruction of the user, it may refer to an implementation scenario in which the external device is in a sleep state, or may refer to an implementation scenario in which the external device is in a normal working state, that is, the present invention is in the external device. There is no restriction on when to send an interrupt signal to the host.
  • the external device when the external device is in an idle state, for example, the external device is not used by the user, the user is waiting for the scenario, or the usage of the external device is lower than a certain threshold.
  • the external device can enter the sleep state under the control of the host; or, the external device can enter the sleep state after detecting that the HSIC bus connected to the host is suspended.
  • the host can restore the HSIC bus from the suspended state to the normal working state.
  • External device After the HSIC bus resumes from the suspended state to the normal operating state, it can wake up from the sleep state.
  • the wake-up method based on the inter-chip high-speed interface HSIC provided by the embodiment is connected to the host through the high-speed interface HSIC bus between the chips.
  • the interrupt signal can be sent to the host through the signal line connected to the host, so that The host wakes up from the sleep state, so that the host and the external device wake up based on the HSIC bus, thereby saving power of the external device.
  • FIG. 3 is a flowchart of still another embodiment of an on-chip high-speed interface HSIC-based wake-up method according to the present invention. As shown in FIG. 3, this embodiment provides an implementation scenario in which a host and a peripheral are based on HSIC bus sleep and wake-up. Includes:
  • the host obtains an external device connected to the host through the inter-chip high-speed interface HSIC bus.
  • the host suspends the HSIC bus to stop the HSIC bus from transmitting data.
  • the host saves the current state of the HSIC controller.
  • the HSIC controller usually performs operations such as HSIC protocol processing, and the host saves the current state of the HSIC controller, so that the current state can be restored after the HSIC bus is powered on.
  • the host enters a sleep state.
  • the external device detects that the HSIC bus is suspended.
  • the external device enters the sleep state.
  • an access point (AP) module of an external device WiFi module can enter a standby sleep state to wait for user access, thereby saving power consumption of the WiFi module.
  • the external device receives an operation instruction of the user.
  • the external device sends an interrupt signal to the host through the signal line.
  • the host After the host enters the standby sleep state, it can respond to the interrupt signal generated by the level change on the signal line between the external device and the host.
  • the external device can send an interrupt signal to the host through the signal line to wake up the host. 5310. The host wakes up from sleep.
  • the host restores the state of the HSIC controller according to the state of the saved HSIC controller.
  • the host restores the HSIC bus from the suspended state to the normal working state, so that the HSIC bus resumes data transmission, and the external device wakes up from the sleep state.
  • S304 and S311 in the above steps may be optional steps.
  • the host can suspend the HSIC bus and enter a sleep state.
  • the external device can also enter the sleep state after detecting that the HSIC bus is suspended.
  • the external device can wake up the host by sending a terminal signal to the host through a signal line connected with the host, thereby implementing sleep and wake-up of the external device and the host based on the HSIC bus, thereby realizing saving equipment. Consumption.
  • FIG. 4 is a flowchart of an embodiment of a hot plugging method based on an inter-chip high-speed interface HSIC according to the present invention. As shown in FIG. 4, the method includes:
  • the host obtains an external device connected to the host through the inter-chip high-speed interface HSIC bus, or the host needs to control the external device to be powered off according to the needs of the service.
  • the host controls the external device to be powered off.
  • HSIC bus enters an initial state to wait for the external device to be powered on.
  • the host controls the external device to be powered on.
  • the host and the external device involved in this embodiment can be connected through the HSIC bus.
  • the situation in which the external device is in an idle state may be: a scenario in which the external device is not used by the user, waiting for the user, or a scenario in which the usage rate of the external device is lower than a certain threshold.
  • the host can obtain the information that the external device is in the idle state through the direct detection. When the external device is in the idle state, the host can also report the message indicating the idle state to the host.
  • the external device may have an independent power supply module, or the external device may have an independent power supply line.
  • the host obtains that the external device is idle, or the host is operating according to the industry.
  • the service needs to control the external device to be powered off. For example, when the host communicates with the external device and learns that the external device is abnormal, the host can control the external device to be powered off. For example, the host can control the power supply module of the external device to stop supplying power to the external device, or the host can disconnect the power supply line of the external device to power off the external device.
  • the host can control the HSIC bus to enter the initial state to wait for the external device to power on.
  • the HSIC bus entering the initial state can recognize the external device when the external device is powered on next time, thereby ensuring normal communication between the host and the external device.
  • the host controls the HSIC bus to enter an initial state specifically, the HSIC controller is re-initialized to implement the HSIC bus to enter an initial state.
  • the host can also save the current state of the HSIC controller and then enter a sleep state to reduce the power consumption of the host.
  • the state of the HSIC register can be restored according to the state of the saved HSIC register, and then the external device is powered on.
  • the host can save the current state of the HSIC controller and control the HSIC bus to be powered off. After that, the host can go to sleep to reduce the power consumption of the host.
  • the host after the host wakes up, it can control the HSIC bus to power up, restore the HSIC register status according to the state of the saved HSIC register, and then control the external device to power on.
  • the hot plugging method based on the inter-chip high-speed interface HSIC provided by the embodiment can control the external device when the external device connected to the host through the HSIC bus is in an idle state or the host needs to control the external device to be powered off according to service requirements. Electricity, so as to achieve hot swapping of external devices, saving equipment power.
  • FIG. 5 is a flowchart of still another embodiment of a hot plugging method based on an inter-chip high-speed interface HSIC according to the present invention. As shown in FIG. 5, this embodiment provides a hot swappable host and peripheral based on a HSIC bus. Implementation scenario, the method includes:
  • the host obtains an external device connected to the host through the high-speed interface HSIC bus between the chips. In an idle state, or when the host needs to control the external device to be powered off according to the needs of the service.
  • the host controls the external device to be powered off.
  • the host controls the HSIC bus to enter an initial state to wait for the external device to be powered on.
  • the host saves the current state of the HSIC controller.
  • the host controls the HSIC bus to be powered off.
  • the host enters a sleep state.
  • the host wakes up from the sleep state.
  • the host controls the HSIC bus to be powered on.
  • the host restores the HSIC register status according to the state of the saved HSIC register.
  • the host controls the external device to be powered on.
  • the host can power on by controlling the external device.
  • the HSIC bus can detect the connection of the external device and can enumerate the external device normally. Thereby implementing the hot plug function of the HSIC interface.
  • the host can be in an idle situation in the external device, or the host can control the external device to be powered off according to service requirements to save power.
  • the host can also control the HSIC bus to enter the initial state, so that after the external device is powered on, the HSIC bus can identify the external device, thereby implementing the HSIC interface to support hot swap and save the device power.
  • FIG. 6 is a schematic structural diagram of an embodiment of a host provided by the present invention. As shown in FIG. 6, the host includes: a HSIC interface 1 1 , a level change interface 12 , and a processor 13 ;
  • Inter-chip high-speed interface HSIC interface 1 1 connected to external devices through the HSIC bus;
  • Level change interface 12 connected to external devices through signal lines, used to receive interrupt signals sent by external devices;
  • the processor 13 is configured to obtain that the external device is in an idle state, and the host is in a sleep state, and the level change interface receives an interrupt signal sent by the external device from the signal line, and is controlled according to the interrupt signal. The host wakes up from the sleep state.
  • the processor 13 is further configured to: control the external device to enter a sleep state after obtaining the external device in an idle state.
  • the processor 13 may be further configured to: suspend the HSIC bus to stop the HSIC bus from transmitting data.
  • the processor 13 after the processor 13 suspends the HSIC bus, it can also be used to save the current state of the HSIC controller and control the HSIC bus to be powered off.
  • the processor 13 controls the host to wake up from the sleep state according to the interrupt signal, and can also be used to control the HSIC bus to power up, and restore the state of the HSIC controller according to the saved state of the HSIC controller.
  • the processor 13 may also be used to restore the HSIC bus from the suspended state to the normal working state, so that the HSIC bus resumes data transmission. , the external device wakes up from sleep.
  • the host provided by the embodiment of the present invention corresponds to the HSIC-based high-speed interface HSIC-based wake-up method provided by the embodiment of the present invention, and is an execution device based on the inter-chip high-speed interface HSIC wake-up method, which implements an inter-chip high-speed interface HSIC.
  • the process of the wake-up method refer to the related description in the embodiment shown in FIG. 1 and FIG. 3 of the present invention, and details are not described herein again.
  • FIG. 7 is a schematic structural diagram of an external device according to an embodiment of the present invention. As shown in FIG. 7, the external device includes: an HSIC interface 21, a level change interface 22, and a processor 23;
  • Inter-chip high-speed interface HSIC interface 21 connected to the host through the HSIC bus;
  • Level change interface 22 connected to the host through a signal line, generates an interrupt under the control of the processor Signal, and send the interrupt signal to the external device through the signal line;
  • the processor 23 is configured to receive an operation instruction of the user, and the control level change interface generates an interrupt signal.
  • the processor 22 is further configured to: the external device is in an idle state, and the external device is controlled to enter a sleep state under the control of the host; or the external device is in an idle state, detecting that the HSIC bus is suspended, and controlling the external device to enter the sleep state status.
  • the processor 23 is further configured to: control the external device to wake up from the sleep state after the HSIC bus resumes from the suspended state to the normal working state.
  • the external device provided by the embodiment of the present invention corresponds to the HSIC-based high-speed interface HSIC-based wake-up method provided by the embodiment of the present invention, and the execution device based on the inter-chip high-speed interface HSIC wake-up method performs the inter-chip high-speed interface HSIC.
  • the process of the wake-up method refer to the related description in the embodiment shown in FIG. 2 and FIG. 3 of the present invention, and details are not described herein again.
  • FIG. 8 is a schematic structural diagram of another embodiment of a host provided by the present invention. As shown in FIG. 8, the host includes: an HSIC interface 31 and a processor 32;
  • the inter-chip high-speed interface HSIC interface 31 is connected to the external device through the HSIC bus; the processor 32 is configured to obtain the external device in an idle state, or to control the external device to be powered off when the external device is powered off according to the needs of the service; The bus enters the initial state to wait for the external device to power up; control the external device to power on.
  • the processor 32 controls the HSIC bus to enter an initial state, specifically: controlling the HSIC controller to re-initialize. Further or alternatively, after the processor 32 controls the HSIC bus to enter the initial state, before the host enters the sleep state, the processor is further configured to: save the current state of the HSIC controller; and control the HSIC bus to be powered off.
  • the processor 32 can also be used to: control the HSIC bus to power up; and restore the HSIC register state according to the state of the saved HSIC register.
  • the host provided by the embodiment of the present invention corresponds to the sleep hot swap based on the inter-chip high-speed interface HSIC provided by the embodiment of the present invention, and the execution device based on the hot plug method of the inter-chip high-speed interface HSIC performs the inter-chip high speed.
  • the hot-swap method of the interface HSIC refer to the related description in the embodiment shown in FIG. 4 and FIG. 5 of the present invention, and details are not described herein again.
  • FIG. 9 is a schematic structural diagram of an embodiment of a wireless terminal according to the present invention.
  • the terminal may include: a host 41 and an external device 42;
  • the host and external devices include a high-speed HSIC interface between the chips, and the HSIC interface of the host and the HSIC interface of the external device are connected through the HSIC bus.
  • the host and the external device include an interface capable of generating a level change, the level change interface of the host and the external device.
  • the level change interface is connected by a signal line.
  • the level change interface can be a general purpose input/output GPIO interface, or an interrupt interface.
  • the host can suspend the HSIC bus and the host is in a sleep state.
  • the host can wake up from the sleep state.
  • the host can control the external device when the external device is in an idle state Dormant; or
  • the external device detects the HSIC bus status, and the external device can be in a sleep state if the HSIC bus is in a suspended state.
  • the host can save the current state of the HSIC controller, and the host can control the HSIC bus to be powered off.
  • the host can control the HSIC bus to be powered on, and the host can restore the state of the HSIC controller according to the saved state of the HSIC controller, restore the HSIC bus, and wake up the external device.
  • the host can detect that the external device is powered off when the external device connected to the host through the interchip high-speed interface HSIC bus is idle, and the host can control the HSIC bus to enter the initial state.
  • the wireless terminal can be a wireless router, a mobile phone or a USB modem.
  • the host when the host obtains an idle state that is connected to the host through the HSIC bus, the host can receive an interrupt signal sent by the external device from the signal line connected to the external device in the sleep state.
  • the interrupt signal wakes up from the sleep state, thereby realizing wake-up of the host and the external device based on the HSIC bus, thereby realizing energy saving of the device.
  • the host can control the external device to be powered off, thereby enabling hot plugging of the external device and saving the power of the device.
  • the host and the external device in the foregoing embodiment may include a High Speed Inter-Chip (HSIC) interface, and the HSIC interface of the host and the HSIC interface of the external device are connected through the HSIC bus, wherein the host and the external device may also be Including an interface capable of generating a level change (for example, a General Purpose Input Output (GPIO) interface, or an interrupt interface), the interface of the level change of the host and the level change of the external device can be connected by a signal line.
  • HSIC High Speed Inter-Chip
  • GPIO General Purpose Input Output
  • the above-mentioned function assignment can be completed by different functional modules as needed.
  • the internal structure of the device is divided into different functional modules to perform all or part of the functions described above.
  • the device and the unit described above refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the modules or units is only a logical function division.
  • there may be another division manner for example, multiple units or components may be used. Combined or can be integrated into another system, or some features can be ignored, or not executed.
  • the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or otherwise.
  • the components displayed for the unit may or may not be physical units, ie may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of a software function unit.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as a standalone product, may be stored in a computer readable storage medium.
  • a computer readable storage medium Including a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform various embodiments of the present application All or part of the steps of the method.
  • the foregoing storage medium includes: a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like, which can store program codes. .

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Abstract

本发明实施例提供一种基于芯片间高速接口HSIC的唤醒、热插拔方法和设备。一种方法包括：主机获得与所述主机通过芯片间高速接口HSIC总线连接的外部设备处于空闲状态；所述主机处于休眠状态；所述主机从与所述外部设备连接的信号线接收所述外部设备发送的中断信号；所述主机根据所述中断信号，从所述休眠状态唤醒。实现主机和外部设备基于HSIC总线的唤醒和热插拔，实现节约设备电能。

Description

基于芯片间高速接口 HSIC的唤醒、 热插拔方法和设备 本申请要求于 2012 年 6 月 21 日提交中国专利局， 申请号为 201210208398.9、 发明名称为 "基于芯片间高速接口 HSIC的唤醒、 热插拔方 法和设备" 的中国专利申请， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及信息技术， 尤其涉及一种基于芯片间高速接口 HSIC的唤醒、 热插拔方法和设备。
背景技术
目前， 芯片间高速接口 （High Speed Inter-Chip, HSIC )釆用芯片间连 接 (Inter-Chip Connectivity, ICC)技术， 能够实现 USB 2.0协议在短距离间传 输， 还能保有类比 USB 2.0连接的软件兼容性。
现有技术中， 釆用 HSIC接口的主机芯片和外设芯片焊接在同一块单板 中， 两颗芯片同时上电、 同时掉电， 使得设备电能消耗较大。
发明内容 本发明实施例提供一种基于芯片间高速接口 HSIC的唤醒、热插拔方法和 设备， 节约设备电能。
一方面， 本发明实施例提供一种基于芯片间高速接口 HSIC的唤醒方法， 包括：
主机获得与所述主机通过芯片间高速接口 HSIC总线连接的外部设备处 于空闲状态；
所述主机处于休眠状态；
所述主机从与所述外部设备连接的信号线接收所述外部设备发送的中断 信号；
所述主机根据所述中断信号， 从所述休眠状态唤醒。 本发明实施例还提供一种基于芯片间高速接口 HSIC的唤醒方法， 包括： 与主机通过芯片间高速接口 HSIC总线连接的外部设备接收到用户的操 作指令；
所述外部设备通过与所述主机连接的信号线向所述主机发送中断信号， 以使所述主机从休眠状态唤醒。
另一方面，本发明实施例还提供一种基于芯片间高速接口 HSIC的热插拔 方法， 包括：
主机获得与所述主机通过芯片间高速接口 HSIC总线连接的外部设备处 于空闲状态， 或主机根据业务的需求需要控制外部设备断电时； 所述主机控 制所述外部设备断电；
所述主机控制所述 HSIC总线进入初始状态， 以等待所述外部设备上电； 所述主机控制所述外部设备上电。
另一方面， 本发明实施例提供一种主机， 包括：
芯片间高速接口 HSIC接口， 通过 HSIC总线与外部设备连接； 电平变化接口， 通过信号线与所述外部设备连接， 用于接收所述外部设 备发送的中断信号；
处理器， 用于获得所述外部设备处于空闲状态， 所述主机处于休眠状态， 所述电平变化接口从所述信号线上接收到所述外部设备发送的中断信号， 则 根据所述中断信号控制所述主机从休眠状态唤醒。
本发明实施例提供一种外部设备， 包括：
芯片间高速接口 HSIC接口， 通过 HSIC总线与主机连接；
电平变化接口， 通过信号线与所述主机连接， 在所述处理器的控制下产 生中断信号， 并将所述中断信号通过所述信号线发送给所述外部设备；
处理器， 用于接收到用户的操作指令， 控制所述电平变化接口产生所述 中断信号。
另一方面， 本发明实施例还提供一种主机， 包括： 芯片间高速接口 HSIC接口， 通过 HSIC总线与外部设备连接； 处理器， 用于获得所述外部设备处于空闲状态， 或根据业务的需求需要 控制外部设备断电时， 控制所述外部设备断电； 控制所述 HSIC总线进入初始 状态， 以等待所述外部设备上电； 控制所述外部设备上电。
本发明实施例提供一种终端， 包括： 主机和外部设备， 所述主机和所述 外部设备包括通过芯片间高速 HSIC接口， 所述主机的 HSIC接口与所述外部 设备的 HSIC接口通过 HSIC总线连接， 所述主机和所述外部设备包括能够产 生电平变化的接口， 所述主机的电平变化接口与所述外部设备的电平变化接 口通过信号线连接。
本发明实施例提供的基于芯片间高速接口 HSIC的唤醒方法和设备， 当主 机获得与主机通过 HSIC总线连接的外部设备处于空闲状态，则主机在休眠状 态下， 从与外部设备连接的信号线接收外部设备发送的中断信号后， 可以根 据所述中断信号， 从所述休眠状态唤醒， 从而实现主机和外部设备基于 HSIC 总线的唤醒， 实现节省设备的电能。
本发明实施例提供的基于芯片间高速接口 HSIC的热插拔方法和设备，当 获得与主机通过 HSIC 总线连接的外部设备处于空闲状态或者主机根据业务 需求需要控制外部设备断电时， 主机可以控制外部设备断电， 从而实现外部 设备的热插拔， 节省设备的电能。 附图说明 为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不 付出创造性劳动性的前提下， 还可以根据这些附图获得其他的附图。
图 1为本发明提供的基于芯片间高速接口 HSIC的唤醒方法一个实施例 的流程图； 图 2为本发明提供的基于芯片间高速接口 HSIC的唤醒方法又一个实施 例的流程图；
图 3为本发明提供的基于芯片间高速接口 HSIC的唤醒方法又一个实施 例的流程图；
图 4为本发明提供的基于芯片间高速接口 HSIC的热插拔方法一个实施 例的流程图；
图 5为本发明提供的基于芯片间高速接口 HSIC的热插拔方法又一个实 施例的流程图；
图 6为本发明提供的主机一个实施例的结构示意图；
图 7为本发明提供的外部设备一个实施例的结构示意图；
图 8为本发明提供的主机另一个实施例的结构示意图；
图 9为本本发明提供的无线终端一个实施例的结构示意图。
具体实施方式 为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例是本发明一部分实施例， 而不是全部的实施例。 基于 本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例中涉及的主机， 可以是个人计算机、 手机、 PAD、 无线路 由器或通用串行总线 ( Universal Serial BUS, USB )调制解调器等各种终端 上的中央处理单元（Central Processing Unit, CPU )。 外部设备， 可以是无 线保真 ( Wireless Fidelity, WiFi ) 芯片模块、 蓝牙模块、 摄像头模块等外设 芯片。
图 1为本发明提供的基于芯片间高速接口 HSIC的唤醒方法一个实施例 的流程图， 如图 1所示， 该方法包括：
5101、 主机获得与主机通过芯片间高速接口 ( High Speed Inter-Chip, HSIC ) 总线连接的外部设备处于空闲状态。
5102、 主机处于休眠状态。
5103、 主机从与所述外部设备连接的信号线接收所述外部设备发送的中 断信号。
5104、 主机根据中断信号， 从休眠状态唤醒。
本实施例中涉及的主机与外部设备可以包括 High Speed Inter-Chip (简 称 HSIC )接口， 主机的 HSIC接口与外部设备的 HSIC接口通过 HSIC总线 连接， 其中， 主机和外部设备还可以包括能够产生电平变化的接口 （例如 General Purpose Input Output (简称 GPIO )接口或中断接口） ， 主机的电 平变化的接口与外部设备的电平变化的接口可以通过信号线连接， 该信号线 可以由一根主机至外部设备之间双向通信的信号线组成， 也可以由一根主机 至外部设备方向的信号线和一个外设至主机方向的信号线组成。 信号线可以 是通用输入 /输出 （ General Purpose Input Output, GPIO )信号线， 也可以 是其他可以产生电平变化的信号线。
其中， 外部设备处于空闲状态可以是指： 外部设备没有用户使用， 等待 用户的场景， 也可以是指外部设备的使用率低于一定门限的场景。
主机可以通过检测获得到外部设备处于空闲状态， 或者， 外部设备处于 空闲状态时， 也可以将用于指示处于空闲状态的消息主动上报给主机。
主机获得外部设备处于空闲状态后， 主机可以将 HSIC总线挂起
( suspend ) , 以使 HSIC总线停止数据传输， 之后， 主机可以进入休眠状态。 其中， 主机可以具有多种休眠状态， 举例来说， 在一种实施场景下， 主机可 以处于掉电状态， 所有软件均不运行， 内存处于自刷新状态； 在另一种实施 场景下， 主机可以处于慢时钟状态。 本发明实施例中对主机如何处于休眠状 态并不限定。 外部设备处于空闲状态后， 可以进入休眠状态。 作为一种可行的实施方 式， 主机获得外部设备处于空闲状态后， 可以控制外部设备进入休眠状态， 举例来说， 主机可以通过软件命令控制外部设备进入休眠状态， 还可以通过 现有的各种方法控制外部设备进入休眠状态。 作为另一种可行的实施方式， 外部设备在检测到 HSIC总线挂起后， 可以进入休眠状态。 其中， 外部设备可 以具有多种休眠状态， 举例来说， 外部设备可以处于低功耗状态， 这种状态 下外部设备为省电模式， 但可以响应用户操作。 例如： wifi芯片这种外部设备 在休眠状态下可以降低功率， 信令帧拉长， 可以响应用户接入。
主机处于休眠状态的过程中， 外部设备可以通过与主机连接的信号线向 主机发送中断信号， 该中断信号可以是高电平信号， 也可以是低电平信号。 主机接收到外部设备发送的中断信号后， 可以从休眠状态唤醒， 主机被唤醒 后， 即可以处于正常工作模式。
主机唤醒后， 可以将 HSIC总线从挂起状态恢复（resume )到正常工作 状态， 以使 HSIC总线恢复数据传输。
在外部设备处于休眠状态的实施场景下，主机将 HSIC总线从挂起状态恢 复到正常工作状态后， HSIC总线恢复数据传输， 外部设备可以从休眠状态唤 醒。 具体的， HSIC总线恢复数据传输后， 可以釆用 HSIC协议中的 resume 协议使外部设备可以从休眠状态唤醒。
作为一种可行的实施方式， 主机将 HSIC总线挂起后， 主机还可以先保存 HSIC控制器的当前状态， 再进入休眠状态。 在这种实施场景下， 主机根据外 部设备发送的中断信号唤醒后， 可以首先根据被保存的 HSIC的状态来恢复 HSIC控制器， 再将挂起的 HSIC总线恢复到正常工作状态。
作为另一种可行的实施方式， 主机将 HSIC总线挂起后， 主机可以保存 HSIC控制器的当前状态， 控制 HSIC总线断电， 之后， 主机再进入休眠状态。 在这种实施场景下， 主机根据外部设备发送的中断信号唤醒后， 可以首先控 制 HSIC总线上电， 再根据保存的 HSIC控制器的状态恢复 HSIC控制器的状 态， 再将挂起的 HSIC总线恢复到正常工作状态。
其中， HSIC总线恢复到正常工作状态后， 外部设备可以从休眠状态进入 正常的工作状态。
本实施例提供的基于芯片间高速接口 HSIC的唤醒方法， 当主机获得与主 机通过 HSIC总线连接的外部设备处于空闲状态， 则主机在休眠状态下， 从与 外部设备连接的信号线接收外部设备发送的中断信号后， 可以根据所述中断 信号， 从所述休眠状态唤醒， 从而实现主机和外部设备基于 HSIC总线的唤 醒， 实现节省设备的电能。
图 2为本发明提供的基于芯片间高速接口 HSIC的唤醒方法又一个实施 例的流程图， 如图 2, 该方法包括：
5201、 与主机通过芯片间高速接口 HSIC总线连接的外部设备接收到用 户的操作指令；
5202、 外部设备通过与主机连接的信号线向主机发送中断信号， 以使主 机从休眠状态唤醒。
外部设备接收到用户的操作指令后， 可以通过与主机连接的信号线向主 机发送中断信号， 从而实现基于 HSIC总线唤醒处于休眠状态的主机。
需要说明的是， 上述的外部设备接收到用户的操作指令， 可以是指外部 设备处于休眠状态的实施场景， 也可以是指外部设备处于正常工作状态的实 施场景， 即， 本发明对于外部设备在什么状态下向主机发送中断信号并不做 出限制。
在一种实施场景下， 当外部设备处于空闲状态时， 例如： 外部设备没有 用户使用， 等待用户的场景， 或者， 外部设备的使用率低于一定门限的场景 下。 外部设备可以在主机的控制下进入休眠状态； 或者， 外部设备可以在检 测到与主机连接的 HSIC总线挂起， 则进入休眠状态。
在外部设备处于休眠状态实施场景下， 主机被外部设备发送的中断信号 唤醒后， 主机可以将 HSIC总线从挂起状态恢复到正常工作状态。 而外部设备 在 HSIC总线从挂起状态恢复到正常工作状态之后， 可以从休眠状态唤醒。 本实施例提供的基于芯片间高速接口 HSIC的唤醒方法，通过芯片间高速 接口 HSIC总线与主机连接， 当接收到用户的操作指令，可以通过与主机连接 的信号线向主机发送中断信号， 以使主机从休眠状态唤醒， 从而实现主机和 外部设备基于 HSIC总线的唤醒， 从而实现节省外部设备的电能。
图 3为本发明提供的基于芯片间高速接口 HSIC的唤醒方法又一个实施 例的流程图， 如图 3, 本实施例提供了主机和外设基于 HSIC总线休眠和唤醒 的一个实施场景， 该方法包括：
5301、 主机获得与主机通过芯片间高速接口 HSIC总线连接的外部设备 处于空闲状态。
5302、 主机将 HSIC总线挂起， 以使 HSIC总线停止数据传输。
5303、 主机保存 HSIC控制器的当前状态。
5304、 主机控制 HSIC总线断电。
其中， HSIC控制器通常进行 HSIC协议处理等操作， 主机保存 HSIC控 制器器的当前状态， 以备 HSIC总线上电后能够恢复当前状态。
5305、 主机进入休眠状态。
5306、 外部设备检测到 HSIC总线挂起。
5307、 外部设备进入休眠状态。
举例来说， 外部设备 WiFi模块的接入点（Access Point, AP )模块可以 进入待机休眠态， 来等待用户接入， 以节省 WiFi模块的电源消耗。
5308、 外部设备接收到用户的操作指令。
5309、 外部设备通过信号线向主机发送中断信号。
主机进入待机休眠状态后， 能够响应外部设备与主机之间的信号线上的 电平变化产生的中断信号。
当有用户操作外部设备时， 例如， 用户通过接入外部设备 WiFi芯片， 则 外部设备可以通过信号线向主机发出一个中断信号来唤醒主机。 5310、 主机从休眠状态唤醒。
5311、 主机控制 HSIC总线上电。
5312、 主机根据保存的 HSIC控制器的状态恢复 HSIC控制器的状态。
5313、 主机将 HSIC 总线从挂起状态恢复到正常工作状态， 以使 HSIC 总线恢复数据传输， 外部设备从休眠状态唤醒。
其中， 上述步骤中的 S304与 S311 可以为可选步骤。
本实施例提供的基于芯片间高速接口 HSIC的唤醒方法，主机在获得外部 设备处于空闲状态后， 主机可以将 HSIC总线挂起， 并进入休眠状态。 外部设 备检测到 HSIC总线挂起后， 也可以进入休眠状态。 当外部设备接收到用户的 操作指令后， 外部设备可以通过与主机之间连接的信号线向主机发送终端信 号来唤醒主机， 从而实现外部设备和主机基于 HSIC总线的休眠和唤醒， 实现 节省设备能耗。
图 4为本发明提供的基于芯片间高速接口 HSIC的热插拔方法一个实施 例的流程图， 如图 4所示， 该方法包括：
5401、 主机获得与主机通过芯片间高速接口 HSIC总线连接的外部设备 处于空闲状态， 或主机根据业务的需求需要控制外部设备断电。
5402、 主机控制外部设备断电。
5403、 主机控制 HSIC总线进入初始状态， 以等待外部设备上电。
5404、 主机控制外部设备上电。
本实施例中涉及的主机与外部设备之间， 可以通过 HSIC总线连接。 其中， 外部设备处于空闲状态可以是指： 外部设备没有用户使用， 等待 用户的场景， 也可以是指外部设备的使用率低于一定门限的场景。 主机可以 通过直接检测获得到外部设备处于空闲状态， 或者， 外部设备处于空闲状态 时， 也可以将用于指示处于空闲状态的消息主动上报给主机。
本实施例中， 外部设备可以具有独立的供电模块， 或者， 外部设备可以 具有独立的供电线路。 主机获得外部设备处于空闲状态， 或者， 主机根据业 务的需求需要控制外部设备断电时， 例如： 主机与外部设备通信的过程中获 知外部设备出现异常等实施场景， 则主机可以控制外部设备断电。 举例来说， 主机可以控制外部设备的供电模块停止向外部设备供电， 或者， 主机可以断 开外部设备的供电线路， 以使外部设备断电。
主机控制外部设备断电之后， 主机可以控制 HSIC总线进入初始状态， 以 等待外部设备上电。 进入初始状态的 HSIC总线在外部设备下次上电接入时， 能够识别外部设备， 从而保证主机与外部设备之间的正常通信。 其中， 主机 控制 HSIC总线进入初始状态， 具体可以是控制 HSIC控制器重新初始化， 以 实现 HSIC总线进入初始状态。
作为一种可行的实施方式， 主机控制 HSIC总线进入初始状态之后， 主机 还可以保存 HSIC控制器的当前状态， 然后进入休眠状态， 以降低主机的功 耗。 在这种实施场景下， 主机唤醒之后， 可以根据保存的 HSIC寄存器的状态 恢复 HSIC寄存器状态， 再控制外部设备上电。
作为另一种可行的实施方式， 主机控制 HSIC总线进入初始状态之后， 主机可以保存 HSIC控制器的当前状态， 控制 HSIC总线断电。 之后， 主机可 以进入休眠状态， 以降低主机的功耗。 在这种实施场景下， 主机唤醒之后， 可以控制 HSIC总线上电， 根据保存的 HSIC寄存器的状态恢复 HSIC寄存器 状态， 再控制外部设备上电。
本实施例提供的基于芯片间高速接口 HSIC的热插拔方法，当获得与主机 通过 HSIC 总线连接的外部设备处于空闲状态或者主机根据业务需求需要控 制外部设备断电时， 主机可以控制外部设备断电， 从而实现外部设备的热插 拔， 节省设备的电能。
图 5为本发明提供的基于芯片间高速接口 HSIC的热插拔方法又一个实 施例的流程图， 如图 5所示， 本实施例提供了主机和外设基于 HSIC总线实 现热插拔的一个实施场景， 该方法包括：
S501、 主机获得与主机通过芯片间高速接口 HSIC总线连接的外部设备 处于空闲状态， 或主机根据业务的需求需要控制外部设备断电时。
S502、 主机控制外部设备断电。
S503、 主机控制 HSIC总线进入初始状态， 以等待外部设备上电。
S504、 主机保存 HSIC控制器的当前状态。
S505、 主机控制 HSIC总线断电。
S506、 主机进入休眠状态。
S507、 主机由休眠状态唤醒。
S508、 主机控制 HSIC总线上电。
S509、 主机根据保存的 HSIC寄存器的状态恢复 HSIC寄存器状态。
S510、 主机控制外部设备上电。
在外部设备需要重新使用的场景下， 主机可以通过控制外部设备上电。 外部设备上电后， HSIC总线可以检测到外部设备的连接， 并且可以正常枚举 外部设备。 从而实现 HSIC接口的热插拔功能。
本实施例提供的基于芯片间高速接口 HSIC的热插拔方法，主机可以在外 部设备处于空闲状场景下， 或者主机可以根据业务需求控制外部设备断电， 以节省电能。主机还可以控制 HSIC总线进入初始状态，以便外部设备上电后， HSIC总线能够识别外部设备， 从而实现 HSIC接口支持热插拔， 节约设备电
•6匕
匕。 图 6为本发明提供的主机一个实施例的结构示意图， 如图 6所示， 该主 机包括： HSIC接口 1 1、 电平变化接口 12和处理器 13;
芯片间高速接口 HSIC接口 1 1 , 通过 HSIC总线与外部设备连接； 电平变化接口 12, 通过信号线与外部设备连接， 用于接收外部设备发送 的中断信号；
处理器 13, 用于获得外部设备处于空闲状态， 主机处于休眠状态， 电平 变化接口从信号线上接收到外部设备发送的中断信号， 则根据中断信号控制 主机从休眠^ 态唤醒。
可选的， 处理器 13还可以用于： 在获得外部设备处于空闲状态之后， 控 制外部设备进入休眠状态。
进一步的或可选的， 在主机处于休眠状态之前， 处理器 13还可以用于： 将 HSIC总线挂起， 以使 HSIC总线停止数据传输。
进一步的或可选的， 处理器 13将 HSIC总线挂起之后， 还可以用于保存 HSIC控制器的当前状态， 控制 HSIC总线断电。
进一步的或可选的， 处理器 13根据中断信号， 控制主机从休眠状态唤醒 之后， 还可以用于控制 HSIC总线上电， 根据保存的 HSIC控制器的状态恢复 HSIC控制器的状态。
进一步的或可选的，处理器 13根据保存的 HSIC控制器的状态恢复 HSIC 控制器的状态之后， 还可以用于将 HSIC总线从挂起状态恢复到正常工作状 态， 以使 HSIC总线恢复数据传输， 外部设备从休眠状态唤醒。
本发明实施例提供的主机， 与本发明实施例提供的基于芯片间高速接口 HSIC的唤醒方法相对应， 为基于芯片间高速接口 HSIC的唤醒方法的执行设 备， 其执行基于芯片间高速接口 HSIC的唤醒方法的过程可参见本发明图 1 和图 3所示实施例中的相关描述， 在此不再赘述。
本实施例提供的主机 当获得与主机通过 HSIC总线连接的外部设备处于 空闲状态， 则主机在休眠状态下， 从与外部设备连接的信号线接收外部设备 发送的中断信号后， 可以根据所述中断信号， 从所述休眠状态唤醒， 从而实 现主机和外部设备基于 HSIC总线的唤醒， 实现节省设备的电能。 图 7为本发明提供的外部设备一个实施例的结构示意图， 如图 7所示， 该外部设备包括： HSIC接口 21、 电平变化接口 22和处理器 23;
芯片间高速接口 HSIC接口 21 , 通过 HSIC总线与主机连接；
电平变化接口 22, 通过信号线与主机连接， 在处理器的控制下产生中断 信号， 并将中断信号通过信号线发送给外部设备；
处理器 23, 用于接收到用户的操作指令， 控制电平变化接口产生中断信 号。
可选的， 处理器 22还可以用于： 外部设备处于空闲状态， 在主机的控制 下控制外部设备进入休眠状态； 或者， 外部设备处于空闲状态， 检测到 HSIC 总线挂起， 控制外部设备进入休眠状态。
进一步的或可选的，外部设备进入休眠状态之后， 处理器 23还可以用于： 在 HSIC总线从挂起状态恢复到正常工作状态之后，控制外部设备从休眠状态 唤醒。
本发明实施例提供的外部设备， 与本发明实施例提供的基于芯片间高速 接口 HSIC的唤醒方法相对应， 为基于芯片间高速接口 HSIC的唤醒方法的执 行设备其执行基于芯片间高速接口 HSIC的唤醒方法的过程可参见本发明图 2和图 3所示实施例中的相关描述， 在此不再赘述。
本实施例提供的外部设备， 通过芯片间高速接口 HSIC总线与主机连接， 当接收到用户的操作指令， 可以通过与主机连接的信号线向主机发送中断信 号， 以使主机从休眠状态唤醒， 从而实现主机和外部设备基于 HSIC总线的唤 醒， 从而实现节省外部设备的电能。 图 8为本发明提供的主机另一个实施例的结构示意图， 如图 8所示， 该 主机包括： HSIC接口 31和处理器 32;
芯片间高速接口 HSIC接口 31 , 通过 HSIC总线与外部设备连接； 处理器 32, 用于获得外部设备处于空闲状态， 或根据业务的需求需要控 制外部设备断电时， 控制外部设备断电； 控制 HSIC总线进入初始状态， 以等 待外部设备上电； 控制外部设备上电。
可选的， 处理器 32控制 HSIC总线进入初始状态具体为： 控制 HSIC控 制器重新初始化。 进一步的或可选的， 处理器 32控制 HSIC总线进入初始状态之后， 当主 机进入休眠状态之前， 处理器还用于： 保存 HSIC控制器的当前状态； 控制 HSIC总线断电。
进一步的或可选的， 主机唤醒之后， 处理器控制外部设备上电之前， 处 理器 32还可以用于： 控制 HSIC总线上电； 根据保存的 HSIC寄存器的状态 恢复 HSIC寄存器状态。
本发明实施例提供的主机， 与本发明实施例提供的基于芯片间高速接口 HSIC的休眠热插拔相对应， 为基于芯片间高速接口 HSIC的热插拔方法的执 行设备其执行基于芯片间高速接口 HSIC的热插拔方法的过程可参见本发明 图 4和图 5所示实施例中的相关描述， 在此不再赘述。
本实施例提供的主机 当获得与主机通过 HSIC总线连接的外部设备处于 空闲状态或者主机根据业务需求需要控制外部设备断电时， 主机可以控制外 部设备断电， 从而实现外部设备的热插拔， 节省设备的电能。 图 9为本发明提供的无线终端一个实施例的结构示意图， 如图 9所示， 该终端可以包括： 主机 41和外部设备 42;
主机和外部设备包括通过芯片间高速 HSIC接口， 主机的 HSIC接口与外 部设备的 HSIC接口通过 HSIC总线连接， 主机和外部设备包括能够产生电平 变化的接口， 主机的电平变化接口与外部设备的电平变化接口通过信号线连 接。
可选的， 电平变化的接口可以为通用输入 /输出 GPIO接口， 或中断接口。 进一步的或可选的， 外部设备处于空闲状态时， 主机可以将 HSIC总线挂 起， 主机处于休眠状态。
进一步的或可选的， 主机通过信号线接收到外部设备发送的中断信号 后， 主机可以从休眠状态唤醒。
进一步的或可选的， 外部设备处于空闲状态时， 主机可以控制外部设备 休眠； 或
外部设备检测 HSIC总线状态， 如果 HSIC总线处于挂起状态， 外部设备 可以处于休眠状态。
进一步的或可选的， 主机将 HSIC总线挂起后， 主机可以保存 HSIC控制 器的当前状态， 主机可以控制 HSIC总线断电。
进一步的或可选的， 主机从休眠状态唤醒之后， 主机可以控制 HSIC总线 上电， 主机可以根据保存的 HSIC控制器的状态恢复 HSIC控制器的状态， 恢 复 HSIC总线， 唤醒外部设备。
进一步的或可选的，主机检测到与主机通过芯片间高速接口 HSIC总线连 接的外部设备处于空闲状态时， 可以控制外部设备断电， 主机可以控制 HSIC 总线进入初始状态。
其中， 无线终端可以为无线路由器， 手机或 USB调制解调器。
本发明实施例提供的终端， 其中包括的主机和外部设备的具体结构和功 能可参见本发明提供的主机和外部设备的实施例， 在此不再赘述。
本发明实施例提供的终端， 当主机获得与主机通过 HSIC总线连接的外部 设备处于空闲状态， 则主机在休眠状态下， 从与外部设备连接的信号线接收 外部设备发送的中断信号后， 可以根据所述中断信号， 从所述休眠状态唤醒， 从而实现主机和外部设备基于 HSIC总线的唤醒， 实现节省设备的电能。 当获 得与主机通过 HSIC总线连接的外部设备处于空闲状态或者主机根据业务需 求需要控制外部设备断电时， 主机可以控制外部设备断电， 从而实现外部设 备的热插拔， 节省设备的电能。
需要说明的是， 上述实施例中的主机与外部设备可以包括 High Speed Inter-Chip (简称 HSIC )接口， 主机的 HSIC接口与外部设备的 HSIC接口 通过 HSIC总线连接， 其中， 主机和外部设备还可以包括能够产生电平变化的 接口（例如 General Purpose Input Output(简称 GPIO )接口， 或中断接口）， 主机的电平变化的接口与外部设备的电平变化的接口可以通过信号线连接。 所属领域的技术人员可以清楚地了解到， 为描述的方便和简洁， 仅以上 述各功能模块的划分进行举例说明， 实际应用中， 可以根据需要而将上述功 能分配由不同的功能模块完成， 即将装置的内部结构划分成不同的功能模块， 以完成以上描述的全部或者部分功能。 上述描述的系统， 装置和单元的具体 工作过程， 可以参考前述方法实施例中的对应过程， 在此不再赘述。
在本申请所提供的几个实施例中， 应该理解到， 所揭露的装置和方法， 可以通过其它的方式实现。 例如， 以上所描述的装置实施例仅仅是示意性的， 例如， 所述模块或单元的划分， 仅仅为一种逻辑功能划分， 实际实现时可以 有另外的划分方式， 例如多个单元或组件可以结合或者可以集成到另一个系 统， 或一些特征可以忽略， 或不执行。 另一点， 所显示或讨论的相互之间的 耦合或直接耦合或通信连接可以是通过一些接口， 装置或单元的间接耦合或 通信连接， 可以是电性， 机械或其它的形式。 为单元显示的部件可以是或者也可以不是物理单元， 即可以位于一个地方， 或者也可以分布到多个网络单元上。 可以根据实际的需要选择其中的部分或 者全部单元来实现本实施例方案的目的。
另外， 在本申请各个实施例中的各功能单元可以集成在一个处理单元中， 也可以是各个单元单独物理存在， 也可以两个或两个以上单元集成在一个单 元中。 上述集成的单元既可以釆用硬件的形式实现， 也可以釆用软件功能单 元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售 或使用时， 可以存储在一个计算机可读取存储介质中。 基于这样的理解， 本 申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的 全部或部分可以以软件产品的形式体现出来， 该计算机软件产品存储在一个 存储介质中， 包括若干指令用以使得一台计算机设备（可以是个人计算机， 服务器， 或者网络设备等）或处理器（processor )执行本申请各个实施例所 述方法的全部或部分步骤。 而前述的存储介质包括： U 盘、 移动硬盘、 只读 存储器 （ROM , Read-Only Memory ), 随机存取存储器 （RAM , Random Access Memory ), 磁碟或者光盘等各种可以存储程序代码的介质。
以上所述， 以上实施例仅用以说明本申请的技术方案， 而非对其限制； 尽管参照前述实施例对本申请进行了详细的说明， 本领域的普通技术人员应 当理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或者对其 中部分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技术方案 的本质脱离本申请各实施例技术方案的精神和范围。

Claims

权 利 要求 书
1、 一种基于芯片间高速接口 HSIC的唤醒方法， 其特征在于， 包括： 主机获得与所述主机通过芯片间高速接口 HSIC总线连接的外部设备处于 空闲状态；
所述主机处于休眠状态；
所述主机从与所述外部设备连接的信号线接收所述外部设备发送的中断信 号；
所述主机根据所述中断信号， 从所述休眠状态唤醒。
2、 根据权利要求 1所述的方法， 其特征在于， 所述主机获得与所述主机通 过芯片间高速接口 HSIC总线连接的外部设备处于空闲状态之后， 还包括： 所述主机控制所述外部设备进入休眠状态。
3、 根据权利要求 1或 2所述的方法， 其特征在于， 所述主机处于休眠状态 之前， 还包括：
所述主机将所述 HSIC总线挂起， 以使所述 HSIC总线停止数据传输。
4、 根据权利要求 3所述的方法， 其特征在于， 所述主机将所述 HSIC总线 挂起之后， 还包括：
所述主机保存 HSIC控制器的当前状态；
所述主机控制所述 HSIC总线断电。
5、根据权利要求 4所述的方法， 其特征在于， 所述主机根据所述中断信号， 从所述休眠状态唤醒之后， 还包括：
所述主机控制所述 HSIC总线上电；
所述主机根据保存的所述 HSIC控制器的状态恢复所述 HSIC控制器的状 态。
6、 根据权利要求 5所述的方法， 其特征在于， 所述主机根据保存的所述 HSIC控制器的状态恢复所述 HSIC控制器的状态之后， 还包括：
所述主机将所述 HSIC总线从挂起状态恢复到正常工作状态， 以使所述 HSIC总线恢复数据传输， 所述外部设备从休眠状态唤醒。
7、 一种基于芯片间高速接口 HSIC的唤醒方法， 其特征在于， 包括： 与主机通过芯片间高速接口 HSIC总线连接的外部设备接收到用户的操作 指令；
所述外部设备通过与所述主机连接的信号线向所述主机发送中断信号， 以 使所述主机从休眠状态唤醒。
8、 根据权利要求 7所述的方法， 其特征在于， 所述与主机通过芯片间高速 接口 HSIC总线连接的外部设备接收到用户的操作指令之前， 还包括：
所述外部设备处于空闲状态；
所述外部设备在所述主机的控制下进入休眠状态； 或者， 所述外部设备检 测到所述 HSIC总线挂起， 所述外部设备进入休眠状态。
9、 根据权利要求 8所述的方法， 其特征在于， 所述外部设备进入休眠状态 之后， 还包括：
所述外部设备在所述 HSIC总线从挂起状态恢复到正常工作状态之后，从休 眠状态唤醒。
10、 一种基于芯片间高速接口 HSIC的热插拔方法， 其特征在于， 包括： 主机获得与所述主机通过芯片间高速接口 HSIC总线连接的外部设备处于 空闲状态， 或主机根据业务的需求需要控制外部设备断电时；
所述主机控制所述外部设备断电；
所述主机控制所述 HSIC总线进入初始状态， 以等待所述外部设备上电； 所述主机控制所述外部设备上电。
1 1、 根据权利要求 10所述的方法， 其特征在于， 所述主机控制所述 HSIC 总线进入初始状态， 包括：
所述主机控制 HSIC控制器重新初始化。
12、 根据权利要求 1 1所述的方法， 其特征在于， 所述主机控制所述 HSIC 总线进入初始状态之后， 当所述主机进入休眠状态之前， 还包括： 所述主机保存 HSIC控制器的当前状态；
所述主机控制所述 HSIC总线断电。
13、 根据权利要求 1 1或 12所述的方法， 其特征在于， 所述主机唤醒之后， 所述主机控制所述外部设备上电之前， 还包括：
所述主机控制所述 HSIC总线上电；
所述主机根据保存的所述 HSIC寄存器的状态恢复所述 HSIC寄存器状态。
14、 一种主机， 其特征在于， 包括：
芯片间高速接口 HSIC接口， 通过 HSIC总线与外部设备连接；
电平变化接口， 通过信号线与所述外部设备连接， 用于接收所述外部设备 发送的中断信号；
处理器， 用于获得所述外部设备处于空闲状态， 所述主机处于休眠状态， 所述电平变化接口从所述信号线上接收到所述外部设备发送的中断信号， 则根 据所述中断信号控制所述主机从休眠状态唤醒。
15、 根据权利要求 14所述的主机， 其特征在于， 所述处理器还用于： 在获 得所述外部设备处于空闲状态之后， 控制所述外部设备进入休眠状态。
16、 根据权利要求 14或 15所述的主机， 其特征在于， 在所述主机处于休 眠状态之前， 所述处理器还用于： 将所述 HSIC总线挂起， 以使所述 HSIC总线 停止数据传输。
17、 根据权利要求 16所述的主机， 其特征在于， 所述处理器将所述 HSIC 总线挂起之后，还用于保存 HSIC控制器的当前状态，控制所述 HSIC总线断电。
18、 根据权利要求 17所述的主机， 其特征在于， 所述处理器根据所述中断 信号， 控制所述主机从所述休眠状态唤醒之后， 还用于控制所述 HSIC总线上 电， 根据保存的所述 HSIC控制器的状态恢复所述 HSIC控制器的状态。
19、 根据权利要求 18所述的主机， 其特征在于， 所述处理器根据保存的所 述 HSIC控制器的状态恢复所述 HSIC控制器的状态之后， 还用于将所述 HSIC 总线从挂起状态恢复到正常工作状态， 以使所述 HSIC总线恢复数据传输， 所述 外部设备从休眠状态唤醒。
20、 一种外部设备， 其特征在于， 包括：
芯片间高速接口 HSIC接口， 通过 HSIC总线与主机连接；
电平变化接口， 通过信号线与所述主机连接， 在所述处理器的控制下产生 中断信号， 并将所述中断信号通过所述信号线发送给所述外部设备；
处理器， 用于接收到用户的操作指令， 控制所述电平变化接口产生所述中 断信号。
21、 根据权利要求 20所述的外部设备， 其特征在于， 所述处理器还用于： 所述外部设备处于空闲状态， 在所述主机的控制下控制所述外部设备进入休眠 状态； 或者， 所述外部设备处于空闲状态， 检测到所述 HSIC总线挂起， 控制所 述外部设备进入休眠状态。
22、 根据权利要求 20或 21所述的外部设备， 其特征在于， 所述外部设备 进入休眠状态之后， 所述处理器还用于： 在所述 HSIC总线从挂起状态恢复到正 常工作状态之后， 控制所述外部设备从休眠状态唤醒。
23、 一种主机， 其特征在于， 包括：
芯片间高速接口 HSIC接口， 通过 HSIC总线与外部设备连接；
处理器， 用于获得所述外部设备处于空闲状态， 或根据业务的需求需要控 制外部设备断电时， 控制所述外部设备断电； 控制所述 HSIC总线进入初始状 态， 以等待所述外部设备上电； 控制所述外部设备上电。
24、根据权利要求 23所述的主机， 其特征在于， 所述处理器控制所述 HSIC 总线进入初始状态具体为： 控制 HSIC控制器重新初始化。
25、 根据权利要求 23或 24所述的主机， 其特征在于， 所述处理器控制所 述 HSIC总线进入初始状态之后， 当所述主机进入休眠状态之前， 所述处理器还 用于： 保存 HSIC控制器的当前状态； 控制所述 HSIC总线断电。
26、 根据权利 24或 25所述的主机， 其特征在于， 所述主机唤醒之后， 所 述处理器控制所述外部设备上电之前， 所述处理器还用于： 控制所述 HSIC总 线上电； 根据保存的所述 HSIC寄存器的状态恢复所述 HSIC寄存器状态。
27、 一种无线终端， 其特征在于， 包括主机和外部设备， 所述主机和所述 外部设备包括通过芯片间高速 HSIC接口， 所述主机的 HSIC接口与所述外部设 备的 HSIC接口通过 HSIC总线连接， 所述主机和所述外部设备包括能够产生电 平变化的接口， 所述主机的电平变化接口与所述外部设备的电平变化接口通过 信号线连接。
28、 根据权利要求 27所述的终端， 其特征在于， 所述电平变化的接口为通 用输入 /输出 GPIO接口， 或中断接口。
29、 根据权利要求 27所述的终端， 其特征在于， 所述外部设备处于空闲状 态时， 所述主机将所述 HSIC总线挂起， 所述主机处于休眠状态。
30、 根据权利要求 27-29任一项所述的终端， 其特征在于， 所述主机通过 所述信号线接收到所述外部设备发送的中断信号后， 所述主机从所述休眠状态 唤醒。
31、 根据权利要求 27所述的终端， 其特征在于， 所述外部设备处于空闲状 态时， 所述主机控制所述外部设备休眠； 或
所述外部设备检测 HSIC总线状态， 如果 HSIC总线处于挂起状态， 所述外 部设备处于休眠状态。
32、 根据权利要求 28所述的终端， 其特征在于， 所述主机将所述 HSIC总 线挂起后， 所述主机保存 HSIC控制器的当前状态， 所述主机控制所述 HSIC总 线断电。
33、 根据权利要求 30所述的终端， 其特征在于， 所述主机从所述休眠状态 唤醒之后， 所述主机控制所述 HSIC总线上电， 所述主机根据保存的所述 HSIC 控制器的状态恢复所述 HSIC控制器的状态， 恢复所述 HSIC总线， 唤醒所述外 部设备。
34、 根据权利要求 27所述的终端， 其特征在于， 所述主机检测到与所述主 机通过芯片间高速接口 HSIC总线连接的外部设备处于空闲状态时，控制所述外 部设备断电， 所述主机控制所述 HSIC总线进入初始状态。
35、 根据权利要求 27-34任一所述的终端， 其特征在于， 所述无线终端为无 线路由器， 手机或 USB调制解调器。
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