WO2021227842A1 - 一种数字脉冲信号宽度测量电路及测量方法 - Google Patents

一种数字脉冲信号宽度测量电路及测量方法 Download PDF

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WO2021227842A1
WO2021227842A1 PCT/CN2021/089530 CN2021089530W WO2021227842A1 WO 2021227842 A1 WO2021227842 A1 WO 2021227842A1 CN 2021089530 W CN2021089530 W CN 2021089530W WO 2021227842 A1 WO2021227842 A1 WO 2021227842A1
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register
signal
pulse signal
edge
sampling
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PCT/CN2021/089530
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French (fr)
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陈虎
许野
万江华
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湖南毂梁微电子有限公司
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Priority to EP21803123.5A priority Critical patent/EP4123318A4/en
Priority to US17/616,688 priority patent/US11852666B2/en
Publication of WO2021227842A1 publication Critical patent/WO2021227842A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/02—Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
    • G01R29/023—Measuring pulse width

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  • the present invention mainly relates to the technical field of high-precision digital pulse signal measurement, and particularly refers to a digital pulse signal width measurement circuit and measurement method.
  • High-precision digital pulse signal width measurement is widely used in pulse sequence period/duty cycle measurement, instantaneous speed measurement, voltage measurement across isolation boundaries, distance in precision instruments, sonar, robot servos, switching power supplies, power devices, touch screens, etc. / Sonar measurement and scanning, capacitive touch sensing and other applications.
  • signal measurement generally involves first converting signals such as voltage, capacitance, speed, and distance into digital pulse signals through analog-to-digital conversion, and then measuring the digital pulse signals.
  • the digital pulse signal width measurement is to use a sampling clock (frequency f), with a clock cycle as the reference unit, the width of a pulse signal is expressed as a real number containing an integer part and a fractional part.
  • the integer part is represented by ⁇ ; the fractional part is caused by misalignment between the edge of the pulse signal and the edge of the sampling clock, and comes from the head and tail of the pulse, namely 1- ⁇ , 1- ⁇ .
  • the relationship between the width ⁇ of the high-level pulse signal and f, ⁇ , ⁇ , ⁇ is:
  • the measurement accuracy of the traditional digital signal measurement circuit is 1 sampling clock cycle 1/f, and it can only measure the integer part ⁇ of the signal width ⁇ , and cannot measure the fractional part 1- ⁇ - ⁇ of the signal width. If you want to improve the measurement accuracy, you can only increase the frequency of the sampling clock, which greatly increases the power consumption and complexity of the hardware circuit.
  • the pulse signal width measurement implemented in the patent US 8384440B2 has the characteristics of high precision and does not require a high-frequency sampling clock.
  • this method limits the working range of the sampling clock.
  • it requires a separate capture delay chain and periodically executes the software calibration procedure, which increases the software and hardware overhead.
  • the technical problem to be solved by the present invention is that: in view of the technical problems existing in the prior art, the present invention provides an ultra-high-precision digital pulse signal width measurement circuit and measurement method with high precision, simple structure, and low resource overhead.
  • the present invention adopts the following technical solutions:
  • a digital pulse signal width measurement circuit which includes:
  • Edge detection and interrupt control unit used to detect the rising edge and falling edge of the pulse signal on the input pin Input, and then control the signal collection
  • Integer encoding unit including counters and registers, used to measure the integer part ⁇ of the width of the high or low level on the input pin Input with 1 cycle 1/f of the sampling clock as the reference unit;
  • the signal capture chain includes a set of delay units DLL and capture registers CAP.
  • the number of delay units DLL and capture registers CAP is equal, set to a positive integer i; the signal on the input pin Input propagates through a delay unit every time There will be a certain amount of delay, set as ⁇ ; the signal capture chain is used to sample each delay unit when the next rising edge of the clock occurs after the rising and falling edges of the pulse signal on the input pin Input DLL output level value;
  • the decimal encoding unit is used to find and record the position of the pulse edge propagating on the signal capture chain according to the sampling result of the signal capture chain;
  • the calibration control unit generates an internal input signal and a sampling control signal after detecting the rising edge of the signal on the input pin Input.
  • the control signal capture chain samples the output of the delay unit DLL; the sampling result is encoded and stored in the calibration register Medium; the step length information is calculated according to the calibration register.
  • the edge detection and interrupt control unit when the edge detection and interrupt control unit performs interrupt control, it generates an interrupt signal Interrupt when detecting the rising or falling edge of the pulse signal on the input pin Input to notify the main control device Read the pulse signal measurement results; the measurement results are stored in the registers in the integer coding and decimal coding logic.
  • the integer coding unit includes a counter Counter[n:1], 4 registers CNTR1[n:1], CNTR2[n:1], CNTF1[n:1], CNTF2[ n:1];
  • the counter Counter[n:1] starts counting from 0 after the edge detection logic detects the rising or falling edge of the pulse; when the rising edge is detected, the counter Counter[n:1] is loaded into the register CNTR1[n :1] To record the measurement results before the rising edge, the register CNTR1[n:1] is loaded into CNTR2[n:1], and the register CNTF1[n:1] is loaded into CNTF2[n:1]; when the falling edge is detected , The counter Counter[n:1] is loaded into the register CNTF1[n:1] to record the measurement result before the falling edge.
  • the capture register CAP[i:1] is used to sample each delay after the rising edge and falling edge of the pulse signal on the input pin Input occur, and the next rising edge of the clock comes.
  • the decimal encoding unit includes encoder R, encoder F, encoding registers ENCR1[m:1], ENCR1[m:1], ENCF1[m:1], ENCF2[m: 1], calibration register CALR1[m:1], CALR2[m:1], step size register STEP[m:1]; the number m of the encoding register ENCR1[m:1] and the delay unit in the signal capture chain
  • the relationship between the number of DLLs i is:
  • the output of the capture register CAP is encoded by the encoder R, and the result is retained in the register ENCR1[m: 1]; after detecting the falling edge of the pulse signal, the output of the capture register CAP is encoded by the encoder F, and the result is retained in the register ENCF1[m:1]; when the rising edge is detected, the register ENCR1[m: 1] Load into ENCR2[m:1], and register ENCF1[m:1] into ENCF2[m:1].
  • the calibration registers CALR1[m:1] and CALR2[m:1] are used to record the position of the pulse edge propagating on the delay unit DLL chain under the control of the calibration control unit ;
  • the value of the step size register STEP[m:1] represents the number of delay units through which the signal on the input pin Input can propagate through the signal capture chain within a sampling clock period 1/f; the STEP[ m:1] is calculated according to the calibration registers CALR1[m:1] and CALR2[m:1].
  • the relationship between the frequency f of the sampling clock and the delay ⁇ of the delay unit and the number i of the delay unit is:
  • the present invention further provides a method for measuring the width of a digital pulse signal, which includes:
  • Step S1 Edge detection; that is, after the edge detection logic detects the rising edge or the falling edge of the pulse signal on the input pin Input, the Rise, Fall, and Rise_or_Fall pulse signals are generated.
  • the Rise, Fall, and Rise_or_Fall pulse signals are used to: 1) Control the Counter in the integer coding unit to restart counting from 0, 2) Control the output level of the signal capture chain sampling DLL; 3) Control the encoder R, in the fractional coding unit F encodes the result in the capture register CAP;
  • Step S2 Integer coding; after detecting the rising or falling edge of the pulse, the counter Counter[n:1] starts to count from 0; when the rising edge is detected, the counter[n:1] is loaded into the register CNTR1[n:1] , The register CNTR1[n:1] is loaded into CNTR2[n:1], the register CNTF1[n:1] is loaded into CNTF2[n:1]; when a falling edge is detected, the counter Counter[n:1] is loaded into the register CNTF1 [n:1];
  • Step S3 Decimal coding; after the rising or falling edge of the pulse signal on the input pin Input, the result of the sampling in the register CAP[i:1] is captured after the rising edge of the next sampling clock to encode, and the pulse edge is found The position of propagation on the delay unit DLL chain;
  • Step S4 Step information calibration; monitoring step information STEP[m:1], that is, the number of delay units that the signal on the input pin Input can propagate through in the signal capture chain within a sampling clock period 1/f .
  • Step S5 Generate an interrupt; select the interrupt control logic to generate an interrupt on the rising edge or the falling edge, and notify the main control device to read the pulse signal measurement result;
  • Step S6 Calculation; the software is based on the registers CNTR1[n:1], CNTR2[n:1], CNTF1[n:1], CNTF2[n:1], and the registers ENCR1[m:1], ENCR2[m:1] , ENCF1[m:1], ENCF2[m:1], and the information in the step size register STEP[m:1], calculate the width of the high and low pulses before the interrupt occurs.
  • the step S4 includes:
  • Step S401 Generate an internal input signal and a sampling control signal; the calibration control logic generates an internal input pulse signal and two sampling control signals after a period of time when the edge detection logic detects the rising edge of the signal on the input pin Input; The input pulse signal is used as the input of the signal capture chain; the sampling control signal controls the timing of sampling the output level value of each delay unit DLL;
  • Step S402 sampling; after the sampling control signal occurs, the output of each delay unit DLL is sampled on the rising edge of the next sampling clock HRCAPCLK, and the result is stored in the capture register; the sampling process is performed twice;
  • Step S403 Encoding; the encoder encodes two consecutive sampling results, and the encoded results are respectively stored in the calibration register;
  • Step S404 calculation; assuming that the time interval of 2 sampling is a positive integer ⁇ sampling clock cycles, the calculation method of STEP is:
  • the digital pulse signal width measurement circuit and measurement method of the present invention have the advantages of high accuracy, simple structure, low resource overhead, etc., and can accurately measure the width of the digital pulse signal without increasing the sampling clock frequency. If a 100MHz sampling clock is used, the accuracy can reach the order of 100ps.
  • the digital pulse signal width measurement circuit and measurement method of the present invention can dynamically calibrate the measurement accuracy in real time according to changes in the actual working environment (such as temperature, operating voltage), with a wide application range, high measurement accuracy, and calibration without Come software overhead.
  • Figure 1 is a schematic diagram of the principle of digital pulse signal measurement.
  • Fig. 2 is a schematic diagram of the structure principle of the measuring circuit in a specific application example of the present invention.
  • Fig. 3 is a schematic diagram of the principle of the measurement method of the present invention in a specific application example.
  • FIG. 2 it is a schematic diagram of the structure of the ultra-high-precision digital pulse signal width measurement circuit of the present invention in a specific application example.
  • the sampling clock and its connection with other circuits are not shown in FIG. 2, but this does not hinder the understanding of the technical solution of the present invention by those of ordinary skill in the art, and does not affect the actual protection scope of the present invention.
  • the ultra-high-precision digital pulse signal width measurement circuit of the present invention includes an edge detection and interrupt control unit, an integer encoding unit, a signal capture chain, a decimal encoding unit, a calibration control unit, and a sampling clock HRCAPCLK; among them:
  • the edge detection and interrupt control unit is used to detect the rising and falling edges of the pulse signal on the input pin Input, and then control the integer encoding unit, decimal encoding unit, calibration control unit, and signal acquisition on the signal capture chain.
  • the rising edge of the pulse signal indicates the beginning of the high level and the end of the low level
  • the falling edge indicates the end of the high level and the beginning of the low level.
  • Output Rise, Fall, Rise_or_Fall indicates that the rising edge, falling edge, rising or falling edge is detected;
  • the integer coding unit is used to measure the integer part ⁇ of the width of the high or low level on the input pin Input with 1 cycle 1/f of the sampling clock HRCAPCLK as the reference unit;
  • the signal capture chain is used to sample the output level value of each delay unit DLL after the rising edge and falling edge of the pulse signal on the input pin Input occur, and the next rising edge of the HRCAPCLK clock comes;
  • the decimal encoding unit when the edge of the pulse signal on the input pin Input is not aligned with the edge of the sampling clock HRCAPCLK, the result of the pulse width measurement will produce a decimal value. As shown in Figure 1, the decimal value is composed of two parts, namely 1- ⁇ and 1- ⁇ .
  • the function of the decimal encoding unit is to find and record the position of the pulse edge propagating on the signal capture chain according to the sampling result of the signal capture chain (capture register CAP);
  • the calibration control unit after detecting the rising edge of the signal on the input pin Input, generates an internal input signal and a sampling control signal, and the control signal capture chain samples the output of the delay unit DLL twice.
  • the 2 sampling results of the signal capture chain are encoded and stored in the calibration register; the step length information is calculated according to the calibration register, and the result is stored in the step length register.
  • the purpose of the interrupt control of the edge detection and interrupt control unit is to generate an interrupt signal Interrupt when the rising or falling edge of the pulse signal on the input pin Input is detected, so as to notify the main control device to read the measurement result of the pulse signal .
  • the measurement results are stored in registers in integer coding and decimal coding logic.
  • the integer coding logic includes a counter Counter[n:1], 4 registers CNTR1[n:1], CNTR2[n:1], CNTF1[n:1], CNTF2[n:1]. Among them, the counter Counter[n:1] starts counting from 0 after the edge detection logic detects the rising or falling edge of the pulse.
  • the counter Counter[n:1] When a rising edge is detected, the counter Counter[n:1] is loaded into the register CNTR1[n:1] to record the measurement results before the rising edge, the register CNTR1[n:1] is loaded into CNTR2[n:1], and the register CNTF1 [n:1] is loaded into CNTF2[n:1]; when a falling edge is detected, the counter Counter[n:1] is loaded into the register CNTF1[n:1] to record the measurement result before the falling edge.
  • the signal capture chain includes a set of delay units DLL and capture register CAP.
  • the number of delay units and registers are equal, set to a positive integer i.
  • a certain amount of delay will be generated, which is set to ⁇ .
  • ⁇ will vary with the working environment of the circuit. For example, when the temperature rises or the working voltage drops, ⁇ will increase; when the temperature drops or the working voltage rises, ⁇ will decrease.
  • the function of the capture register CAP is to sample the output level value of each delay unit DLL after the rising edge and falling edge of the pulse signal on the input pin Input occur, and the next rising edge of the HRCAPCLK clock comes.
  • the decimal encoding unit includes encoder R, encoder F, encoding register ENCR1[m:1], ENCR2[m:1], ENCF1[m:1], ENCF2[m:1], calibration register CALR1[m:1], CALR2[m:1], step size register STEP[m:1].
  • the relationship between the number m of the encoding register ENCR1[m:1] and the number i of the delay unit DLL in the signal capture chain is:
  • the edge detection logic detects the rising edge of the pulse signal on the input pin Input
  • the output of the capture register CAP is encoded by the encoder R, and the result is retained in the register ENCR1[m:1]
  • edge detection logic After detecting the falling edge of the pulse signal, the output of the capture register CAP is encoded by the encoder F, and the result is retained in the register ENCF1[m:1].
  • the register ENCR1[m:1] is loaded into ENCR2[m:1]
  • the register ENCF1[m:1] is loaded into ENCF2[m:1].
  • the calibration registers CALR1[m:1] and CALR2[m:1] are used to record the propagation position of the pulse edge on the delay unit DLL chain under the control of the calibration controller.
  • the value of the step size register STEP[m:1] represents the number of delay units that the signal on the input pin Input can propagate through in the signal capture chain within a sampling clock cycle 1/f.
  • STEP[m:1] is calculated based on the calibration registers CALR1[m:1] and CALR2[m:1].
  • the function of the calibration control unit is to generate an internal input signal and a sampling control signal after detecting the rising edge of the signal on the input pin Input, and control the capture register CAP to sample the output of the delay unit DLL twice.
  • the 2 sampling results of the capture register CAP are encoded by the encoder R and stored in the calibration registers CALR1[m:1], CALR2[m:1].
  • the step length information is calculated according to the calibration registers CALR1[m:1] and CALR2[m:1], and the result is stored in the step length register STEP[m:1].
  • the relationship between the frequency f of the sampling clock and the delay ⁇ of the delay unit and the number i of the delay unit is:
  • the present invention further provides an ultra-high-precision digital pulse signal width measurement method, including:
  • Step S1 Edge detection; that is, after the edge detection logic detects the rising edge or the falling edge of the pulse signal on the input pin Input, the Rise, Fall, and Rise_or_Fall pulse signals are generated.
  • the Rise, Fall, and Rise_or_Fall pulse signals are used to: 1) Control the Counter in the integer coding unit to restart counting from 0, 2) Control the output level of the signal capture chain sampling DLL; 3) Control the encoder R, in the fractional coding unit F encodes the result in the capture register CAP;
  • Step S2 Integer coding; after detecting the rising or falling edge of the pulse, the counter Counter[n:1] starts to count from 0; when the rising edge is detected, the counter[n:1] is loaded into the register CNTR1[n:1] , The register CNTR1[n:1] is loaded into CNTR2[n:1], the register CNTF1[n:1] is loaded into CNTF2[n:1]; when a falling edge is detected, the counter Counter[n:1] is loaded into the register CNTF1 [n:1];
  • Step S3 Decimal coding; after the rising or falling edge of the pulse signal on the input pin Input, the result of the sampling in the register CAP[i:1] is captured after the rising edge of the next sampling clock to encode, and the pulse edge is found The position of propagation on the delay unit DLL chain;
  • Step S4 Step information calibration; monitoring step information STEP[m:1], that is, the number of delay units that the signal on the input pin Input can propagate through in the signal capture chain within a sampling clock period 1/f .
  • Step S5 Generate an interrupt; select the interrupt control logic to generate an interrupt on the rising edge or the falling edge, and notify the main control device to read the pulse signal measurement result;
  • Step S6 Calculation; the software is based on the registers CNTR1[n:1], CNTR2[n:1], CNTF1[n:1], CNTF2[n:1], and the registers ENCR1[m:1], ENCR2[m:1] , ENCF1[m:1], ENCF2[m:1], and the information in the step size register STEP[m:1], calculate the width of the high and low pulses before the interrupt occurs.
  • the ultra-high-precision digital pulse signal width measurement in the present invention can be divided into a rising edge measurement mode and a falling edge measurement mode according to the position of the edge where the interrupt occurs.
  • the widths of the high and low pulses before the interrupt occurs are:
  • the widths of the high and low pulses before the interrupt occurs are:
  • decimal encoding in the present invention is to encode the result (stored in the capture register CAP[i:1]) sampled on the rising edge of the next sampling clock HRCAPCLK after the rising edge of the pulse signal on the input pin Input comes;
  • the function of the encoder R and the encoder F is to find the position of the pulse edge propagating on the delay unit DLL chain according to the sampling result of the capture register CAP[i:1].
  • the encoded position information is stored in the registers ENCR1[m:1] and ENCF1[m:1].
  • the encoder R encodes the sampling result in the capture register CAP[i:1].
  • the coding rules are:
  • Encoder F encodes the sampling result in the capture register CAP[i:1].
  • the coding rules are:
  • step information calibration in the present invention is as follows:
  • Step S401 Generate an internal input signal and a sampling control signal.
  • the calibration control logic generates an internal input pulse signal and 2 sampling control signals after a period of time when the edge detection logic detects the rising edge of the signal on the input pin Input.
  • the internal input pulse signal is used as the input of the signal capture chain; the sampling control signal controls the timing of sampling the output level value of each delay unit DLL.
  • Step S402 sampling. After the sampling control signal occurs, the output of each delay unit DLL is sampled on the rising edge of the next sampling clock HRCAPCLK, and the result is stored in the capture register CAP[i:1]. The sampling process is carried out twice.
  • Step S403 encoding.
  • Encoder R encodes two consecutive sampling results, and the encoded results are stored in calibration registers CALR1[m:1] and CALR2[m:1] respectively.
  • Step S404 calculation. Assuming that the time interval of 2 samplings is a positive integer ⁇ sampling clock cycles, the calculation method of STEP is:

Abstract

一种数字脉冲信号宽度测量电路及测量方法，该测量电路包括：采样时钟，用于驱动电路中的所有寄存器；边沿检测与中断控制单元，用于检测输入引脚Input上脉冲信号的上升沿、下降沿，进而对信号采集进行控制；整数编码单元，包括计数器和寄存器，用来以采样时钟的1个周期1/f为基准单位，测量输入引脚Input上高或低电平的宽度的整数部分μ；信号捕捉链，用来采样每个延时单元DLL的输出电平值；小数编码单元，用来找出并记录脉冲边沿在信号捕捉链上传播的位置；校准控制单元，用来进行校准。该测量方法基于上述测量电路来实现。本发明具有精度高、结构简单、资源开销小等优点。

Description

一种数字脉冲信号宽度测量电路及测量方法
相关申请的交叉引用
本申请以申请日为“2020-05-14”、申请号为“202010404936.6”、发明创造名称为“一种数字脉冲信号宽度测量电路及测量方法”的中国专利申请为基础，并主张其优先权，该中国专利申请的全文在此引用至本申请中，以作为本申请的一部分。
【技术领域】
本发明主要涉及到高精度数字脉冲信号测量技术领域，特指一种数字脉冲信号宽度测量电路及测量方法。
【背景技术】
大量工业级和消费类设备、仪器中，普遍需要对电压、电流、电容、速度、距离等信号进行测量，测量精度直接影响设备、仪器的精度。
高精度数字脉冲信号宽度测量广泛引用于精密仪器、声呐、机器人伺服、开关电源、功率器件、触摸屏等设备中的脉冲序列周期/占空比测量、瞬时速度测量、穿越隔离边界的电压测量、距离/声呐测量和扫描、容感触摸感知等应用。
数字信号处理器件中，信号测量一般是先将电压、电容、速度、距离等信号经模拟数字转换量化成数字脉冲信号，再对数字脉冲信号进行测量。如图1所示，数字脉冲信号宽度测量就是采用一个采样时钟(频率为f)，以一个时钟周期为基准单位，将一个脉冲信号的宽度表示成一个包含整数部分和小数部分的实数。图1中，整数部分用μ表示；小数部分是因脉冲信号的边沿与采样时钟的边沿不对齐产生，来源于脉冲的头部和尾部，即1-α、1–β。在图1中，高电平脉冲信号的宽度λ与f、μ、α、β的关系为：
λ＝(μ+1-α-β)×1/f   (1)
传统数字信号测量电路的测量精度为1个采样时钟周期1/f，只能测量信号宽度λ的整数部分μ，无法测量信号宽度的小数部分1-α-β。如要提高测量精度，只能提高采样时钟的频率，从而极大地增加了硬件电路的功耗和复杂度。
如在专利US 8384440B2中所实现的脉冲信号宽度测量就具有高精度的特点，并且不需要高频的采样时钟。但该方法限制了采样时钟的工作范围，同时，因需要一条单独的捕捉延时链并周期性地执行软件校准程序，增加了软硬件开销。
【发明内容】
本发明要解决的技术问题就在于：针对现有技术存在的技术问题，本发明提供一种具 有精度高、结构简单、资源开销小的超高精度数字脉冲信号宽度测量电路及测量方法。
为解决上述技术问题，本发明采用以下技术方案：
一种数字脉冲信号宽度测量电路，其包括：
采样时钟，用于驱动电路中的所有寄存器；
边沿检测与中断控制单元，用于检测输入引脚Input上脉冲信号的上升沿、下降沿，进而对信号采集进行控制；
整数编码单元，包括计数器和寄存器，用来以采样时钟的1个周期1/f为基准单位，测量输入引脚Input上高或低电平的宽度的整数部分μ；
信号捕捉链，包括一组延时单元DLL和捕捉寄存器CAP，所述延时单元DLL和捕捉寄存器CAP的数量相等，设为正整数i；输入引脚Input上的信号每传播经过一个延时单元时会产生一定量的延时，设为δ；所述信号捕捉链用来在输入引脚Input上脉冲信号的上升沿、下降沿发生后，下一个时钟上升沿来临时采样每个延时单元DLL的输出电平值；
小数编码单元，用来根据信号捕捉链的采样结果，找出并记录脉冲边沿在信号捕捉链上传播的位置；
校准控制单元，在检测到输入引脚Input上信号的上升沿后，产生内部输入信号和采样控制信号，控制信号捕捉链对延时单元DLL的输出进行采样；采样结果经编码后保存在校准寄存器中；步长信息是根据校准寄存器计算得出。
作为本发明测量电路的进一步改进：所述边沿检测与中断控制单元在进行中断控制时，在检测到输入引脚Input上脉冲信号的上升沿或下降沿时产生中断信号Interrupt，以通知主控设备读取脉冲信号测量结果；测量结果保存在整数编码、小数编码逻辑中的寄存器中。
作为本发明测量电路的进一步改进：所述整数编码单元包括一个计数器Counter[n:1]、4个寄存器CNTR1[n:1]、CNTR2[n:1]、CNTF1[n:1]、CNTF2[n:1]；所述计数器Counter[n:1]在边沿检测逻辑检测到脉冲上升或下降沿后开始从0计数；检测到上升沿时，计数器Counter[n:1]加载到寄存器CNTR1[n:1]以记录上升沿来临前的测量结果，寄存器CNTR1[n:1]加载到CNTR2[n:1]，寄存器CNTF1[n:1]加载到CNTF2[n:1]；检测到下降沿时，计数器Counter[n:1]加载到寄存器CNTF1[n:1]以记录下降沿来临前的测量结果。
作为本发明测量电路的进一步改进：所述捕捉寄存器CAP[i:1]用来在输入引脚Input上脉冲信号的上升沿、下降沿发生后，下一个时钟上升沿来临时采样每个延时单元DLL的输出电平值。
作为本发明测量电路的进一步改进：所述小数编码单元包括编码器R、编码器F，编码寄存器ENCR1[m:1]、ENCR1[m:1]、ENCF1[m:1]、ENCF2[m:1]，校准寄存器CALR1[m:1]、 CALR2[m:1]，步长寄存器STEP[m:1]；所述编码寄存器ENCR1[m:1]的数量m与信号捕捉链中延时单元DLL的数量i之间的关系为：
m＝log 2i。
作为本发明测量电路的进一步改进：当进行边沿检测时，在检测到输入引脚Input上脉冲信号的上升沿来临后，捕捉寄存器CAP的输出经编码器R编码，结果保留在寄存器ENCR1[m:1]中；在检测到脉冲信号的下降沿来临后，捕捉寄存器CAP的输出经编码器F编码，结果保留在寄存器ENCF1[m:1]中；在检测到上升沿时，寄存器ENCR1[m:1]加载到ENCR2[m:1]，寄存器ENCF1[m:1]加载到ENCF2[m:1]。
作为本发明测量电路的进一步改进：所述校准寄存器CALR1[m:1]、CALR2[m:1]的用来在校准控制单元的控制下，记录脉冲边沿在延时单元DLL链上传播的位置；所述步长寄存器STEP[m:1]的值表示一个采样时钟周期1/f内，输入引脚Input上的信号在信号捕捉链上可以传播经过的延时单元的数量；所述STEP[m:1]是根据校准寄存器CALR1[m:1]、CALR2[m:1]计算得出。
作为本发明测量电路的进一步改进：所述采样时钟的频率f与延时单元的延时δ、延时单元的数量i之间的关系是：
1/f<i×δ，其中i为正整数。
本发明进一步提供一种数字脉冲信号宽度测量方法，其包括：
步骤S1：边沿检测；即在边沿检测逻辑检测到输入引脚Input上脉冲信号的上升沿或下降沿后，产生Rise、Fall、Rise_or_Fall脉冲信号。Rise、Fall、Rise_or_Fall脉冲信号用于：1)控制整数编码单元中的Counter从0开始重新计数，2)控制信号捕捉链采样DLL的输出电平；3)控制小数编码单元中的编码器R、F对捕捉寄存器CAP中的结果进行编码；
步骤S2：整数编码；在检测到脉冲上升或下降沿后，计数器Counter[n:1]开始从0计数；检测到上升沿时，计数器Counter[n:1]加载到寄存器CNTR1[n:1]，寄存器CNTR1[n:1]加载到CNTR2[n:1]，寄存器CNTF1[n:1]加载到CNTF2[n:1]；检测到下降沿时，计数器Counter[n:1]加载到寄存器CNTF1[n:1]；
步骤S3:小数编码；对输入引脚Input上脉冲信号的上升沿或下降沿来临后，下一个采样时钟上升沿后捕捉寄存器CAP[i:1]中采样到的结果进行编码，找出脉冲边沿在延时单元DLL链上传播的位置；
步骤S4:步长信息校准；监测步长信息STEP[m:1]，即一个采样时钟周期1/f内，输入引脚Input上的信号在信号捕捉链上可以传播经过的延时单元的数量。
步骤S5：产生中断；中断控制逻辑中选择在上升沿或下降沿产生中断，通知主控设备读取脉冲信号测量结果；
步骤S6：计算；软件根据寄存器CNTR1[n:1]、CNTR2[n:1]、CNTF1[n:1]、CNTF2[n:1]，寄存器ENCR1[m:1]、ENCR2[m:1]、ENCF1[m:1]、ENCF2[m:1]，和步长寄存器STEP[m:1]中的信息，计算出中断发生前高、低电平脉冲的宽度。
作为本发明测量方法的进一步改进：所述步骤S4包括：
步骤S401：产生内部输入信号和采样控制信号；校准控制逻辑在边沿检测逻辑检测到输入引脚Input上信号的上升沿的一段时间间隔之后，产生一个内部输入脉冲信号，2个采样控制信号；内部输入脉冲信号作为信号捕捉链的输入；采样控制信号控制采样每个延时单元DLL的输出电平值的时机；
步骤S402：采样；采样控制信号发生后，在下一个采样时钟HRCAPCLK上升沿采样每个延时单元DLL的输出，结果保存在捕捉寄存器中；采样过程进行2次；
步骤S403：编码；编码器对连续两次采样结果进行编码，编码后的结果分别保存在校准寄存器中；
步骤S404：计算；设2次采样的时间间隔为正整数ω个采样时钟周期，则STEP的计算方式为：
STEP＝(CALR1–CALR2)/ω。
与现有技术相比，本发明的优点在于：
1、本发明的数字脉冲信号宽度测量电路及测量方法，具有精度高、结构简单、资源开销小等优点，在不需要提高采样时钟频率的情况下，可精确测量数字脉冲信号宽度。如采用100MHz的采样时钟，精度可达到100ps量级。
2、本发明的数字脉冲信号宽度测量电路及测量方法，能够根据实际工作环境(如温度、工作电压)的变化，动态实时地校准测量精度，适用范围广、测量精度高，且校准不会带来软件开销。
【附图说明】
图1是数字脉冲信号测量的原理示意图。
图2是本发明在具体应用实例中测量电路的结构原理示意图。
图3是本发明在具体应用实例中测量方法的原理示意图。
【具体实施方式】
以下将结合说明书附图和具体实施例对本发明做进一步详细说明。
如图2所示，为本发明的超高精度数字脉冲信号宽度测量电路在具体应用实例中的结 构原理图。为简化起见，在图2中并未画出采样时钟及其与其它电路的连接关系，但这不妨碍本领域普通人员对于本发明技术方案的理解，也不影响本发明的实际保护范围。
本发明的超高精度数字脉冲信号宽度测量电路，包括边沿检测与中断控制单元、整数编码单元、信号捕捉链、小数编码单元、校准控制单元、采样时钟HRCAPCLK；其中：
采样时钟HRCAPCLK，用于驱动电路中的所有寄存器；
边沿检测与中断控制单元，用于检测输入引脚Input上脉冲信号的上升沿、下降沿，进而控制整数编码单元、小数编码单元、校准控制单元、以及信号捕捉链上的信号采集。其中，脉冲信号的上升沿表示高电平的开始、低电平的结束，下降沿表示高电平的结束、低电平的开始。输出Rise、Fall、Rise_or_Fall表示检测到上升沿、下降沿、上升或下降沿；
整数编码单元，用来以采样时钟HRCAPCLK的1个周期1/f为基准单位，测量输入引脚Input上高或低电平的宽度的整数部分μ；
信号捕捉链，用来在输入引脚Input上脉冲信号的上升沿、下降沿发生后，下一个HRCAPCLK时钟上升沿来临时采样每个延时单元DLL的输出电平值；
小数编码单元，当输入引脚Input上脉冲信号的边沿与采样时钟HRCAPCLK的边沿不对齐时，脉冲宽度测量的结果会产生小数值。如图1所示，小数值由2个部分组成，即1-α、1–β。小数编码单元的作用是用来根据信号捕捉链(捕捉寄存器CAP)的采样结果，找出并记录脉冲边沿在信号捕捉链上传播的位置；
校准控制单元，在检测到输入引脚Input上信号的上升沿后，产生内部输入信号和采样控制信号，控制信号捕捉链对延时单元DLL的输出进行2次采样。信号捕捉链的2次采样结果经编码后保存在校准寄存器中；步长信息是根据校准寄存器计算得出，结果保存在步长寄存器中。
在具体应用实例中，边沿检测与中断控制单元的中断控制目的就是在检测到输入引脚Input上脉冲信号的上升沿或下降沿时产生中断信号Interrupt，以通知主控设备读取脉冲信号测量结果。测量结果保存在整数编码、小数编码逻辑中的寄存器中。
在具体应用实例中，整数编码逻辑包括一个计数器Counter[n:1]、4个寄存器CNTR1[n:1]、CNTR2[n:1]、CNTF1[n:1]、CNTF2[n:1]。其中计数器Counter[n:1]在边沿检测逻辑检测到脉冲上升或下降沿后开始从0计数。检测到上升沿时，计数器Counter[n:1]加载到寄存器CNTR1[n:1]以记录上升沿来临前的测量结果，寄存器CNTR1[n:1]加载到CNTR2[n:1]，寄存器CNTF1[n:1]加载到CNTF2[n:1]；检测到下降沿时，计数器Counter[n:1]加载到寄存器CNTF1[n:1]以记录下降沿来临前的测量结果。
在具体应用实例中，信号捕捉链包括一组延时单元DLL和捕捉寄存器CAP。延时单 元和寄存器的数量相等，设为正整数i。输入引脚Input上的信号每传播经过一个延时单元时会产生一定量的延时，设为δ。δ会随电路的工作环境而变化。如温度上升或工作电压下降时，δ会增大；温度下降或工作电压升高时，δ会减小。捕捉寄存器CAP的作用是在输入引脚Input上脉冲信号的上升沿、下降沿发生后，下一个HRCAPCLK时钟上升沿来临时采样每个延时单元DLL的输出电平值。
在具体应用实例中，小数编码单元包括编码器R、编码器F，编码寄存器ENCR1[m:1]、ENCR2[m:1]、ENCF1[m:1]、ENCF2[m:1]，校准寄存器CALR1[m:1]、CALR2[m:1]，步长寄存器STEP[m:1]。编码寄存器ENCR1[m:1]的数量m与信号捕捉链中延时单元DLL的数量i之间的关系为：
m＝log 2i   (2)
在具体应用实例中，边沿检测逻辑检测到输入引脚Input上脉冲信号的上升沿来临后，捕捉寄存器CAP的输出经编码器R编码，结果保留在寄存器ENCR1[m:1]中；边沿检测逻辑检测到脉冲信号的下降沿来临后，捕捉寄存器CAP的输出经编码器F编码，结果保留在寄存器ENCF1[m:1]中。检测到上升沿时，寄存器ENCR1[m:1]加载到ENCR2[m:1]，寄存器ENCF1[m:1]加载到ENCF2[m:1]。
在具体应用实例中，校准寄存器CALR1[m:1]、CALR2[m:1]的作用是在校准控制器的控制下，记录脉冲边沿在延时单元DLL链上传播的位置。步长寄存器STEP[m:1]的值表示一个采样时钟周期1/f内，输入引脚Input上的信号在信号捕捉链上可以传播经过的延时单元的数量。STEP[m:1]是根据校准寄存器CALR1[m:1]、CALR2[m:1]计算得出。
由于信号捕捉链中延时单元DLL的延时δ会随电路的工作环境而变化，为了精确表示脉冲测量结果的小数部分，需要动态监测步长信息STEP，即一个采样时钟周期1/f内，输入引脚Input上的信号在信号捕捉链上可以传播经过的延时单元的数量。校准控制单元的作用是在检测到输入引脚Input上信号的上升沿后，产生内部输入信号和采样控制信号，控制捕捉寄存器CAP对延时单元DLL的输出进行2次采样。捕捉寄存器CAP的2次采样结果经编码器R编码后保存在校准寄存器CALR1[m:1]、CALR2[m:1]中。步长信息是根据校准寄存器CALR1[m:1]、CALR2[m:1]计算得出，结果保存在步长寄存器STEP[m:1]中。
在具体应用实例中，采样时钟的频率f与延时单元的延时δ、延时单元的数量i之间的关系是：
1/f<i×δ，i为正整数   (3)
如图3所示，本发明进一步提供一种超高精度数字脉冲信号宽度测量方法，包括：
步骤S1：边沿检测；即在边沿检测逻辑检测到输入引脚Input上脉冲信号的上升沿或下降沿后，产生Rise、Fall、Rise_or_Fall脉冲信号。Rise、Fall、Rise_or_Fall脉冲信号用于：1)控制整数编码单元中的Counter从0开始重新计数，2)控制信号捕捉链采样DLL的输出电平；3)控制小数编码单元中的编码器R、F对捕捉寄存器CAP中的结果进行编码；
步骤S2：整数编码；在检测到脉冲上升或下降沿后，计数器Counter[n:1]开始从0计数；检测到上升沿时，计数器Counter[n:1]加载到寄存器CNTR1[n:1]，寄存器CNTR1[n:1]加载到CNTR2[n:1]，寄存器CNTF1[n:1]加载到CNTF2[n:1]；检测到下降沿时，计数器Counter[n:1]加载到寄存器CNTF1[n:1]；
步骤S3:小数编码；对输入引脚Input上脉冲信号的上升沿或下降沿来临后，下一个采样时钟上升沿后捕捉寄存器CAP[i:1]中采样到的结果进行编码，找出脉冲边沿在延时单元DLL链上传播的位置；
步骤S4:步长信息校准；监测步长信息STEP[m:1]，即一个采样时钟周期1/f内，输入引脚Input上的信号在信号捕捉链上可以传播经过的延时单元的数量。
步骤S5：产生中断；中断控制逻辑中选择在上升沿或下降沿产生中断，通知主控设备读取脉冲信号测量结果；
步骤S6：计算；软件根据寄存器CNTR1[n:1]、CNTR2[n:1]、CNTF1[n:1]、CNTF2[n:1]，寄存器ENCR1[m:1]、ENCR2[m:1]、ENCF1[m:1]、ENCF2[m:1]，和步长寄存器STEP[m:1]中的信息，计算出中断发生前高、低电平脉冲的宽度。
在具体应用实例中，根据中断发生的边沿位置不同，本发明中的超高精度数字脉冲信号宽度测量可以分为上升沿测量模式和下降沿测量模式。
1)、上升沿测量模式；
如图3所示，此时，中断发生前的高、低电平脉冲的宽度分别为：
PWD_H0＝PWD(B)＝CNTR2+(ENCF2-ENCR2)/STEP           (4)
PWD_L0＝PWD(A)＝CNTR1+(ENCR1-ENCF2)/STEP           (5)
2)、下降沿测量模式；
如图3所示，此时，中断发生前的高、低电平脉冲的宽度分别为：
PWD_H1＝PWD(C’)＝CNTF2+(ENCF2-ENCR2)/STEP          (6)
PWD_H0＝PWD(A’)＝CNTF1+(ENCF1-ENCR1)/STEP          (7)
PWD_L0＝PWD(B’)＝CNTR1+(ENCR1-ENCF2)/STEP          (8)
本发明中的小数编码的目的在于对输入引脚Input上脉冲信号的上升沿来临后，下一个采样时钟HRCAPCLK上升沿采样到的结果(保存在捕捉寄存器CAP[i:1]中)进行编码；
即，结合图2中的电路可知，编码器R、编码器F的作用是根据捕捉寄存器CAP[i:1]的采样结果，找出脉冲边沿在延时单元DLL链上传播的位置。编码后的位置信息保存在寄存器ENCR1[m:1]、ENCF1[m:1]中。
编码器R是对捕捉寄存器CAP[i:1]中的采样结果进行编码。
在具体应用实例中，编码规则为：
Figure PCTCN2021089530-appb-000001
若
Figure PCTCN2021089530-appb-000002
使得
Figure PCTCN2021089530-appb-000003
且CAP[i]＝0，则：
ENCR1[m:1]＝x   (9)
编码器F是对捕捉寄存器CAP[i:1]中的采样结果进行编码。
在具体应用实例中，编码规则为：
Figure PCTCN2021089530-appb-000004
若
Figure PCTCN2021089530-appb-000005
使得
Figure PCTCN2021089530-appb-000006
且CAP[i]＝1，则：
ENCF1[m:1]＝x   (10)
本发明中的步长信息校准的流程如下：
步骤S401：产生内部输入信号和采样控制信号。校准控制逻辑在边沿检测逻辑检测到输入引脚Input上信号的上升沿的一段时间间隔之后，产生一个内部输入脉冲信号，2个采样控制信号。内部输入脉冲信号作为信号捕捉链的输入；采样控制信号控制采样每个延时单元DLL的输出电平值的时机。
步骤S402：采样。采样控制信号发生后，在下一个采样时钟HRCAPCLK上升沿采样每个延时单元DLL的输出，结果保存在捕捉寄存器CAP[i:1]中。采样过程进行2次。
步骤S403：编码。编码器R对连续两次采样结果进行编码，编码后的结果分别保存在校准寄存器CALR1[m:1]、CALR2[m:1]中。
步骤S404：计算。设2次采样的时间间隔为正整数ω个采样时钟周期，则STEP的计算方式为：
STEP＝(CALR1–CALR2)/ω   (11)。
以上仅是本发明的优选实施方式，本发明的保护范围并不仅局限于上述实施例，凡属于本发明思路下的技术方案均属于本发明的保护范围。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理前提下的若干改进和润饰，应视为本发明的保护范围。

Claims (10)

  1. 一种数字脉冲信号宽度测量电路，其特征在于，包括：
    采样时钟，用于驱动电路中的所有寄存器；
    边沿检测与中断控制单元，用于检测输入引脚Input上脉冲信号的上升沿、下降沿，进而对信号采集进行控制；
    整数编码单元，包括计数器和寄存器，用来以采样时钟的1个周期1/f为基准单位，测量输入引脚Input上高或低电平的宽度的整数部分μ；
    信号捕捉链，包括一组延时单元DLL和捕捉寄存器CAP，所述延时单元DLL和捕捉寄存器CAP的数量相等，设为正整数i；输入引脚Input上的信号每传播经过一个延时单元时会产生一定量的延时，设为δ；所述信号捕捉链用来在输入引脚Input上脉冲信号的上升沿、下降沿发生后，下一个时钟上升沿来临时采样每个延时单元DLL的输出电平值；
    小数编码单元，用来根据信号捕捉链的采样结果，找出并记录脉冲边沿在信号捕捉链上传播的位置；
    校准控制单元，在检测到输入引脚Input上信号的上升沿后，产生内部输入信号和采样控制信号，控制信号捕捉链对延时单元DLL的输出进行采样；采样结果经编码后保存在校准寄存器中；步长信息是根据校准寄存器计算得出。
  2. 根据权利要求1所述的数字脉冲信号宽度测量电路，其特征在于，所述边沿检测与中断控制单元在进行中断控制时，在检测到输入引脚Input上脉冲信号的上升沿或下降沿时产生中断信号Interrupt，以通知主控设备读取脉冲信号测量结果；测量结果保存在整数编码、小数编码逻辑中的寄存器中。
  3. 根据权利要求1所述的数字脉冲信号宽度测量电路，其特征在于，所述整数编码单元包括一个计数器Counter[n:1]、4个寄存器CNTR1[n:1]、CNTR2[n:1]、CNTF1[n:1]、CNTF2[n:1]；所述计数器Counter[n:1]在边沿检测逻辑检测到脉冲上升或下降沿后开始从0计数；检测到上升沿时，计数器Counter[n:1]加载到寄存器CNTR1[n:1]以记录上升沿来临前的测量结果，寄存器CNTR1[n:1]加载到CNTR2[n:1]，寄存器CNTF1[n:1]加载到CNTF2[n:1]；检测到下降沿时，计数器Counter[n:1]加载到寄存器CNTF1[n:1]以记录下降沿来临前的测量结果。
  4. 根据权利要求1或2或3所述的数字脉冲信号宽度测量电路，其特征在于，所述捕捉寄存器CAP用来在输入引脚Input上脉冲信号的上升沿、下降沿发生后，下一个时钟上升沿来临时采样每个延时单元DLL的输出电平值。
  5. 根据权利要求1或2或3所述的数字脉冲信号宽度测量电路，其特征在于，所述小数编码单元包括编码器R、编码器F，编码寄存器ENCR1[m:1]、ENCR2[m:1]、ENCF1[m:1]、ENCF2[m:1]，校准寄存器CALR1[m:1]、CALR2[m:1]，步长寄存器STEP[m:1]；所述编码寄存器ENCR1[m:1]的数量m与信号捕捉链中延时单元DLL的数量i之间的关系为：
    m＝log 2i。
  6. 根据权利要求5所述的数字脉冲信号宽度测量电路，其特征在于，当进行边沿检测时，在检测到输入引脚Input上脉冲信号的上升沿来临后，捕捉寄存器CAP的输出经编码器R编码，结果保留在寄存器ENCR1[m:1]中；在检测到脉冲信号的下降沿来临后，捕捉寄存器CAP的输出经编码器F编码，结果保留在寄存器ENCF1[m:1]中；在检测到上升沿时，寄存器ENCR1[m:1]加载到ENCR2[m:1]，寄存器ENCF1[m:1]加载到ENCF2[m:1]。
  7. 根据权利要求5所述的数字脉冲信号宽度测量电路，其特征在于，所述校准寄存器CALR1[m:1]、CALR2[m:1]的用来在校准控制单元的控制下，记录脉冲边沿在延时单元DLL链上传播的位置；所述步长寄存器STEP[m:1]的值表示一个采样时钟周期1/f内，输入引脚Input上的信号在信号捕捉链上可以传播经过的延时单元的数量；所述STEP[m:1]是根据校准寄存器CALR1[m:1]、CALR2[m:1]计算得出。
  8. 根据权利要求1或2或3所述的数字脉冲信号宽度测量电路，其特征在于，所述采样时钟的频率f与延时单元的延时δ、延时单元的数量i之间的关系是：
    1/f<i×δ，其中i为正整数。
  9. 一种数字脉冲信号宽度测量方法，其特征在于，包括：
    步骤S1：边沿检测；即在边沿检测逻辑检测到输入引脚Input上脉冲信号的上升沿或下降沿后，产生Rise、Fall、Rise_or_Fall脉冲信号；
    步骤S2：整数编码；在检测到脉冲上升或下降沿后，计数器Counter[n:1]开始从0计数；检测到上升沿时，计数器Counter[n:1]加载到寄存器CNTR1[n:1]，寄存器CNTR1[n:1]加载到CNTR2[n:1]，寄存器CNTF1[n:1]加载到CNTF2[n:1]；检测到下降沿时，计数器Counter[n:1]加载到寄存器CNTF1[n:1]；
    步骤S3：小数编码；对输入引脚Input上脉冲信号的上升沿或下降沿来临后，下一个采样时钟上升沿后捕捉寄存器CAP[i:1]中采样到的结果进行编码，找出脉冲边沿在延时单元DLL链上传播的位置；
    步骤S4：步长信息校准；监测步长信息STEP[m:1]，即一个采样时钟周期1/f内，输入引脚Input上的信号在信号捕捉链上可以传播经过的延时单元的数量；
    步骤S5：产生中断；中断控制逻辑中选择在上升沿或下降沿产生中断，通知主控设备 读取脉冲信号测量结果；
    步骤S6：计算；软件根据寄存器CNTR1[n:1]、CNTR2[n:1]、CNTF1[n:1]、CNTF2[n:1]，寄存器ENCR1[m:1]、ENCR2[m:1]、ENCF1[m:1]、ENCF2[m:1]，和步长寄存器STEP[m:1]中的信息，计算出中断发生前高、低电平脉冲的宽度。
  10. 根据权利要求9所述的数字脉冲信号宽度测量方法，其特征在于，所述步骤S4包括：
    步骤S401：产生内部输入信号和采样控制信号；校准控制逻辑在边沿检测逻辑检测到输入引脚Input上信号的上升沿的一段时间间隔之后，产生一个内部输入脉冲信号，2个采样控制信号；内部输入脉冲信号作为信号捕捉链的输入；采样控制信号控制采样每个延时单元DLL的输出电平值的时机；
    步骤S402：采样；采样控制信号发生后，在下一个采样时钟HRCAPCLK上升沿采样每个延时单元DLL的输出，结果保存在捕捉寄存器中；采样过程进行2次；
    步骤S403：编码；编码器对连续两次采样结果进行编码，编码后的结果分别保存在校准寄存器中；
    步骤S404：计算；设2次采样的时间间隔为正整数ω个采样时钟周期，则STEP的计算方式为：
    STEP＝(CALR1–CALR2)/ω。
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