WO2021227673A1 - 一种高线性hemt器件及其制备方法 - Google Patents

一种高线性hemt器件及其制备方法 Download PDF

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Publication number
WO2021227673A1
WO2021227673A1 PCT/CN2021/082805 CN2021082805W WO2021227673A1 WO 2021227673 A1 WO2021227673 A1 WO 2021227673A1 CN 2021082805 W CN2021082805 W CN 2021082805W WO 2021227673 A1 WO2021227673 A1 WO 2021227673A1
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fluorine
layer
barrier layer
doped regions
region
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PCT/CN2021/082805
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English (en)
French (fr)
Inventor
郑雪峰
马晓华
唐振凌
马佩军
王冲
宓珉瀚
何云龙
王小虎
卢阳
杜鸣
郝跃
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西安电子科技大学
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Priority claimed from CN202010403434.1A external-priority patent/CN111668305A/zh
Priority claimed from CN202010402529.1A external-priority patent/CN111668303A/zh
Priority claimed from CN202010402538.0A external-priority patent/CN111668304A/zh
Application filed by 西安电子科技大学 filed Critical 西安电子科技大学
Priority to US17/355,644 priority Critical patent/US20210359121A1/en
Publication of WO2021227673A1 publication Critical patent/WO2021227673A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • the invention belongs to the technical field of semiconductors, and specifically relates to a high linear HEMT device and a preparation method thereof.
  • the traditional first-generation semiconductor materials represented by Si and the second-generation semiconductor materials represented by GaAs have gradually become difficult to meet the increasing frequency demand. Therefore, the third-generation semiconductor materials represented by GaN materials have received extensive attention.
  • GaN materials have the characteristics of high band gap, high breakdown field strength, and high electron velocity, which can achieve faster working speed and higher reliability.
  • the high electron mobility transistor (HEMT) made of AlGaN/GaN heterojunction has extremely high performance by virtue of the high concentration and high mobility two-dimensional electron gas (2DEG) formed at the heterojunction interface
  • Speed has broad application prospects in communications and other fields.
  • the linearity of semiconductor devices is an important parameter.
  • the transconductance of the device will increase first and then decrease after reaching a certain peak value as the gate-source bias voltage increases.
  • the phenomenon of transconductance drop will affect the linearity of the device and limit the working range of the device.
  • a gradient composition barrier structure is usually used to reduce the 2DEG concentration to increase the electron saturation speed or a Fin structure to reduce the source series resistance to ensure that the transconductance of the device remains stable in a larger gate voltage range, thereby improving the linearity of the device.
  • a Fin wide gradient structure or a barrier thickness gradient structure can also be used to improve the linearity of the device.
  • the use of a graded composition barrier structure that requires a barrier layer with a high Al composition will cause the deterioration of the surface quality of the device;
  • the use of Fin structure and Fin wide graded structure involves an etching process in the preparation process, which will introduce a large amount of etching Damage, the left sidewall of the channel will also generate a large amount of parasitic capacitance, which will affect the performance of the device; and the barrier thickness gradient structure requires precise etching depth control of the barrier layer structure, which is too difficult for the process.
  • the present invention provides a high linear HEMT device and a preparation method thereof.
  • the technical problem to be solved by the present invention is realized through the following technical solutions:
  • a high linear HEMT device from bottom to top, includes: a substrate layer, a buffer layer, a barrier layer, and a metal electrode layer.
  • the metal electrode layer includes a source electrode, a gate electrode, and a drain electrode from left to right; wherein,
  • the barrier layer includes a plurality of fluorine-doped regions F1 to Fm uniformly arranged in sequence, where m is a positive integer and m ⁇ 2, and the fluorine ion concentration of the plurality of fluorine-doped regions F1 to Fm includes at least two types.
  • the device further includes a dielectric layer, the dielectric layer is disposed between the source electrode and the drain electrode, and the gate electrode is disposed above the dielectric layer.
  • Another embodiment of the present invention also provides a high linear HEMT device, which includes a substrate layer, a buffer layer, a barrier layer, and a metal electrode layer from bottom to top.
  • the two ends of the metal electrode layer are provided with source electrodes and Drain electrode, a dielectric layer is arranged between the source electrode and the drain electrode, and the gate electrode is arranged above the dielectric layer; wherein, the dielectric layer includes a plurality of fluorine-doped regions F1 to Fm arranged uniformly in sequence. It is a positive integer and m ⁇ 2, and the fluorine ion concentration of the plurality of fluorine-doped regions F1 to Fm includes at least two types.
  • the fluorine-doped regions F1 to Fm are located under the gate electrode and arranged along the gate width direction.
  • the fluorine ion concentration of the fluorine-doped regions F1 to Fm sequentially increases or decreases from the fluorine-doped region F1 to the fluorine-doped region Fm.
  • the fluorine ion concentration of the fluorine-doped regions F1 to Fm sequentially increases or decreases from the fluorine-doped region F1 and the fluorine-doped region Fm to the middle.
  • the fluorine ion concentration of the fluorine-doped regions F1 to Fm includes two different concentrations, and the two fluorine-doped regions with different concentrations are arranged at intervals.
  • the device further includes at least one of a nucleation layer, an insertion layer, a capping layer, and a passivation layer; wherein,
  • the nucleation layer is disposed between the substrate layer and the buffer layer;
  • the insertion layer is arranged between the buffer layer and the barrier layer;
  • the cap layer is disposed between the barrier layer and the metal electrode layer;
  • the passivation layer is arranged in the area between the electrodes above the barrier layer.
  • a high linearity HEMT device which includes a substrate layer, a buffer layer, a barrier layer, and a metal electrode layer from bottom to top.
  • the metal electrode layer includes a source layer from left to right.
  • the negative ion concentration includes at least two kinds.
  • Another embodiment of the present invention also provides a high linear HEMT device, which includes a substrate layer, a buffer layer, a barrier layer, and a metal electrode layer from bottom to top.
  • the two ends of the metal electrode layer are provided with source electrodes and The drain electrode, a dielectric layer is arranged between the source electrode and the drain electrode, and the gate electrode is arranged above the dielectric layer; wherein, the dielectric layer includes several negatively charged ion doped regions F1 to Fm uniformly arranged in sequence, m is a positive integer and m ⁇ 2, and the negative ion concentration of the plurality of negative ion doping regions F1 to Fm includes at least two types.
  • Another embodiment of the present invention also provides a method for manufacturing a high-linearity HEMT device, including:
  • Step 1 Obtain and clean an epitaxial substrate; wherein, the epitaxial substrate includes a barrier layer;
  • Step 2 Fabricating a source electrode and a drain electrode on the barrier layer
  • Step 3 Perform mesa etching on the epitaxial substrate to form an isolation mesa on the barrier layer;
  • Step 4 Perform fluorine ion implantation on the barrier layer to form several fluorine doped regions; wherein the fluorine doped regions are located between the source electrode and the drain electrode;
  • Step 5 Fabricate a gate electrode on the fluorine-doped region to complete the fabrication of a high linear HEMT device.
  • step 4 it further includes:
  • a dielectric layer is deposited on the barrier layer; wherein the dielectric layer is disposed between the source electrode and the drain electrode.
  • step 4 includes:
  • step 4 includes:
  • the 1+jth fluorine implantation region and the mjth fluorine implantation region are photoetched on the barrier layer, and fluorine ion implantation is performed respectively to form the 1+jth fluorine-doped region and the mjth fluorine implantation region.
  • Doped region, wherein the fluorine ion concentration n 1+j of the 1+jth fluorine doped region is equal to the fluorine ion concentration n mj of the mjth fluorine doped region, and satisfies n j ⁇ n 1 +j or n j >n 1+j , where
  • n is an odd number
  • n is an even number.
  • step 4 includes:
  • the k-th fluorine implantation region is photoetched on the barrier layer, and fluorine ion implantation is performed to form several fluorine doped regions with the same concentration; wherein k is an odd or even number greater than or equal to 1, and k ⁇ m.
  • step 4 further includes:
  • the first fluorine implantation region is lithographically etched on the barrier layer, and fluorine ion implantation is performed to form several fluorine doped regions with the same concentration; where l is an even or odd number greater than or equal to 1, and l ⁇ m.
  • Another embodiment of the present invention also provides a method for manufacturing a high linearity HEMT device, including:
  • Step A Obtain and clean an epitaxial substrate; wherein, the epitaxial substrate includes a barrier layer;
  • Step B fabricating a source electrode and a drain electrode on the barrier layer
  • Step C Perform mesa etching on the epitaxial substrate to form an isolation mesa on the barrier layer;
  • Step D depositing a dielectric layer on the barrier layer between the source electrode and the drain electrode;
  • Step E Perform fluorine ion implantation on the dielectric layer to form several fluorine doped regions; wherein the fluorine doped regions are located between the source electrode and the drain electrode;
  • Step F fabricating a gate electrode in the region corresponding to the fluorine-doped region on the dielectric layer to complete the fabrication of the high linear HEMT device.
  • the high linear HEMT device compensates for each other's transconductance in the barrier layer under the gate electrode or in the fluorine-doped regions of different concentrations in the dielectric layer, and can achieve relatively stable transconductance in a larger gate-source bias range, without A large number of adjustments to the device and material structure can make the device have good linearity;
  • the high linearity MIS-HEMT device provided by the present invention can reduce the gate leakage, improve the device withstand voltage, widen the gate voltage swing of the normal operation of the device, and further improve the linearity of the device through the application of the dielectric gate structure.
  • the high linear HEMT device provided by the present invention has a simple process, good compatibility, is convenient for device preparation and process adjustment, and introduces small additional effects, and has higher feasibility and repeatability;
  • the structure of the high linear HEMT device provided by the present invention is similar to the common HEMT device, and is compatible with other related optimization technologies such as field plate structure, and achieves characteristics such as high breakdown voltage and high output current while maintaining high linearity.
  • FIG. 1 is a schematic structural diagram of a high linear HEMT device provided by an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of the gate electrode of the device shown in FIG. 1;
  • FIG. 3 is a plan view of the arrangement of fluorine-doped regions of the device shown in FIG. 1;
  • FIG. 4 is a schematic structural diagram of another high-linearity HEMT device provided by an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another high-linearity HEMT device provided by an embodiment of the present invention.
  • FIG. 6 is a flow chart of a method for preparing the high linearity HEMT device shown in FIG. 1;
  • FIG. 7 is another flow chart of the method for manufacturing the high linearity HEMT device shown in FIG. 1;
  • FIG. 8a to 8f are schematic diagrams of the process of preparing the high linear HEMT device shown in FIG. 1;
  • 9a-9b are schematic diagrams of a fluorine injection process provided by an embodiment of the present invention.
  • 10a to 10b are schematic diagrams of another fluorine injection process provided by an embodiment of the present invention.
  • FIG. 11 is a flowchart of a method for manufacturing the high linearity HEMT device shown in FIG. 4;
  • FIG. 12 is a flowchart of a method for fabricating the high linear HEMT device shown in FIG. 5.
  • FIG. 1 is a schematic structural diagram of a high linear HEMT device provided by an embodiment of the present invention, which includes from bottom to top:
  • the metal electrode layer 40 includes a source electrode 41, a gate electrode 42 and a drain electrode 43 in sequence from left to right; wherein, the barrier layer 30 includes a uniform arrangement in sequence
  • the fluorine-doped regions F1 to Fm, m is a positive integer and m ⁇ 2, and the fluorine ion concentration of the fluorine-doped regions F1 to Fm includes at least two types.
  • the fluorine-doped regions F1 to Fm are located under the gate electrode 42 and arranged along the gate width direction.
  • FIG. 2 is a schematic cross-sectional view of the gate electrode of the device shown in FIG. 1;
  • FIG. 3 is a top view of the arrangement of fluorine-doped regions in the device shown in FIG. 1.
  • the barrier layer 30 under the gate region 42 is divided into several regions F1 to Fm along the gate width direction, and different regions are doped with fluorine ions of different concentrations. Fluoride ion doping will change the 2DEG concentration of the corresponding region under the gate, and then adjust the threshold voltage of the corresponding region. Further, the threshold voltage adjustment effect of the fluorine ion doping on the region is affected by the fluorine ion concentration. Therefore, the device can be regarded as a parallel connection of several HEMT devices with different transconductance distributions. Through this parallel structure, the transconductance between the discrete HEMT devices is compensated for each other, so as to realize the transconductance value in a larger gate-source bias voltage range. The relative stability.
  • the fluorine ion concentration of the fluorine-doped regions F1 to Fm sequentially increases or decreases from the fluorine-doped region F1 to the fluorine-doped region Fm.
  • the fluorine ion concentration of the fluorine-doped regions F1 to Fm sequentially increases or decreases from the fluorine-doped region F1 and the fluorine-doped region Fm to the middle.
  • the fluorine ion concentration of several fluorine-doped regions F1 to Fm gradually increases from both ends to the middle, where the fluorine ion concentration of the fluorine-doped regions F1 and Fm can be expressed as n1, and the fluorine-doped regions F2 and Fm-
  • the fluoride ion concentration of 1 can be expressed as n2, and so on, where n 1 ⁇ n 2 ⁇ ....
  • the fluorine ion concentration of several fluorine-doped regions F1 to Fm gradually decreases from the two ends to the middle, and satisfies n 1 >n 2 >....
  • the fluorine ion concentration of the fluorine doped regions F1 to Fm may also include two different concentrations, and the two fluorine doped regions with different concentrations are arranged at intervals.
  • it may be the first fluorine doped region F1, the third fluorine doped region F3... and other odd-numbered fluorine doped regions with the same fluorine ion concentration, the second fluorine doped region F2, the fourth fluorine doped region
  • the fluorine ion concentration of the even-numbered fluorine-doped regions is the same as F4...etc.
  • fluorine-doped regions of odd-numbered items are doped, and the fluorine-doped regions of even-numbered items are not doped, or the fluorine-doped regions of even-numbered items are doped and the fluorine-doped regions of odd items are not doped.
  • the substrate 10 may be a substrate such as silicon, sapphire, silicon carbide, or a combination thereof; the material of the buffer layer 20 may be GaN, etc., and the material of the barrier layer 30 may be AlGaN, InAlN, or the like.
  • the device in this embodiment further includes at least one of a nucleation layer, an insertion layer, a cap layer, and a passivation layer; wherein,
  • the nucleation layer is arranged between the substrate layer 10 and the buffer layer 20;
  • the insertion layer is arranged between the buffer layer 20 and the barrier layer 30;
  • the cap layer is disposed between the barrier layer 30 and the metal electrode layer 40;
  • the passivation layer is disposed in the area between the electrodes above the barrier layer 30.
  • a nucleation layer can be added between the substrate 10 and the buffer layer 20, the material of which can be AlN, etc.; further, in order to obtain a high concentration of 2DEG, a nucleation layer can be added to the buffer layer 20.
  • Add an insertion layer between the barrier layer 30 and the barrier layer 30, the material of which can be AlN, etc.; at the same time, in order to obtain high-quality ohmic contacts and Schottky contacts, and improve the carrier mobility, the barrier layer 30 and the metal electrode layer Add a cap layer in between, and its material can be GaN or the like.
  • a passivation layer can also be prepared in the region between the electrodes above the barrier layer 30, and the material can be SiN or the like.
  • the stability of the device thereby improving the linearity of the device.
  • this method does not need to start from the physical mechanism of the device's own transconductance characteristics, and directly uses the devices with different transconductance characteristics to compensate each other, avoiding a large number of adjustments to the device and material structure, and reducing the design difficulty.
  • the linearization effect has not diminished.
  • the structure of the high-linearity HEMT device provided by this embodiment is similar to that of common HEMT devices, and is compatible with other related optimization technologies such as field plate structure, and achieves characteristics such as high breakdown voltage and high output current while maintaining high linearity.
  • FIG. 4 is a schematic diagram of another high-linearity HEMT device structure provided by an embodiment of the present invention.
  • the high-linearity HEMT device structure provided in the first embodiment above it further includes a dielectric layer 50, wherein the dielectric layer 50 is arranged between the source electrode 41 and the drain electrode 43, and the gate electrode 42 is arranged above the dielectric layer 50.
  • a high-dielectric constant dielectric material is used to realize a high-linearity MIS-HEMT device, which can maintain high gate control capability and device transconductance while suppressing leakage.
  • the high-linearity HEMT device provided by this embodiment can reduce gate leakage, improve device withstand voltage, widen the gate voltage swing for normal operation of the device through the application of dielectric gate structure, further improve device linearity, and improve device performance. Features such as gain and power added efficiency.
  • the remaining structures of the HEMT device provided in this embodiment such as the fluorine-doped region, nucleation layer, insertion layer, capping layer, etc., are the same as the high linear HEMT device provided in the first embodiment, and the detailed structure will not be omitted here. Go into details.
  • FIG. 5 is a schematic structural diagram of another high linear HEMT device provided by an embodiment of the present invention. It includes from bottom to top:
  • the substrate layer 10, the buffer layer 20, the barrier layer 30 and the metal electrode layer 40 are provided with a source electrode 41 and a drain electrode 43 at both ends of the metal electrode layer 40, a dielectric layer 50 is provided between the source electrode 41 and the drain electrode 43, and the gate
  • the electrode 42 is arranged above the dielectric layer 50; wherein, the dielectric layer 50 includes several fluorine-doped regions F1 to Fm uniformly arranged in sequence, m is a positive integer and m ⁇ 2, and the fluorine ion concentration of the several fluorine-doped regions F1 to Fm is at least Including two kinds.
  • the high linear HEMT device provided by this embodiment can reduce the gate leakage, improve the withstand voltage of the device, expand the gate voltage swing of the normal operation of the device, and further improve the linearity of the device through the application of the dielectric gate structure.
  • the fluorine implantation area is limited to the dielectric layer under the gate.
  • the fluorine ions are far from the conductive channel and cannot easily enter the channel, thereby avoiding the influence of fluorine ions on the electron mobility of the channel. The influence of fluorine injection on the transport characteristics of the device is reduced.
  • the remaining structures of the HEMT device provided in this embodiment such as the fluorine-doped region, nucleation layer, insertion layer, capping layer, etc., are the same as the high linear HEMT device provided in the first embodiment, and the detailed structure will not be omitted here. Go into details.
  • This embodiment provides a high linear HEMT device, which includes a substrate layer 10, a buffer layer 20, a barrier layer 30, and a metal electrode layer 40 from bottom to top.
  • the metal electrode layer 40 includes a source electrode 41 from left to right.
  • the ion concentration includes at least two types.
  • the high linear HEMT device provided in this embodiment has the same structure as the device provided in the first embodiment. The only difference is that in addition to fluorine doping, the negatively charged ion doped region in this embodiment can also use other negatively charged ions, such as oxygen, Nitrogen, chlorine, etc. are doped to modulate the transconductance of the region under the gate to achieve high linearity.
  • the negatively charged ion doped region in this embodiment can also use other negatively charged ions, such as oxygen, Nitrogen, chlorine, etc. are doped to modulate the transconductance of the region under the gate to achieve high linearity.
  • This embodiment provides a high-linearity HEMT device, which includes from bottom to top: a substrate layer 10, a buffer layer 20, a barrier layer 30, and a metal electrode layer 40. Both ends of the metal electrode layer 40 are provided with a source electrode 41 and a leakage current.
  • a dielectric layer 50 is arranged between the source electrode 41 and the drain electrode 43, and the gate electrode 42 is arranged above the dielectric layer 50; wherein, the dielectric layer 50 includes several negatively charged ion doped regions F1 to Fm uniformly arranged in sequence, where m is A positive integer and m ⁇ 2, the negative ion concentration of the several negative ion doping regions F1 to Fm includes at least two types.
  • the high linear HEMT device provided in this embodiment has the same structure as the device provided in the third embodiment above.
  • the only difference is that in addition to fluorine doping, the negatively charged ion doped region in this embodiment can also use other negatively charged ions, such as oxygen. , Nitrogen, Chlorine, etc. are doped to modulate the transconductance of the region under the gate to achieve high linearity.
  • FIG. 6 is a flowchart of a method for preparing the high linearity HEMT device shown in FIG. 1; specifically including:
  • Step 1 Obtain and clean the epitaxial substrate; wherein, the epitaxial substrate includes a barrier layer.
  • the epitaxial substrate may sequentially include a sapphire substrate, a GaN buffer layer, and an AlGaN barrier layer from bottom to top.
  • the obtained epitaxial substrate may also include a nucleation layer and an insertion layer, wherein the nucleation layer is located between the sapphire substrate and the GaN buffer layer, and the insertion layer is located between the GaN buffer layer and the AlGaN barrier layer .
  • Step 2 Fabricate source and drain electrodes on the barrier layer.
  • (2c) Evaporate the first metal layer on the surface of the first mask layer to obtain source and drain metals
  • (2d) Use a lift-off process to remove the first mask layer and the first metal layer, and perform rapid annealing to form a source electrode and a drain electrode on the barrier layer.
  • the first mask layer is the source and drain region mask patterns
  • the first metal layer is the source and drain metal layers.
  • Step 3 Perform mesa etching on the epitaxial substrate to form an isolation mesa on the barrier layer.
  • Step 4 Perform fluorine ion implantation on the barrier layer to form several fluorine doped regions; wherein the fluorine doped regions are located between the source electrode and the drain electrode.
  • FIG. 7 is another flow chart of the method for manufacturing the high linearity HEMT device shown in FIG. 1.
  • step 4 may include:
  • this embodiment adopts a fluorine-based reactive plasma etching process for fluorine ion implantation, wherein the reactive gas is CF 4 plasma, the power is 60-200 W, and the etching time is 50-300 s. The higher the power and the longer the time, the higher the injection concentration.
  • the fluorine ion concentration of the m fluorine-doped regions increases or decreases from one end to the other end, in the specific preparation process, it is necessary to first form a fluorine implantation area and perform fluorine ion implantation, and so on. Until the formation of m fluorine ion concentration increases from one end to the other end of a series of fluorine doped regions.
  • step 4 may further include:
  • the fluorine ion concentration n 1+j of the 1+j- th fluorine-doped area is equal to the fluorine ion concentration n mj of the mj-th fluorine-doped area, and satisfies n j ⁇ n 1+j or n j > n 1+j , where,
  • n is an odd number
  • n is an even number.
  • the fluorine ion concentration of the m fluorine-doped regions increases or decreases from both ends to the middle, it is possible to simultaneously form two fluorine-implanted regions with the same fluorine ion concentration and perform fluorine ion implantation. Then, a next set of fluorine-doped regions with the same concentration is prepared, and so on, until a series of fluorine-doped regions with m fluorine ion concentrations gradually increasing or decreasing from the two ends to the middle is formed.
  • step 4 may further include:
  • the k-th fluorine implantation region is photoetched on the barrier layer, and fluorine ion implantation is performed to form several fluorine doped regions with the same concentration; where k is an odd or even number greater than or equal to 1, and k ⁇ m.
  • fluorine ion doped regions with a certain concentration and a concentration of zero intervals are formed.
  • the first fluorine implantation region is photoetched on the barrier layer, and fluorine ion implantation is performed to form several fluorine doped regions with the same concentration; where l is an even or odd number greater than or equal to 1, and l ⁇ m.
  • post-annealing may be performed immediately after the fluorine ion implantation in step 4, wherein the annealing temperature is above 340° C. and the time is above 10 minutes.
  • annealing is performed after the gate electrode is formed, and it can actually be performed after fluorine implantation.
  • Step 5 Fabricate a gate electrode on the fluorine-doped region to complete the fabrication of a high linear HEMT device.
  • the second mask layer is the gate region mask pattern
  • the second metal layer is the gate metal layer
  • the annealing process in step (5c) may also be performed after the fluoride ion implantation in step 4, wherein the annealing temperature is above 340° C. and the time is above 10 minutes.
  • the epitaxial substrate obtained in step 1 in this embodiment may further include a capping layer disposed on the barrier layer, and then the source and drain electrodes are fabricated and subsequent processes are performed.
  • the high-linearity HEMT device provided by this embodiment has simple process, good compatibility, easy device preparation and process adjustment, and small additional effects introduced, which has higher feasibility and repeatability; at the same time, the transfer curve of the device is affected by fluorine injection
  • the parameters of each discrete device are easy to obtain, and the process flow is easy to control.
  • the preparation method of the present invention will be described in detail by taking as an example the preparation of a HEMT device in which the fluorine injection concentration increases from one end to the other end.
  • Figures 8a to 8f are schematic diagrams of the process of fabricating the high linear HEMT device shown in Figure 1, which specifically includes:
  • the mask layer and the metal layer are removed by a lift-off process, and rapid annealing is performed to obtain the source electrode 41 and the drain electrode 43.
  • step S2 glue is applied to the surface of the sample obtained in step S2, a photoresist mask is obtained after the glue is spun, and the mesa area mask pattern is formed by photolithography and development after drying;
  • the masked sample is etched to obtain an isolated mesa.
  • S4 Implanting fluorine ions of different concentrations in the AlGaN barrier layer 30 in stages and regions to form m fluorine-doped regions with different fluorine ion concentrations.
  • the first fluorine implantation region F1 is lithographically etched on the gate region of the AlGaN barrier layer 30: firstly, the surface of the sample obtained in step S3 is coated and spun to obtain a photoresist mask, and then it is baked, and The pattern of the first fluorine injection region F1 under the gate is formed by photolithography and development; as shown in FIG. 8c;
  • the fluorine-based reactive plasma etching process is used to inject fluorine into the first fluorine-implanted area F1, where the reactive gas is CF 4 plasma, the power is 60-200W, and the etching time is 50-300s so that the fluorine ions in the area F1
  • the concentration is n1.
  • the fluorine implantation regions F2, F3,..., Fm under the gate are respectively photoetched, and fluorine is implanted respectively, and the fluorine ion concentrations are n 2 , n 3 ,..., n m , where n 1 ⁇ n 2 ⁇ whil ⁇ n m-1 ⁇ n m , as shown in Fig. 8d, a series of fluorine-doped regions with increasing fluoride ion concentration from one end to the other end are finally obtained, as shown in Fig. 8e.
  • the entire sample is annealed to activate fluoride ions, where the annealing temperature is above 340°C and the time is above 10 minutes.
  • step S4 apply glue on the sample obtained in step S4 and spin off the glue to obtain a photoresist mask, which is dried, and then a mask pattern of the gate electrode region is formed by photolithography and development techniques;
  • the mask layer and the metal layer are removed by the lift-off process to obtain the gate electrode 40 to complete the device preparation.
  • the following takes the preparation of a HEMT device in which the fluorine injection concentration gradually increases from both ends to the middle as an example for description, which specifically includes the following steps:
  • Step A Obtain a sample piece containing the sapphire substrate 10, the GaN buffer layer 20 and the AlGaN barrier layer 30, and clean the sample piece;
  • Step B fabricating a source 41 and a drain 43 on the AlGaN barrier layer 30;
  • Step C Perform mesa etching on the sample to form an isolation mesa on the barrier layer 30;
  • steps A to C are the same as steps S1 to S3 of the third embodiment, and will not be repeated here.
  • Step D Inject fluorine ions of different concentrations into the AlGaN barrier layer 30 in stages and regions to form m fluorine doped regions with different fluorine ion concentrations.
  • FIGS. 9a-9b are schematic diagrams of a fluorine injection process provided by an embodiment of the present invention.
  • the first set of fluorine implanted regions F1 and Fm are photoetched on the gate region of the AlGaN barrier layer 30:
  • step C the surface of the sample obtained in step C is coated with glue and the glue is spun to obtain a photoresist mask, and then after drying, the pattern of the first group of fluorine injection regions F1 and Fm under the grid is formed by photolithography and development; as shown in Figure 9a Shown
  • the second group of fluorine implanted regions F2 and Fm-1 under the gate are respectively photoetched and fluorine ion implanted to obtain fluorine doped regions F2 and Fm-1 with a fluorine ion concentration of n 2, and so on.
  • n1 ⁇ n2 ⁇ n3 ⁇ a fluorine ion concentration of n 2, and so on.
  • Step E Fabricate the gate electrode 42 on the barrier layer 30 between the source electrode 41 and the drain electrode 43 in the region corresponding to the fluorine-doped region.
  • the specific steps are the same as the step S5 of the fifth embodiment above, and will not be repeated here.
  • the following takes the preparation of a HEMT device with two fluorine implantation concentrations and two different concentrations of fluorine doped regions arranged at intervals as an example for description, which specifically includes the following steps:
  • FIGS. 10a to 10b are schematic diagrams of another fluorine injection process provided by an embodiment of the present invention.
  • the k-th fluorine implantation region is photoetched on the barrier layer, and fluorine ion implantation is performed to form several fluorine doped regions with the same concentration; where k is an odd or even number greater than or equal to 1, and k ⁇ m. In this embodiment, k is an odd number for description, as shown in FIG. 10a. Then, fluorine ion implantation is not performed on the remaining areas.
  • the even-numbered regions can also be melted with another concentration of ions, namely
  • the first fluorine implantation region is photoetched on the barrier layer, and fluorine ion implantation is performed to form several fluorine doped regions with the same concentration; where l is an even or odd number greater than or equal to 1, and l ⁇ m.
  • the gate electrode 42 is fabricated in the region corresponding to the fluorine-doped region on the barrier layer 30 between the source electrode 41 and the drain electrode 43.
  • the specific steps are the same as the step S5 of the seventh embodiment, and will not be repeated here.
  • This embodiment provides a method for preparing a high-linearity HEMT device to prepare the high-linearity HEMT device provided in the second embodiment.
  • FIG. 11 is a flowchart of a method for fabricating the high linear HEMT device shown in FIG. 4.
  • the device shown in FIG. 4 also includes a dielectric layer located between the source electrode 41 and the drain electrode 43 and under the gate electrode 42.
  • a dielectric layer is deposited on the barrier layer.
  • a uniform Si 3 N 4 or Al 2 O 3 dielectric layer is deposited on the barrier layer where the fluorine implantation is completed.
  • the material, thickness and process of the dielectric layer should be designed with a comprehensive consideration of its influence on the gate control capability of the device and the suppression of gate leakage.
  • a gate electrode is prepared on the dielectric layer to complete the device preparation.
  • FIG. 12 is a flowchart of a method for fabricating the high linearity HEMT device shown in FIG. 5. specifically,
  • Step A Obtain and clean the epitaxial substrate; wherein, the epitaxial substrate includes a barrier layer;
  • Step B fabricating source electrodes and drain electrodes on the barrier layer
  • Step C Perform mesa etching on the epitaxial substrate to form an isolation mesa on the barrier layer;
  • Step D Depositing a dielectric layer on the barrier layer between the source electrode and the drain electrode;
  • Step E Perform fluorine ion implantation on the dielectric layer to form several fluorine doped regions; wherein the fluorine doped regions are located between the source electrode and the drain electrode;
  • Step F Fabricate a gate electrode in the region corresponding to the fluorine-doped region on the dielectric layer to complete the fabrication of the high linear HEMT device.
  • the fluorine-doped region is located in the dielectric layer above the barrier layer. Therefore, in the specific preparation process, the dielectric layer needs to be deposited first, and then fluorine injection is performed. A fluorine-doped region is formed in the dielectric layer, and finally a gate electrode is prepared in the dielectric layer.
  • performing fluorine ion implantation on the dielectric layer to form several fluorine doped regions is the same as the method of performing fluorine ion implantation on the barrier layer to form several fluorine doped regions provided in the seventh to ninth embodiments above. The detailed process will not be repeated here.
  • the process flow may be different from the foregoing flow, for example, the order of mesa isolation and source and drain electrode preparation can be interchanged.
  • the device structure may also include optimized structures such as a nucleation layer, an insertion layer, a cap layer, and a passivation layer. Regardless of the specific implementation, all structural, method, or functional transformations based on the device structure proposed in the present invention should be included in the protection scope of the present invention.

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Abstract

一种高线性HEMT器件，自下而上依次包括：衬底层(10)、缓冲层(20)、势垒层(30)以及金属电极层(40)，金属电极层(40)从左至右依次包括源电极(41)、栅电极(42)以及漏电极(43)；其中，势垒层(30)包括依次均匀排列的若干氟掺杂区F1～Fm，m为正整数且m≥2。高线性HEMT器件通过栅电极(42)下势垒层(30)不同浓度氟掺杂区F1～Fm跨导相互补偿，能实现在较大栅源偏压范围内跨导的相对稳定，无需对器件和材料结构进行大量调整便可使器件具有很好的线性度。

Description

一种高线性HEMT器件及其制备方法 技术领域
本发明属于半导体技术领域，具体涉及一种高线性HEMT器件及其制备方法。
背景技术
随着5G通信技术的普及与6G通信技术的研发进展，传统的以Si为代表的第一代半导体材料及以GaAs为代表的第二代半导体材料渐渐难以满足日益增长的频率需求。因此，以GaN材料为代表的第三代半导体材料得到了广泛的关注。相比Si与GaAs材料，GaN材料具高禁带宽度、高击穿场强、高电子速度等特性，能实现更快的工作速度与更高的可靠性。特别是基于AlGaN/GaN异质结所制成的高电子迁移率晶体管(HEMT)，凭借异质结界面处形成的高浓度、高迁移率的二维电子气(2DEG)，具有极高的工作速度，在通讯等领域具有广阔的应用前景。
在通讯等领域中，半导体器件的线性度是一个重要参数。然而，普通HEMT器件由于电子饱和速度下降与器件串联电阻增大等因素，会出现随着栅源偏压的增大，器件跨导先上升，达到一定峰值后再下降的现象。跨导下降现象会影响器件的线性度，限制器件的工作范围。为此，通常采用渐变组分势垒结构降低2DEG浓度提高电子饱和速度或者采用Fin结构降低源串联电阻的方式保证器件跨导在较大的栅压范围内保持稳定，从而提高器件线性度。此外，还可以采用Fin宽渐变结构或者势垒厚度渐变结构等方式来提高器件线性度。
然而，采用渐变组分势垒结构要求高Al组分的势垒层，会造成器件表面质量的恶化；采用Fin结构以及Fin宽渐变结构其制备过程中涉及刻蚀工艺，会引入大量的刻蚀损伤，留下的沟道侧壁也会产生大量寄生电容，影响器件性能；而势垒厚度渐变结构需要对势垒层结构进行精确的刻蚀深度控制，工艺难度过高。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种高线性HEMT器件及其制备方法。本发明要解决的技术问题通过以下技术方案实现：
一种高线性HEMT器件，自下而上依次包括：衬底层、缓冲层、势垒层以及金属电极层，所述金属电极层从左至右依次包括源电极、栅电极以及漏电极；其中，所述势垒层包括依次均匀排列的若干氟掺杂区F1～Fm，m为正整数且m≥2，所述若干氟掺杂区F1～Fm的氟离子浓度至少包括两种。
在本发明的一个实施例中，所述器件还包括介质层，所述介质层设置于所述源电极和所述漏电极之间，所述栅电极设置于所述介质层上方。
本发明的另一个实施例还提供了一种高线性HEMT器件，自下而上依次包括：衬底层、缓冲层、势垒层以及金属电极层，所述金属电极层两端设有源电极和漏电极，所述源电极和漏电极之间设有介质层，所述栅电极设置于所述介质层上方；其中，所述介质层包括依次均匀排列的若干氟掺杂区F1～Fm，m为正整数且m≥2，所述若干氟掺杂区F1～Fm的氟离子浓度至少包括两种。
在本发明的一个实施例中，所述氟掺杂区F1～Fm位于所述栅电极下方并沿栅宽方向排列。
在本发明的一个实施例中，所述氟掺杂区F1～Fm的氟离子浓度从所述氟掺杂区F1至所述氟掺杂区Fm依次递增或者递减。
在本发明的一个实施例中，所述氟掺杂区F1～Fm的氟离子浓度从所述氟掺杂区F1和所述氟掺杂区Fm依次向中间递增或者递减。
在本发明的一个实施例中，所述氟掺杂区F1～Fm的氟离子浓度包括两种不同浓度，且两种不同浓度的氟掺杂区间隔排列。
在本发明的一个实施例中，所述器件还包括成核层、插入层、盖帽层以及钝化层中的至少一层；其中，
所述成核层设置于所述衬底层和所述缓冲层之间；
所述插入层设置于所述缓冲层和所述势垒层之间；
所述盖帽层设置于所述势垒层与所述金属电极层之间；
所述钝化层设置于所述势垒层上方各电极之间的区域。
本发明的另一个实施例还提供了一种高线性HEMT器件，自下而上依次包括：衬底层、缓冲层、势垒层以及金属电极层，所述金属电极层从左至右依次包括源电极、栅电极以及漏电极；其中，所述势垒层包括依次均匀排列的若干负电离子掺杂区F1～Fm，m为正整数且m≥2，所述若干负电离子掺杂区F1～Fm的负电离子浓度至少包括两种。
本发明的另一个实施例还提供了一种高线性HEMT器件，自下而上依次包括：衬底层、缓冲层、势垒层以及金属电极层，所述金属电极层两端设有源电极和漏电极，所述源电极和漏电极之间设有介质层，所述栅电极设置于所述介质层上方；其中，所述介质层包括依次均匀排列的若干负电离子掺杂区F1～Fm，m为正整数且m≥2，所述若干负电离子掺杂区F1～Fm的负电离子浓度至少包括两种。
本发明的例又一个实施例还提供了一种高线性HEMT器件的制备方法，包括：
步骤1：获取外延基片并进行清洗；其中，所述外延基片包括势垒层；
步骤2：在所述势垒层上制作源电极和漏电极；
步骤3：对所述外延基片进行台面刻蚀，以在所述势垒层上形成隔离台面；
步骤4：对所述势垒层进行氟离子注入以形成若干氟掺杂区；其中，所述氟掺杂区位于所述源电极和所述漏电极之间；
步骤5：在所述氟掺杂区上面制作栅电极，以完成高线性HEMT器件的制备。
在本发明的一个实施例中，在步骤4之后，还包括：
在所述势垒层上淀积介质层；其中，所述介质层设置于所述源电极和所述漏电极之间。
在本发明的一个实施例中，步骤4包括：
(4a)在所述势垒层上光刻第一个氟注入区域；
(4b)对所述第一个氟注入区域进行氟离子注入以形成第一个氟掺杂区，其中，所述第一个氟掺杂区的氟离子浓度为n 1；
(4c)在所述势垒层上光刻第i个氟注入区域，并分别进行氟离子注入以形成第i个氟掺杂区，其中，所述第i个氟掺杂区的氟离子浓度为n i，且满足n i-1＜n i或者n i-1＞n i，其中，2≤i≤m，i、m均为正整数。
在本发明的另一个实施例中，步骤4包括：
(41)在所述势垒层上光刻第一个氟注入区域和第m个氟注入区域；
(42)对所述第一个氟注入区域和所述第m个氟注入区域进行氟离子注入以形成第一个氟掺杂区和第m个氟掺杂区，其中，所述第一个氟掺杂区的氟离子浓度n 1和所述第m个氟掺杂区的氟离子浓度n m相等；
(43)在所述势垒层上光刻第1+j个氟注入区域和第m-j个氟注入区，并分别进行氟离子注入以形成第1+j个氟掺杂区和第m-j个氟掺杂区，其中，所述第1+j个氟掺杂区的氟离子浓度n 1+j和所述第m-j 个氟掺杂区的氟离子浓度n m-j相等，且满足n j＜n 1+j或者n j＞n 1+j，其中，
Figure PCTCN2021082805-appb-000001
m为奇数；
Figure PCTCN2021082805-appb-000002
m为偶数。
在本发明的另一个实施例中，步骤4包括：
在所述势垒层上光刻第k个氟注入区域，并进行氟离子注入以形成浓度相同的若干氟掺杂区；其中，k为大于等于1的奇数或者偶数，且k≤m。
在本发明的一个实施例中，步骤4还包括：
在所述势垒层上光刻第l个氟注入区域，并进行氟离子注入以形成浓度相同的若干氟掺杂区；其中，l为大于等于1的偶数或者奇数，且l≤m。
本发明的又一个实施例还提供了一种高线性HEMT器件的制备方法，包括：
步骤A：获取外延基片并进行清洗；其中，所述外延基片包括势垒层；
步骤B：在所述势垒层上制作源电极和漏电极；
步骤C：对所述外延基片进行台面刻蚀，以在所述势垒层上形成隔离台面；
步骤D：在所述源电极和所述漏电极之间的势垒层上淀积介质层；
步骤E：对所述介质层进行氟离子注入以形成若干氟掺杂区；其中，所述氟掺杂区位于所述源电极和所述漏电极之间；
步骤F：在所述介质层上与氟掺杂区对应的区域制作栅电极，以完成高线性HEMT器件的制备。
本发明的有益效果：
1、本发明提供的高线性HEMT器件通过栅电极下势垒层或者介质层中不同浓度氟掺杂区域跨导相互补偿，能实现在较大栅源偏压范围内跨导的相对稳定，无需对器件和材料结构进行大量调整便可使器件具有很好的线性度；
2、本发明提供的高线性MIS-HEMT器件可通过介质栅结构的应用，降低栅漏电，提高器件耐压，扩宽器件正常工作的栅压摆幅，进一步提高器件线性度，同时提高了器件的增益、功率附加效率等特性；
3、本发明提供的高线性HEMT器件工艺简单，兼容性好，便于器件制备与工艺调节，且引入的附加效应小，具有更高的可行性和重复性；
4、本发明提供的高线性HEMT器件结构与常用HEMT器件类似，可与其他相关优化技术如场板结构等兼容，保持高线性度的同时实现高击穿电压、高输出电流等特性。
以下将结合附图及实施例对本发明做进一步详细说明。
附图说明
图1是本发明实施例提供的一种高线性HEMT器件结构示意图；
图2是图1所示器件栅电极处剖面示意图；
图3是图1所示器件氟掺杂区域排布的俯视图；
图4是本发明实施例提供的另一种高线性HEMT器件结构示意图；
图5是本发明实施例提供的又一种高线性HEMT器件结构示意图；
图6是制备图1所示的高线性HEMT器件的方法流程图；
图7是制备图1所示的高线性HEMT器件的方法的另一种流程图；
图8a～8f是制备图1所示的高线性HEMT器件的过程示意图；
图9a～9b是本发明实施例提供的一种氟注入工艺的方法示意图；
图10a～10b是本发明实施例提供的另一种氟注入工艺的方法示意图；
图11是制备图4所示的高线性HEMT器件的方法流程图；
图12是制备图5所示的高线性HEMT器件的方法流程图。
具体实施方式
下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。
实施例一
请参见图1，图1是本发明实施例提供的一种高线性HEMT器件结构示意图，其自下而上依次包括：
衬底层10、缓冲层20、势垒层30以及金属电极层40，金属电极层40从左至右依次包括源电极41、栅电极42以及漏电极43；其中，势垒层30包括依次均匀排列的若干氟掺杂区F1～Fm，m为正整数且m≥2，若干氟掺杂区F1～Fm的氟离子浓度至少包括两种。
进一步地，所述氟掺杂区F1～Fm位于所述栅电极42下方并沿栅宽方向排列。
请参见图2和图3，图2是图1所示器件栅电极处剖面示意图；图3是图1所示器件氟掺杂区域排布的俯视图。
具体地，栅极区42下方的势垒层30中沿栅宽方向划分有若干区域F1～Fm，不同的区域中实现了不同浓度的氟离子掺杂。氟离子掺杂会改变对应栅下区域的2DEG浓度，进而调节对应区域的阈值电压。进一步地，氟离子掺杂对该区域的阈值电压调节效果受氟离子浓度影响。因而该器件可视为若干跨导分布各不相同的HEMT器件的并联，通过这一并联结构，各分立HEMT器件间跨导相互补偿，从而实现在较大的栅源偏压范围内跨导值的相对稳定。
进一步地，氟掺杂区F1～Fm的氟离子浓度从氟掺杂区F1至氟掺杂区Fm依次递增或者递减。
具体地，若干氟掺杂区F1～Fm的氟离子浓度可以分别表示为n 1、n 2、n 3、……、n m，其中，n 1＜n 2＜……＜n m-1＜n m或者n 1＞n 2＞……＞n m-1＞n m，实现氟离子浓度从一端向另一端递增或者递减的氟掺杂区。
在本发明的另一个实施例中，氟掺杂区F1～Fm的氟离子浓度从氟掺杂区F1和氟掺杂区Fm依次向中间递增或者递减。
具体地，若干氟掺杂区F1～Fm的氟离子浓度由两端到中间逐渐增加，其中，氟掺杂区F1和Fm的氟离子浓度均可表示为n1，氟掺杂区F2和Fm-1的氟离子浓度均可表示为n2，以此类推，其中，n 1<n 2<……。
或者，若干氟掺杂区F1～Fm的氟离子浓度由两端到中间逐渐降低，满足n 1＞n 2＞……。
在本发明的另一个实施例中，氟掺杂区F1～Fm的氟离子浓度还可以包括两种不同浓度，且两种不同浓度的氟掺杂区间隔排列。例如，其可以是第一氟掺杂区F1、第三氟掺杂区F3……等奇数项的氟掺杂区的氟离子浓度相同，第二氟掺杂区F2、第四氟掺杂区F4……等偶数项的氟掺杂区的氟离子浓度相同。还可以是奇数项的氟掺杂区进行掺杂，偶数项的氟掺杂区不进行掺杂，或者偶数项的氟掺杂区进行掺杂，奇数项的氟掺杂区不进行掺杂。
以上仅列举了几种氟掺杂区F1～Fm的氟离子浓度分配方式，对于实际应用中氟离子的掺杂浓度，只要满足氟掺杂区F1～Fm包括两种以上氟离子浓度即可，对此，本实施例不做限定。
本实施例中，衬底10可以是硅、蓝宝石、碳化硅等衬底或其组合；缓冲层20的材料可为GaN等，势垒层30的材料可为AlGaN、InAlN等。
进一步地，本实施例中的器件还包括成核层、插入层、盖帽层以及钝化层中的至少一层；其中，
成核层设置于衬底层10和缓冲层20之间；
插入层设置于缓冲层20和势垒层30之间；
盖帽层设置于势垒层30与金属电极层40之间；
钝化层设置于势垒层30上方各电极之间的区域。
在实际器件中，为了获得高质量的外延结构，可在衬底10与缓冲层20间增加成核层，其材料可以为AlN等；进一步地，为了获得高浓度的2DEG，可在缓冲层20与势垒层30间增加插入层，其材料可以为AlN等；同时，为了获得高质量的欧姆接触和肖特基接触，并提高载流子迁移率，可在势垒层30与金属电极层间增加盖帽层，其材料可为GaN等。此外，为了优化器件电学特性，还可以在势垒层30上方电极之间的区域制备钝化层，其材料可以是SiN等。
本实施例提供的高线性HEMT器件在栅宽方向上，通过一系列跨导峰值相近而峰值点互有平移的器件间跨导相互补偿、共同作用，从而在较大栅压范围内实现跨导的稳定，从而提高器件线性度。相比现有方式，这种方法无需从器件自身跨导特性的物理机理上着手，直接利用不同跨导特性器件互相补偿，避免了对器件和材料结构的大量调整，减小了设计难度，而线性化效果并无减弱。
此外，本实施例提供的高线性HEMT器件结构与常用HEMT器件类似，可与其他相关优化技术如场板结构等兼容，保持高线性度的同时实现高击穿电压、高输出电流等特性。
实施例二
请参见图4，图4是本发明实施例提供的另一种高线性HEMT器件结构示意图，其在上述实施例一提供的高线性HEMT器件结构基础上，还包括介质层50，其中，介质层50设置于源电极41和漏电极43之间，栅电极42设置于介质层50上方。
进一步地，本实施例通过使用高介电常数的介质材料，实现了高线性MIS-HEMT器件，在抑制漏电的同时能够保持较高的栅控能力与器件跨导。此外，本实施例提供的高线性HEMT器件可通过介质栅结构的应用，降低栅漏电，提高器件耐压，扩宽器件正常工作的栅压摆幅，进一步提高器件线性度，同时提高了器件的增益、功率附加效率等特性。
需要说明的是，本实施例提供的HEMT器件其余结构，例如氟掺杂区域、成核层、插入层、盖帽层等与上述实施例一提供的高线性HEMT器件相同，详细结构在此不再赘述。
实施例三
请参见图5，图5是本发明实施例提供的又一种高线性HEMT器件结构示意图；其自下而上依次包括：
衬底层10、缓冲层20、势垒层30以及金属电极层40，金属电极层40两端设有源电极41和漏电极43，源电极41和漏电极43之间设有介质层50，栅电极42设置于介质层50上方；其中，介质层50包括依次均匀排列的若干氟掺杂区F1～Fm，m为正整数且m≥2，若干氟掺杂区F1～Fm的氟离子浓度至少包括两种。
本实施例提供的高线性HEMT器件可通过介质栅结构的应用，降低栅漏电，提高器件耐压，扩宽器件正常工作的栅压摆幅，进一步提高器件线性度，同时提高了器件的增益、功率附加效率等特性。此外，本实施例将氟注入区域限定在栅下介质层中，这种结构中氟离子距离导电沟道较远，且不易进入沟道，从而避免了氟离子对沟道电子迁移率的影响，减小了氟注入对器件输运特性的影响。
需要说明的是，本实施例提供的HEMT器件其余结构，例如氟掺杂区域、成核层、插入层、盖帽层等与上述实施例一提供的高线性HEMT器件相同，详细结构在此不再赘述。
实施例四
本实施例提供了一种高线性HEMT器件，自下而上依次包括：衬底层10、缓冲层20、势垒层30以及金属电极层40，金属电极层40从左至右依次包括源电极41、栅电极42以及漏电极43；其中，势垒层30包括依次均匀排列的若干负电离子掺杂区F1～Fm，m为正整数且m≥2，若干负电离子掺杂区F1～Fm的负电离子浓度至少包括两种。
本实施例提供的高线性HEMT器件与上述实施例一提供的器件结构相同，区别仅在于本实施例中的负电离子掺杂区除了可以进行氟掺杂，还可以采用其他负电离子，例如氧、氮、氯等进行掺杂，以对栅下区域跨导进行调制，从而实现高线性度。
实施例五
本实施例提供了一种高线性HEMT器件，自下而上依次包括：衬底层10、缓冲层20、势垒层30以及金属电极层40，金属电极层40两端设有源电极41和漏电极43，源电极41和漏电极43之间设有介质层50，栅电极42设置于介质层50上方；其中，介质层50包括依次均匀排列的若干负电离子掺杂区F1～Fm，m为正整数且m≥2，若干负电离子掺杂区F1～Fm的负电离子浓度至少包括两种。
本实施例提供的高线性HEMT器件与上述实施例三提供的器件结构相同，区别仅在于本实施例中的负电离子掺杂区除了可以进行氟掺杂，还可以可采用其他负电离子，例如氧、氮、氯等进行掺杂，以对栅下区域跨导进行调制，从而实现高线性度。
实施例六
本实施例提供了一种高线性HEMT器件制备方法，用以制备上述实施例一提供的高线性HEMT器件。请参见图6，图6是制备图1所示的高线性HEMT器件的方法流程图；具体包括：
步骤1：获取外延基片并进行清洗；其中，外延基片包括势垒层。
具体地，外延基片自下而上可以依次包括蓝宝石衬底、GaN缓冲层、AlGaN势垒层。
在本实施例中，获取的外延基片还可以包含成核层和插入层，其中，成核层位于蓝宝石衬底和GaN缓冲层之间，插入层位于GaN缓冲层和AlGaN势垒层之间。
步骤2：在势垒层上制作源电极和漏电极。
(2a)在外延基片的表面涂胶并甩胶，得到光刻胶掩膜；
(2b)对外延基片进行烘干，并通过光刻和显影技术形成第一掩膜层；
(2c)在第一掩膜层表面蒸发第一金属层，以得到源、漏极金属；
(2d)利用剥离工艺去除第一掩膜层以及第一金属层，并进行快速退火，以在势垒层上形成源电极和漏电极。
在本实施例中，第一掩膜层即为源、漏区域掩膜图形，第一金属层即为源、漏极金属层。
步骤3：对外延基片进行台面刻蚀，以在势垒层上形成隔离台面。
(3a)在在步骤2所得的样品表面涂胶，并甩胶后得到光刻胶掩膜；
(3b)对样品进行烘干，并通过光刻和显影形成台面区域掩膜图形；
(3c)对做好掩膜的样品进行刻蚀，以在势垒层上形成隔离台面。
步骤4：对势垒层进行氟离子注入以形成若干氟掺杂区；其中，氟掺杂区位于源电极和漏电极之间。
请参见图7，图7是制备图1所示的高线性HEMT器件的方法的另一种流程图，在本发明的一 个实施例中，步骤4可以包括：
(4a)在势垒层上光刻第一个氟注入区域，
(4b)对第一个氟注入区域进行氟离子注入以形成第一个氟掺杂区，其中，第一个氟掺杂区的氟离子浓度为n 1；
(4c)在势垒层上光刻第i个氟注入区域，并分别进行氟离子注入以形成第i个氟掺杂区，其中，第i个氟掺杂区的氟离子浓度为n i，n i-1＜n i或者n i-1＞n i，其中，2≤i≤m，i、m均为正整数。
具体地，本实施例采用氟基反应等离子体刻蚀工艺进行氟离子注入，其中，反应气体为CF 4等离子体，功率为60～200W，刻蚀时间为50～300s。功率越高，时间越长，则注入浓度越高。
在本实施例中，由于m个氟掺杂区的氟离子浓度是从一端向另一端递增或者递减的，在具体制备过程中，需要先形成氟注入区域并进行氟离子注入，以此类推，直至形成m个氟离子浓度从一端向另一端递增的一系列氟掺杂区。
在本发明的另一个实施例中，步骤4还可以包括：
(41)在势垒层上光刻第一个氟注入区域和第m个氟注入区域；
(42)对第一个氟注入区域和第m个氟注入区域进行氟离子注入以形成第一个氟掺杂区和第m个氟掺杂区，其中，第一个氟掺杂区的氟离子浓度n 1和第m个氟掺杂区的氟离子浓度n m相等；
(43)在势垒层上光刻第1+j个氟注入区域和第m-j个氟注入区，并分别进行氟离子注入以形成第1+j个氟掺杂区和第m-j个氟掺杂区，其中，第1+j个氟掺杂区的氟离子浓度n 1+j和第m-j个氟掺杂区的氟离子浓度n m-j相等，且满足n j＜n 1+j或者n j＞n 1+j，其中，
Figure PCTCN2021082805-appb-000003
m为奇数；
Figure PCTCN2021082805-appb-000004
m为偶数。
在本实施例中，由于m个氟掺杂区的氟离子浓度是从两端向中间递增或者递减的，因此，可以同时形成两个氟离子浓度相同的氟注入区域，并进行氟离子注入，然后在制备下一组浓度相同的氟掺杂区，以此类推，直至形成m个氟离子浓度由两端到中间逐渐增加或者减少的一系列氟掺杂区。
在本发明的另一个实施例中，步骤4还可以包括：
在势垒层上光刻第k个氟注入区域，并进行氟离子注入以形成浓度相同的若干氟掺杂区；其中，k为大于等于1的奇数或者偶数，且k≤m。
通过对间隔排列的氟注入区域进行氟离子注入，形成了具有一定浓度和浓度为零间隔排列的氟离子掺杂区。
此外，在上述步骤之后，还包括：
在势垒层上光刻第l个氟注入区域，并进行氟离子注入以形成浓度相同的若干氟掺杂区；其中，l为大于等于1的偶数或者奇数，且l≤m。
通过对间隔排列的氟注入区域进行两次氟离子注入，形成了具有两种不同浓度间隔排列的氟离子掺杂区。
进一步地，为了激活注入的氟离子，可以在步骤4进行氟离子注入之后立刻进行后退火，其中，退火温度在340℃以上，时间在10min以上。本发明提供的流程中退火在制成栅电极后进行，实际也可在氟注入后。
步骤5：在氟掺杂区上面制作栅电极，以完成高线性HEMT器件的制备。
(5a)在步骤4所得的样品表面涂胶并甩胶，得到光刻胶掩膜；
(5b)对样品进行烘干，并通过光刻和显影技术形成第二掩膜层；
(5b)在第二掩膜层表面蒸发第二金属层，以得到栅极金属；
(5c)利用剥离工艺去除第二掩膜层以及第二金属层，并进行快速退火，得到栅电极，以完成器件制备。
在本实施例中，第二掩膜层即为栅区域掩膜图形，第二金属层即为栅极金属层。
进一步地，为了激活注入的氟离子，步骤(5c)中的退火工艺也可以在步骤4进行氟离子注入之后进行，其中，退火温度在340℃以上，时间在10min以上。
可选的，本实施例中步骤1获取的外延基片还可以包括设置于势垒层之上的盖帽层，然后再制作源漏电极以及后面工艺的制程。
本实施例提供的高线性HEMT器件工艺简单、兼容性好、便于器件制备与工艺调节，且引入的附加效应小，具有更高的可行性和重复性；同时，因通过氟注入对器件转移曲线进行调整的研究在过往增强型器件的研究中已有大量数据，可直接参考相关研究成果，各分立器件参数易于获取，工艺流程易于控制。
实施例七
下面以制备氟注入浓度由一端向另一端递增的HEMT器件为例来对本发明的制备方法进行详细说明。
请参见图8a～8f，图8a～8f是制备图1所示的高线性HEMT器件的过程示意图，具体包括：
S1：获取含有蓝宝石衬底10、GaN缓冲层20以及AlGaN势垒层30的样片，并对样片进行清洗，如图8a所示；
S2：在AlGaN势垒层30上制作源级41、漏极43，如图8b所示；
具体地，在S1所得样品表面涂胶并甩胶，得到光刻胶掩膜；并进行烘干，然后通过光刻和显影技术形成源、漏区域掩膜图形；
在做好掩膜的样品表面蒸发得到源、漏极金属；
利用剥离工艺去除掩膜层及金属层，并进行快速退火，得到源电极41和漏电极43。
S3：对样品进行台面刻蚀，以在所述势垒层30上形成隔离台面；
具体地，在步骤S2所得的样品表面涂胶，甩胶后得到光刻胶掩膜，经烘干后通过光刻和显影形成台面区域掩膜图形；
对做好掩膜的样品进行刻蚀，得到隔离台面。
S4：在AlGaN势垒层30中分次、分区域注入不同浓度的氟离子，以形成m个氟离子浓度不同的氟掺杂区。
具体地，在AlGaN势垒层30的栅极区域上光刻第一个氟注入区域F1：首先在步骤S3所得样品表面涂胶并甩胶，得到光刻胶掩膜，然后进行烘干，并通过光刻和显影形成栅下第一氟注入区域F1图形；如图8c所示；
利用氟基反应等离子体刻蚀工艺对做第一氟注入区域F1进行氟注入，其中，反应气体为CF 4等离子体，功率为60～200W，刻蚀时间为50～300s使得区域F1内氟离子浓度为n1。
参照上述过程，分别光刻栅下氟注入区域F2、F3、……、Fm，并对其分别进行氟注入，其氟离子浓度分别为n 2、n 3、……、n m，其中，n 1<n 2<……<n m-1<n m，如图8d所示，最终得到氟离 子浓度从一端向另一端递增的一系列氟掺杂区，如图8e所示。
对整个样品进行退火处理以激活氟离子，其中，退火温度在340℃以上，时间在10min以上。
S5：在源电极41和漏电极43间的势垒层30上与氟掺杂区对应的区域制作栅电极42，如图8f所示。
具体地，在步骤S4所得样品上涂胶并甩胶，得到光刻胶掩膜，并进行烘干，然后通过光刻和显影技术形成栅电极区域掩膜图形；
在做好掩膜的样品表面蒸发栅极金属；
利用剥离工艺去除掩膜层及金属层，得到栅电极40，以完成器件制备。
实施例八
在上述实施例六的基础上，下面以制备氟注入浓度由两端到中间逐渐增加的HEMT器件为例进行说明，具体包括以下步骤：
步骤A：获取含有蓝宝石衬底10、GaN缓冲层20以及AlGaN势垒层30的样片，并对样片进行清洗；
步骤B：在AlGaN势垒层30上制作源级41、漏极43；
步骤C：对样品进行台面刻蚀，以在所述势垒层30上形成隔离台面；
在本实施例中，步骤A～C与实施例三的步骤S1～S3相同，在此不再赘述。
步骤D：在AlGaN势垒层30中分次、分区域注入不同浓度的氟离子，以形成m个氟离子浓度不同的氟掺杂区。
本实施例的氟注入浓度是由两端到中间逐渐增加的。请参见图9a～9b，图9a～9b是本发明实施例提供的一种氟注入工艺的方法示意图。
首先，在AlGaN势垒层30的栅极区域上光刻第一组氟注入区域F1和Fm：
具体地，在步骤C所得样品表面涂胶并甩胶，得到光刻胶掩膜，然后经烘干后通过光刻和显影形成栅下第一组氟注入区域F1和Fm的图形；如图9a所示；
利用氟基反应等离子体刻蚀工艺对第一组氟注入区域进行氟注入，使得区域F1、Fm内氟离子浓度为均为n 1；
参照上述过程，分别光刻栅下第二组氟注入区域F2和Fm-1并进行氟离子注入，得到氟离子浓度为n 2的氟掺杂区F2和Fm-1，以此类推。其中，n1<n2<n3<……，如图9b所示；
最终，在势垒层30中形成氟离子浓度由两端到中间逐渐增加的一系列氟掺杂区。
步骤E：在源电极41和漏电极43间的势垒层30上与氟掺杂区对应的区域制作栅电极42，具体步骤与上述实施例五的步骤S5相同，在此不再赘述。
实施例九
在上述实施例六的基础上，下面以制备氟注入浓度为两种且两种不同浓度的氟掺杂区间隔排列的HEMT器件为例进行说明，具体包括以下步骤：
具体地，可按照实施例六中的步骤1至3的步骤制备具有势垒层隔离台面的样本，然后进行氟离子注入。请参见图10a～10b，图10a～10b是本发明实施例提供的另一种氟注入工艺的方法示意图。
首先，在势垒层上光刻第k个氟注入区域，并进行氟离子注入以形成浓度相同的若干氟掺杂区；其中，k为大于等于1的奇数或者偶数，且k≤m。本实施例以k为奇数进行说明，如图10a所示。然后对其余区域不进行氟离子注入。
经过上述操作，形成了具有一定浓度和浓度为零间隔排列的氟离子掺杂区。
进一步地，在对奇数区域进行离子注入之后，还可以对偶数区域祝融另一种浓度的离子，即
在势垒层上光刻第l个氟注入区域，并进行氟离子注入以形成浓度相同的若干氟掺杂区；其中，l为大于等于1的偶数或者奇数，且l≤m。
至此，形成了具有两种浓度且两种浓度间隔排列的氟注入区域，如图10b所示。
最后，在源电极41和漏电极43间的势垒层30上与氟掺杂区对应的区域制作栅电极42，具体步骤与上述实施例七的步骤S5相同，在此不再赘述。
实施例十
本实施例提供了一种高线性HEMT器件制备方法，用以制备上述实施例二提供的高线性HEMT器件。请参见图11，图11是制备图4所示的高线性HEMT器件的方法流程图。
由于图4所示的器件相比图1所示的器件，还包括了位于源电极41和漏电极43之间，且位于栅电极42下方的介质层。相应的，在制备过程中，可在上述实施例四提供等方法基础上，在完成步骤4之后，在在势垒层上淀积介质层。
具体地，在完成氟注入的势垒层上，淀积一均匀的Si 3N 4或Al 2O 3介质层。介质层的材料、厚度和工艺要综合考虑其对器件栅控能力的影响和对栅漏电的抑制作用等进行设计。
介质层制备完成后，再在介质层上制备栅电极，从而完成器件制备。
进一步地，本实施例提供等制备方法其余步骤可参考上述实施例六、实施例七、以及实施例八，在此不再赘述。
实施例十一
本实施例提供了一种高线性HEMT器件制备方法，用以制备上述实施例三提供的高线性HEMT器件。请参见图12，图12是制备图5所示的高线性HEMT器件的方法流程图。具体地，
步骤A：获取外延基片并进行清洗；其中，外延基片包括势垒层；
步骤B：在势垒层上制作源电极和漏电极；
步骤C：对外延基片进行台面刻蚀，以在势垒层上形成隔离台面；
步骤D：在源电极和漏电极之间的势垒层上淀积介质层；
步骤E：对介质层进行氟离子注入以形成若干氟掺杂区；其中，氟掺杂区位于源电极和漏电极之间；
步骤F：在介质层上与氟掺杂区对应的区域制作栅电极，以完成高线性HEMT器件的制备。
由于图5所示的器件相比图4所示的器件，其氟掺杂区位于势垒层上方的介质层，因此，在具体制备过程中，需要先淀积介质层，然后再进行氟注入以在介质层中形成氟掺杂区，最后在介质层制备栅电极。
具体地，本实施例在介质层进行氟离子注入以形成若干氟掺杂区与上述实施例七至实施例九提供的在势垒层进行氟离子注入以形成若干氟掺杂区的方法相同，详细过程在此不再赘述。
本发明提供的高线性HEMT器件制备方法在实际中，工艺流程可能与上述流程不同，如台面隔离和源、漏电极制备的顺序可以互换等。此外，器件结构中也可能包括成核层、插入层、盖帽层以及钝化层等优化结构。无论具体实现方式如何，所有基于本发明所提出的器件结构所进行的结构、方法或功能上的变换均应包含在本发明的保护范围内。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (17)

  1. 一种高线性HEMT器件，其特征在于，自下而上依次包括：衬底层(10)、缓冲层(20)、势垒层(30)以及金属电极层(40)，所述金属电极层(40)从左至右依次包括源电极(41)、栅电极(42)以及漏电极(43)；其中，所述势垒层(30)包括依次均匀排列的若干氟掺杂区F1～Fm，m为正整数且m≥2，所述若干氟掺杂区F1～Fm的氟离子浓度至少包括两种。
  2. 根据权利要求1所述的高线性HEMT器件，其特征在于，还包括介质层(50)，所述介质层(50)设置于所述源电极(41)和所述漏电极(43)之间，所述栅电极(42)设置于所述介质层(50)上方。
  3. 一种高线性HEMT器件，其特征在于，自下而上依次包括：衬底层(10)、缓冲层(20)、势垒层(30)以及金属电极层(40)，所述金属电极层(40)两端设有源电极(41)和漏电极(43)，所述源电极(41)和漏电极(43)之间设有介质层(50)，所述栅电极(42)设置于所述介质层(50)上方；其中，所述介质层(50)包括依次均匀排列的若干氟掺杂区F1～Fm，m为正整数且m≥2，所述若干氟掺杂区F1～Fm的氟离子浓度至少包括两种。
  4. 根据权利要求1或3所述的高线性HEMT器件，其特征在于，所述氟掺杂区F1～Fm位于所述栅电极(42)下方并沿栅宽方向排列。
  5. 根据权利要求4所述的高线性HEMT器件，其特征在于，所述氟掺杂区F1～Fm的氟离子浓度从所述氟掺杂区F1至所述氟掺杂区Fm依次递增或者递减。
  6. 根据权利要求4所述的高线性HEMT器件，其特征在于，所述氟掺杂区F1～Fm的氟离子浓度从所述氟掺杂区F1和所述氟掺杂区Fm依次向中间递增或者递减。
  7. 根据权利要求4所述的高线性HEMT器件，其特征在于，所述氟掺杂区F1～Fm的氟离子浓度包括两种不同浓度，且两种不同浓度的氟掺杂区间隔排列。
  8. 根据权利要求4所述的高线性HEMT器件，其特征在于，还包括成核层、插入层、盖帽层以及钝化层中的至少一层；其中，
    所述成核层设置于所述衬底层(10)和所述缓冲层(20)之间；
    所述插入层设置于所述缓冲层(20)和所述势垒层(30)之间；
    所述盖帽层设置于所述势垒层(30)与所述金属电极层(40)之间；
    所述钝化层设置于所述势垒层(30)上方各电极之间的区域。
  9. 一种高线性HEMT器件，其特征在于，自下而上依次包括：衬底层(10)、缓冲层(20)、势垒层(30)以及金属电极层(40)，所述金属电极层(40)从左至右依次包括源电极(41)、栅电极(42)以及漏电极(43)；其中，所述势垒层(30)包括依次均匀排列的若干负电离子掺杂区F1～Fm，m为正整数且m≥2，所述若干负电离子掺杂区F1～Fm的负电离子浓度至少包括两种。
  10. 一种高线性HEMT器件，其特征在于，自下而上依次包括：衬底层(10)、缓冲层(20)、势垒层(30)以及金属电极层(40)，所述金属电极层(40)两端设有源电极(41)和漏电极(43)，所述源电极(41)和漏电极(43)之间设有介质层(50)，所述栅电极(42)设置于所述介质层(50)上方；其中，所述介质层(50)包括依次均匀排列的若干负电离子掺杂区F1～Fm，m为正整数且m≥2，所述若干负电离子掺杂区F1～Fm的负电离子浓度至少包括两种。
  11. 一种高线性HEMT器件的制备方法，其特征在于，包括：
    步骤1：获取外延基片并进行清洗；其中，所述外延基片包括势垒层；
    步骤2：在所述势垒层上制作源电极和漏电极；
    步骤3：对所述外延基片进行台面刻蚀，以在所述势垒层上形成隔离台面；
    步骤4：对所述势垒层进行氟离子注入以形成若干氟掺杂区；其中，所述氟掺杂区位于所述源电 极和所述漏电极之间；
    步骤5：在所述氟掺杂区上面制作栅电极，以完成高线性HEMT器件的制备。
  12. 根据权利要求11所述的制备方法，其特征在于，在步骤4之后，还包括：
    在所述势垒层上淀积介质层；其中，所述介质层设置于所述源电极和所述漏电极之间。
  13. 根据权利要求11所述的制备方法，其特征在于，步骤4包括：
    (4a)在所述势垒层上光刻第一个氟注入区域；
    (4b)对所述第一个氟注入区域进行氟离子注入以形成第一个氟掺杂区，其中，所述第一个氟掺杂区的氟离子浓度为n 1；
    (4c)在所述势垒层上光刻第i个氟注入区域，并分别进行氟离子注入以形成第i个氟掺杂区，其中，所述第i个氟掺杂区的氟离子浓度为n i，且满足n i-1＜n i或者n i-1＞n i，其中，2≤i≤m，i、m均为正整数。
  14. 根据权利要求11所述的制备方法，其特征在于，步骤4包括：
    (41)在所述势垒层上光刻第一个氟注入区域和第m个氟注入区域；
    (42)对所述第一个氟注入区域和所述第m个氟注入区域进行氟离子注入以形成第一个氟掺杂区和第m个氟掺杂区，其中，所述第一个氟掺杂区的氟离子浓度n 1和所述第m个氟掺杂区的氟离子浓度n m相等；
    (43)在所述势垒层上光刻第1+j个氟注入区域和第m-j个氟注入区，并分别进行氟离子注入以形成第1+j个氟掺杂区和第m-j个氟掺杂区，其中，所述第1+j个氟掺杂区的氟离子浓度n 1+j和所述第m-j个氟掺杂区的氟离子浓度n m-j相等，且满足n j＜n 1+j或者n j＞n 1+j，其中，
    Figure PCTCN2021082805-appb-100001
    m为奇数；
    Figure PCTCN2021082805-appb-100002
    m为偶数。
  15. 根据权利要求11所述的制备方法，其特征在于，步骤4包括：
    在所述势垒层上光刻第k个氟注入区域，并进行氟离子注入以形成浓度相同的若干氟掺杂区；其中，k为大于等于1的奇数或者偶数，且k≤m。
  16. 根据权利要求15所述的制备方法，其特征在于，还包括：
    在所述势垒层上光刻第l个氟注入区域，并进行氟离子注入以形成浓度相同的若干氟掺杂区；其中，l为大于等于1的偶数或者奇数，且l≤m。
  17. 一种高线性HEMT器件的制备方法，其特征在于，包括：
    步骤A：获取外延基片并进行清洗；其中，所述外延基片包括势垒层；
    步骤B：在所述势垒层上制作源电极和漏电极；
    步骤C：对所述外延基片进行台面刻蚀，以在所述势垒层上形成隔离台面；
    步骤D：在所述源电极和所述漏电极之间的势垒层上淀积介质层；
    步骤E：对所述介质层进行氟离子注入以形成若干氟掺杂区；其中，所述氟掺杂区位于所述源电极和所述漏电极之间；
    步骤F：在所述介质层上与氟掺杂区对应的区域制作栅电极，以完成高线性HEMT器件的制备。
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CN104966731A (zh) * 2015-07-06 2015-10-07 大连理工大学 具有三明治栅极介质结构的hemt器件及其制备方法
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CN111668303A (zh) * 2020-05-13 2020-09-15 西安电子科技大学 一种高线性hemt器件及其制备方法
CN111668304A (zh) * 2020-05-13 2020-09-15 西安电子科技大学 一种高线性mis-hemt器件及其制备方法
CN111668305A (zh) * 2020-05-13 2020-09-15 西安电子科技大学 一种高线性mis-hemt器件及其制备方法

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