CN112885891A - 一种提高氮化镓hemt功率器件击穿电压的结构及其制备方法 - Google Patents
一种提高氮化镓hemt功率器件击穿电压的结构及其制备方法 Download PDFInfo
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Abstract
本发明提供了一种提高氮化镓HEMT功率器件击穿电压的结构及其制备方法，结构包括衬底、外延层、源极、漏极以及栅极；所述外延层位于所述衬底上方，包括由下至上设置的成核层、第一材料层、沟道层以及势垒层；所述沟道层内具有二维电子气，所述势垒层内具有离子掺杂区域。本发明通过在栅极、漏极之间引入离子掺杂区域，改变沟道中部分区域的二维电子气浓度，在栅极一侧改变电场分布，该峰值电场显著低于无离子掺杂区域的器件，栅漏间的电场均匀性得到加强，电场分布得到有效改善，避免栅边缘电场峰值引起器件的提前击穿，器件可以承受更高的漏极电压。最终器件的击穿电压得到提升，且器件的频率特性不会降低。
Description
技术领域
本发明属于功率半导体技术领域，尤其是涉及一种提高氮化镓HEMT功率器件击穿电压的结构及其制备方法。
背景技术
GaN作为第三代宽禁带化合物半导体材料,具有禁带宽度大、击穿电压高、电子漂移速度快和抗辐射能力强等特点，AlGaN/GaN结构的HEMT器件具有耐高温、耐高压、良好的高频大功率等特性。AlGaN/GaN异质结具有较强的极化效应,即使在未掺杂时，器件也可获得高达1×1013cm-2面密度的二维电子气。近年来，在现有AlGaN/GaN异质结构的基础上，如何进一步优化GaN HEMT器件结构和提升器件击穿电压成为研究的热点。
造成器件击穿的因素有多方面：
1、栅极边缘电场强度过高；当在AlGaN/GaN HEMT器件漏极施加较高电压时，沟道中的耗尽区会逐渐移动至漏极一侧。势垒层的极化正电荷引起的电场分布会集中指向栅极边缘，在边缘位置形成峰值电场。当电场强度超出器件的耐压能力时，器件容易发生击穿现象。
2、栅极泄漏电流；器件的表面的缺陷、沾污、悬挂键等容易形成表面态，其表面漂移点到现象造成栅极的泄漏电流。当栅极电压过高时，电子通过栅极峰值电场的边缘隧穿到栅源之间的表面态中，造成器件击穿。
为解决以上问题，通常在器件中设计场板，利用场板技术将峰值电场平坦化的分布于栅漏之间，以提高器件的击穿电压。但场板的引入会带来额外的电容，降低器件的频率特性。
发明内容
为解决上述问题，本发明提供了一种提高氮化镓HEMT功率器件击穿电压的结构及其制备方法。
为实现上述目的，本发明的技术方案为：
一种提高氮化镓HEMT功率器件击穿电压的结构，包括：
衬底；
外延层，位于所述衬底上方，包括由下至上设置的成核层、第一材料层、沟道层以及势垒层；所述沟道层内具有二维电子气，所述势垒层内具有离子掺杂区域；
源极，位于所述外延层上方；
漏极，位于所述外延层上方；
栅极，位于所述源极与漏极之间；
其中，所述离子掺杂区域位于栅极与漏极之间，靠近栅极一侧。
进一步的，所述势垒层包括第二材料层。
进一步的，所述势垒层还包括第三材料层，所述第三材料层位于沟道层与第二材料层之间，所述第三材料层的禁带宽度大于第二材料层。
进一步的，所述势垒层还包括第四材料层，所述第四材料层位于第二材料层上方。
进一步的，所述离子掺杂区域的宽度为栅极与漏极间距的1％～90％，高度为所述势垒层的厚度。
一种提高氮化镓HEMT功率器件击穿电压的结构的制备方法，包括以下步骤：
提供衬底，在衬底上形成外延层，所述外延层包括由下至上堆叠而成的成核层、第一材料层、沟道层以及势垒层；
在势垒层内进行离子掺杂形成离子掺杂区域；
对离子掺杂区域进行快速热处理，使掺杂离子分布均匀；
并在外延层表面采用光刻和蒸发工艺形成源极和漏极；
在源极、掺杂区域之间的外延层表面形成栅极，并使栅极靠近离子掺杂区域。
进一步的，所述离子掺杂所采用的离子元素为氟、硅、磷、硫、氯、锗、砷以及硒中的一种或多种组合，浓度为1×1012cm-3～1×1018cm-3。
进一步的，所述快速热处理的温度为200℃～1300℃，时间为5s～600s。
相对于现有技术，本发明的有益效果在于：
本发明在形成源极、漏极后并未立即制作栅极，而是在预设的栅极边缘的特定区域进行离子掺杂。而在栅极、漏极之间引入离子掺杂区域，可以改变沟道中部分区域的二维电子气浓度，在栅极一侧改变电场分布，该峰值电场显著低于无离子掺杂区域的器件，栅漏间的电场均匀性得到加强，电场分布得到有效改善，避免栅边缘电场峰值引起器件的提前击穿，器件可以承受更高的漏极电压。最终器件的击穿电压得到提升，且器件的频率特性不会降低。
附图说明
图1A～图1C为本公开实施例1中提高氮化镓HEMT功率器件击穿电压的结构的制备方法示意图。
图2A～图2C为本公开实施例2中提高氮化镓HEMT功率器件击穿电压的结构的制备方法示意图。
图3A～图3C为本公开实施例3中提高氮化镓HEMT功率器件击穿电压的结构的制备方法示意图。
图中：1、衬底；2、外延层；201、成核层；202、第一材料层；203、沟道层；204、第二材料层；205、二维电子气；206、第三材料层；207、第四材料层；3、离子掺杂区域；4、源极；5、栅极；6、漏极。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
实施例1：
参照图1A-图1C，本实施例中一种提高氮化镓HEMT功率器件击穿电压的结构的制备方法，包括以下步骤：
步骤1：如图1A所示，选择碳化硅为衬底1材料，在衬底1上依次由下至上形成成核层201、第一材料层202、沟道层203以及第二材料层204；其中成核层201的材料为氮化铝，第一材料层202的材料为氮化镓，沟道层203的材料为氮化镓，第二材料层204的材料为铝镓氮；利用光刻工艺，将非离子掺杂区域遮挡，利用注入工艺在第二材料层204中引入砷离子，浓度为5×1013cm-3，形成离子掺杂区域3，离子掺杂区域3宽度LIMP为1um；
步骤2：进行快速热处理，处理温度350℃，时间为200s，使掺杂的砷离子分布均匀；
步骤3：如图1B所示，在第二材料层204表面采用光刻和蒸发工艺形成源极4和漏极6，其中，源极4、漏极6位于离子掺杂区域3两侧，源极4到漏极6距离LSD为5um；
步骤4：如图1C所示，利用光刻和蒸发工艺在源极4和漏极6之间制备栅极5，栅极5宽度LG为0.5um，栅极5与源极4的间距LSG为1um，栅极5与漏极6的间距LGD为3.5um，栅极5边缘与离子掺杂区域3相邻。
在其他相同条件下，相对于传统的半导体器件，本实施例的半导体器件的击穿电压由440V提升为590V。
实施例2：
参照图2A-图2C，本实施例中一种提高氮化镓HEMT功率器件击穿电压的结构的制备方法，包括以下步骤：
步骤1：如图2A所示，选择碳化硅为衬底1材料，在衬底1上依次由下至上形成成核层201、第一材料层202、沟道层203、第三材料层206以及第二材料层204；其中成核层201的材料为氮化铝，第一材料层202的材料为氮化镓，沟道层203的材料为氮化镓，第三材料层206的材料为铟镓氮，第二材料层204的材料为铝镓氮；利用光刻工艺，将非离子掺杂区域遮挡，利用注入工艺在第二材料层204、第三材料层206中引入氟离子，浓度为1.5×1015cm-3，形成离子掺杂区域3，离子掺杂区域3宽度LIMP为0.8um；
步骤2：进行快速热处理，处理温度500℃，时间为90s，使掺杂的氟离子分布均匀；
步骤3：如图2B所示，在第二材料层204表面采用光刻和蒸发工艺形成源极4和漏极6，其中，源极4、漏极6位于离子掺杂区域3两侧，源极4到漏极6距离LSD为4um；
步骤4：如图2C所示，利用光刻和蒸发工艺在源极4和漏极6之间制备栅极5，栅极5宽度LG为0.35um，栅极5与源极4的间距LSG为0.9um，栅极5与漏极6的间距LGD为2.75um，栅极5边缘与离子掺杂区域3相邻。
在其他相同条件下，相对于传统的半导体器件，本实施例的半导体器件的击穿电压由310V提升为390V。
实施例3：
参照图3A-图3C，本实施例中一种提高氮化镓HEMT功率器件击穿电压的结构的制备方法，包括以下步骤：
步骤1：如图3A所示，选择碳化硅为衬底1材料，在衬底1上依次由下至上形成成核层201、第一材料层202、沟道层203、第二材料层204以及第四材料层207；其中成核层201的材料为氮化铝，第一材料层202的材料为氮化镓，沟道层203的材料为氮化镓，第二材料层204的材料为铝镓氮，第四材料层207的材料为氮化镓；利用光刻工艺，将非离子掺杂区域遮挡，利用注入工艺在第二材料层204、第四材料层207中引入磷离子，浓度为6×1014cm-3，形成离子掺杂区域3，离子掺杂区域3宽度LIMP为0.6um；
步骤2：进行快速热处理，处理温度430℃，时间为160s，使掺杂的磷离子分布均匀；
步骤3：如图3B所示，在第四材料层207表面采用光刻和蒸发工艺形成源极4和漏极6，其中，源极4、漏极6位于离子掺杂区域3两侧，源极4到漏极6距离LSD为3.5um；
步骤4：如图3C所示，利用光刻和蒸发工艺在源极4和漏极6之间制备栅极5，栅极5宽度LG为0.25um，栅极5与源极4的间距LSG为0.75um，栅极5与漏极6的间距LGD为2.5um，栅极5边缘与离子掺杂区域3相邻。
在其他相同条件下，相对于传统的半导体器件，本实施例的半导体器件的击穿电压由210V提升为280V。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (8)
1.一种提高氮化镓HEMT功率器件击穿电压的结构，其特征在于，包括：
衬底；
外延层，位于所述衬底上方，包括由下至上设置的成核层、第一材料层、沟道层以及势垒层；所述沟道层内具有二维电子气，所述势垒层内具有离子掺杂区域；
源极，位于所述外延层上方；
漏极，位于所述外延层上方；
栅极，位于所述源极与漏极之间；
其中，所述离子掺杂区域位于栅极与漏极之间，靠近栅极一侧。
2.根据权利要求1所述的提高氮化镓HEMT功率器件击穿电压的结构，其特征在于：所述势垒层包括第二材料层。
3.根据权利要求2所述的提高氮化镓HEMT功率器件击穿电压的结构，其特征在于：所述势垒层还包括第三材料层，所述第三材料层位于沟道层与第二材料层之间，所述第三材料层的禁带宽度大于第二材料层。
4.根据权利要求2或3所述的提高氮化镓HEMT功率器件击穿电压的结构，其特征在于：所述势垒层还包括第四材料层，所述第四材料层位于第二材料层上方。
5.根据权利要求1或2或3所述的提高氮化镓HEMT功率器件击穿电压的结构，其特征在于：所述离子掺杂区域的宽度为栅极与漏极间距的1％～90％，高度为所述势垒层的厚度。
6.一种提高氮化镓HEMT功率器件击穿电压的结构的制备方法，其特征在于包括以下步骤：
提供衬底，在衬底上形成外延层，所述外延层包括由下至上堆叠而成的成核层、第一材料层、沟道层以及势垒层；
在势垒层内进行离子掺杂形成离子掺杂区域；
对离子掺杂区域进行快速热处理，使掺杂离子分布均匀；
并在外延层表面采用光刻和蒸发工艺形成源极和漏极；
在源极、掺杂区域之间的外延层表面形成栅极，并使栅极靠近离子掺杂区域。
7.根据权利要求6所述的提高氮化镓HEMT功率器件击穿电压的结构的制备方法，其特征在于：所述离子掺杂所采用的离子元素为氟、硅、磷、硫、氯、锗、砷以及硒中的一种或多种组合，浓度为1×1012cm-3～1×1018cm-3。
8.根据权利要求6所述的提高氮化镓HEMT功率器件击穿电压的结构的制备方法，其特征在于：所述快速热处理的温度为200℃～1300℃，时间为5s～600s。
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| WO2023082058A1 (en) * | 2021-11-09 | 2023-05-19 | Innoscience (Suzhou) Technology Co., Ltd. | Nitride-based semiconductor device and method for manufacturing thereof |
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| CN113809155A (zh) * | 2021-08-25 | 2021-12-17 | 西安电子科技大学 | 一种带有终端结构的GaN基射频器件及其制作方法 |
| WO2023082058A1 (en) * | 2021-11-09 | 2023-05-19 | Innoscience (Suzhou) Technology Co., Ltd. | Nitride-based semiconductor device and method for manufacturing thereof |
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