WO2021226833A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021226833A1
WO2021226833A1 PCT/CN2020/089818 CN2020089818W WO2021226833A1 WO 2021226833 A1 WO2021226833 A1 WO 2021226833A1 CN 2020089818 W CN2020089818 W CN 2020089818W WO 2021226833 A1 WO2021226833 A1 WO 2021226833A1
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WO
WIPO (PCT)
Prior art keywords
pads
thin film
film transistor
electrically connected
level signal
Prior art date
Application number
PCT/CN2020/089818
Other languages
English (en)
French (fr)
Inventor
都蒙蒙
董向丹
马宏伟
刘彪
张波
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/089818 priority Critical patent/WO2021226833A1/zh
Priority to US17/276,624 priority patent/US11728228B2/en
Priority to CN202080000721.6A priority patent/CN114026489B/zh
Priority to EP20897680.3A priority patent/EP4152084A4/en
Publication of WO2021226833A1 publication Critical patent/WO2021226833A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • OLED display devices are one of the hot spots in the field of flat panel display device research today.
  • OLED display light-emitting devices have bright colors, good viewing angles, high contrast, and response speed.
  • Fast, bendable, low power consumption and other advantages have attracted people's attention.
  • OLED display devices, especially active matrix organic light-emitting diode (AMLOED) display devices have broader application prospects in the display field in the future, and they have broad application space in multiple display fields such as mobile display, vehicle display, and medical display.
  • AMLOED active matrix organic light-emitting diode
  • An embodiment of the present disclosure provides a display substrate, including: a base substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixel units located in the display area; a plurality of data lines located in the display area Multiple data transmission lines located in the peripheral area on at least one side of the display area and electrically connected to the multiple data lines respectively; multiple first pads And a plurality of second pads located on a side of the plurality of data transmission lines away from the display area, and the plurality of first pads and the plurality of second pads are respectively along the direction of the boundary of the display area Extending, the plurality of second pads are located between the plurality of first pads and the plurality of data transmission lines, and are electrically connected to the plurality of data transmission lines; and the plurality of third pads are located on the Between the plurality of first pads and the plurality of second pads, and at least part of the plurality of third pads are electrically connected to the plurality of second pads; A device located between the plurality of second pads and the plurality of third pads,
  • At least one of the multiple multiplexers includes: a first thin film transistor and a second thin film transistor, and the first thin film transistor includes a first source electrode, a first drain electrode, and a first thin film transistor.
  • the second thin film transistor includes a second source, a second drain, and a second gate, one of the first source and the first drain, and the second source and One of the second drains is electrically connected to the same pad of the plurality of third pads, and the other one of the first source and the first drain is electrically connected to all One of the plurality of second pads, the other one of the second source electrode and the second drain electrode is electrically connected to the other pad of the plurality of second pads, so
  • the first gate is electrically connected to the first control line
  • the second gate is electrically connected to the second control line
  • the first control line is used to access a first level signal
  • the second control The line is used to connect the second level signal, and the first level signal and the second level signal are used to make the first grid and the second grid in the multiplex
  • the plurality of third pads further include: a first control terminal pad, which is electrically connected to the first control line; and a second control terminal pad, The second control terminal pad is electrically connected to the second control line.
  • the display substrate further includes a first level signal line and a second level signal line located between the plurality of first pads and the plurality of third pads, and the plurality of The first pads include at least one first-level input pad and at least one second-level input pad, and the at least one first-level signal line is electrically connected to the first control terminal pad and the second control terminal pad.
  • One of the terminal pads and the at least one first-level input pad, and the second-level signal line is electrically connected to the other of the first control terminal pad and the second control terminal pad and the The at least one second level input pad.
  • the display substrate further includes a first level connection portion and a second level connection portion, the number of the at least one first level input pad is multiple, and the at least one second level connection portion
  • the number of flat input pads is multiple;
  • the first level connecting portion is located between the plurality of first level input pads and the first level signal line, and is connected to the first level signal line.
  • the signal line is electrically connected to the plurality of first-level input pads;
  • the second level connecting portion is located between the plurality of second-level input pads and the second-level signal line, and It is electrically connected to the second-level signal line and the plurality of second-level input pads.
  • first level connection part and the first level signal line are an integral structure
  • second level connection part and the second level signal line are an integral structure
  • the first level signal is a positive voltage signal or a negative voltage signal
  • the second level signal is a positive voltage signal or a negative voltage signal
  • the value range of the positive voltage signal is between 6V and 8V, and the value range of the negative voltage signal is between -8V and -6V.
  • the first control line, the second control line, the first level signal line, the second level signal line, the gate of the first thin film transistor and the gate of the second thin film transistor are made of the same material and arranged on the same layer.
  • the plurality of third pads are configured to input test signals to the plurality of sub-pixels, and the plurality of first pads and the plurality of second pads are configured to be integrated with the same Circuit device binding.
  • the display substrate further includes a third-level signal line, a fourth-level signal line, and a plurality of electrostatic discharge structures.
  • the third-level signal line is used to provide a positive-level signal.
  • the fourth level signal line is used to provide a negative level signal, wherein at least one electrostatic discharge structure includes: a third thin film transistor, the gate of the third thin film transistor is electrically connected to the third level signal line, and the third One of the source and drain of the thin film transistor is electrically connected to the third level signal line, and the other is electrically connected to the pad corresponding to one of the plurality of third pads; the fourth thin film transistor, the The gate of the fourth thin film transistor is electrically connected to the third level signal line, one of the source and drain of the fourth thin film transistor is electrically connected to the third level signal line, and the other is electrically connected to the plurality of The corresponding pad in the third pad is electrically connected; a fifth thin film transistor, the gate of the fifth thin film transistor is electrically connected to the corresponding pad in the plurality
  • the third thin film transistor and the fourth thin film transistor each include an active layer
  • the gates in the third thin film transistor and the fourth thin film transistor include first strip-shaped sub-gates and The second strip-shaped sub-gate
  • the one of the source and the drain in each of the third thin film transistor and the fourth thin film transistor has a first arm and a second connected to each other An arm portion, the first arm portion extends along a first direction, the second arm portion extends along a second direction crossing the first direction, and the first arm portion passes through a first via structure and an active Layer connection, the second arm portion is connected to the first strip-shaped sub-gate through the second via structure and connected to the second strip-shaped sub-gate through the third via structure.
  • the electrostatic discharge structure further includes: a first connection portion and a second connection portion, the first connection portion and the active layer are made of the same material and arranged on the same layer, and the The two connecting portions are made of the same material and arranged on the same layer as the source and drain electrodes.
  • the first connecting portion is connected to the third thin film transistor and the fourth thin film transistor through a third via structure.
  • the source and drain in each thin film transistor are connected to the one, the first connection part is also connected to the second connection part through a fourth via structure, and the second connection part is connected through a fifth The via structure is connected to the third level signal line.
  • At least one of the plurality of sub-pixel units includes a pixel circuit and a light-emitting element, and the pixel circuit is located between the base substrate and the light-emitting element; the light-emitting element includes a first layer stacked in sequence.
  • the pixel circuit includes at least one thin film transistor, and the thin film transistor includes The gate on the substrate, the source and drain on the side of the gate away from the base substrate, the source or the drain of the thin film transistor is electrically connected to the second electrode; the at least one thin film The source and drain of the transistor are arranged on the same layer as the plurality of first pads, the plurality of second pads, and the plurality of third pads.
  • the first level connection portion, the first level signal line, the second level connection portion, the second level signal line, and the thin film transistor in the pixel circuit The gate is located on the same layer.
  • the display substrate is a foldable substrate, the display substrate includes a bending area, and the plurality of second pads are farther from the display area than the bending area.
  • the embodiment of the present disclosure also provides a display device, including: the display substrate according to any one of the above embodiments; and an integrated circuit device, the integrated circuit device is connected to the plurality of first pads and the The second pad is bound.
  • the orthographic projection of the integrated circuit device on the base substrate at least partially covers the orthographic projection of the plurality of third pads on the base substrate.
  • the multiple multiplexers are configured to be turned off when the display device is in operation.
  • FIG. 1 is a schematic diagram of a display substrate according to some embodiments of the present disclosure
  • FIG. 2 is an enlarged schematic diagram of the layout area of the integrated circuit device in FIG. 1;
  • FIG. 3 is a schematic diagram of an integrated circuit device layout area of a display substrate according to other embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of the line connection relationship in the layout area of the integrated circuit device shown in FIG. 3;
  • FIG. 5 is an enlarged view of part E in FIG. 2, schematically showing a multiplexer in a display substrate according to some embodiments of the present disclosure
  • Figure 6 is a schematic cross-sectional view taken along the line P-P in Figure 5;
  • Figure 7 is an enlarged view of part F in Figure 2;
  • FIG. 8 schematically shows a circuit schematic diagram of an array test assembly on a display substrate according to some embodiments of the present disclosure
  • Fig. 9 is a schematic cross-sectional view taken along the line Q-Q in Fig. 7;
  • Fig. 10 is a schematic cross-sectional view taken along the line K-K in Fig. 7;
  • FIG. 11 is a schematic diagram of a film structure of a display area on a display substrate according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 13 shows a schematic diagram of an integrated circuit device layout area of a display substrate according to still other embodiments of the present disclosure.
  • first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.
  • first element may be named as the second element, and similarly, the second element may be named as the first element.
  • second element may be named as the first element.
  • the term "and/or" as used herein includes any and all combinations of one or more of the related listed items.
  • the expressions “located on the same layer” and “disposed on the same layer” generally mean that the first component and the second component can use the same material and can be formed by the same patterning process.
  • the expressions “located on different layers” and “different layer settings” generally mean that the first part and the second part are formed by different patterning processes.
  • the manufacturing process of the display panel it is necessary to continuously detect product quality problems, and timely screen out unqualified products from the inspection process, so as to adjust the process in time to achieve high-yield and low-cost production. Since materials or components such as the light-emitting layer and driver integrated circuits are relatively expensive, electrical properties will be tested before evaporating light-emitting materials and bonding circuit devices (such as integrated circuit devices, etc.). Only if the semi-finished products can meet the quality requirements, can they enter The next stage of the process. The commonly used detection method to detect whether the electrical properties of the panel are defective before evaporating the luminescent material is called the AT test (array test).
  • the test signal needs to be input into the TFT (thin film transistor) array in the display substrate to check whether the electrical properties of the various parts of the display substrate meet the requirements, such as whether the on-off of the circuit is consistent with the design.
  • the test signal can usually be directly connected through the cable of the flexible circuit board to input it to the TFT array in the display substrate.
  • the flat cable may no longer be arranged on the display substrate or the test signal cannot be introduced to the display substrate only through the flat cable due to the problem of the circuit connection.
  • the desired TFT array is the desired TFT array.
  • FIG. 1 shows an example of such a display substrate 100.
  • the display substrate 100 is applied to a COP display device.
  • a display area 10 and a peripheral area 20 are provided on this display substrate.
  • the display area 10 is used to display an image, and may include, for example, a plurality of sub-pixel units PIX (for example, the sub-pixel units may be arranged in an array).
  • the peripheral area 20 is located at the periphery of the display area 10 (for example, it can be arranged around the display area 10), and is used for laying out peripheral circuits (for example, driving integrated circuit devices, connecting wires, etc.).
  • the size of the frame of the display device is largely limited by the size and layout of the peripheral area 20.
  • the peripheral area 20 on each side of the display area there is often a peripheral area 20 with the most integrated circuit elements, which requires a larger area.
  • the peripheral area is located below the display area in FIG. 1.
  • the display substrate is provided with a bending area 30 in the peripheral area 20.
  • the bending area 30 is flexible. In the final product, the bending area 30 can be bent, so that a part of the peripheral area of the display substrate can be folded to the side of the display device opposite to the display surface, thereby reducing the width of the frame.
  • a high-level signal line VDD and a low-level signal line VSS may be provided in the peripheral area 20 to provide a level signal for the array test component 40.
  • the peripheral area 20 may also be provided with an interface 60 connected to a flexible printed circuit board.
  • a plurality of data lines DATA may also be provided in the display area 10, which are respectively electrically connected to the plurality of sub-pixel units PIX.
  • the data line DATA is used to provide required data driving signals for each sub-pixel unit PIX.
  • a plurality of data transmission lines DATAL (shown by dotted lines in FIG. 1) may be provided in the peripheral area 20 on at least one side of the display area 10, which are respectively electrically connected to the plurality of data lines DATA, and are used in the peripheral circuit of the display substrate. And the data line DATA.
  • the foldable part of the display substrate is usually provided with an interface to the external circuit of the display substrate and related wiring.
  • an integrated circuit device placement area 21 is included in the peripheral area 20, as shown by the dashed box in FIG. 1.
  • the integrated circuit device layout area 21 is used for layout of integrated circuit devices, and correspondingly, a plurality of first pads 31 and a plurality of second pads 32 are provided in the integrated circuit device layout area 21.
  • the plurality of first pads 31 and the plurality of second pads 32 can be used for bonding with integrated circuit devices.
  • the plurality of first pads 31 may be used to electrically connect the input signals of the integrated circuit device
  • the plurality of second pads 32 may be used to electrically connect the output signals of the integrated circuit device.
  • the plurality of first pads 31 and the plurality of second pads 32 may be located, for example, on the side of the plurality of data transmission lines DATAL away from the display area 10.
  • the plurality of first pads 31 and the plurality of second pads The two pads 32 respectively extend in the direction of the boundary K of the display area 10.
  • the plurality of second pads 32 may be located between the plurality of first pads 31 and the plurality of data transmission lines DATAL, and It is electrically connected with the plurality of data transmission lines DATAL.
  • the plurality of first pads 31 and the plurality of second pads 32 may be electrically connected to the corresponding input pins and output pins of the integrated circuit (IC) device, respectively. Connection (for example, by welding, etc.).
  • the integrated circuit device can provide each sub-pixel unit in the display area 10 with a signal on the data line DATA when the display device is working, which means that at least some pins in the integrated circuit device are connected to each sub-pixel unit. Therefore, in the manufacturing process of the display substrate, some test signals can be input from these pins to detect whether the driving circuit of the sub-pixel unit has manufacturing defects.
  • the test signal can be corresponding to the plurality of first pads 31 The pads are input to the integrated circuit device, and then transferred to each sub-pixel unit in the display area 10 through the output terminal of the integrated circuit device, so as to realize the electrical property test.
  • the AT test is performed before the light-emitting layer is fabricated and the integrated circuit device is installed. Therefore, when the AT test is performed, the integrated circuit device has not been installed. Therefore, it is impossible to use the plurality of first pads 31 to perform AT test.
  • an array test assembly 40 is provided in the integrated circuit device layout area 21.
  • the array test component 40 is located between the plurality of first pads 31 and the plurality of second pads 32. After the integrated circuit device is installed, at least most of the array test assembly 40 will be covered by the integrated circuit device, which means that the array test assembly 40 will not increase the additional wiring area of the display substrate.
  • the layout of the array test component 40 makes full use of the gap between the first pad 31 and the second pad 32 in the integrated circuit device layout area 21, which is very helpful for reducing the wiring area.
  • the array test assembly 40 is only used in AT testing, it will not be covered by integrated circuit devices in subsequent processes and will not have any adverse effects on the function of the device.
  • the array test assembly 40 may include a plurality of third pads 33 for electrically connecting the array test circuit and a plurality of connection terminals electrically connected to the plurality of second pads 32 41.
  • the plurality of third pads 33 can be used to electrically connect with an external array test circuit 50.
  • the array test circuit 50 is used to provide test signals for AT testing.
  • the test signals can be level signals to test whether the circuit has defects such as open circuits or short circuits, or other special signals used to test the electrical properties of the TFT array.
  • the array test component 40 may include a plurality of test channels, and each test channel is electrically connected to one or some of the plurality of second bonding pads 32 through one or more connection terminals 41 to perform corresponding tests.
  • Each test channel obtains a test signal from its corresponding pad among the plurality of third pads 33 and transmits the corresponding test signal to the circuit to be tested via the corresponding connection terminal 41.
  • the electrical connection between the array test circuit 50 and at least some of the plurality of third pads 33 can be achieved in a variety of ways, for example, by drawing probes from the array test circuit 50 and making the probes connect to the plurality of third pads.
  • the corresponding pads in the disk 33 are in contact, or the input wires can be drawn from the array test circuit 50 to be fixedly connected to the corresponding pads of the plurality of third pads 33, and so on.
  • the electrical connection between the array test circuit 50 and the corresponding pads of the plurality of third pads 33 does not mean that the array test circuit 50 is electrically connected to all the pads of the plurality of third pads 33 at the same time, for example, an array
  • the test circuit 50 may be electrically connected to only a part of the plurality of third pads 33 (such as one or several pads) at the same time.
  • the plurality of third pads 33 are located between the plurality of first pads 31 and the plurality of second pads 32, and at least a part of the plurality of third pads 33 is connected to the plurality of pads.
  • the corresponding pads of the second pads 32 are electrically connected.
  • the second pads 32 may be electrically connected to the data line DATA in the display area 10
  • at least some of the plurality of third pads 33 are electrically connected to the corresponding second pads 32
  • a plurality of multiplexers 42 may be provided in the array test assembly 40.
  • a plurality of multiplexers 42 may be located between the plurality of second pads 32 and the plurality of third pads 33, and at least one of the plurality of multiplexers 42 is electrically connected to all At least two second pads 32 of the plurality of second pads 32 and one third pad 33 of the plurality of third pads 33.
  • the at least one multiplexer 42 may include: an input terminal 421, a first output terminal 422, a second output terminal 423, a first control switch 424 and a second control switch 425.
  • the input terminal 421 is electrically connected to one of the plurality of third pads 33, and the first output terminal 422 is electrically connected to one of the plurality of second pads 32 (may be referred to as the first pad).
  • An output pad 321) is electrically connected, the second output terminal 423 is electrically connected to another pad (which may be referred to as the second output pad 322) of the plurality of second pads 32, and the first control switch 424 is used to control the connection and disconnection of the input terminal 421 and the first output terminal 422, and the second control switch 425 is used to control the connection and disconnection of the input terminal 421 and the second output terminal 423.
  • the multiplexer 42 can have two states.
  • the first control switch 424 In the first working state, the first control switch 424 is turned on and the second control switch 425 is turned off, and the signal input from the input terminal 421 is only provided to the first output. In the second working state, the first control switch 424 is turned off and the second control switch 425 is turned on, and the signal input from the input terminal 421 is only provided to the second output terminal 423. In this way, if it is possible to alternately control the on and off of the first control switch 424 and the second control switch 425, the multiplexer 42 can be controlled to switch back and forth between the first working state and the second working state, thereby Make it possible to complete the test for two or more output channels through one input channel. This can reduce the wiring area, which is beneficial to narrow the frame of the display device.
  • first working state and second working state are only exemplary.
  • the multiplexer 42 may also have other states, for example, the first control switch 424 and the first control switch 424 and the second working state.
  • the two control switches 425 are both in the third working state of the on state, and the first control switch 424 and the second control switch 425 are both in the non-working state of the off state.
  • the array test component 40 may further include a first control line 426 and a second control line 427.
  • the first control line 426 is electrically connected to the control terminal of the first control switch 424 of each multiplexer 42, and the second control line 427 is controlled by the second control switch 425 of each multiplexer 42. Terminals are electrically connected.
  • the signals on the first control line 426 and the second control line 427 can be input from the outside, for example, input through a plurality of third pads 33.
  • the plurality of third pads 33 may include: a first control terminal pad MUX1 and a second control terminal pad MUX2.
  • the first control terminal pad MUX1 is electrically connected to the first control line 426
  • the second control terminal pad MUX2 is electrically connected to the second control line 427.
  • the control signal input from the first control terminal pad MUX1 and the second control terminal pad MUX2 to the first control line 426 and the second control line 427 may be a periodic pulse signal, a clock signal, or the like.
  • the above-mentioned control switch may be implemented by a thin film transistor structure.
  • the first control switch 424 may include a first thin film transistor T1, and the control terminal of the first control switch 424 is the gate G1 of the first thin film transistor T1, so One of the source and drain SD1 (for example, the source) of the first thin film transistor T1 is electrically connected to the input terminal 421 of the multiplexer 42, and the source and drain of the first thin film transistor T1
  • the other SD2 (for example, the drain) is electrically connected to the first output terminal 422 of the multiplexer 42;
  • the second control switch 425 includes a second thin film transistor T2, and the second control switch
  • the control terminal of 425 is the gate G2 of the second thin film transistor T2, and one of the source and drain of the second thin film transistor T2 SD1' (for example, the source) is also multiplexed with the The input terminal 421 of the multiplexer 42 is electrically connected, and the other SD2 ′
  • one SD1 of the source and drain of the first thin film transistor T1 and one of the source and drain SD1' of the second thin film transistor T2 are connected to the plurality of third pads 33
  • the same pad in the first thin film transistor T1 is electrically connected
  • the other SD2 of the source and drain of the first thin film transistor T1 is electrically connected to one of the plurality of second pads 32
  • the second thin film transistor The other SD2' of the source and drain of T2 is electrically connected to the other of the plurality of second pads
  • the gate G1 of the first thin film transistor T1 is electrically connected to the first control pad.
  • Line 426, the gate G2 of the second thin film transistor T2 is electrically connected to the second control line 427.
  • FIG. 6 shows a cross-sectional view of the above-mentioned double transistor structure (the first thin film transistor T1 and the second thin film transistor T2) taken along the line P-P.
  • 6 shows the base substrate 1, the active layer located on the base substrate 1, the gate insulating layer 3 located on the side of the active layer 2 away from the base substrate 1, and the gate insulating layer The gate G1 and the gate G2 on the side of the layer 3 away from the active layer 2.
  • a buffer layer BUF may also be provided between the active layer 2 and the base substrate 1.
  • only the portions of the active layer 2 that overlap the first control line 426 and the second control line 427 are used as the channel regions of the first thin film transistor T1 and the second thin film transistor T2, respectively.
  • the first thin film transistor T1 and the second thin film transistor T2 in the multiplexer 42 have a more balanced structure
  • the first thin film transistor T1 may include a first stretch A1
  • the second thin film transistor T2 may include a second stretch Section A2.
  • the first extension A1 and the second extension A2 may be provided in the same layer, for example, in the active layer 2.
  • the first stretch A1 is connected to the other SD2 of the source and drain of the first thin film transistor T1 that are electrically connected to the first output terminal 422 of the multiplexer 42
  • the second stretch A2 It is connected to the other SD2' of the source and drain of the second thin film transistor T2 electrically connected to the second output terminal 423 of the multiplexer 42.
  • the orthographic projections of the first extension A1 and the second extension A2 on the base substrate 1 overlap with the orthographic projections of the first control line 426 on the base substrate 1, and the first extension A1 and the second extension A2 overlap
  • the orthographic projection on the base substrate 1 overlaps with the orthographic projection of the second control line 427 on the base substrate 1.
  • the overlapping area of the first extension A1 with the first control line 426 and the second control line 427 and the overlapping area of the second extension A2 with the first control line 426 and the second control line 427 are substantially the same. This can make the parasitic capacitances in the first thin film transistor T1 and the second thin film transistor T2 more consistent, thereby making the test signals output by the two output terminals of the multiplexer 42 more uniform and stable.
  • a single multiplexer 42 may have more The output channel, for example, can multiplex one input signal to four, eight or even more output signals to further reduce the area occupied by the array test component 40.
  • the array test component 40 is only used in the AT test stage, and is ineffective in the subsequent production stage and the use stage of the final product. Therefore, it is hoped that the array test assembly 40 will not affect the subsequent production test of the display device and the normal use of the final product as much as possible. Therefore, the multiple multiplexers 41 described above may be configured to be turned off during the display stage of the display substrate. The multiple multiplexers 41 described above can also be configured to be turned off during the subsequent production test stage of the display device (for example, the test after the luminescent material layer is evaporated, the test after the integrated circuit device is installed, etc.).
  • the electrical connection between the plurality of third pads 33 and the data line DATA will be cut off during the display stage of the display substrate and the subsequent production test stage, thereby preventing the components used for the AT test from interfering with the display operation of the display substrate and subsequent testing.
  • the first control line 426 is connected to the first level signal and the second control line 427 is connected to the second level signal to make the multiplexer 42
  • the gate G1 of the first thin film transistor T1 and the gate G2 of the second thin film transistor T2 are turned off during the display phase of the display substrate.
  • the plurality of first pads 31 may include: a first level input pad 311 and a second level input pad 312.
  • the number of the first level input pad 311 and the second level input pad 312 may be one or more.
  • the first-level input pad 311 and the first control terminal pad MUX1 are electrically connected through a first-level signal line 313, and are used to access a first-level signal.
  • the first control switch 424 in the multiplexer 42 remains open.
  • the second-level input pad 312 and the second control terminal pad MUX2 are electrically connected through a second-level signal line 314 for accessing a second-level signal.
  • the second control switch 425 in the multiplexer 42 remains open.
  • both the first-level signal and the second-level signal may be high-level signals (VGH) (such as positive voltage signals, for example, the voltage is between 6V and 8V).
  • VGH high-level signals
  • two adjacent first-level input pads 311 are electrically connected to each other, and two adjacent second-level input pads 312 are also electrically connected to each other. This helps to improve the stability of the signal.
  • the embodiments of the present disclosure are not limited to this.
  • the first level input pad 311 and the second level input pad 312 may be composed of one independent pad, or may be provided with a plurality of first level input pads electrically connected to each other.
  • the level input pad 311 and a plurality of second level input pads 312 electrically connected to each other.
  • the first control terminal pad MUX1 and the second control terminal pad MUX2 merely indicate the order, and the first control terminal pad MUX1 and the second control terminal pad MUX2 can both be Interchangeable.
  • the display substrate may further include a first level connection part 315 and a second level connection part 316, and the number of the first level input pads 311 may be set to multiple The number of the second level input pads 312 can also be set to multiple.
  • the first level connection portion 315 is located between the plurality of first level input pads 311 and the first level signal line 313', and is connected to the first level signal line 313' and the first level signal line 313'.
  • the plurality of first level input pads 311 are electrically connected; the second level connection portion 316 is located between the plurality of second level input pads 312 and the second level signal line 314', It is electrically connected to the second-level signal line 314 ′ and the plurality of second-level input pads 312.
  • the first level connection part 315 and the second level connection part 316 may be arranged on the same layer as the first level signal line 313' and the second level signal line 314', instead of being connected to the first level input
  • the pad 311 and the second level input pad 312 are arranged in the same layer.
  • first level connection portion 315 may be electrically connected to a plurality of first level input pads 311 through a via structure
  • second level connection portion 316 may also be electrically connected to a plurality of second level input pads through a via structure. ⁇ 312.
  • first level connection portion 315 and the first level signal line 313' may be an integral structure, and the second level connection portion 316 and the second level signal line 314 'Can be a one-piece structure.
  • the above-mentioned connection method enables the first control switch 424 and the second control switch 425 in the multiplexer 42 to remain open when the integrated circuit device has an input signal (which may be a test signal or a normal working signal). It can be seen from FIGS. 3 and 4 that the output terminal of the multiplexer 42 is connected to the output terminal of the integrated circuit device. Therefore, if the first control switch 424 and the first control switch 424 in the multiplexer 42 are connected to the output terminal of the integrated circuit device If the second control switch 425 is not kept open, leakage current may be generated, which may cause interference to the output signal of the integrated circuit device (in normal operation, it may be the data line driving signal, and in the subsequent test phase, it may be other test signals).
  • both the first level signal and the second level signal can be a high level signal (VGH).
  • VGH high level signal
  • the designs of the first control switch 424 and the second control switch 425 in the multiplexer 42 are various.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
  • the first control switch 424 and the second control switch 425 adopts an N-type transistor, it can be designed to be turned off under the control of a high-level signal (VGH), as described above, here
  • the corresponding first-level signal and second-level signal may be a high-level signal (VGH).
  • the first control switch 424 and the second control switch 425 adopts a P-type transistor, it can be designed to be turned off under the control of a low-level signal (VGL).
  • the first At least one of the one-level signal and the second-level signal may also be a low-level signal (VGL) (such as a negative voltage signal, for example, a voltage between -8V and -6V).
  • the first control line 426, the second control line 427, the first level signal line 313, the second level signal line 314, the gate G1 of the first thin film transistor T1 and the The gate G2 of the second thin film transistor T2 is made of the same material and arranged on the same layer. This can simplify the process and save costs.
  • the array test component 40 may also include a high-level signal (VGH) line 51 (for example, used to provide a positive-level signal (for example, a voltage between 6V and 8V), which may also be referred to as a third-level signal.
  • VGH high-level signal
  • Signal line and low-level signal (VGL) lines (for example, used to provide negative-level signals (for example, voltage between -8V to -6V), can also be referred to as fourth-level signal lines) 52 and multiple electrostatic discharges Structure 43.
  • the electrostatic discharge structure 43 is used to discharge static electricity in time to prevent the accumulation of static electricity from damaging the array test assembly 40.
  • FIG. 8 shows a schematic diagram of the circuit structure corresponding to a single input channel in the array test component 40.
  • the multiplexer 42 and the electrostatic discharge structure 43 are shown in the figure.
  • the at least one electrostatic discharge structure 43 includes: a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6.
  • the gate G3 of the third thin film transistor T3 is electrically connected to the high-level signal line 51, one of the source and drain of the third thin film transistor T3 SD31 is electrically connected to the high-level signal line 51, and the third The other SD32 of the source and drain of the thin film transistor T3 is electrically connected to an input terminal (a pad corresponding to one of the plurality of third pads 33) of the array test component 40.
  • the gate G4 of the fourth thin film transistor T4 is electrically connected to the high-level signal line 51, one of the source and drain of the fourth thin film transistor T4 SD41 is electrically connected to the high-level signal line 51, and the fourth The other SD42 of the source and drain of the thin film transistor T4 is electrically connected to the corresponding input terminal of the array test component 40 (the corresponding pad among the plurality of third pads 33).
  • the fourth thin film transistor T4 and the third thin film transistor T3 may be connected in parallel.
  • the gate G5 of the fifth thin film transistor T5 is electrically connected to the input terminal (the corresponding pad of the plurality of third pads 33) corresponding to the array test component 40, and the source of the fifth thin film transistor T5 SD51, one of the drain and the drain, is electrically connected to the low-level signal line 52, and the other SD52 of the source and drain of the fifth thin film transistor T5 is connected to the input terminal (a plurality of third pads) corresponding to the array test component 40
  • the corresponding pads in 33) are electrically connected.
  • the gate G6 of the sixth thin film transistor T6 is electrically connected to the corresponding pad in the third row of pads 33, and one of the source and drain of the sixth thin film transistor T6 SD61 is at a low level.
  • the signal line 52 is electrically connected, and the other SD62 of the source and drain of the sixth thin film transistor T6 is electrically connected to the corresponding pad among the plurality of third pads 33.
  • the test signal line Signal is used to electrically connect the corresponding input end of the array test component 40 (that is, the corresponding pad among the plurality of third pads 33) to the multiplexer 42 Input 421. Since the electrostatic voltage appearing on the test signal line Signal may be a positive voltage or a negative voltage, in the embodiment of the present disclosure, the test signal line Signal provides two ways to release static electricity, that is, through the third thin film transistor T3 The fourth thin film transistor T4 and the fourth thin film transistor T4 are released to the high-level signal line 51 and the fifth thin film transistor T5 and the sixth thin film transistor T6 are released to the low-level signal line 52.
  • the third thin film transistor T3 and the fourth thin film transistor T4 When the voltage difference between the node on the test signal line Signal and the high-level signal line 51 is greater than the threshold voltage of the third thin film transistor T3 and the fourth thin film transistor T4, the third thin film transistor T3 and the fourth thin film transistor T4 will be Turn on, so that the electrostatic voltage on the test signal line Signal is discharged to the high-level signal line 51.
  • the voltage difference between the node on the test signal line Signal and the low-level signal line 52 is greater than the threshold voltage of the fifth thin film transistor T5 and the sixth thin film transistor T6, the fifth thin film transistor T5 and the sixth thin film transistor T6 will It is turned on, so that the electrostatic voltage on the test signal line Signal is discharged to the low-level signal line 52.
  • the fourth thin film transistor T4 is located on the side of the third thin film transistor T3 away from the display area 10.
  • the sixth thin film transistor T6 is located on the side of the fifth thin film transistor T5 away from the display area 10.
  • the parallel structure of the fourth thin film transistor T4 and the third thin film transistor T3 and the parallel structure of the sixth thin film transistor T6 and the fifth thin film transistor T5 help to improve the discharge capability of the electrostatic discharge structure 43.
  • the third thin film transistor T3 includes an active layer A3, and the orthographic projection of the active layer A3 on the base substrate 1 may have a rectangular shape, for example.
  • one end of the active layer A3 is connected to one of the source and drain of the third thin film transistor T3 SD31 (for example, L-shaped) through a via H31, and the other end of the active layer A3 One end is connected to the other SD32 (for example, strip shape) of the source and drain of the third thin film transistor T3 through a via H32.
  • SD31 for example, L-shaped
  • a gate insulating layer GI is provided on the side of the active layer A3 away from the base substrate 1, and a gate insulating layer GI is provided on the side of the gate insulating layer GI away from the base substrate 1.
  • a pole G3 (the gate G3 has, for example, a first strip-shaped sub-gate G31 and a second strip-shaped sub-gate G32 arranged side by side), and an interlayer dielectric layer IDL is provided on the side of the gate G3 away from the base substrate 1 .
  • a second gate insulating layer GI2 may also be provided on the interlayer dielectric layer IDL and the gate G3.
  • the one SD31 and the other SD32 of the source and drain of the third thin film transistor T3 are arranged on the side of the interlayer dielectric layer IDL away from the base substrate 1.
  • a buffer layer BUF may also be provided between the base substrate 1 and the active layer A3.
  • Fig. 9 shows a cross-sectional view along the line Q-Q in Fig. 7. 9 shows that the other SD32 of the source and drain of the third thin film transistor T3 is connected to the first strip-shaped sub-gate G31 through a via H33, and connected to the second strip-shaped sub-gate G31 through a via H34.
  • the gate G32 is also connected to the first connecting portion 61 through the via H 35.
  • the first connecting portion 61 is also electrically connected to the second connecting portion 62 through the via hole H 36, and the second connecting portion 62 is electrically connected to the high-level signal line 51 via the via hole H37.
  • the other SD32 of the source and drain of the third thin film transistor T3 may be formed of, for example, a part of the test signal line Signal.
  • the one SD31 and the other SD32 of the source and drain of the third thin film transistor T3, the test signal line Signal, and the second connection portion 62 are made of the same material and located on the same layer, and A connecting portion 61 and the active layer A3 are made of the same material and arranged in the same layer.
  • the first strip-shaped sub-gate G31 and the second strip-shaped sub-gate G32 and the high-level signal line 51 are made of the same material and arranged in the same layer. The same layer.
  • the arrangement of the first connecting portion 61 can increase the resistance between the one SD31 (for example, the drain) of the source and drain of the third thin film transistor T3 and the high-level signal line 51, which is beneficial to prevent The third thin film transistor T3 is damaged due to excessive discharge current. It can be seen from FIG.
  • the one SD31 of the source and drain of the third thin film transistor T3 has a first arm portion 63 and a second arm portion 64 connected to each other, and the first arm portion 63 extends along Extending in the first direction (for example, the x direction in the figure), the second arm portion 64 is along a second direction (for example, y Direction), the first arm portion 63 is connected to the active layer A3 through the via hole H31, and the second arm portion 64 is connected to the first strip-shaped sub-gate G31 through the via hole H33 and is connected to the second sub-gate G31 through the via hole H34.
  • the strip-shaped sub-gate G32 is connected.
  • a buffer layer BUF may also be provided between the base substrate 1 and the first connection portion 61.
  • An interlayer dielectric layer IDL may be provided on the side of the gate G3 away from the base substrate 1.
  • a second gate insulating layer GI2 may also be provided on the interlayer dielectric layer IDL and the gate G3.
  • the structures of other thin film transistors in the electrostatic discharge structure 43 are similar to those of the third thin film transistor T3, and will not be described one by one here.
  • one, two, three, or four of the third thin film transistor T3, the fourth thin film transistor T4, the fifth thin film transistor T5, and the sixth thin film transistor T6 The gate of the transistor includes a first strip-shaped sub-gate and a second strip-shaped sub-gate which are arranged side by side. One end of the first strip-shaped sub-gate is electrically connected to one end of the second strip-shaped sub-gate. Structure connection such as holes). This dual-gate design can better improve the driving capability of the transistor.
  • At least some of the plurality of second pads 32 are electrically connected to the plurality of data lines DATA (for example, see FIG. 1) in the display area 10, respectively. This helps to test the electrical properties of the circuit units in the display area 10 during the production process.
  • FIG. 11 schematically shows the film structure of the sub-pixel unit in the display area 10.
  • at least one of the plurality of sub-pixels includes a pixel circuit 560 and a light-emitting element 550, and the pixel circuit 560 is located between the base substrate 1 and the light-emitting element 550.
  • the pixel circuit 560 is located between the base substrate 1 and the light-emitting element 550.
  • the light-emitting element 550 includes a first electrode 553 (e.g., a cathode), a light-emitting layer 552, and a second electrode 551 (e.g., an anode) that are stacked in sequence.
  • the second electrode 551 is located on the light-emitting layer facing the substrate.
  • the pixel circuit 560 includes at least one thin film transistor.
  • the thin film transistor includes a gate 450 located on the base substrate 1, a source 491 and a drain located on the side of the gate 450 away from the base substrate 1.
  • the electrode 492, the source 491 or the drain 492 of the thin film transistor is electrically connected to the second electrode 551.
  • the source 491 and the drain 492 in the at least one thin film transistor and the plurality of first pads 31, the plurality of second pads 32, and the plurality of third pads 33 are arranged on the same layer ( This layer can be called a source and drain layer), and can be formed by the same patterning process.
  • the first level connection portion 315, the first level signal line 313', the second level connection portion 316, the second level signal line 314', and the The gate electrode 450 of the thin film transistor in the pixel circuit 560 is located in the same layer, and can be formed by the same patterning process.
  • the film structure of the sub-pixel unit may further include a buffer layer 420, an active layer 430, a first gate insulating layer 440, a second gate insulating layer 460, and a second gate insulating layer 460 sequentially located on the base substrate 1.
  • the second gate layer (the layer where the gate 450 is located may be referred to as the first gate layer), the interlayer dielectric layer 480, the passivation layer 510, the planarization layer 520, the pixel defining layer 540, and the encapsulation layer 570.
  • the base substrate 1 is, for example, a flexible PI (polyimide) substrate made of transparent materials;
  • the buffer layer 420 is made of transparent insulating materials, such as silicon oxide, silicon nitride, etc.;
  • the active layer 430 includes
  • the active region in the thin film transistor in the pixel circuit can be made of semiconductor material;
  • the first gate insulating layer 440 can be made of transparent insulating material, such as silicon oxide, silicon nitride, etc.;
  • the first gate layer can be made of, for example, Made of metal materials, the gate 450 in the thin film transistor and the first electrode 471 in the storage electrode can be formed in the first gate layer;
  • the second gate insulating layer 460 is made of a transparent insulating material, such as silicon oxide, silicon nitride
  • the second gate layer can be used to form the second electrode 470 of the storage electrode, for example.
  • the interlayer dielectric layer 80 is made of transparent insulating materials, such as silicon oxide, silicon nitride, etc.; the source and drain layers are made of metal materials, for example, and the passivation layer 510 is made of transparent insulating materials, such as silicon oxide, silicon nitride, etc. production.
  • the planarization layer 520 is made of a transparent organic material, such as silicon oxide, silicon nitride, or the like.
  • the pixel defining layer 540 is supported by a transparent organic material, used to define the light-emitting area in the sub-pixel unit, and can be formed by a patterning process.
  • the encapsulation layer 570 includes a first inorganic encapsulation layer 571, an organic encapsulation layer 572, and a second inorganic encapsulation layer 573 that are sequentially disposed away from the base substrate 1.
  • the first inorganic encapsulation layer 571, the organic encapsulation layer 572, and the second inorganic encapsulation layer 573 are stacked. When set, the encapsulation layer 170 is light-transmissive.
  • FIG. 11 is only schematic, and mainly embodies the layer structure of the sub-pixel units in the display area 10 constituting the OLED display substrate, and embodies the structure of the pixel circuit through thin film transistors.
  • the signal is transmitted to the light-emitting element to achieve light emission.
  • the display substrate may be a foldable substrate, the display substrate includes a bending area 30, and the plurality of second pads 32 are farther from the display area than the bending area 30 10.
  • the plurality of first pads 31 and the plurality of third pads 33 are also farther away from the display area 10 than the bending area 30.
  • the integrated circuit device layout area 40 including the plurality of first pads 31, the plurality of second pads 32, and the plurality of third pads 33 can be folded to the bottom of the display screen. Back side, thereby reducing the bezel width of the display device.
  • the orthographic projection of the integrated circuit device on the base substrate 1 at least partially covers the array test assembly 40 Orthographic projection on the base substrate 1. This allows the array test assembly 40 to be completely covered by the integrated circuit device in the final product without occupying extra space.
  • the orthographic projection of the integrated circuit device on the base substrate 1 may be consistent with the orthographic projection of the integrated circuit device placement area 21 on the base substrate 1.
  • the array test component 40 is a general term for the structure for AT test disposed between the plurality of first pads 31 and the plurality of second pads 32.
  • the array test component 40 may include, for example, a plurality of third pads 33, a plurality of multiplexers 42, a high-level signal line 51 and a low-level signal line 52, and a plurality of electrostatic discharge structures 43, At least some of the first level signal line 313, the second level signal line 314, and so on.
  • the source and drain of the thin film transistor can be used interchangeably. Therefore, in the above expression, “one of the source and the drain” and “the source and the drain” are used.
  • the expression “the other of them” means one or the other of them, without making a specific distinction between the source and the drain.
  • the display device may include the display substrate 100 and the integrated circuit device 400 in any of the foregoing embodiments, and the integrated circuit device 400 is connected to the plurality of first pads 31 and the plurality of The two pads 32 are bound.
  • the orthographic projection of the integrated circuit device 400 on the base substrate 1 at least partially covers the orthographic projection of the plurality of third pads 33 on the base substrate 1, for example, completely covers the plurality of third pads 33.
  • the multiple multiplexers 42 may be configured to be turned off when the display device is working.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a smart watch, a tablet computer, and so on.

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Abstract

一种显示基板（100）和显示装置。该显示基板（100）包括：衬底基板（1），包括显示区（10）和围绕显示区的周边区（20）；多个子像素单元（PIX），位于显示区（10）；多条数据线（DATA），位于显示区（10）且分别与多个子像素单元（PIX）电连接；多条数据传输线（DATAL），位于显示区（10）至少一侧的周边区（20），且分别与多条数据线（DATA）电连接；多个第一焊盘（31）和多个第二焊盘（32），多个第二焊盘（32）位于多个第一焊盘（31）和多条数据传输线（DATAL）之间，且与多条数据传输线（DATAL）电连接；多个第三焊盘（33），位于多个第一焊盘（31）和多个第二焊盘（32）之间，且多个第三焊盘（33）中的至少部分焊盘与多个第二焊盘（32）电连接；多个多路复用器（42），位于多个第二焊盘（32）和多个第三焊盘（33）之间，多个多路复用器（42）中的至少一个电连接多个第二焊盘（32）中的至少两个第二焊盘（32）和多个第三焊盘（33）中的一个第三焊盘（33）。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板和显示装置。
背景技术
随着显示技术的进步，有机发光二极管(Organic Light Emitting Diode，OLED)显示装置是当今平板显示装置研究领域的热点之一，OLED显示发光装置具有色彩鲜艳，可视角度好，对比度高，响应速度快，可弯折、功耗低等优点而备受人们关注。OLED显示装置，尤其是有源矩阵有机发光二极管(AMLOED)显示装置，在未来显示领域的应用前景更为广泛，其在移动显示、车载显示、医疗显示等多个显示领域有着广阔的应用空间。
为了提高OLED显示装置的产品良率，在显示装置的生产工艺的不同阶段可能需要进行一些测试，根据测试的结果来确定在当前阶段制作的成品或半成品是否合格，如果不合格可以根据实际情况来进行修复或弃用。这种方式可以避免在前一阶段已经出现不合格问题的半成品未经处理而直接进入下一阶段的工艺，从而能够节省成本和提高良率。
公开内容
本公开的实施例提供一种显示基板，包括：衬底基板，包括显示区和围绕所述显示区的周边区；多个子像素单元，位于所述显示区；多条数据线，位于所述显示区且分别与所述多个子像素单元电连接；多条数据传输线，位于所述显示区至少一侧的所述周边区，且分别与所述多条数据线电连接；多个第一焊盘和多个第二焊盘，位于所述多条数据传输线远离所述显示区的一侧，所述多个第一焊盘和所述多个第二焊盘分别沿所述显示区边界的方向延伸，所述多个第二焊盘位于所述多个第一焊盘和所述多条数据传输线之间，且与所述多条数据传输线电连接；多个第三焊盘，位于所述多个第一焊盘和所述多个第二焊盘之间，且所述多个第三焊盘中的至少部分焊盘与所述多个第二焊盘电连接；多个多路复用器，位于所述多个第二焊盘和所述多个第三焊盘之间，所述多个多路复用器中的至少一个电 连接所述多个第二焊盘中的至少两个第二焊盘和所述多个第三焊盘中的一个第三焊盘。
在一些实施例中，所述多个多路复用器中的至少一个包括：第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管包括第一源极、第一漏极和第一栅极，所述第二薄膜晶体管包括第二源极、第二漏极和第二栅极，所述第一源极和所述第一漏极中的一者以及所述第二源极和所述第二漏极中的一者与所述多个第三焊盘中的同一个焊盘电连接，所述第一源极和所述第一漏极中的另一者电连接至所述多个第二焊盘中的一个焊盘，所述第二源极和所述第二漏极中的另一者电连接至所述多个第二焊盘中的另一个焊盘，所述第一栅极电连接所述第一控制线，所述第二栅极电连接所述第二控制线，所述第一控制线用于接入第一电平信号，所述第二控制线用于接入第二电平信号，所述第一电平信号和所述第二电平信号用于使多路复用器中的第一栅极和第二栅极在显示基板的显示阶段关断。
在一些实施例中，所述多个第三焊盘还包括：第一控制端焊盘，所述第一控制端焊盘与所述第一控制线电连接；以及第二控制端焊盘，所述第二控制端焊盘与所述第二控制线电连接。
在一些实施例中，所述显示基板还包括位于所述多个第一焊盘和所述多个第三焊盘之间的第一电平信号线和第二电平信号线，所述多个第一焊盘包括至少一个第一电平输入焊盘和至少一个第二电平输入焊盘，所述至少一个第一电平信号线电连接所述第一控制端焊盘和第二控制端焊盘中的一个和所述至少一个第一电平输入焊盘，所述第二电平信号线电连接所述第一控制端焊盘和第二控制端焊盘中的另一个和所述至少一个第二电平输入焊盘。
在一些实施例中，所述显示基板还包括第一电平连接部和第二电平连接部，所述至少一个第一电平输入焊盘的数量为多个，所述至少一个第二电平输入焊盘的数量为多个；所述第一电平连接部位于所述多个第一电平输入焊盘和所述第一电平信号线之间，且与所述第一电平信号线和所述多个第一电平输入焊盘电连接；所述第二电平连接部位于所述多个第二电平输入焊盘和所述第二电平信号线之间，且与所述第二电平信号线和所述多个第二电平输入焊盘电连接。
在一些实施例中，所述第一电平连接部和所述第一电平信号线为一体结构，所述第二电平连接部和所述第二电平信号线为一体结构。
在一些实施例中，所述第一电平信号为正电压信号或负电压信号，所述第二 电平信号为正电压信号或负电压信号。
在一些实施例中，所述正电压信号的数值范围在6V到8V之间，所述负电压信号的数值范围在-8V到-6V之间。
在一些实施例中，所述第一控制线、第二控制线、第一电平信号线、第二电平信号线、所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的栅极由相同材料制成且布置于同一层。
在一些实施例中，所述多个第三焊盘被配置为向所述多个子像素输入测试信号，所述多个第一焊盘和所述多个第二焊盘被配置为与同一集成电路器件绑定。
在一些实施例中，所述显示基板还包括第三电平信号线和第四电平信号线以及多个静电释放结构，所述第三电平信号线用于提供正电平信号，所述第四电平信号线用于提供负电平信号，其中，至少一个静电释放结构包括：第三薄膜晶体管，所述第三薄膜晶体管的栅极与第三电平信号线电连接，所述第三薄膜晶体管的源极和漏极中一者与第三电平信号线电连接，另一者与所述多个第三焊盘中的一个对应的焊盘电连接；第四薄膜晶体管，所述第四薄膜晶体管的栅极与第三电平信号线电连接，所述第四薄膜晶体管的源极和漏极中一者与第三电平信号线电连接，另一者与所述多个第三焊盘中的所述对应的焊盘电连接；第五薄膜晶体管，所述第五薄膜晶体管的栅极与所述多个第三焊盘中的所述对应的焊盘电连接，所述第五薄膜晶体管的源极和漏极中一者与第四电平信号线电连接，另一者与所述多个第三焊盘中的所述对应的焊盘电连接；以及第六薄膜晶体管，所述第六薄膜晶体管的栅极与所述多个第三焊盘中的所述对应的焊盘电连接，所述第六薄膜晶体管的源极和漏极中一者与第四电平信号线电连接，另一者与所述多个第三焊盘中的所述对应的焊盘电连接。
在一些实施例中，所述第三薄膜晶体管和所述第四薄膜晶体管均包括有源层且所述第三薄膜晶体管和所述第四薄膜晶体管中的栅极包括第一条状子栅极和第二条状子栅极，所述第三薄膜晶体管和所述第四薄膜晶体管中的每一薄膜晶体管中的源极和漏极中的所述一者具有相互连接的第一臂部和第二臂部，所述第一臂部沿着第一方向延伸，所述第二臂部沿着与第一方向交叉的第二方向延伸，所述第一臂部通过第一过孔结构与有源层连接，所述第二臂部通过第二过孔结构与第一条状子栅极连接并通过第三过孔结构与第二条状子栅极连接。
在一些实施例中，所述静电释放结构还包括：第一连接部和第二连接部，所 述第一连接部与所述有源层由相同材料制成且布置于同一层，所述第二连接部与所述源极和漏极由相同材料制成且布置于同一层，所述第一连接部通过第三过孔结构与所述第三薄膜晶体管和所述第四薄膜晶体管中的每一薄膜晶体管中的源极和漏极中的所述一者相连，所述第一连接部还通过第四过孔结构与所述第二连接部相连，所述第二连接部通过第五过孔结构与第三电平信号线相连。
在一些实施例中，所述多个子像素单元中至少一个包括像素电路和发光元件，所述像素电路位于所述衬底基板和所述发光元件之间；所述发光元件包括依次层叠设置的第一电极、发光层以及第二电极，所述第二电极位于所述发光层面向所述衬底基板的一侧；所述像素电路包括至少一个薄膜晶体管，所述薄膜晶体管包括位于所述衬底基板上的栅极、位于所述栅极远离所述衬底基板一侧的源极和漏极，所述薄膜晶体管的源极或漏极与所述第二电极电连接；所述至少一个薄膜晶体管中的源极和漏极与所述多个第一焊盘、所述多个第二焊盘和所述多个第三焊盘设置在同一层。
在一些实施例中，所述第一电平连接部、所述第一电平信号线、所述第二电平连接部、所述第二电平信号线和所述像素电路中的薄膜晶体管的栅极位于同一层。
在一些实施例中，所述显示基板为可折叠基板，所述显示基板包括弯折区域，所述多个第二焊盘比弯折区域更远离显示区。
本公开的实施例还提供了一种显示装置，包括：如上述任一实施例所述的显示基板；以及集成电路器件，所述集成电路器件与所述多个第一焊盘和所述多个第二焊盘绑定。
在一些实施例中，所述集成电路器件在衬底基板上的正投影至少部分地覆盖所述多个第三焊盘在衬底基板上的正投影。
在一些实施例中，所述多个多路复用器配置成在所述显示装置工作时是关断的。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本公开的其它特征、目的和优点将会变得更明显：
图1为根据本公开的一些实施例的显示基板的示意图；
图2为图1中的集成电路器件布设区域的放大示意图；
图3为根据本公开的另一些实施例的显示基板的集成电路器件布设区域的示意图；
图4为图3中所示的集成电路器件布设区域中的线连接关系示意图；
图5为图2中的局部E的放大图，示意性地示出了根据本公开的一些实施例的显示基板中的多路复用器；
图6为沿图5中的线P-P截得的示意性剖视图；
图7为图2中的局部F的放大图；
图8示意性地示出了根据本公开的一些实施例的显示基板上的阵列测试组件的电路原理图；
图9为沿图7中的线Q-Q截得的示意性剖视图；
图10为沿图7中的线K-K截得的示意性剖视图；
图11为根据本公开的实施例的显示基板上的显示区的膜层结构的示意图；
图12为根据本公开的实施例的显示装置的示意图；以及
图13示出了根据本公开的再一些实施例的显示基板的集成电路器件布设区域的示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
应该理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件，但是这些元件不应受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。例如，在不脱离示例实施例的范围的情况下，第一元件可以被命名为 第二元件，类似地，第二元件可以被命名为第一元件。如在这里使用的术语“和/或”包括一个或多个相关所列的项目的任意组合和所有组合。
应该理解的是，当元件或层被称作“形成在”另一元件或层“上”时，该元件或层可以直接地或间接地形成在另一元件或层上。也就是，例如，可以存在中间元件或中间层。相反，当元件或层被称作“直接形成在”另一元件或层“上”时，不存在中间元件或中间层。应当以类似的方式来解释其它用于描述元件或层之间的关系的词语(例如，“在...之间”与“直接在...之间”、“相邻的”与“直接相邻的”等)。
本文中使用的术语仅是为了描述特定实施例的目的，而不意图限制实施例。如本文中所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。还将理解的是，当在此使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组合。
在本文中，如无特别说明，表述“位于同一层”、“同层设置”一般表示的是：第一部件和第二部件可以使用相同的材料并且可以通过同一构图工艺形成。表述“位于不同层”、“不同层设置”一般表示的是：第一部件和第二部件通过不同构图工艺形成。
在显示面板的生产制造过程中，需要不断地检测产品的质量问题，从检测的过程中及时筛选出不合格的产品，从而及时调整工艺，以实现高良率、低成本生产。由于发光层、驱动集成电路等材料或部件相对昂贵，因此在蒸镀发光材料和绑定电路器件(例如集成电路器件等)之前均会进行电学性质的检测，如果半成品能够符合质量要求，才能进入下一阶段的工艺过程。常用的在蒸镀发光材料之前检测面板电学性质是否存在不良的检测方法称为AT测试(阵列测试)。
在进行AT测试时，需要将测试信号分别输入显示基板中的TFT(薄膜晶体管)阵列中来检测显示基板的各个部分的电学性质是否符合要求，例如电路的通断与设计是否一致等。对于COF封装的显示面板而言，由于具有FPC(柔性电路板)，通常可以直接将测试信号通过柔性电路板的排线处接入而将其输入至显示基板中的TFT阵列。然而，随着对于显示面板的窄边框的需求越来越高，对于某些显示面板可能不再将排线设置在显示基板上或者由于电路连接关系的问题仅仅通过排线无法将测试信号引入到所希望的TFT阵列中。
例如，图1给出了这样一种显示基板100的示例。该显示基板100应用于 COP显示装置中。在这种显示基板上，设有显示区10和周边区20。显示区10用于显示图像，例如可以包括多个子像素单元PIX(例如子像素单元可以成阵列方式布置)。周边区20位于显示区10的周边(例如可围绕显示区10设置)，用于布设周围电路(例如驱动集成电路器件、连接走线等)等。显示装置的边框的尺寸在很大程度上受限于周边区20的大小和布设。对于显示装置的设计而言，在显示区各个侧面的周边区20中，往往会有一个周边区20中集成最多的电路元件，也就需要更大的面积。例如在图1所示的示例中，该周边区位于图1中显示区的下方。为了减小这个周边区对于显示装置的边框变窄的制约，该显示基板在周边区20中设置有弯折区域30。该弯折区域30是挠性的。在最终的产品中，该弯折区域30可以弯曲，从而使得显示基板的周边区域的一部分可以被折叠到显示装置的与显示面相反的一侧，从而减小边框的宽度。应当理解，上述显示区10和周边区20中的电路结构均可承载于衬底基板1(参见图10)之上。在周边区20中例如可以设置有高电平信号线VDD和低电平信号线VSS，为阵列测试组件40提供电平信号。作为示例，周边区20还可以设置有与柔性印刷电路板连接的接口60。在显示区10中还可以设置多条数据线DATA，分别与所述多个子像素单元PIX电连接。数据线DATA用于为各个子像素单元PIX提供所需要的数据驱动信号。在显示区10的至少一侧的周边区20中可以设置多条数据传输线DATAL(如图1中虚线所示)，分别与所述多条数据线DATA电连接，用于在显示基板的周边电路和数据线DATA之间传输信号。
显示基板能够被折叠的部分上通常会设置有与显示基板外部电路的接口以及相关的走线。在图1所示的示例中，在周边区20中包括集成电路器件布设区域21，如图1中的虚线框所示。该集成电路器件布设区域21用于布设集成电路器件，相应地，该集成电路器件布设区域21中设置有多个第一焊盘31和多个第二焊盘32。所述多个第一焊盘31和多个第二焊盘32可用于与集成电路器件绑定。例如，多个第一焊盘31可用于电连接集成电路器件的输入信号，多个第二焊盘32可用于电连接集成电路器件的输出信号。多个第一焊盘31和多个第二焊盘32例如可位于所述多条数据传输线DATAL远离所述显示区10的一侧，所述多个第一焊盘31和所述多个第二焊盘32分别沿所述显示区10的边界K的方向延伸，所述多个第二焊盘32可位于所述多个第一焊盘31和所述多条数据传输线DATAL之间，且与所述多条数据传输线DATAL电连接。当集成电路器件安装在 集成电路器件布设区域21中时，多个第一焊盘31和多个第二焊盘32可以分别与集成电路(IC)器件的对应的输入引脚和输出引脚电连接(例如通过焊接等方式)。例如，该集成电路器件可以在显示装置工作时为显示区10中的各个子像素单元提供数据线DATA上的信号，这意味着该集成电路器件中的至少一些引脚是与各个子像素单元中的电路相连接的，因此在显示基板的制作过程中，可以通过从这些引脚中输入一些测试信号来检测子像素单元的驱动电路是否存在制作缺陷。为在对于在模组工艺(MDL)后进行电学性质测试的情况，由于此时集成电路器件已经安装在集成电路器件布设区域21中，所以可以将测试信号从多个第一焊盘31中对应的焊盘输入集成电路器件，然后再经过集成电路器件的输出端传递给显示区10中的各个子像素单元，从而实现电学性质的测试。
然而，对于前面所述的AT测试，情况则有所不同。如前所述，AT测试是在制作发光层和安装集成电路器件之前进行的，因此，在进行AT测试时，集成电路器件还没有被安装。于是，是无法使用所述多个第一焊盘31进行AT测试的。
为此，在根据本公开的实施例的显示基板上，在集成电路器件布设区域21中设置有阵列测试组件40。该阵列测试组件40位于所述多个第一焊盘31和所述多个第二焊盘32之间。在集成电路器件安装之后，阵列测试组件40的至少大部分将被集成电路器件所覆盖，这就意味着阵列测试组件40将不会增加显示基板的额外的布线面积。阵列测试组件40的布设充分利用了集成电路器件布设区域21中的第一焊盘31和第二焊盘32之间的空隙，对于减小布线面积很有帮助。另外，由于阵列测试组件40仅仅在AT测试中使用，因此，其在后续工艺中被集成电路器件所覆盖也不会对器件的功能产生任何不利影响。
在根据本公开的实施例中，所述阵列测试组件40可以包括用于电连接阵列测试电路的多个第三焊盘33以及与所述多个第二焊盘32电连接的多个连接端41。所述多个第三焊盘33可以用来与外部的阵列测试电路50电连接。阵列测试电路50用来为AT测试提供测试信号，测试信号例如可以是电平信号用来测试电路是否存在断路或短路等缺陷，或者还可以是其他用来测试TFT阵列的电学性质的专门的信号。作为示例，阵列测试组件40可以包括多个测试通道，每个测试通道通过一个或多个连接端41与多个第二焊盘32中的某个或某些焊盘电连接以进行相应的测试。每个测试通道从多个第三焊盘33中其所对应的焊盘获得测试信号并经由对应的连接端41将相应的测试信号输送给需要检测的电路。阵列测试电 路50与多个第三焊盘33中的至少一些焊盘的电连接可以通过多种方式来实现，例如可以通过从阵列测试电路50引出探针并使探针与多个第三焊盘33中对应的焊盘接触，或者可通过从阵列测试电路50引出输入线头与多个第三焊盘33中对应的焊盘固接等等。阵列测试电路50与所述多个第三焊盘33中对应的焊盘的电连接并不意味着阵列测试电路50同时与多个第三焊盘33中的所有焊盘均电连接，例如阵列测试电路50在同一时刻可以仅与所述多个第三焊盘33中的一部分焊盘(如一个或几个焊盘)电连接。多个第三焊盘33位于所述多个第一焊盘31和所述多个第二焊盘32之间，且所述多个第三焊盘33中的至少部分焊盘与所述多个第二焊盘32中对应的焊盘电连接。由于第二焊盘32中的至少一些焊盘可与显示区10中的数据线DATA电连接，因此，多个第三焊盘33中的至少部分焊盘与对应的第二焊盘32电连接，可以用于为显示区10中的多个子像素单元PIX输入测试信号。
在一些实施例中，为了减小所述多个第三焊盘33的焊盘数量和阵列测试组件40中的布线面积，可以在阵列测试组件40中设置多个多路复用器42。多个多路复用器42可位于所述多个第二焊盘32和所述多个第三焊盘33之间，所述多个多路复用器42中的至少一个电连接至所述多个第二焊盘32中的至少两个第二焊盘32和所述多个第三焊盘33中的一个第三焊盘33。如图2和图5所示，至少一个多路复用器42可以包括：输入端421、第一输出端422、第二输出端423、第一控制开关424和第二控制开关425。所述输入端421与所述多个第三焊盘33中的一个焊盘电连接，所述第一输出端422与所述多个第二焊盘32中的一个焊盘(可称为第一输出焊盘321)电连接，所述第二输出端423与所述多个第二焊盘32中的另一个焊盘(可称为第二输出焊盘322)电连接，第一控制开关424用于控制输入端421与第一输出端422的接通和断开，第二控制开关425用于控制输入端421与第二输出端423的接通和断开。通常，多路复用器42可以具有两种状态，在第一工作状态中，第一控制开关424接通而第二控制开关425断开，输入端421输入的信号仅被提供至第一输出端422；而在第二工作状态中，第一控制开关424断开而第二控制开关425接通，输入端421输入的信号仅被提供至第二输出端423。这样，如果能够交替地控制第一控制开关424和第二控制开关425的接通和断开，则可以控制多路复用器42在第一工作状态和第二工作状态之间往复切换，从而使得可以通过一个输入通道就可以完成对于两个或更多个输出 通道的测试。这可以减少布线面积，有益于窄化显示装置的边框。需要说明的是，上述第一工作状态和第二工作状态仅仅是示例性的，在本公开的实施例中，多路复用器42还可以有其他状态，例如，第一控制开关424和第二控制开关425均处于接通状态的第三工作状态以及第一控制开关424和第二控制开关425均处于断开状态的非工作状态。
为了控制第一控制开关424和第二控制开关425的操作，所述阵列测试组件40还可以包括第一控制线426和第二控制线427。所述第一控制线426与各个多路复用器42的第一控制开关424的控制端电连接，所述第二控制线427与各个多路复用器42的第二控制开关425的控制端电连接。第一控制线426和第二控制线427上的信号可以从外部输入，例如通过多个第三焊盘33来输入。作为示例，多个第三焊盘33可以包括：第一控制端焊盘MUX1和第二控制端焊盘MUX2。第一控制端焊盘MUX1与所述第一控制线426电连接，第二控制端焊盘MUX2与所述第二控制线427电连接。作为示例，从第一控制端焊盘MUX1和第二控制端焊盘MUX2输入到第一控制线426和第二控制线427中的控制信号可以为周期性的脉冲信号或时钟信号等。
在一些实施例中，上述控制开关可以由薄膜晶体管结构来实现。例如，如图2和图5所示，所述第一控制开关424可以包括第一薄膜晶体管T1，所述第一控制开关424的控制端为所述第一薄膜晶体管T1的栅极G1，所述第一薄膜晶体管T1的源极和漏极中的一者SD1(例如为源极)与所述多路复用器42的输入端421电连接，第一薄膜晶体管T1的源极和漏极中的另一者SD2(例如为漏极)与所述多路复用器42的第一输出端422电连接；所述第二控制开关425包括第二薄膜晶体管T2，所述第二控制开关425的控制端为所述第二薄膜晶体管T2的栅极G2，所述第二薄膜晶体管T2的源极和漏极中的一者SD1’(例如为源极)也与所述多路复用器42的输入端421电连接，另一者SD2’(例如为漏极)与所述多路复用器42的第二输出端423电连接。在一些实施例中，第一薄膜晶体管T1的源极和漏极中的一者SD1以及第二薄膜晶体管T2的源极和漏极中的一者SD1’与所述多个第三焊盘33中的同一个焊盘电连接，第一薄膜晶体管T1的源极和漏极中的另一者SD2电连接至所述多个第二焊盘32中的一个焊盘，所述第二薄膜晶体管T2的源极和漏极中的另一者SD2’电连接至所述多个第二焊盘中的另一个焊盘，所述第一薄膜晶体管T1的栅极G1电连接所述第一控制线426，所述第 二薄膜晶体管T2的栅极G2电连接所述第二控制线427。
图6给出了上述双晶体管结构(第一薄膜晶体管T1和第二薄膜晶体管T2)图中沿着线P-P截得的剖视图。在图6中示出了衬底基板1、位于衬底基板1上的有源层2、位于有源层2的远离衬底基板1的一侧上的栅极绝缘层3以及位于栅极绝缘层3的远离有源层2的一侧上的栅极G1和栅极G2。作为示例，在有源层2和衬底基板1之间还可以设置有缓冲层BUF。在图5示出的示例中，有源层2中仅仅与第一控制线426和第二控制线427相交叠的部分分别用作第一薄膜晶体管T1和第二薄膜晶体管T2的沟道区，而其他部分则被导体化起到电连接作用。为了使多路复用器42中的第一薄膜晶体管T1和第二薄膜晶体管T2具有更平衡的结构，第一薄膜晶体管T1可以包括第一伸展部A1而第二薄膜晶体管T2可以包括第二伸展部A2。第一伸展部A1和第二伸展部A2可设置在同一层中，例如设置在有源层2中。第一伸展部A1与第一薄膜晶体管T1中的与所述多路复用器42的第一输出端422电连接的源极和漏极中的另一者SD2相连接，第二伸展部A2与第二薄膜晶体管T2中的与所述多路复用器42的第二输出端423电连接的源极和漏极中的另一者SD2’相连接。第一伸展部A1和第二伸展部A2在衬底基板1上的正投影与第一控制线426在衬底基板1上的正投影相交叠，且第一伸展部A1和第二伸展部A2在衬底基板1上的正投影与第二控制线427在衬底基板1上的正投影相交叠。第一伸展部A1与第一控制线426和第二控制线427的交叠面积和第二伸展部A2与第一控制线426和第二控制线427的交叠面积是基本相同的。这可以使第一薄膜晶体管T1和第二薄膜晶体管T2中的寄生电容更为一致，从而使得多路复用器42的两个输出端输出的测试信号更为均匀和稳定。
尽管上述以具有两个输出通道的多路复用器作为示例进行了介绍，但是应当理解，本公开的实施例不限于此，例如根据实际需要，单个多路复用器42可以具有更多的输出通道，例如可将一路输入信号复用至四路、八路甚至更多路输出信号，以进一步减小阵列测试组件40所占据的面积。
如前所述，阵列测试组件40仅仅在AT测试阶段使用，而在后续生产阶段以及最终产品的使用阶段都是不起作用的。因此，希望阵列测试组件40尽可能不影响显示装置的后续生产测试以及最终产品的正常使用。因此，上述多个多路复用器41可配置为在显示基板的显示阶段被关断。上述多个多路复用器41还可配置为在显示装置的后续生产测试阶段(例如蒸镀发光材料层后的测试、安装集成 电路器件后的测试等)被关断。这样，多个第三焊盘33与数据线DATA的电连接将在显示基板的显示阶段以及后续生产测试阶段被切断，从而防止用于AT测试的组件对于显示基板的显示操作以及后续测试产生干扰。在一些实施例中，可以通过在所述第一控制线426上接入第一电平信号而在所述第二控制线427上接入第二电平信号来使多路复用器42中的第一薄膜晶体管T1的栅极G1和第二薄膜晶体管T2的栅极G2在显示基板的显示阶段关断。
在一些实施例中，如图3所示，上述多个第一焊盘31可以包括：第一电平输入焊盘311和第二电平输入焊盘312。第一电平输入焊盘311和第二电平输入焊盘312的数量可以有一个或更多个。所述第一电平输入焊盘311与所述第一控制端焊盘MUX1通过第一电平信号线313电连接，用于接入第一电平信号，所述第一电平信号使多路复用器42中的第一控制开关424保持断开。所述第二电平输入焊盘312与所述第二控制端焊盘MUX2通过第二电平信号线314电连接，用于接入第二电平信号，所述第二电平信号使多路复用器42中的第二控制开关425保持断开。作为示例，第一电平信号和第二电平信号均可为高电平信号(VGH)(如正电压信号，例如电压在6V至8V之间)。在图3所示的示例中，两个相邻的第一电平输入焊盘311彼此电连接，两个相邻的第二电平输入焊盘312也彼此电连接。这有利于提高信号的稳定性。然而，本公开的实施例不限于此，例如第一电平输入焊盘311和第二电平输入焊盘312可以为一个独立的焊盘构成，或者可以是设置多个彼此电连接的第一电平输入焊盘311以及多个彼此电连接的第二电平输入焊盘312。在此，所述第一控制端焊盘MUX1和所述第二控制端焊盘MUX2仅仅是表示次序，所述第一控制端焊盘MUX1和所述第二控制端焊盘MUX2两者是可以互换的。
在一些实施例中，如图13所示，显示基板上还可包括第一电平连接部315和第二电平连接部316，而第一电平输入焊盘311的数量可以设置为多个，第二电平输入焊盘312的数量也可以设置为多个。所述第一电平连接部315位于所述多个第一电平输入焊盘311和所述第一电平信号线313’之间，且与所述第一电平信号线313’和所述多个第一电平输入焊盘311电连接；所述第二电平连接部316位于所述多个第二电平输入焊盘312和所述第二电平信号线314’之间，且与所述第二电平信号线314’和所述多个第二电平输入焊盘312电连接。作为示例，第一电平连接部315和第二电平连接部316可以与第一电平信号线313’和第二电平信 号线314’布置于同一层，而不与第一电平输入焊盘311和第二电平输入焊盘312同层布置。例如，第一电平连接部315可以通过过孔结构电连接至多个第一电平输入焊盘311，第二电平连接部316也可以通过过孔结构电连接至多个第二电平输入焊盘312。
在一些实施例中，所述第一电平连接部315和所述第一电平信号线313’可以为一体结构，所述第二电平连接部316和所述第二电平信号线314’可以为一体结构。
上述连接方式使得当集成电路器件具有输入信号时(可以是测试信号或正常工作信号)，多路复用器42中的第一控制开关424和第二控制开关425就可以保持断开。从图3和图4中可以看出，多路复用器42的输出端是与集成电路器件的输出端相连接的，因此，如果多路复用器42中的第一控制开关424和第二控制开关425不保持断开，则有可能产生漏电流，从而对于集成电路器件的输出信号(在正常工作中可能是数据线驱动信号，在后续测试阶段可能是其他测试信号)造成干扰。因此，上述连接方式能够避免阵列测试组件40对于后续生产步骤中的测试或显示装置成品的工作信号造成干扰。在上述的示例中，第一电平信号和第二电平信号均可为高电平信号(VGH)。然而，应当理解，多路复用器42中的第一控制开关424和第二控制开关425的设计是多种多样的。例如，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。于是，如果第一控制开关424和第二控制开关425中的至少一者采用N型晶体管，则可以设计成高电平信号(VGH)的控制下是断开的，如前所述，在此情况下，相应的第一电平信号和第二电平信号可为高电平信号(VGH)。而如果第一控制开关424和第二控制开关425中的至少一者采用P型晶体管，则可以设计成在低电平信号(VGL)的控制下是断开的，在这种情况下，第一电平信号和第二电平信号中的至少一者也可为低电平信号(VGL)(如负电压信号，例如电压在-8V至-6V之间)。
在一些实施例中，所述第一控制线426、第二控制线427、第一电平信号线313、第二电平信号线314、所述第一薄膜晶体管T1的栅极G1和所述第二薄膜 晶体管T2的栅极G2由相同材料制成且布置于同一层。这可以简化工艺，节约成本。
在一些实施例中，阵列测试组件40还可以包括高电平信号(VGH)线51(例如用于提供正电平信号(例如电压在6V至8V之间)，亦可称为第三电平信号线)和低电平信号(VGL)线(例如用于提供负电平信号(例如电压在-8V至-6V之间)，亦可称为第四电平信号线)52以及多个静电释放结构43。静电释放结构43用于及时释放静电，以防止静电的积聚给阵列测试组件40造成损坏。
图8给出了阵列测试组件40中单个输入通道所对应的电路结构的原理图。图中示出了多路复用器42以及静电释放结构43。至少一个静电释放结构43包括：第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5和第六薄膜晶体管T6。所述第三薄膜晶体管T3的栅极G3与高电平信号线51电连接，所述第三薄膜晶体管T3的源极和漏极中一者SD31与高电平信号线51电连接，第三薄膜晶体管T3的源极和漏极中的另一者SD32与阵列测试组件40对应的输入端(多个第三焊盘33中的一个对应的焊盘)电连接。所述第四薄膜晶体管T4的栅极G4与高电平信号线51电连接，所述第四薄膜晶体管T4的源极和漏极中一者SD41与高电平信号线51电连接，第四薄膜晶体管T4的源极和漏极中的另一者SD42与阵列测试组件40对应的输入端(多个第三焊盘33中的所述对应的焊盘)电连接。第四薄膜晶体管T4和第三薄膜晶体管T3可以是并联的。所述第五薄膜晶体管T5的栅极G5与阵列测试组件40对应的输入端(多个第三焊盘33中的所述对应的焊盘)电连接，所述第五薄膜晶体管T5的源极和漏极中一者SD51与低电平信号线52电连接，第五薄膜晶体管T5的源极和漏极中的另一者SD52与阵列测试组件40对应的输入端(多个第三焊盘33中的所述对应的焊盘)电连接。所述第六薄膜晶体管T6的栅极G6与第三排焊盘33中的所述对应的焊盘电连接，所述第六薄膜晶体管T6的源极和漏极中一者SD61与低电平信号线52电连接，第六薄膜晶体管T6的源极和漏极中的另一者SD62与多个第三焊盘33中的所述对应的焊盘电连接。
从图8中可以看出，测试信号线Signal用于将阵列测试组件40对应的输入端(即多个第三焊盘33中的所述对应的焊盘)电连接至多路复用器42的输入端421。由于在测试信号线Signal上出现的静电电压可能是正电压也可能是负电压，因此，在本公开的实施例中为测试信号线Signal提供了两种释放静电的途径，即 通过第三薄膜晶体管T3和第四薄膜晶体管T4向高电平信号线51释放和通过第五薄膜晶体管T5和第六薄膜晶体管T6向低电平信号线52释放。当测试信号线Signal上的节点与高电平信号线51之间的电压差大于第三薄膜晶体管T3和第四薄膜晶体管T4的阈值电压时，第三薄膜晶体管T3和第四薄膜晶体管T4将被接通，从而使测试信号线Signal上的静电电压向高电平信号线51释放。而当测试信号线Signal上的节点与低电平信号线52之间的电压差大于第五薄膜晶体管T5和第六薄膜晶体管T6的阈值电压时，第五薄膜晶体管T5和第六薄膜晶体管T6将被接通，从而使测试信号线Signal上的静电电压向低电平信号线52释放。第四薄膜晶体管T4位于第三薄膜晶体管T3远离显示区10的一侧。第六薄膜晶体管T6位于第五薄膜晶体管T5远离显示区10的一侧。第四薄膜晶体管T4和第三薄膜晶体管T3的并联结构以及第六薄膜晶体管T6和第五薄膜晶体管T5的并联结构有助于提高静电释放结构43的放电能力。
下面以第三薄膜晶体管T3为例对静电释放结构43中的上述薄膜晶体管的结构进行简要的介绍。如图7所示，第三薄膜晶体管T3包括有源层A3，所述有源层A3在衬底基板1上的正投影例如可以具有矩形形状。如图7和图10所示，有源层A3的一端通过过孔H31与第三薄膜晶体管T3的源极和漏极中的一者SD31(例如为L形)相连，有源层A3的另一端通过过孔H32与第三薄膜晶体管T3的源极和漏极中的另一者SD32(例如为条形)相连。在图10中可以看出，在有源层A3的远离衬底基板1的一侧上设有栅极绝缘层GI，在栅极绝缘层GI的远离衬底基板1的一侧上设有栅极G3(该栅极G3例如具有并排设置的第一条状子栅极G31和第二条状子栅极G32)，在栅极G3的远离衬底基板1的一侧上设置有层间介质层IDL。作为示例，在层间介质层IDL和栅极G3还可以设置有第二栅极绝缘层GI2。第三薄膜晶体管T3的源极和漏极中的所述一者SD31和另一者SD32设置在层间介质层IDL的远离衬底基板1的一侧。作为示例，在衬底基板1和有源层A3之间还可以设置有缓冲层BUF。图9示出了沿着图7中的线Q-Q的剖视图。图9中示出了第三薄膜晶体管T3的源极和漏极中的所述另一者SD32通过过孔H33连接至第一条状子栅极G31，并通过过孔H34连接至第二条状子栅极G32，还通过过孔H 35连接至第一连接部61。所述第一连接部61还通过过孔H 36电连接至第二连接部62，第二连接部62又通过过孔H37电连接至高电平信号线51。第三薄膜晶体管T3的源极和漏极中的所述另一者SD32例如可以 由测试信号线Signal的一部分形成。其中，所述第三薄膜晶体管T3的源极和漏极中的所述一者SD31和另一者SD32、测试信号线Signal以及第二连接部62由相同材料制成并位于同一层，且第一连接部61与有源层A3由相同材料制成并设置在同一层，第一条状子栅极G31和第二条状子栅极G32与高电平信号线51由相同材料制成并设置在同一层。第一连接部61的设置可以增大所述第三薄膜晶体管T3的源极和漏极中的所述一者SD31(例如漏极)与高电平信号线51之间的电阻，有利于防止第三薄膜晶体管T3由于放电电流过大而被损坏。从图7中可以看出，第三薄膜晶体管T3的源极和漏极中的所述一者SD31具有相互连接的第一臂部63和第二臂部64，所述第一臂部63沿着第一方向(例如图中的x方向)延伸，所述第二臂部64沿着与第一方向(例如图中的x方向)交叉(例如垂直)的第二方向(例如图中的y方向)延伸，所述第一臂部63通过过孔H31与有源层A3连接，所述第二臂部64通过过孔H33与第一条状子栅极G31连接并通过过孔H34与第二条状子栅极G32连接。作为示例，与图9相似，在衬底基板1和第一连接部61之间还可以设置有缓冲层BUF。在栅极G3的远离衬底基板1的一侧上可以设置有层间介质层IDL。作为示例，在层间介质层IDL和栅极G3还可以设置有第二栅极绝缘层GI2。
静电释放结构43中的其他薄膜晶体管的结构与第三薄膜晶体管T3类似，在此不再逐一描述。在一些实施例中，所述第三薄膜晶体管T3、所述第四薄膜晶体管T4、所述第五薄膜晶体管T5和所述第六薄膜晶体管T6中的一个、两个、三个或四个薄膜晶体管的栅极包括并排设置的第一条状子栅极和第二条状子栅极，第一条状子栅极的一端与第二条状子栅极的一端电连接(可以直接连接，也可以通过过孔等结构连接)。这种双子栅极设计可以更好地提高晶体管的驱动能力。
在一些实施例中，所述多个第二焊盘32中的至少一些焊盘与显示区10中的多条数据线DATA(例如参见图1)分别电连接。这有助于在生产过程中对显示区10中的电路单元的电学性质进行测试。
图11示意性地示出了显示区10中子像素单元的膜层结构。如图11所示，在一些实施例中，所述多个子像素中至少一个包括像素电路560和发光元件550，所述像素电路560位于所述衬底基板1和所述发光元件550之间。受限于图幅，仅能示出像素电路560的一部分，在图11中由虚线框所示。
所述发光元件550包括依次层叠设置的第一电极553(例如为阴极)、发光层552以及第二电极551(例如为阳极)，所述第二电极551位于所述发光层面向所述衬底基板的一侧。所述像素电路560包括至少一个薄膜晶体管，所述薄膜晶体管包括位于所述衬底基板1上的栅极450、位于所述栅极450远离所述衬底基板1一侧的源极491和漏极492，所述薄膜晶体管的源极491或漏极492与所述第二电极551电连接。所述至少一个薄膜晶体管中的源极491和漏极492与所述多个第一焊盘31、所述多个第二焊盘32和所述多个第三焊盘33设置在同一层(该层可称为源漏层)，可以采用同一构图工艺形成。
在一些实施例中，所述第一电平连接部315、所述第一电平信号线313’、所述第二电平连接部316、所述第二电平信号线314’和所述像素电路560中的薄膜晶体管的栅极450位于同一层，可以采用同一构图工艺形成。
在一些实施例中，子像素单元的膜层结构还可包括依次位于衬底基板1上的缓冲层420、有源层430、第一栅极绝缘层440、第二栅极绝缘层460、第二栅极层(上述栅极450所在的层可称为第一栅极层)、层间介质层480、钝化层510、平坦化层520、像素界定层540以及封装层570。
具体地，衬底基板1例如为柔性PI(聚酰亚胺)基板，采用透明材质制成；缓冲层420采用透明绝缘材料，例如为氧化硅、氮化硅等制成；有源层430包括像素电路中薄膜晶体管中的有源区，可以采用半导体材料制成；第一栅极绝缘层440采用透明绝缘材料，例如为氧化硅、氮化硅等制成；第一栅极层例如可以采用金属材料制作，在第一栅极层中可以形成薄膜晶体管中的栅极450以及存储电极中的第一电极471；第二栅极绝缘层460采用透明绝缘材料，例如为氧化硅、氮化硅等制成；第二栅极层例如可以用于形成存储电极的第二电极470。层间介质层80采用透明绝缘材料，例如为氧化硅、氮化硅等制成；源漏极层例如采用金属材料制作；钝化层510采用透明绝缘材料，例如为氧化硅、氮化硅等制成。平坦化层520采用透明有机材料，例如为氧化硅、氮化硅等制成。像素界定层540采用透明有机材料支撑，用于限定子像素单元中的发光区，可以采用构图工艺形成。封装层570包括依次远离衬底基板1设置的第一无机封装层571、有机封装层572以及第二无机封装层573，第一无机封装层571、有机封装层572以及第二无机封装层573叠置设置，封装层170是透光的。
本领域技术人员应当理解的是，图11中示出的结构仅是示意性的，主要体 现构成OLED显示基板的显示区10中的子像素单元的层结构，以及体现通过薄膜晶体管将像素电路的信号传输给发光元件来实现发光。
在一些实施例中，如图1所示，所述显示基板可以为可折叠基板，所述显示基板包括弯折区域30，所述多个第二焊盘32比弯折区域30更远离显示区10。相应地多个第一焊盘31和多个第三焊盘33也比弯折区域30更远离显示区10。这样，通过弯折区域30的弯折，可以将包括上述多个第一焊盘31、多个第二焊盘32和多个第三焊盘33的集成电路器件布设区域40折叠到显示屏幕的背侧，从而减小显示装置的边框宽度。
在一些实施例中，在所述集成电路器件布设区域21上已经安装有集成电路器件的情况下，所述集成电路器件在衬底基板1上的正投影至少部分地覆盖所述阵列测试组件40在衬底基板1上的正投影。这使得在最终产品中阵列测试组件40被集成电路器件完全覆盖，而不会占据多余的空间。作为示例，集成电路器件在衬底基板1上的正投影可以与集成电路器件布设区域21在衬底基板1上的正投影一致。
在本公开的实施例中，阵列测试组件40是设置于多个第一焊盘31和多个第二焊盘32之间的用于AT测试的结构的统称。如前所述，阵列测试组件40例如可包括多个第三焊盘33、多个多路复用器42、高电平信号线51和低电平信号线52以及多个静电释放结构43、第一电平信号线313、第二电平信号线314等等中的至少一些。
在本公开的实施例中，薄膜晶体管的源极和漏极是可以互换使用的，因此，在上述表述中，采用“源极和漏极中的一者”以及“源极和漏极中的另一者”的表述来表示它们中的一个或另一个，而不对源极和漏极进行具体区分。
本公开一些实施例还提供一种显示装置。如图12所示，该显示装置可以包括前述的任一实施例中的显示基板100以及集成电路器件400，所述集成电路器件400与所述多个第一焊盘31和所述多个第二焊盘32绑定。
在一些实施例中，所述集成电路器件400在衬底基板1上的正投影至少部分地覆盖所述多个第三焊盘33在衬底基板1上的正投影，例如完全覆盖所述多个第三焊盘33在衬底基板1上的正投影。这有助于节省显示基板的布线面积。
在一些实施例中，所述多个多路复用器42可以配置成在所述显示装置工作时是关断的。
作为示例，显示装置可以为：电视、显示器、数码相框、手机、智能手表、平板电脑等任何具有显示功能的产品或部件。
以上描述仅为本公开的示例性实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (18)

  1. 一种显示基板，包括：
    衬底基板，包括显示区和围绕所述显示区的周边区；
    多个子像素单元，位于所述显示区；
    多条数据线，位于所述显示区且分别与所述多个子像素单元电连接；
    多条数据传输线，位于所述显示区至少一侧的所述周边区，且分别与所述多条数据线电连接；
    多个第一焊盘和多个第二焊盘，位于所述多条数据传输线远离所述显示区的一侧，所述多个第一焊盘和所述多个第二焊盘分别沿所述显示区边界的方向延伸，所述多个第二焊盘位于所述多个第一焊盘和所述多条数据传输线之间，且与所述多条数据传输线电连接；
    多个第三焊盘，位于所述多个第一焊盘和所述多个第二焊盘之间，且所述多个第三焊盘中的至少部分焊盘与所述多个第二焊盘电连接；
    多个多路复用器，位于所述多个第二焊盘和所述多个第三焊盘之间，所述多个多路复用器中的至少一个电连接所述多个第二焊盘中的至少两个第二焊盘和所述多个第三焊盘中的一个第三焊盘。
  2. 根据权利要求1所述的显示基板，其中，所述多个多路复用器中的至少一个包括：第一薄膜晶体管和第二薄膜晶体管，所述第一薄膜晶体管包括第一源极、第一漏极和第一栅极，所述第二薄膜晶体管包括第二源极、第二漏极和第二栅极，所述第一源极和所述第一漏极中的一者以及所述第二源极和所述第二漏极中的一者与所述多个第三焊盘中的同一个焊盘电连接，所述第一源极和所述第一漏极中的另一者电连接至所述多个第二焊盘中的一个焊盘，所述第二源极和所述第二漏极中的另一者电连接至所述多个第二焊盘中的另一个焊盘，所述第一栅极电连接所述第一控制线，所述第二栅极电连接所述第二控制线，所述第一控制线用于接入第一电平信号，所述第二控制线用于接入第二电平信号，所述第一电平信号和所述第二电平信号用于使多路复用器中的第一栅极和第二栅极在显示基板的显示阶段关断。
  3. 根据权利要求2所述的显示基板，其中，所述多个第三焊盘还包括：
    第一控制端焊盘，所述第一控制端焊盘与所述第一控制线电连接；以及
    第二控制端焊盘，所述第二控制端焊盘与所述第二控制线电连接。
  4. 根据权利要求3所述的显示基板，还包括位于所述多个第一焊盘和所述多个第三焊盘之间的第一电平信号线和第二电平信号线，所述多个第一焊盘包括至少一个第一电平输入焊盘和至少一个第二电平输入焊盘，所述至少一个第一电平信号线电连接所述第一控制端焊盘和第二控制端焊盘中的一个和所述至少一个第一电平输入焊盘，所述第二电平信号线电连接所述第一控制端焊盘和第二控制端焊盘中的另一个和所述至少一个第二电平输入焊盘。
  5. 根据权利要求4所述的显示基板，还包括第一电平连接部和第二电平连接部，所述至少一个第一电平输入焊盘的数量为多个，所述至少一个第二电平输入焊盘的数量为多个；
    所述第一电平连接部位于所述多个第一电平输入焊盘和所述第一电平信号线之间，且与所述第一电平信号线和所述多个第一电平输入焊盘电连接；
    所述第二电平连接部位于所述多个第二电平输入焊盘和所述第二电平信号线之间，且与所述第二电平信号线和所述多个第二电平输入焊盘电连接。
  6. 根据权利要求5所述的显示基板，其中，所述第一电平连接部和所述第一电平信号线为一体结构，所述第二电平连接部和所述第二电平信号线为一体结构。
  7. 根据权利要求4所述的显示基板，其中，所述第一电平信号为正电压信号或负电压信号，所述第二电平信号为正电压信号或负电压信号。
  8. 根据权利要求7所述的显示基板，其中，所述正电压信号的数值范围在6V到8V之间，所述负电压信号的数值范围在-8V到-6V之间。
  9. 根据权利要求5所述的显示基板，其中，所述第一控制线、第二控制线、第一电平信号线、第二电平信号线、所述第一薄膜晶体管的栅极和所述第二薄膜晶体管的栅极由相同材料制成且布置于同一层。
  10. 根据权利要求1至9中任一项所述的显示基板，其中，所述多个第三焊盘被配置为向所述多个子像素输入测试信号，所述多个第一焊盘和所述多个第二焊盘被配置为与同一集成电路器件绑定。
  11. 根据权利要求1至9中任一项所述的显示基板，还包括第三电平信号线和第四电平信号线以及多个静电释放结构，所述第三电平信号线用于提供正电平信号，所述第四电平信号线用于提供负电平信号，其中，至少一个静电释放结构 包括：
    第三薄膜晶体管，所述第三薄膜晶体管的栅极与第三电平信号线电连接，所述第三薄膜晶体管的源极和漏极中一者与第三电平信号线电连接，另一者与所述多个第三焊盘中的一个对应的焊盘电连接；
    第四薄膜晶体管，所述第四薄膜晶体管的栅极与第三电平信号线电连接，所述第四薄膜晶体管的源极和漏极中一者与第三电平信号线电连接，另一者与所述多个第三焊盘中的所述对应的焊盘电连接；
    第五薄膜晶体管，所述第五薄膜晶体管的栅极与所述多个第三焊盘中的所述对应的焊盘电连接，所述第五薄膜晶体管的源极和漏极中一者与第四电平信号线电连接，另一者与所述多个第三焊盘中的所述对应的焊盘电连接；以及
    第六薄膜晶体管，所述第六薄膜晶体管的栅极与所述多个第三焊盘中的所述对应的焊盘电连接，所述第六薄膜晶体管的源极和漏极中一者与第四电平信号线电连接，另一者与所述多个第三焊盘中的所述对应的焊盘电连接。
  12. 根据权利要求11所述的显示基板，其中，所述第三薄膜晶体管和所述第四薄膜晶体管均包括有源层且所述第三薄膜晶体管和所述第四薄膜晶体管中的栅极包括第一条状子栅极和第二条状子栅极，所述第三薄膜晶体管和所述第四薄膜晶体管中的每一薄膜晶体管中的源极和漏极中的所述一者具有相互连接的第一臂部和第二臂部，所述第一臂部沿着第一方向延伸，所述第二臂部沿着与第一方向交叉的第二方向延伸，所述第一臂部通过第一过孔结构与有源层连接，所述第二臂部通过第二过孔结构与第一条状子栅极连接并通过第三过孔结构与第二条状子栅极连接。
  13. 根据权利要求12所述的显示基板，其中，所述静电释放结构还包括：第一连接部和第二连接部，所述第一连接部与所述有源层由相同材料制成且布置于同一层，所述第二连接部与所述源极和漏极由相同材料制成且布置于同一层，所述第一连接部通过第三过孔结构与所述第三薄膜晶体管和所述第四薄膜晶体管中的每一薄膜晶体管中的源极和漏极中的所述一者相连，所述第一连接部还通过第四过孔结构与所述第二连接部相连，所述第二连接部通过第五过孔结构与第三电平信号线相连。
  14. 根据权利要求5至9中任一项所述的显示基板，其中，所述多个子像素单元中至少一个包括像素电路和发光元件，所述像素电路位于所述衬底基板和所 述发光元件之间；
    所述发光元件包括依次层叠设置的第一电极、发光层以及第二电极，所述第二电极位于所述发光层面向所述衬底基板的一侧；
    所述像素电路包括至少一个薄膜晶体管，所述薄膜晶体管包括位于所述衬底基板上的栅极、位于所述栅极远离所述衬底基板一侧的源极和漏极，所述薄膜晶体管的源极或漏极与所述第二电极电连接；
    所述至少一个薄膜晶体管中的源极和漏极与所述多个第一焊盘、所述多个第二焊盘和所述多个第三焊盘设置在同一层。
  15. 根据权利要求14所述的显示基板，其中，所述第一电平连接部、所述第一电平信号线、所述第二电平连接部、所述第二电平信号线和所述像素电路中的薄膜晶体管的栅极位于同一层。
  16. 根据权利要求1至15中任一项所述的显示基板，其中，所述显示基板为可折叠基板，所述显示基板包括弯折区域，所述多个第二焊盘比弯折区域更远离显示区。
  17. 一种显示装置，包括：
    根据权利要求1-16中任一项所述的显示基板；以及
    集成电路器件，所述集成电路器件与所述多个第一焊盘和所述多个第二焊盘绑定。
  18. 根据权利要求17所述的显示装置，其中，所述集成电路器件在衬底基板上的正投影至少部分地覆盖所述多个第三焊盘在衬底基板上的正投影。
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