WO2017185716A1 - 静电防护与测试复合单元、阵列基板以及显示装置 - Google Patents

静电防护与测试复合单元、阵列基板以及显示装置 Download PDF

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WO2017185716A1
WO2017185716A1 PCT/CN2016/105953 CN2016105953W WO2017185716A1 WO 2017185716 A1 WO2017185716 A1 WO 2017185716A1 CN 2016105953 W CN2016105953 W CN 2016105953W WO 2017185716 A1 WO2017185716 A1 WO 2017185716A1
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Prior art keywords
signal line
thin film
film transistor
drain
electrostatic protection
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PCT/CN2016/105953
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English (en)
French (fr)
Inventor
郝学光
乔勇
吴新银
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京东方科技集团股份有限公司
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Priority to US15/538,392 priority Critical patent/US10311765B2/en
Publication of WO2017185716A1 publication Critical patent/WO2017185716A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1306—Details
    • G02F1/1309—Repairing; Testing
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Definitions

  • At least one embodiment of the invention relates to an electrostatic protection and test composite unit, an array substrate, and a display device.
  • test unit In the structural design of a Thin Film Transistor liquid crystal display (TFT-LCD), the test unit and the Electrostatic Discharge (ESD) unit (electrostatic protection unit) are separated and designed.
  • ESD Electrostatic Discharge
  • the test unit is located on the side of the data line; the ESD unit is located on the side of the data line or at the four corners of the display.
  • the separation of the designed test unit and the electrostatic discharge unit has a large footprint, which is disadvantageous for obtaining a narrow bezel and/or a high resolution display panel.
  • At least one embodiment of the present invention provides an electrostatic protection and test composite unit, an array substrate, and a display device to occupy a small area in order to obtain a narrow bezel and/or a high resolution display panel.
  • At least one embodiment of the present invention provides an electrostatic protection and test composite unit including a first signal line, a first thin film transistor and a second thin film transistor electrically connected to the first signal line, and the a second signal line electrically connected to the thin film transistor, a third signal line and a fourth signal line electrically connected to the second thin film transistor, the composite unit being configured to provide a test for the first signal line in a first stage
  • the signal is also configured to provide electrostatic protection for the first signal line in a second phase.
  • At least one embodiment of the present invention further provides an array substrate comprising any of the electrostatic protection and test composite units described in the embodiments of the present invention.
  • At least one embodiment of the present invention further provides a display device including any of the array substrates according to the embodiments of the present invention.
  • FIG. 1 is a schematic diagram of a circuit structure (equivalent circuit) of an electrostatic protection and test composite unit according to an embodiment of the present invention
  • FIG. 2 is a schematic plan view of an electrostatic protection and test composite unit according to an embodiment of the present invention.
  • FIG. 3 is a schematic plan view of a static protection and test composite unit group according to an embodiment of the present invention.
  • FIG. 4 is a schematic plan view showing another electrostatic protection and test composite unit group according to an embodiment of the present invention.
  • FIG. 5 is a schematic plan view of another electrostatic protection and test composite unit according to an embodiment of the present invention.
  • FIG. 6 is a schematic plan view of another electrostatic protection and test composite unit according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a display area and a peripheral area of an array substrate according to an embodiment of the invention.
  • a Thin Film Transistor is abbreviated as a TFT.
  • the first thin film transistor is abbreviated as a first TFT
  • the second thin film transistor is abbreviated as a second TFT
  • the third thin film transistor is abbreviated as a third TFT.
  • the source and the drain are opposite to each other.
  • the drain is also replaced with a source.
  • S represents a source
  • D represents a drain.
  • test unit of the liquid crystal cell is used as follows:
  • the electrical test fixture is used to provide the display with the required signal through the Cell test unit;
  • step 3 Select the good product selected in step 2 to perform the chip bonding process; after the process step is completed, the Cell test unit is discarded.
  • Embodiments of the present disclosure are based on this, integrating a test unit and an electrostatic discharge (electrostatic protection) unit to form an electrostatic protection and test composite unit to reduce the footprint.
  • the signal of the test phase (high-level or low-level signal, etc.) can be provided to the electrostatic protection and test composite unit through the electrical test fixture, and the signal of the electrostatic discharge phase (high level or low level) Signal, etc.)
  • the chip is supplied to the electrostatic protection and test compound unit.
  • At least one embodiment of the present disclosure provides an electrostatic protection and test composite unit.
  • the composite unit includes a first signal line 10, a first TFT 01 and a second electrically connected to the first signal line 10.
  • the TFT 02, the second signal line 20 electrically connected to the first TFT 01, the third signal line 30 and the fourth signal line 40 electrically connected to the second TFT 02, the composite unit is configured to be the first signal line 10 in the first stage
  • a test signal is provided and configured to provide static protection for the first signal line 10 in a second phase.
  • the first stage is a test phase and the second stage is an electrostatic protection phase (electrostatic discharge phase).
  • test phase refers to the stage of testing the display screen before chip bonding
  • static electricity protection phase refers to the stage of electrostatically discharging the static charge accumulated on the first signal line after chip bonding.
  • the ESD and test composite unit occupies a small area to obtain a narrow bezel and/or high resolution display panel.
  • the source in the N-type TFT, the source is at a low level, the drain is at a high level, and a positive gate voltage (a gate-source voltage difference greater than 0) can turn on the N-type TFT.
  • a positive gate voltage a gate-source voltage difference greater than 0
  • the source is extremely high, the drain is low, and the negative gate voltage (gate-source voltage difference is less than 0) can turn on the P-type TFT.
  • the drain and the gate are electrically connected to form a diode will be described as an example.
  • the gate may be electrically connected to the drain to form a diode, or the gate and the drain may be connected to different signal lines, but the signal line connected to the gate and the signal line connected to the drain may be connected to the same signal, thereby forming The structure of the diode.
  • the embodiment of the present disclosure is described by way of example, but is not limited thereto.
  • the embodiment provides a static protection and test composite unit.
  • the composite unit includes a first signal line 10, a first TFT 01 and a second TFT 02 electrically connected to the first signal line 10, and a second signal line 20 electrically connected to the first TFT 01, a third signal line 30 and a fourth signal line 40 electrically connected to the second TFT 02, the composite unit being configured to provide a test signal for the first signal line 10 in the first stage And configured to provide static protection for the first signal line 10 in the second stage.
  • the first phase is the testing phase and the second phase is the electrostatic protection phase (electrostatic discharge phase).
  • the first TFT 01, the second TFT 02, the second signal line 20, the third signal line 30, and the fourth signal line 40 have both an electrostatic protection function and a test function. That is, in the test phase, the first TFT 01, the second TFT 02, the second signal line 20, the third signal line 30, and the fourth signal line 40 have a test function, and in the electrostatic discharge phase, the first TFT 01, the second TFT 02, and the second Signal line 20, third signal line 30, and fourth letter Line 40 has an electrostatic protection function.
  • test and ESD composite design is adopted, and the test unit discarded after the completion of the binding process is converted into an ESD protection device, which increases the layout space of the layout, and is advantageous for narrow border and high-resolution product design.
  • the electrical test fixture can be utilized to provide the display panel with the desired signal for illumination by the electrostatic protection and test composite unit of the present embodiment.
  • the second signal line 20, the third signal line 30, and the fourth signal line 40 are high level signal lines, and the first TFT 01 and the second TFT 02 are turned on.
  • the test signals applied by the second signal line 20 and the third signal line 30 are transmitted to the first signal line 10.
  • the second signal line 20, the third signal line 30, and the fourth signal line 40 may be low-level signal lines, which are not limited in the embodiment of the present disclosure.
  • the first thin film transistor and the second thin film transistor are configured to be turned on when the second signal line, the third signal line, and the fourth signal line are applied with the first level or the second level signal, and
  • the first level or second level signal applied by the second signal line and the third signal line is transmitted to the first signal line for testing.
  • the first level refers to a high level and the second level refers to a low level.
  • the test finished product is subjected to a chip bonding process.
  • the second signal line 20 is connected to the VGH (high level) of the chip.
  • the pin, the third signal line 30 and the fourth signal line 40 are connected to the VGL (low level) pin of the chip.
  • the second signal line 20 is connected to the VGL (low level) pin of the chip, and the third signal line 30 and the fourth signal line 40 are connected.
  • the line connects the chip's VGH (high) pin.
  • the second signal line 20 in the electrostatic discharge phase, is a high level signal line, and the third signal line 30 and the fourth signal line 40 are low level signal lines, such that the first The static charge accumulated on the signal line 10 is derived via the first TFT 01 and the second signal line 20 or is derived via the second TFT 02 and the third signal line 30.
  • the second signal line 20 may be a low level signal line
  • the third signal line 30 and the fourth signal line 40 may be a high level signal line, such that the first signal line 10 is on the first signal line 10.
  • the accumulated static charge is derived from the first TFT 01 and the second signal line 20 or is derived through the second TFT 02 and the third signal line 30, which is not limited by the embodiment of the present disclosure.
  • a positive electrostatic charge or a negative electrostatic charge can be accumulated on the first signal line.
  • the first signal line may be a data line, a gate line, a clock signal line, or the like in the array substrate, which is not limited herein.
  • the array substrate is, for example, a substrate constituting a liquid crystal display panel or an organic light emitting diode display panel, which is not limited herein. As long as it is a signal line containing static electricity to be discharged. Taking a liquid crystal display panel as an example, a single display panel can be completed by an array manufacturing process and a box-forming process. This step uses the usual process flow in the industry, and will not be described herein.
  • the positive static charge accumulated on the first signal line is released through the high level signal line
  • the negative static charge accumulated on the first signal line is released through the low level signal line.
  • the charge is discharged through a TFT and a high-level signal line or a low-level signal line connected to the TFT.
  • static charge is discharged to the second signal line through the first TFT or to the third signal line through the second TFT.
  • the first thin film transistor and the second signal line are configured to be applied when the second signal line is applied with the first level signal, and the third signal line and the fourth signal line are applied with the second level signal
  • the static charge accumulated on the first signal line, the second thin film transistor and the third signal line are configured to apply a second level signal to the second signal line, and the third signal line and the fourth signal line are applied with the first level
  • the static charge accumulated on the first signal line is derived.
  • the first level refers to a high level and the second level refers to a low level.
  • the first TFT 01 is an N-type TFT
  • the second TFT 02 is an N-type TFT.
  • the first TFT 01 may be a P-type TFT
  • the second TFT 02 may be a P-type TFT
  • the first TFT 01 may be an N-type TFT
  • the second TFT 02 may be a P-type TFT
  • the second TFT 02 is an N-type TFT, which is not limited by the embodiment of the present disclosure.
  • the first TFT 01 includes a first source 011, a first drain 012, a first gate 013, and a first active layer 014; the first signal line 10 and the first The drain 012 is electrically connected, and the second signal line 20 is electrically connected to the first source 011.
  • the first gate 013 is electrically connected to the first drain 012. It should be noted that, in other examples, the first signal line 10 is electrically connected to the first source 011, and the second signal line 20 is electrically connected to the first drain 012, which is not limited by the embodiment of the present disclosure. .
  • the second TFT 02 includes a second source 021, a second drain 022, a second gate 023, and a second active layer 024; the first signal line 10 and the second The source 021 is electrically connected, the third signal line 30 is electrically connected to the second drain 022, and the second gate 023 is electrically connected to the fourth signal line 40. It should be noted that, in other examples, the first signal line 10 and the second drain 022 may be electrically connected, and the third signal line 30 is electrically connected to the second source 021.
  • a TFT includes a source, a drain, a gate, and an active layer, and a source and The drains are provided on both sides of the active layer.
  • the source and drain may be electrically connected directly to the active layer; they may also be electrically connected to the active layer through vias.
  • the first source 011 and the first drain 012 are electrically connected to the first active layer 014 through via holes, respectively, and the second source 021 and the second drain 022 respectively pass through the via and the second The source layer 024 is electrically connected.
  • one of the signal lines may be at the intersection.
  • a connecting portion is disposed on the other conductive layer, and both ends of the connecting portion are electrically connected to both ends of the disconnected signal line through the insulating layer via.
  • the first gate electrode 013 and the second gate electrode 023 are formed in the same layer, and the first signal line 10, the second signal line 20, the third signal line 30, and the fourth signal line 40 are formed in the same layer as an example. .
  • An insulating layer may be disposed between the layer in which the first gate electrode 013 and the second gate electrode 023 are located and the layer in which the first signal line 10, the second signal line 20, the third signal line 30, and the fourth signal line 40 are located.
  • the two intersecting signal lines can be electrically connected through the connection portion.
  • the first signal line 10 is disconnected at a position crossing the second signal line 20, and is electrically disconnected through the connection portion 002 and the via hole 001 in the same layer as the first gate electrode 013 and the second gate electrode 023. It should be noted that the embodiments of the present disclosure are not limited thereto.
  • the manner of electrical connection is not limited. For example, it may be directly electrically connected, or formed integrally, or may be electrically connected through a via, as long as electrical connection can be achieved.
  • the first signal line 10 includes a first portion 101
  • the second signal line 20 includes a first portion 201
  • the first portion 101 of the first signal line 10 acts as a first drain 012
  • the first portion 201 of the second signal line 20 acts as First source 011.
  • the first portion 101 of the first signal line 10 may serve as the first source 011
  • the first portion 201 of the second signal line 20 may serve as the first drain 012. Embodiments of the present disclosure This is not limited.
  • the first signal line 10 includes a second portion 102
  • the third signal line 30 includes a first portion 301
  • the second portion 102 of the first signal line 10 serves as a second source 021
  • the first portion of the third signal line 30 301 is used as the second drain 022.
  • the second portion 102 of the first signal line 10 may serve as the second drain 022
  • the first portion 301 of the third signal line 30 may serve as the second source 021. This example does not limit this.
  • the fourth signal line 40 includes a first portion 401 and the first portion 401 of the fourth signal line 40 serves as a second gate 023.
  • FIG. 2 is only an example and is not limited.
  • the first portion of the second signal line 20 in FIG. 2 may also serve as the first drain 012, the first portion of the first gate and the second signal line 20. (the first drain 012) is electrically connected.
  • the first TFT 01 and the second TFT are P-type TFTs, and in the test phase, the second signal line 20, the third signal line 30, and the fourth signal line 40 may be low.
  • the level signal line, the first TFT 01 and the second TFT 02 are turned on, and the test signals applied by the second signal line 20 and the third signal line 30 are transmitted to the first signal line 10.
  • the second signal line 20 is The low level signal line
  • the third signal line 30 and the fourth signal line 40 are high level signal lines, such that the static charge accumulated on the first signal line 10 is derived via the first TFT 01 and the second signal line 20 or via the second The TFT 02 and the third signal line 30 are derived.
  • the static protection and test composite unit group formed by the plurality of first signal lines 10 may be as shown in FIG. 3, and each of the first signal lines is any one of the electrostatic protection and test composite units described in this embodiment.
  • the odd-numbered column and the even-numbered column are respectively any one of the electrostatic protection and test composite unit structures described in the embodiment, for example, the odd-numbered columns correspond to the second signal line 20 and the third signal.
  • the line 30 and the fourth signal line 40, the even columns correspond to the sixth signal line 60, the fourth signal line 40, and the seventh signal line 70. Only the first first signal line 1001, the second first signal line 1002, the N-1th first signal line 1003, and the Nth first signal line 1004 are shown in FIGS. 3 and 4.
  • the embodiment further provides a method for fabricating a static electricity protection and test composite unit, the method comprising the following steps.
  • An interlayer insulating layer is formed and a via hole is formed in the interlayer insulating layer, and a pattern of a connection portion is formed on the interlayer insulating layer on which the via hole is formed, and signal lines broken at the intersection are electrically connected.
  • electrostatic protection and test composite unit of the embodiment of the present disclosure It should be noted that the electrostatic protection and test composite unit of the embodiment of the present disclosure It is not limited to the method given above.
  • the static electricity protection and test composite unit provided in this embodiment is different from the first embodiment in that, as shown in FIG. 5, the static electricity protection and test composite unit further includes a third TFT 03 and a first portion electrically connected to the first signal line 10.
  • the fifth TFT 03 is electrically connected to the fifth signal line 50.
  • the second TFT 02, the third signal line 30, and the fourth signal line 40 are configured to provide a test signal for the first signal line 10 in the first stage, the first TFT 01, the third TFT 03, the second signal line 20, and the fifth signal line
  • the 50 is configured to provide static protection for the first signal line 10 in the second phase.
  • the first phase is the testing phase and the second phase is the electrostatic protection phase (electrostatic discharge phase).
  • the second TFT 02, the third signal line 30, and the fourth signal line 40 have a test function; in the electrostatic discharge phase, the first TFT 01, the third TFT 03, the second signal line 20, and the fifth signal line 50 have Electrostatic protection.
  • the third TFT 03 includes a third source 031, a third drain 032, a third gate 033, and a third active layer 034; a fifth signal line 50 and a third source 031 Electrically connected, the first signal line 10 is electrically connected to the third drain 032; the third gate 033 is electrically connected to the third drain 032; and the second source 021 of the second TFT 02 is shared as the third drain of the third TFT 03. 032.
  • the fifth signal line 50 may be electrically connected to the third drain 032, and the first signal line 10 is electrically connected to the third source 031, which is not limited by the embodiment of the present disclosure. .
  • the second source 021 of the second TFT 02 may be shared as the third drain 032 of the third TFT 03, or the second drain 022 of the second TFT 02 may be shared as the third source of the third TFT 03. 031, or the second drain 022 of the second TFT 02 is shared as the third drain 032 of the third TFT 03, which is not limited by the embodiment of the present disclosure.
  • the third source 031 and the third drain 032 are electrically connected to the third active layer 034 through via holes, respectively.
  • the second TFT 02 is a P-type TFT.
  • the third signal line 30 and the fourth signal line 40 are low-level signal lines, and the second TFT 02 is turned on, and the third signal line is turned on.
  • the applied test signal is transmitted to the first signal line 10.
  • the third signal line 30 and the fourth signal line 40 may be high-level signal lines in the testing phase, which is not limited by the embodiment of the present disclosure.
  • the first TFT 01 is an N-type TFT
  • the third TFT 03 is a P-type TFT.
  • the second signal line 20 is a high-level signal line
  • the fifth signal line 50 is a low-voltage.
  • Flat signal line so that the static charge accumulated on the first signal line 10 passes through the first TFT 01 and the second
  • the signal line 20 is derived or derived via the third TFT 03 and the fifth signal line 50.
  • the positive static charge accumulated on the first signal line 10 is led out through the first TFT 01 and the second signal line 20, and the negative static charge accumulated on the first signal line 10 is derived through the third TFT 03 and the fifth signal line 50.
  • the second signal line 20 is a low-level signal line
  • the fifth signal line 50 is a high-level signal line, which is not limited by the embodiment of the present disclosure.
  • the fifth signal line 50 includes a first portion 501, and the first portion 501 of the fifth signal line 50 serves as a third source 031 or a third drain 032.
  • the third signal line 30 and the fourth signal line 40 are the same as the fifth signal line 50 as a low level signal line. It should be noted that, in other examples, the third signal line 30 and the fourth signal line 40 and the fifth signal line 50 may be the same as the high level signal line, which is not limited by the embodiment of the present disclosure.
  • the third TFT 03 is an N-type TFT
  • the first TFT 01 and the second TFT 02 are also N-type TFTs
  • the second source 021 of the second TFT 02 is shared as a third drain of the third TFT 03. 032.
  • the third signal line 30 and the fourth signal line 40 are high level signal lines
  • the second TFT 02 is turned on, and the test signal applied by the third signal line 30 is transmitted to the first signal line 10.
  • the second signal line 20 is a low level signal line
  • the third signal line 30 and the fourth signal line 40 are the same as the fifth signal line 50 as a high level signal line.
  • the static charge accumulated on the first signal line 10 is caused to be derived via the first TFT 01 and the second signal line 20 or derived through the third TFT 03 and the fifth signal line 50.
  • the positive static charge accumulated on the first signal line 10 is led out through the third TFT 03 and the fifth signal line 50, and the negative static charge accumulated on the first signal line 10 is derived via the first TFT 01 and the second signal line 20. .
  • This embodiment provides an array substrate comprising any of the static electricity protection and test composite units described in Embodiment 1 or Embodiment 2.
  • the array substrate includes a display area 100 and a peripheral area 200 located outside of the display area 100, and an electrostatic protection and test composite unit may be disposed in the peripheral area 200.
  • the peripheral area may be located on at least one side of the display area, or the peripheral area may be disposed around the display area.
  • the display area is located in the middle of the array substrate, for example surrounded by a non-display area, and the display area includes a plurality of sub-pixel units arranged in an array, each sub-pixel unit including a TFT as a switching element.
  • a pixel electrode or the like electrically connected to the drain of the TFT may be disposed in the display region, and will not be described in detail herein.
  • This embodiment provides a display device including any of the array substrates described in Embodiment 3.
  • the display device may be a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, and a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, and a navigation device including the display device. Any product or component that has a display function.
  • a display device such as a liquid crystal display, an electronic paper, an OLED (Organic Light-Emitting Diode) display, and a television, a digital camera, a mobile phone, a watch, a tablet, a notebook computer, and a navigation device including the display device. Any product or component that has a display function.

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Abstract

一种静电防护与测试复合单元、阵列基板以及显示装置。该复合单元包括第一信号线(10)、与第一信号线(10)电连接的第一薄膜晶体管(01)和第二薄膜晶体管(02)，与第一薄膜晶体管(01)电连接的第二信号线(20)、与第二薄膜晶体管(02)电连接的第三信号线(30)和第四信号线(40)，该复合单元被配置在第一阶段为第一信号线(10)提供测试信号并被配置在第二阶段为第一信号线(10)提供静电防护，第一阶段为测试阶段，第二阶段为静电防护阶段。该复合单元可占用较小的面积，以便获得窄边框和/或者高分辨率的显示面板。

Description

静电防护与测试复合单元、阵列基板以及显示装置 技术领域
本发明至少一实施例涉及一种静电防护与测试复合单元、阵列基板以及显示装置。
背景技术
薄膜晶体管液晶显示器(Thin Film Transistor liquid crystal display,TFT-LCD)的结构设计中，测试单元与静电放电(Electrostatic Discharge，ESD)单元(静电防护单元)采用分离设计的方式。通常测试单元位于数据线的边侧；ESD单元位于数据线的边侧或显示屏四个角的位置。分离设计的测试单元与静电放电单元占用面积较大，不利于获得窄边框和/或者高分辨率的显示面板。
发明内容
本发明的至少一实施例提供一种静电防护与测试复合单元、阵列基板以及显示装置，以占用较小的面积，以便获得窄边框和/或者高分辨率的显示面板。
本发明的至少一实施例提供一种静电防护与测试复合单元，该复合单元包括第一信号线、与所述第一信号线电连接的第一薄膜晶体管和第二薄膜晶体管，与所述第一薄膜晶体管电连接的第二信号线、与所述第二薄膜晶体管电连接的第三信号线和第四信号线，该复合单元被配置来在第一阶段为所述第一信号线提供测试信号并被配置来在第二阶段为所述第一信号线提供静电防护。
本发明的至少一实施例还提供一种阵列基板，包括本发明实施例所述的任一静电防护与测试复合单元。
本发明的至少一实施例还提供一种显示装置，包括本发明实施例所述的任一阵列基板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为本发明一实施例提供的一种静电防护与测试复合单元的电路结构(等效电路)示意图；
图2为本发明一实施例提供的一种静电防护与测试复合单元的平面示意图；
图3为本发明一实施例提供的一种静电防护与测试复合单元组的平面示意图；
图4为本发明一实施例提供的另一种静电防护与测试复合单元组的平面示意图；
图5为本发明一实施例提供的另一种静电防护与测试复合单元的平面示意图；
图6为本发明一实施例提供的另一种静电防护与测试复合单元的平面示意图；
图7为本发明一实施例提供的阵列基板的显示区域和周边区域的示意图。
附图标记：
10-第一信号线；01-第一TFT；02-第二TFT；03-第三TFT；20-第二信号线；30-第三信号线；40-第四信号线；50-第五信号线；60-第六信号线；70-第七信号线；011-第一源极；012-第一漏极；013-第一栅极；014-第一有源层；021-第二源极；022-第二漏极；023-第二栅极；024-第一有源层；101-第一信号线的第一部分；102-第一信号线的第二部分；1001-第一条第一信号线；1002-第二条第一信号线；1003-第N-1条第一信号线；1004-第N条第一信号线；201-第二信号线的第一部分；301-第三信号线的第一部分；401-第四信号线的第一部分；031-第三源极；032-第三漏极；033-第三栅极；034-第三有源层；501-第五信号线的第一部分；100-显示区域；200-周边区域；001-过孔；002-连接部。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的实施例中，薄膜晶体管(Thin Film Transistor，TFT)简写为TFT。相应的，第一薄膜晶体管简写为第一TFT，第二薄膜晶体管简写为第二TFT，第三薄膜晶体管简写为第三TFT。并且，本公开的实施例中，源极和漏极相对而言，可相互替换。例如，将源极替换为漏极的情况下，漏极亦替换为源极。各附图中，“S”表示源极，“D”表示漏极。
以液晶显示屏为例，通常，液晶盒(Cell)的测试单元的使用方法如下：
(1)显示屏的Cell制作完成后，没有进行芯片绑定(Bonding)之前，利用电学测试治具通过Cell的测试单元为显示屏提供点亮所需信号；
(2)显示屏点亮后需要对显示屏的显示效果及电学特性进行综合评价；
(3)挑选步骤2中所选良品，进行芯片Bonding工艺；该工艺步骤完成后Cell测试单元被废弃。
本公开的实施例基于此，将测试单元和静电放电(静电防护)单元整合形成静电防护与测试复合单元，以减小占用面积。本公开的实施例中，测试阶段的信号(高电平或者低电平信号等)可通过电学测试治具提供给静电防护与测试复合单元，静电放电阶段的信号(高电平或者低电平信号等)可通 过芯片提供给静电防护与测试复合单元。
本公开至少一实施例提供一种静电防护与测试复合单元，如图1和图5所示，该复合单元包括第一信号线10、与第一信号线10电连接的第一TFT01和第二TFT02，与第一TFT01电连接的第二信号线20、与第二TFT02电连接的第三信号线30和第四信号线40，该复合单元被配置来在第一阶段为第一信号线10提供测试信号并被配置来在第二阶段为第一信号线10提供静电防护。本公开的实施例中，第一阶段为测试阶段，第二阶段为静电防护阶段(静电放电阶段)。例如，测试阶段是指在芯片绑定之前对显示屏进行测试的阶段，静电防护阶段是指在芯片绑定之后对第一信号线上积累的静电荷进行静电放电的阶段。该静电防护与测试复合单元占用较小的面积，从而可获得窄边框和/或者高分辨率的显示面板。
下面通过几个具体的实施例来进行说明。需要说明的是，以下各实施例中，N型TFT中，源极为低电平，漏极为高电平，正的栅压(栅源压差大于0)可打开N型TFT。P型TFT中，源极为高电平，漏极为低电平，负的栅压(栅源压差小于0)可打开P型TFT。本公开的实施例中，以漏极与栅极电连接形成二极管为例进行说明。栅极可与漏极电连接以构成二极管，或者虽然栅极与漏极与不同的信号线相连，但与栅极相连的信号线和与漏极相连的信号线可以连接同一信号，从而可形成二极管的结构。本公开的实施例以其为例进行说明，但并不限于此。
实施例1
本实施例提供一种静电防护与测试复合单元，如图1和图2所示，该复合单元包括第一信号线10、与第一信号线10电连接的第一TFT01和第二TFT02，与第一TFT01电连接的第二信号线20、与第二TFT02电连接的第三信号线30和第四信号线40，该复合单元被配置来在第一阶段为第一信号线10提供测试信号并被配置来在第二阶段为第一信号线10提供静电防护。第一阶段为测试阶段，第二阶段为静电防护阶段(静电放电阶段)。第一TFT01、第二TFT02、第二信号线20、第三信号线30和第四信号线40既具有静电防护功能又具有测试功能。即，在测试阶段，第一TFT01、第二TFT02、第二信号线20、第三信号线30和第四信号线40具有测试功能，在静电放电阶段，第一TFT01、第二TFT02、第二信号线20、第三信号线30和第四信 号线40具有静电防护功能。
本实施例将测试与ESD复合设计，将完成绑定工艺后废弃的测试单元转化为ESD保护器件，增大了版图布图空间，利于窄边框与高分辨率产品设计。
例如，可利用电学测试治具通过本实施例的静电防护与测试复合单元为显示面板提供点亮所需信号。一些示例中，如图1和图2所示，测试阶段，第二信号线20、第三信号线30和第四信号线40为高电平信号线，第一TFT01和第二TFT02导通，将第二信号线20和第三信号线30施加的测试信号传递给第一信号线10。需要说明的是，在另一些示例中，亦可第二信号线20、第三信号线30和第四信号线40为低电平信号线，本公开的实施例对此不作限定。
例如，第一阶段，第一薄膜晶体管和第二薄膜晶体管被配置来在第二信号线、第三信号线和第四信号线被施加第一电平或第二电平信号时导通，并将第二信号线和第三信号线施加的第一电平或第二电平信号传递给第一信号线以进行测试。例如，第一电平是指高电平，第二电平是指低电平。
然后将测试完成的良品进行芯片绑定(Bonding)工艺，例如，本实施例的静电防护与测试复合单元中，如图2所示，第二信号线20连接芯片的VGH(高电平)引脚，第三信号线30和第四信号线40线连接芯片的VGL(低电平)引脚。或者，在另一些示例中，也可以本实施例的静电防护与测试复合单元中，第二信号线20连接芯片的VGL(低电平)引脚，第三信号线30和第四信号线40线连接芯片的VGH(高电平)引脚。一些示例中，如图1和图2所示，静电放电阶段，第二信号线20为高电平信号线，第三信号线30和第四信号线40为低电平信号线，使得第一信号线10上积累的静电荷经第一TFT01以及第二信号线20导出或者经第二TFT02以及第三信号线30导出。需要说明的是，在另一些示例中，亦可第二信号线20为低电平信号线，第三信号线30和第四信号线40为高电平信号线，使得第一信号线10上积累的静电荷经第一TFT01以及第二信号线20导出或者经第二TFT02以及第三信号线30导出，本公开的实施例对此不作限定。
第一信号线上可积累正的静电荷或负的静电荷。例如，第一信号线可为阵列基板中的数据线、栅线、时钟信号线等，在此不作限定。阵列基板例如为构成液晶显示面板或有机发光二极管显示面板的一个基板，在此不作限定， 只要是其中包含待释放静电的信号线即可。以液晶显示面板为例，可通过阵列制造工艺，成盒工艺完成单个显示面板的制作，该步骤采用业界通常的工艺流程，在此不再赘述。
例如，本公开的实施例中，第一信号线上积累的正的静电荷通过高电平信号线释放，第一信号线上积累的负的静电荷通过低电平信号线释放。例如，静电荷释放时通过一个TFT以及与该TFT相连的高电平信号线或低电平信号线将电荷导出。例如，静电荷通过第一TFT释放给第二信号线，或者通过第二TFT释放给第三信号线。例如，第二阶段，第一薄膜晶体管以及第二信号线被配置来在第二信号线被施加第一电平信号，第三信号线和第四信号线被施加第二电平信号时，导出第一信号线上积累的静电荷，第二薄膜晶体管以及第三信号线被配置来在第二信号线被施加第二电平信号，第三信号线和第四信号线被施加第一电平信号时，导出第一信号线上积累的静电荷。例如，第一电平是指高电平，第二电平是指低电平。
一些示例中，如图1和图2所示，第一TFT01为N型TFT，第二TFT02为N型TFT。需要说明的是，在另一些示例中，亦可第一TFT01为P型TFT，第二TFT02为P型TFT，或者，第一TFT01为N型TFT，第二TFT02为P型TFT，第一TFT01为P型TFT，第二TFT02为N型TFT，本公开的实施例对此不作限定。
一些示例中，如图1和图2所示，第一TFT01包括第一源极011、第一漏极012、第一栅极013和第一有源层014；第一信号线10与第一漏极012电连接，第二信号线20与第一源极011电连接。第一栅极013与第一漏极012电连接。需要说明的是，在另一些示例中，亦可第一信号线10与第一源极011电连接，第二信号线20与第一漏极012电连接，本公开的实施例对此不作限定。
一些示例中，如图1和图2所示，第二TFT02包括第二源极021、第二漏极022、第二栅极023和第二有源层024；第一信号线10与第二源极021电连接，第三信号线30与第二漏极022电连接；第二栅极023与第四信号线40电连接。需要说明的是，在另一些示例中，亦可第一信号线10与第二漏极022电连接，第三信号线30与第二源极021电连接。
本公开的实施例中，一个TFT包括源极、漏极、栅极和有源层，源极和 漏极分设在有源层的两侧。在一些示例中，源极和漏极可直接与有源层电连接；也可以通过过孔与有源层电连接。如图2所示，第一源极011和第一漏极012分别通过过孔与第一有源层014电连接，第二源极021和第二漏极022分别通过过孔与第二有源层024电连接。
需要说明的是，本公开的实施例中，第一信号线、第二信号线、第三信号线、第四信号线以及其他信号线之间若有交叉部分，其中一条信号线可在交叉处断开，在其他导电层设置连接部，该连接部的两端可通过绝缘层过孔与断开的信号线的两端电连接。
图2中，以第一栅极013和第二栅极023同层形成，第一信号线10、第二信号线20、第三信号线30、第四信号线40同层形成为例进行说明。第一栅极013和第二栅极023所在的层与第一信号线10、第二信号线20、第三信号线30和第四信号线40所在的层之间可设置绝缘层。两条交叉的信号线之间可通过连接部电连接。例如，第一信号线10在和第二信号线20交叉的地方断开，通过与第一栅极013和第二栅极023同层的连接部002以及过孔001电连接断开处。需要说明的是，本公开的实施例不限于此。
需要说明的是，本公开的实施例中，对电连接的方式不作限定。例如可直接电连接，或者一体形成，也可通过过孔电连接，只要是能实现电连接即可。
一些示例中，第一信号线10包括第一部分101，第二信号线20包括第一部分201，第一信号线10的第一部分101作为第一漏极012，第二信号线20的第一部分201作为第一源极011。需要说明的是，在另一些示例中，亦可第一信号线10的第一部分101作为第一源极011，第二信号线20的第一部分201作为第一漏极012，本公开的实施例对此不作限定。
一些示例中，第一信号线10包括第二部分102，第三信号线30包括第一部分301，第一信号线10的第二部分102作为第二源极021，第三信号线30的第一部分301作为第二漏极022。需要说明的是，在另一些示例中，亦可第一信号线10的第二部分102作为第二漏极022，第三信号线30的第一部分301作为第二源极021，本公开的实施例对此不作限定。
一些示例中，第四信号线40包括第一部分401，第四信号线40的第一部分401作为第二栅极023。
需要说明的是，图2中只是例举，并非限定，例如，图2中第二信号线20的第一部分亦可作为第一漏极012，第一栅极与第二信号线20的第一部分(第一漏极012)电连接，此情况下，第一TFT01和第二TFT为P型TFT，在测试阶段，第二信号线20、第三信号线30和第四信号线40可为低电平信号线，第一TFT01和第二TFT02导通，将第二信号线20和第三信号线30施加的测试信号传递给第一信号线10，在静电放电阶段，第二信号线20为低电平信号线，第三信号线30和第四信号线40为高电平信号线，使得第一信号线10上积累的静电荷经第一TFT01以及第二信号线20导出或者经第二TFT02以及第三信号线30导出。
一些示例中，多条第一信号线10形成的静电防护与测试复合单元组可如图3所示，每条第一信号线均为本实施例所述的任意一种静电防护与测试复合单元结构，或者，也可如图4所示，奇数列和偶数列分别为本实施例所述的任意一种静电防护与测试复合单元结构，例如，奇数列对应第二信号线20、第三信号线30和第四信号线40，偶数列对应第六信号线60、第四信号线40和第七信号线70。图3和图4中仅示出了第一条第一信号线1001、第二条第一信号线1002、第N-1条第一信号线1003和第N条第一信号线1004。
例如，本实施例还提供一种静电防护与测试复合单元的制作方法，该方法包括如下步骤。
(1)在衬底基板上形成缓冲层；
(2)在缓冲层上形成半导体层，该半导体层003包括第一有源层014、第二有源层024的图形；
(3)在半导体层上形成栅极绝缘层；
(4)在栅极绝缘层上形成第一栅极013、第二栅极023的图形；
(5)在栅极绝缘层上形成过孔；
(6)在形成了过孔的栅极绝缘层上形成第一TFT01的第一源极011和第一漏极012、第二TFT02的第二源极021和第二漏极022、以及第一信号线、第二信号线、第三信号线和第四信号线同层设置的部分的图形；
(7)形成层间绝缘层并在该层间绝缘层内形成过孔，在形成了过孔的层间绝缘层上形成连接部的图形，将在交叉处断开的信号线电连接。
需要说明的是，本公开的实施例的静电防护与测试复合单元的制作方法 不限于上述给出的方法。
实施例2
本实施例提供的静电防护与测试复合单元与实施例1的不同之处在于：如图5所示，静电防护与测试复合单元还包括与第一信号线10电连接的第三TFT03和与第三TFT03电连接的第五信号线50。第二TFT02、第三信号线30和第四信号线40被配置来在第一阶段为第一信号线10提供测试信号，第一TFT01、第三TFT03、第二信号线20和第五信号线50被配置来在第二阶段为第一信号线10提供静电防护。第一阶段为测试阶段，第二阶段为静电防护阶段(静电放电阶段)。即，在测试阶段，第二TFT02、第三信号线30和第四信号线40具有测试功能；在静电放电阶段，第一TFT01、第三TFT03、第二信号线20和第五信号线50具有静电防护功能。
一些示例中，如图5所示，第三TFT03包括第三源极031、第三漏极032、第三栅极033和第三有源层034；第五信号线50与第三源极031电连接，第一信号线10与第三漏极032电连接；第三栅极033与第三漏极032电连接；第二TFT02的第二源极021共用为第三TFT03的第三漏极032。需要说明的是，在另一些示例中，亦可第五信号线50与第三漏极032电连接，第一信号线10与第三源极031电连接，本公开的实施例对此不作限定。在另一些示例中，亦可第二TFT02的第二源极021共用为第三TFT03的第三漏极032，或者，第二TFT02的第二漏极022共用为第三TFT03的第三源极031，或者，第二TFT02的第二漏极022共用为第三TFT03的第三漏极032，本公开的实施例对此不作限定。例如，第三源极031和第三漏极032分别通过过孔与第三有源层034电连接。
一些示例中，第二TFT02为P型TFT，如图5所示，测试阶段，第三信号线30和第四信号线40为低电平信号线，第二TFT02导通，将第三信号线30施加的测试信号传递给第一信号线10。需要说明的是，在另一些示例中，测试阶段，第三信号线30和第四信号线40可为高电平信号线，本公开的实施例对此不作限定。
一些示例中，如图5所示，第一TFT01为N型TFT，第三TFT03为P型TFT，静电放电阶段，第二信号线20为高电平信号线，第五信号线50为低电平信号线，使得第一信号线10上积累的静电荷经第一TFT01以及第二 信号线20导出或者经第三TFT03以及第五信号线50导出。例如，使得第一信号线10上积累的正的静电荷经第一TFT01以及第二信号线20导出，第一信号线10上积累的负的静电荷经第三TFT03以及第五信号线50导出。需要说明的是，在另一些示例中，亦可第二信号线20为低电平信号线，第五信号线50为高电平信号线，本公开的实施例对此不作限定。
一些示例中，如图5所示，第五信号线50包括第一部分501，第五信号线50的第一部分501作为第三源极031或第三漏极032。
一些示例中，如图5所示，第三信号线30和第四信号线40与第五信号线50同为低电平信号线。需要说明的是，在另一些示例中，第三信号线30和第四信号线40与第五信号线50可同为高电平信号线，本公开的实施例对此不作限定。
一些示例中，如图6所示，第三TFT03为N型TFT，第一TFT01和第二TFT02也为N型TFT，第二TFT02的第二源极021共用为第三TFT03的第三漏极032，测试阶段，第三信号线30和第四信号线40为高电平信号线，第二TFT02导通，将第三信号线30施加的测试信号传递给第一信号线10。在静电放电阶段，第二信号线20为低电平信号线，第三信号线30和第四信号线40与第五信号线50同为高电平信号线。使得第一信号线10上积累的静电荷经第一TFT01以及第二信号线20导出或者经第三TFT03以及第五信号线50导出。例如，使得第一信号线10上积累的正的静电荷经第三TFT03以及第五信号线50导出，第一信号线10上积累的负的静电荷经第一TFT01以及第二信号线20导出。
实施例3
本实施例提供一种阵列基板，包括实施例1或实施例2所述的任一静电防护与测试复合单元。
一些示例中，如图7所示，阵列基板包括显示区域100和位于显示区域100外的周边区域200，静电防护与测试复合单元可设置在周边区域200中。例如，周边区域可位于显示区的至少一侧，或者周边区域可围绕显示区设置。例如，显示区位于阵列基板的中部，例如被非显示区围绕，显示区包括按阵列排列的多个亚像素单元，每个亚像素单元包括TFT作为开关元件。例如，显示区内还可设置有与TFT漏极电连接的像素电极等，在此不再详述。
实施例4
本实施例提供一种显示装置，包括实施例3所述的任一阵列基板。
所述显示装置可以为液晶显示器、电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
有以下几点需要说明：
(1)除非另作定义，本公开的实施例附图中的同一标号代表同一含义。
(2)本发明实施例附图中，只涉及到与本发明实施例涉及到的结构，其他结构可在本公开的基础上参考通常设计。
(3)为了清晰起见，在用于描述本发明的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(4)在不冲突的情况下，本发明的不同的实施例及同一实施例中的特征可以相互组合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。
本专利申请要求于2016年4月26日递交的中国专利申请第201620362982.3号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (19)

  1. 一种静电防护与测试复合单元，其中，该复合单元包括第一信号线、与所述第一信号线电连接的第一薄膜晶体管和第二薄膜晶体管，与所述第一薄膜晶体管电连接的第二信号线、与所述第二薄膜晶体管电连接的第三信号线和第四信号线，该复合单元被配置来在第一阶段为所述第一信号线提供测试信号并被配置来在第二阶段为所述第一信号线提供静电防护。
  2. 根据权利要求1所述的静电防护与测试复合单元，其中，所述第一薄膜晶体管包括第一栅极、第一源极和第一漏极；所述第一信号线与所述第一漏极电连接，所述第二信号线与所述第一源极电连接，或者，所述第一信号线与所述第一源极电连接，所述第二信号线与所述第一漏极电连接；所述第一栅极与所述第一漏极或所述第一源极电连接；
    所述第二薄膜晶体管包括第二栅极、第二源极和第二漏极；所述第一信号线与所述第二源极电连接，所述第三信号线与所述第二漏极电连接，或者，所述第一信号线与所述第二漏极电连接，所述第三信号线与所述第二源极电连接；所述第二栅极与所述第四信号线电连接。
  3. 根据权利要求2所述的静电防护与测试复合单元，其中，所述第一阶段，所述第一薄膜晶体管和所述第二薄膜晶体管被配置来在所述第二信号线、所述第三信号线和所述第四信号线被施加第一电平或第二电平信号时导通，并将所述第二信号线和所述第三信号线施加的第一电平或第二电平信号传递给所述第一信号线以进行测试。
  4. 根据权利要求2所述的静电防护与测试复合单元，其中，所述第二阶段，所述第一薄膜晶体管以及所述第二信号线被配置来在所述第二信号线被施加第一电平信号，所述第三信号线和所述第四信号线被施加第二电平信号时，导出所述第一信号线上积累的静电荷，所述第二薄膜晶体管以及所述第三信号线被配置来在所述第二信号线被施加第二电平信号，所述第三信号线和所述第四信号线被施加第一电平信号时，导出所述第一信号线上积累的静电荷。
  5. 根据权利要求1-4任一项所述的静电防护与测试复合单元，其中，所述第一薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管，所述第二薄膜晶体 管为N型薄膜晶体管或P型薄膜晶体管。
  6. 根据权利要求2-4任一项所述的静电防护与测试复合单元，其中，所述第一信号线包括第一部分，所述第二信号线包括第一部分，所述第一信号线的第一部分作为所述第一漏极，所述第二信号线的第一部分作为所述第一源极，或者，所述第一信号线的第一部分作为所述第一源极，所述第二信号线的第一部分作为所述第一漏极。
  7. 根据权利要求2-4任一项所述的静电防护与测试复合单元，其中，所述第一信号线包括第二部分，所述第三信号线包括第一部分，所述第一信号线的第二部分作为所述第二源极，所述第三信号线的第一部分作为所述第二漏极，或者，所述第一信号线的第二部分作为所述第二漏极，所述第三信号线的第一部分作为所述第二源极。
  8. 根据权利要求2-4任一项所述的静电防护与测试复合单元，其中，所述第四信号线包括第一部分，所述第四信号线的第一部分作为所述第二栅极。
  9. 根据权利要求2所述的静电防护与测试复合单元，其中，还包括与所述第一信号线电连接的第三薄膜晶体管和与所述第三薄膜晶体管电连接的第五信号线，所述第二薄膜晶体管、所述第三信号线和所述第四信号线被配置来在第一阶段为所述第一信号线提供测试信号，所述第一薄膜晶体管、所述第三薄膜晶体管、所述第二信号线和所述第五信号线被配置来在第二阶段为所述第一信号线提供静电防护。
  10. 根据权利要求9所述的静电防护与测试复合单元，其中，所述第三薄膜晶体管包括第三栅极、第三源极和第三漏极；所述第五信号线与所述第三源极电连接，所述第一信号线与所述第三漏极电连接，或者，所述第五信号线与所述第三漏极电连接，所述第一信号线与所述第三源极电连接；所述第三栅极与所述第三漏极或所述第三源极电连接；所述第二薄膜晶体管的所述第二漏极或所述第二源极共用为所述第三薄膜晶体管的所述第三源极或所述第三漏极。
  11. 根据权利要求10所述的静电防护与测试复合单元，其中，所述测试阶段，所述第三信号线和所述第四信号线为高电平信号线或低电平信号线，所述第二薄膜晶体管导通，将所述第三信号线施加的测试信号传递给所述第一信号线。
  12. 根据权利要求9-11任一项所述的静电防护与测试复合单元，其中，所述静电放电阶段，所述第二信号线为低电平信号线，所述第五信号线为高电平信号线，或者，所述第二信号线为高电平信号线，所述第五信号线为低电平信号线，使得所述第一信号线上积累的静电荷经所述第一薄膜晶体管以及所述第二信号线导出或者经所述第三薄膜晶体管以及所述第五信号线导出。
  13. 根据权利要求9-11任一项所述的静电防护与测试复合单元，其中，所述第三信号线和所述第四信号线与所述第五信号线同为高电平信号线或低电平信号线。
  14. 根据权利要求10或11所述的静电防护与测试复合单元，其中，所述第五信号线包括第一部分，所述第五信号线的第一部分作为所述第三源极或所述第三漏极。
  15. 根据权利要求9-11任一项所述的静电防护与测试复合单元，其中，所述第三薄膜晶体管为N型薄膜晶体管或P型薄膜晶体管。
  16. 一种阵列基板，包括权利要求1-15任一项所述的静电防护与测试复合单元。
  17. 根据权利要求16所述的阵列基板，其中，所述阵列基板包括显示区域和位于所述显示区域外的周边区域，所述的静电防护与测试复合单元位于所述周边区域中。
  18. 一种显示装置，包括权利要求16或17所述的阵列基板。
  19. 根据权利要求18所述的显示装置，其中，所述显示装置包括液晶显示装置和有机发光二极管显示装置。
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