WO2021225125A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2021225125A1
WO2021225125A1 PCT/JP2021/017272 JP2021017272W WO2021225125A1 WO 2021225125 A1 WO2021225125 A1 WO 2021225125A1 JP 2021017272 W JP2021017272 W JP 2021017272W WO 2021225125 A1 WO2021225125 A1 WO 2021225125A1
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Prior art keywords
layer
main surface
electrode
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2021/017272
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English (en)
French (fr)
Japanese (ja)
Inventor
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to DE112021000398.4T priority Critical patent/DE112021000398B4/de
Priority to US17/801,798 priority patent/US12476162B2/en
Priority to JP2022519955A priority patent/JP7656593B2/ja
Priority to CN202180032864.XA priority patent/CN115516644A/zh
Priority to DE212021000199.8U priority patent/DE212021000199U1/de
Publication of WO2021225125A1 publication Critical patent/WO2021225125A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025048467A priority patent/JP2025085827A/ja
Priority to US19/363,687 priority patent/US20260047478A1/en
Ceased legal-status Critical Current

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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
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    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07552—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in structures or sizes
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    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • Patent Document 1 discloses a technique relating to a vertical semiconductor element using a SiC semiconductor substrate.
  • One embodiment of the present invention provides a semiconductor device with reduced on-resistance.
  • a semiconductor layer having a first main surface, a second main surface opposite to the first main surface, a first electrode layer formed on the first main surface, and the above-mentioned
  • a semiconductor device including a mold layer covering a film, the semiconductor layer including a semiconductor substrate constituting the second main surface, and the thickness of the semiconductor substrate being thinner than the thickness of the plating layer.
  • One embodiment of the present invention is a semiconductor layer having a first main surface and a second main surface opposite to the first main surface, and includes a semiconductor substrate constituting the second main surface.
  • a first electrode layer is formed on the first main surface of the semiconductor, an insulating film covering the end portion of the first electrode layer is formed, and a plating layer covering at least a part other than the end portion of the first electrode layer is formed.
  • a mold layer covering the insulating film is formed, and the semiconductor substrate is ground from the second main surface side until the thickness of the semiconductor substrate becomes thinner than the thickness of the plating layer, and the semiconductor substrate is ground.
  • a method for manufacturing a semiconductor device which forms a second electrode layer on the second main surface of the semiconductor layer after the semiconductor layer.
  • One embodiment of the present invention includes a semiconductor substrate having a first thickness, a semiconductor layer having a main surface, and a main surface arranged on the main surface and having a second thickness less than the first thickness.
  • a semiconductor device including a surface electrode and a pad electrode arranged on the main surface electrode and having a third thickness exceeding the first thickness.
  • One embodiment of the present invention comprises a semiconductor layer having a first thickness and including a main surface, and a main surface electrode arranged on the main surface and having a second thickness less than the first thickness.
  • a photosensitive resin layer having a third thickness exceeding the second thickness by covering the peripheral portion of the main surface electrode so as to expose the inner portion of the main surface electrode, and the inside of the main surface electrode.
  • a thermosetting resin layer having a fourth thickness exceeding the third thickness and the main surface electrode are covered with the photosensitive resin layer sandwiched so as to expose the square portion.
  • a semiconductor device comprising a pad electrode having a fifth thickness exceeding the third thickness, which is arranged on the inner portion of the above.
  • FIG. 1 is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.
  • FIG. 3 is a diagram showing a detailed configuration of an outer peripheral portion of the semiconductor device shown in FIG.
  • FIG. 4 is a diagram showing a detailed configuration of a semiconductor layer of the semiconductor device shown in FIG.
  • FIG. 5A is a first cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 5B is a second cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 5C is a third cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 5D is a fourth cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 5E is a fifth cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 5F is a sixth cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 5G is a seventh cross-sectional view showing a method of manufacturing the semiconductor device shown in FIG.
  • FIG. 6A is a first cross-sectional view showing a method of grinding a semiconductor substrate.
  • FIG. 6B is a second cross-sectional view showing a method of grinding a semiconductor substrate.
  • FIG. 6C is a third cross-sectional view showing a method of grinding a semiconductor substrate.
  • FIG. 7 is a diagram showing the relationship between the thickness of the semiconductor substrate and the on-resistance.
  • FIG. 8 is a plan view of the semiconductor device according to the second embodiment.
  • FIG. 9 is a cross-sectional view of the semiconductor device shown in FIG.
  • FIG. 10 is a diagram showing a detailed configuration of an outer peripheral portion of the semiconductor device shown in FIG.
  • FIG. 11 is a diagram showing an example of a semiconductor package according to the third embodiment.
  • FIG. 12 is a diagram showing an example of the semiconductor package shown in FIG.
  • FIG. 13 is a diagram showing another example of the semiconductor package according to the third embodiment.
  • FIG. 14 is a cross-sectional view of a semiconductor device having a structure in which a nickel layer is formed on a plating layer.
  • FIG. 15 is a cross-sectional view of a semiconductor device including a plating layer having a two-layer structure.
  • FIG. 16 is a plan view of the semiconductor device according to the modified example.
  • FIG. 17A is a first cross-sectional view showing a dicing step according to a modified example.
  • FIG. 17B is a second cross-sectional view showing a dicing step according to a modified example.
  • FIG. 17C is a third cross-sectional view showing a dicing step according to a modified example.
  • FIG. 18A is a first cross-sectional view showing a dicing step according to another modified example.
  • FIG. 18B is a second cross-sectional view showing a dicing step according to another modified example.
  • FIG. 18C is a third cross-sectional view showing a dicing step according to another modified example.
  • the terms “upper” and “lower” do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition, but are based on the stacking order in the stacking configuration. It is used as a term defined by the relative positional relationship with.
  • one of the semiconductor layers, the first main surface side is the upper side (upper side)
  • the other second main surface side is the lower side (lower side).
  • the semiconductor device vertical transistor
  • the first main surface side may be the lower side (lower side) and the second main surface side may be the upper side (upper side).
  • the semiconductor device may be used in a posture in which the first main surface and the second main surface are inclined or orthogonal to the horizontal plane.
  • the terms “upper” and “lower” are applied when the two components are spaced apart from each other so that another component is interposed between the two components. It is also applied when the two components are arranged so that the two components are in close contact with each other.
  • FIG. 1 is a plan view of the semiconductor device according to the first embodiment.
  • FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG. 1 (cross-sectional view taken along the line II-II of FIG. 1).
  • the semiconductor device 100 shown in FIG. 1 is a semiconductor chip that functions as a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor).
  • the semiconductor device 100 is, for example, a power semiconductor device used for supplying and controlling electric power.
  • the semiconductor device 100 includes a semiconductor layer 101, a first electrode layer 102, a second electrode layer 103, an insulating film 104, a plating layer 105, and a mold layer 106.
  • the semiconductor layer 101 is a SiC semiconductor layer containing a SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor.
  • the semiconductor layer 101 is formed in a rectangular plate shape in a plan view.
  • the plan view means viewing from a direction perpendicular to the first main surface 101a or the second main surface 101b (viewing from the z-axis direction in the drawing).
  • the length of one side of the semiconductor layer 101 is, for example, 1 mm or more and 10 mm or less, but may be 2 mm or more and 5 mm or less.
  • the semiconductor layer 101 has a first main surface 101a and a second main surface 101b that faces the first main surface 101a. Further, the semiconductor layer 101 includes a semiconductor substrate 101c constituting the second main surface 101b and an epitaxial layer 101d located on the semiconductor substrate 101c. The epitaxial layer 101d is obtained by epitaxial growth of the semiconductor substrate 101c.
  • the thickness t1 of the semiconductor layer 101 is smaller than the thickness t2 of the plating layer 105, which will be described later, and is smaller than the thickness t3 of the mold layer 106.
  • the thickness of the semiconductor substrate 101c is, for example, 5 ⁇ m or more and 40 ⁇ m or less, and more preferably 5 ⁇ m or more and 20 ⁇ m or less.
  • the thickness of the epitaxial layer 101d is, for example, 10 ⁇ m or more and 20 ⁇ m or less.
  • the thickness of the semiconductor substrate 101c is smaller than the thickness of the epitaxial layer 101d.
  • the semiconductor layer 101 is not limited to the SiC semiconductor layer, and may be a semiconductor layer made of another wide bandgap semiconductor such as GaN, or may be a Si semiconductor layer.
  • the first electrode layer 102 is formed on the first main surface 101a.
  • the first electrode layer 102 may be referred to as a "first main surface electrode".
  • the first electrode layer 102 includes a first electrode layer 102 g that functions as a gate electrode and a first electrode layer 102s that functions as a source electrode.
  • the first electrode layer 102 is made of, for example, aluminum.
  • the first electrode layer 102 may be formed of other materials such as titanium, nickel, copper, silver, gold, titanium nitride, and tungsten.
  • the first electrode layer 102s may have an area of 50% or more of the area of the semiconductor substrate 101c (first main surface 101a) in a plan view.
  • the first electrode layer 102s may have an area of 70% or more of the area of the semiconductor substrate 101c (first main surface 101a) in a plan view.
  • the first electrode layer 102g may have an area of 20% or less of the area of the semiconductor substrate 101c (first main surface 101a) in a plan view.
  • the first electrode layer 102g may have an area of 10% or less of the area of the semiconductor substrate 101c (first main surface 101a) in a plan view.
  • the first electrode layer 102s is arranged in a region including the center position of the semiconductor substrate 101c in a plan view.
  • the first electrode layer 102g is arranged in a region avoiding the first electrode layer 102s.
  • the first electrode layer 102g may be arranged in a region including the central position of the semiconductor substrate 101c in a plan view, and the first electrode layer 102s may be arranged so as to surround the periphery of the first electrode layer 102g.
  • the second electrode layer 103 is formed on the second main surface 101b.
  • the second electrode layer 103 may be referred to as a "second main surface electrode".
  • the second electrode layer 103 functions as a drain electrode.
  • the second electrode layer 103 is formed of, for example, a laminated film of titanium, nickel, and gold.
  • the second electrode layer 103 may be formed of other materials such as aluminum, copper, silver, titanium nitride, and tungsten.
  • the insulating film 104 covers the entire circumference of the outer peripheral portion of the first electrode layer 102 (that is, both ends in the x-axis direction and both ends in the y-axis direction).
  • the outer peripheral portion of the first electrode layer 102 may be referred to as a peripheral portion of the first electrode layer 102.
  • the insulating film 104 includes a first portion 104a and a second portion 104b.
  • the first portion 104a rides on the first electrode layer 102. More specifically, the first portion 104a rides on the peripheral edge of the first electrode layer 102.
  • the second portion 104b is located outside the first portion 104a and covers a region other than the first electrode layer 102. That is, the second portion 104b does not ride on the first electrode layer 102.
  • the first portion 104a further includes an inner end portion 104a1 and a flat portion 104a2.
  • the inner end portion 104a1 is an end portion of a portion of the first portion 104a located on the inner side of the semiconductor layer 101 in a plan view.
  • the inner end portion 104a1 is obliquely inclined downward toward the inner portion of the first electrode layer 102 in a cross-sectional view.
  • the flat portion 104a2 is located on the outer side of the inner end portion 104a1 (peripheral side of the semiconductor layer 101) and has a substantially uniform thickness.
  • the insulating film 104 is, for example, an organic film containing a photosensitive resin.
  • the insulating film 104 is formed of, for example, polyimide, PBO (polybenzoxazole), or the like.
  • the insulating film 104 may be an inorganic film formed of silicon nitride (SiN), silicon oxide (SiO 2), or the like.
  • the insulating film 104 may have a single-layer structure, or may have a laminated structure in which a plurality of types of materials are laminated.
  • the insulating film 104 may include both an organic film and an inorganic film.
  • the insulating film 104 preferably includes an inorganic film and an organic film laminated in this order from the first main surface 101a side.
  • the maximum thickness of the insulating film 104 is about 10 ⁇ m.
  • the plating layer 105 is a metal layer that covers at least a part of the first electrode layer 102.
  • the plating layer 105 covers at least a part of the first electrode layer 102 other than the end portion (that is, the portion covered with the insulating film 104). As shown in FIG. 1, in plan view, the plating layer 105 is surrounded by the mold layer 106.
  • the plating layer 105 includes a plating layer 105 (first plating layer) on the side of the first electrode layer 102g and a plating layer 105 (second plating layer) on the side of the first electrode layer 102s.
  • the plating layer 105 formed on the first electrode layer 102 g functions as a gate pad (pad electrode) having a rectangular shape in a plan view.
  • the plating layer 105 formed on the first electrode layer 102s functions as a source pad (pad electrode).
  • the pad is a portion to which the bonding wire is bonded when the semiconductor device 100 is packaged.
  • the plating layer 105 also functions as a support member for the mold layer 106.
  • the plating layer 105 is formed of, for example, a material different from that of the first electrode layer 102.
  • the plating layer 105 is formed of, for example, copper or a copper alloy containing copper as a main component.
  • the plating layer 105 may be formed of another metal material.
  • the thickness t2 of the plating layer 105 is larger than the thickness of the insulating film 104. More specifically, the thickness t2 of the plating layer 105 is larger than the maximum thickness of the insulating film 104 located on the first electrode layer 102. As a result, the top of the plating layer 105 is higher than the top of the insulating film 104.
  • the thickness t2 of the plating layer 105 is, for example, 30 ⁇ m or more and 100 ⁇ m or less.
  • the thickness t2 of the plating layer 105 may be 100 ⁇ m or more and 200 ⁇ m or less.
  • the side surface 105a of the plating layer 105 extends vertically or substantially vertically.
  • the side surface 105a does not necessarily have to extend linearly in cross-sectional view and may include curves and irregularities.
  • the side surface 105a is located in a region where both the first electrode layer 102 and the insulating film 104 overlap each other. More specifically, the side surface 105a is located on the flat portion 104a2 of the insulating film 104. That is, the plating layer 105 covers the inner end portion 104a1 and the flat portion 104a2 of the first portion 104a. By locating the side surface 105a on the flat portion 104a2, the plating layer 105 can be formed more stably than in the case where the side surface 105a is positioned on the inner end portion 104a1 having a relatively large variation in thickness.
  • the mold layer 106 is a resin layer that covers at least a part of the insulating film 104. In this form, the mold layer 106 also covers a part of the first main surface 101a.
  • the mold layer 106 is located on the outer peripheral portion of the semiconductor layer 101 on the first main surface 101a side.
  • the outer peripheral portion of the semiconductor layer 101 (first main surface 101a) may be referred to as the peripheral portion of the semiconductor layer 101 (first main surface 101a).
  • the mold layer 106 is a rectangular ring along the outer peripheral portion of the semiconductor layer 101.
  • the mold layer 106 is also located between the gate pad (plating layer 105 on the first electrode layer 102g) and the source pad (plating layer 105 on the first electrode layer 102s). That is, the mold layer 106 is formed only on the first main surface 101a of the semiconductor layer 101, and exposes the second main surface 101b and the side surface of the semiconductor layer 101.
  • the inner surface of the mold layer 106 is in direct contact with the side surface 105a of the plating layer 105.
  • the inner surface of the mold layer 106 includes an inner surface on the side of the first electrode layer 102g (first inner surface) and an inner surface on the side of the first electrode layer 102s (second inner surface).
  • the mold layer 106 is formed of, for example, a thermosetting resin (epoxy resin).
  • the mold layer 106 may be formed of an epoxy resin containing carbon, glass fiber and the like.
  • the thickness t3 of the mold layer 106 is, for example, 30 ⁇ m or more and 100 ⁇ m or less.
  • the thickness t3 of the mold layer 106 may be 100 ⁇ m or more and 200 ⁇ m or less.
  • the upper surface of the mold layer 106 and the upper surface of the plating layer 105 are flush with each other or substantially flush with each other.
  • the source pad may have an area of 50% or more of the area of the semiconductor substrate 101c (first main surface 101a) in a plan view.
  • the source pad may have an area of 70% or more of the area of the semiconductor substrate 101c (first main surface 101a) in a plan view.
  • the gate pad may have an area of 20% or less of the area of the semiconductor substrate 101c (first main surface 101a) in a plan view.
  • the gate pad may have an area of 10% or less of the area of the semiconductor substrate 101c (first main surface 101a) in a plan view.
  • the source pad is arranged in a region including the center position of the semiconductor substrate 101c in a plan view.
  • the gate pad is arranged in an area avoiding the source pad.
  • the gate pad may be arranged in a region including the center position of the semiconductor substrate 101c in a plan view, and the source pad may be arranged so as to surround the periphery of the gate pad.
  • FIG. 3 is a view showing a detailed configuration of an outer peripheral portion of the semiconductor device 100 (a cross-sectional view showing the details of region III in FIG. 2).
  • the gate finger 102a and the outer peripheral source contact 102b are also shown.
  • the insulating film 104 includes a first insulating film 104c located on the first electrode layer 102s and a second insulating film 104d located on the first insulating film 104c.
  • the first insulating film 104c is an inorganic film formed of silicon nitride, silicon oxide, or the like.
  • the second insulating film 104d is an organic film formed of polyimide, PBO, or the like.
  • the insulating film 104 includes a third insulating film 104e located below the outer peripheral source contact 102b. More specifically, the third insulating film 104e is located between the outer peripheral source contact 102b and the semiconductor layer 101.
  • the third insulating film 104e is an inorganic film formed of silicon nitride, silicon oxide, or the like.
  • such an insulating film 104 is provided to suppress the invasion of water into the end portion of the first electrode layer 102s and the occurrence of ion migration.
  • a durability test in a high temperature and high humidity environment or a reliability test such as a temperature cycle test is performed, the insulating film 104 deteriorates, moisture invades from the deteriorated part, or ion migration occurs at the deteriorated part. May occur. That is, the deterioration of the insulating film 104 may cause a failure of the semiconductor device.
  • the insulating film 104 is further covered with the mold layer 106. As a result, deterioration of the insulating film 104 is suppressed, and the reliability of the semiconductor device 100 is improved.
  • the end portion of the first electrode layer 102s, the gate finger 102a, and the outer peripheral source contact 102b are basically covered with the first insulating film 104c, but in the example of FIG. 3, the end portion of the first electrode layer 102s , The gate finger 102a, and the outer peripheral source contact 102b are covered with the second insulating film 104d, and the first insulating film 104c is omitted. With such a configuration, the stress is relaxed.
  • FIG. 4 is a diagram showing a detailed configuration of the semiconductor layer 101.
  • the semiconductor layer 101 is not shaded to represent a cross section from the viewpoint of easy viewing of the drawing.
  • the semiconductor layer 101 specifically includes a semiconductor substrate 101c and an epitaxial layer 101d.
  • the semiconductor device 100 shown in FIG. 4 is an example of a switching device and includes a vertical transistor 2.
  • the vertical transistor 2 is, for example, a vertical MISFET.
  • the semiconductor device 100 includes a semiconductor layer 101, a gate electrode 20, a source electrode 30, and a drain electrode 40.
  • the drain electrode 40 corresponds to the second electrode layer 103.
  • the semiconductor layer 101 includes a semiconductor layer 101 containing SiC (silicon carbide) as a main component.
  • the semiconductor layer 101 is an n-type SiC semiconductor layer containing a SiC single crystal.
  • the SiC single crystal is, for example, a 4H-SiC single crystal.
  • the 4H-SiC single crystal has an off angle inclined within 10 ° with respect to the [11-20] direction from the (0001) plane.
  • the off angle may be 0 ° or more and 4 ° or less.
  • the off angle may be greater than 0 ° and less than 4 °.
  • the off angle is set, for example, in the range of 2 ° or 4 °, 2 ° ⁇ 0.2 ° or 4 ° ⁇ 0.4 °.
  • the semiconductor layer 101 is formed in the shape of a rectangular parallelepiped chip.
  • the semiconductor layer 101 has a first main surface 101a and a second main surface 101b.
  • the semiconductor layer 101 has a semiconductor substrate 101c and an epitaxial layer 101d.
  • the semiconductor substrate 101c contains a SiC single crystal.
  • the lower surface of the semiconductor substrate 101c is the second main surface 101b.
  • the second main surface 101b is a carbon surface (000-1) surface on which the carbon of the SiC crystal is exposed.
  • the epitaxial layer 101d is an n- type SiC semiconductor layer laminated on the upper surface of the semiconductor substrate 101c and containing a SiC single crystal.
  • the upper surface of the epitaxial layer 101d is the first main surface 101a.
  • the first main surface 101a is a silicon surface (0001) surface on which the silicon of the SiC crystal is exposed.
  • a drain electrode 40 is connected to the second main surface 101b of the semiconductor layer 101.
  • the semiconductor substrate 101c is provided as an n + type drain region.
  • the epitaxial layer 101d is provided as an n- type drain drift region.
  • the concentration of n-type impurities in the semiconductor substrate 101c is, for example, 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 21 cm -3 or less.
  • the n-type impurity concentration of the epitaxial layer 101d is lower than the n-type impurity concentration of the semiconductor substrate 101c, for example, 1.0 ⁇ 10 15 cm -3 or more and 1.0 ⁇ 10 17 cm -3 or less.
  • impurity concentration means the peak value of the impurity concentration.
  • the epitaxial layer 101d of the semiconductor layer 101 includes a deep well region 15, a body region 16, a source region 17, and a contact region 18.
  • the deep well region 15 is formed in the semiconductor layer 101 along the source trench 32.
  • the deep well region 15 is also referred to as a pressure resistance holding region.
  • the deep well region 15 is a p - type semiconductor region.
  • the p-type impurity concentration in the deep well region 15 is, for example, 1.0 ⁇ 10 17 cm -3 or more and 1.0 ⁇ 10 19 cm -3 or less.
  • the p-type impurity concentration in the deep well region 15 is higher than, for example, the n-type impurity concentration in the epitaxial layer 101d.
  • the deep well region 15 includes a side wall portion 15a along the side wall 32a of the source trench 32 and a bottom wall portion 15b along the bottom wall 32b of the source trench 32.
  • the thickness of the bottom wall portion 15b (length in the z-axis direction) is, for example, greater than or equal to the thickness of the side wall portion 15a (length in the x-axis direction). At least a part of the bottom wall portion 15b may be located in the semiconductor substrate 101c.
  • the body region 16 is a p- type semiconductor region provided on the surface layer portion of the first main surface 101a of the semiconductor layer 101.
  • the body region 16 is provided between the gate trench 22 and the source trench 32 in a plan view.
  • the body region 16 is provided in a strip shape extending along the y-axis direction in a plan view.
  • the body region 16 is connected to the deep well region 15.
  • the p-type impurity concentration in the body region 16 is, for example, 1.0 ⁇ 10 16 cm -3 or more and 1.0 ⁇ 10 19 cm -3 or less.
  • the p-type impurity concentration in the body region 16 may be equal to the impurity region in the deep well region 15.
  • the p-type impurity concentration in the body region 16 may be higher than the p-type impurity concentration in the deep well region 15.
  • the source region 17 is an n + type semiconductor region provided on the surface layer portion of the first main surface 101a of the semiconductor layer 101.
  • the source region 17 is a part of the body region 16.
  • the source region 17 is provided in a region along the gate trench 22.
  • the source region 17 is in contact with the gate insulating layer 23.
  • the source region 17 is provided in a strip shape extending along the y-axis direction in a plan view.
  • the width (length in the x-axis direction) of the source region 17 is, for example, 0.2 ⁇ m or more and 0.6 ⁇ m or less. As an example, the width of the source region 17 may be about 0.4 ⁇ m.
  • the concentration of n-type impurities in the source region 17 is, for example, 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 21 cm -3 or less.
  • the contact region 18 is a p + type semiconductor region provided on the surface layer portion of the first main surface 101a of the semiconductor layer 101.
  • the contact region 18 may be considered to be a part (high concentration portion) of the body region 16.
  • the contact region 18 is provided in a region along the source trench 32.
  • the contact region 18 is in contact with the barrier cambium 33. Further, the contact area 18 is connected to the source area 17.
  • the contact region 18 is provided in a strip shape extending along the y-axis direction in a plan view.
  • the width (length in the x-axis direction) of the contact region 18 is, for example, 0.1 ⁇ m or more and 0.4 ⁇ m or less. As an example, the width of the contact region 18 may be about 0.2 ⁇ m.
  • the p-type impurity concentration in the contact region 18 is, for example, 1.0 ⁇ 10 18 cm -3 or more and 1.0 ⁇ 10 21 cm -3 or less.
  • a plurality of trench gate structures 21 and a plurality of trench source structures 31 are provided on the first main surface 101a of the semiconductor layer 101.
  • the trench gate structure 21 and the trench source structure 31 are alternately and repeatedly provided one by one along the x-axis direction. In FIG. 4, only the range in which one trench gate structure 21 is sandwiched between two trench source structures 31 is shown.
  • Both the trench gate structure 21 and the trench source structure 31 are provided in a strip shape extending along the y-axis direction.
  • the x-axis direction is the [11-20] direction and the y-axis direction is the [1-100] direction.
  • the x-axis direction may be the [1-100] direction ([-1100] direction).
  • the y-axis direction may be the [11-20] direction.
  • the trench gate structure 21 and the trench source structure 31 are arranged alternately along the x-axis direction to form a striped structure in a plan view.
  • the distance between the trench gate structure 21 and the trench source structure 31 is, for example, 0.3 ⁇ m or more and 1.0 ⁇ m or less.
  • the trench gate structure 21 includes a gate trench 22, a gate insulating layer 23, and a gate electrode 20.
  • the gate trench 22 is formed by digging the first main surface 101a of the semiconductor layer 101 toward the second main surface 101b.
  • the gate trench 22 has a rectangular cross-sectional shape in the xz cross section, and is an elongated groove-shaped recess extending along the y-axis direction.
  • the gate trench 22 has a length on the order of millimeters in the longitudinal direction (y-axis direction).
  • the gate trench 22 has a length of, for example, 1 mm or more and 10 mm or less.
  • the length of the gate trench 22 may be 2 mm or more and 5 mm or less.
  • the total length of one or more gate trenches 22 per unit area may be 0.5 ⁇ m / ⁇ m2 or more and 0.75 ⁇ m / ⁇ m2 or less.
  • the gate insulating layer 23 is provided in a film shape along the side wall 22a and the bottom wall 22b of the gate trench 22.
  • the gate insulating layer 23 partitions a concave space inside the gate trench 22.
  • the gate insulating layer 23 contains, for example, silicon oxide.
  • the gate insulating layer 23 may contain at least one of impurity-free silicon, silicon nitride, aluminum oxide, aluminum nitride or aluminum oxynitride.
  • the thickness of the gate insulating layer 23 is, for example, 0.01 ⁇ m or more and 0.5 ⁇ m or less.
  • the thickness of the gate insulating layer 23 may be uniform or may vary depending on the portion.
  • the gate insulating layer 23 includes a side wall portion 23a along the side wall 22a of the gate trench 22 and a bottom wall portion 23b along the bottom wall 22b of the gate trench 22.
  • the thickness of the bottom wall portion 23b may be thicker than the thickness of the side wall portion 23a.
  • the thickness of the bottom wall portion 23b is, for example, 0.01 ⁇ m or more and 0.2 ⁇ m or less.
  • the thickness of the side wall portion 23a is, for example, 0.05 ⁇ m or more and 0.5 ⁇ m or less.
  • the gate insulating layer 23 may include an upper surface portion provided on the upper surface of the source region 17 outside the gate trench 22. The thickness of the upper surface portion may be thicker than the thickness of the side wall portion 23a.
  • the gate electrode 20 is an example of a control electrode of the vertical transistor 2.
  • the gate electrode 20 is embedded in the gate trench 22.
  • a gate insulating layer 23 is provided between the gate electrode 20 and the side wall 22a and the bottom wall 22b of the gate trench 22. That is, the gate electrode 20 is embedded in the concave space partitioned by the gate insulating layer 23.
  • the gate electrode 20 is, for example, a conductive layer containing conductive polysilicon.
  • the gate electrode 20 may contain at least one of a metal such as titanium, nickel, copper, aluminum, silver, gold and tungsten, or a conductive metal nitride such as titanium nitride.
  • the aspect ratio of the trench gate structure 21 is defined by the ratio of the depth (length in the z-axis direction) of the trench gate structure 21 to the width (length in the x-axis direction) of the trench gate structure 21.
  • the aspect ratio of the trench gate structure 21 is, for example, the same as the aspect ratio of the gate trench 22.
  • the aspect ratio of the trench gate structure 21 is, for example, 0.25 or more and 15.0 or less.
  • the width of the trench gate structure 21 is, for example, 0.2 ⁇ m or more and 2.0 ⁇ m or less. As an example, the width of the trench gate structure 21 may be about 0.4 ⁇ m.
  • the depth of the trench gate structure 21 is, for example, 0.5 ⁇ m or more and 3.0 ⁇ m or less. As an example, the depth of the trench gate structure 21 may be about 1.0 ⁇ m.
  • the trench source structure 31 includes a deep well region 15, a source trench 32, a barrier cambium 33, and a source electrode 30.
  • the source trench 32 is formed by digging the first main surface 101a of the semiconductor layer 101 toward the second main surface 101b.
  • the source trench 32 has a rectangular cross-sectional shape in the xz cross section, and is an elongated groove-shaped recess extending along the y-axis direction.
  • the source trench 32 is deeper than, for example, the gate trench 22. That is, the bottom wall 32b of the source trench 32 is located closer to the second main surface 101b than the bottom wall 22b of the gate trench 22.
  • the barrier forming layer 33 is provided in a film shape along the side wall 32a and the bottom wall 32b of the source trench 32.
  • the barrier cambium 33 partitions a concave space inside the source trench 32.
  • the barrier forming layer 33 is formed by using a material different from that of the source electrode 30.
  • the barrier cambium 33 has a higher potential barrier than the potential barrier between the source electrode 30 and the deep well region 15.
  • the barrier forming layer 33 is an insulating barrier forming layer.
  • the barrier cambium 33 contains at least one of impurity-free silicon, silicon oxide, silicon nitride, aluminum oxide, aluminum nitride or aluminum oxynitride.
  • the barrier forming layer 33 may be formed by using the same material as the gate insulating layer 23. In this case, the barrier forming layer 33 may have the same film thickness as the gate insulating layer 23.
  • the barrier forming layer 33 and the gate insulating layer 23 are formed by using silicon oxide, they can be formed at the same time by a thermal oxidation treatment method.
  • the barrier forming layer 33 may be a conductive barrier forming layer.
  • the barrier cambium 33 contains at least one of conductive polysilicon, tungsten, platinum, nickel, cobalt or molybdenum.
  • the source electrode 30 is embedded in the source trench 32.
  • a barrier forming layer 33 is provided between the source electrode 30 and the side wall 32a and the bottom wall 32b of the source trench 32. That is, the source electrode 30 is embedded in the concave space partitioned by the barrier forming layer 33.
  • the source electrode 30 is, for example, a conductive layer containing conductive polysilicon.
  • the source electrode 30 may be n-type polysilicon to which n-type impurities are added, or p-type polysilicon to which p-type impurities are added.
  • the source electrode 30 may contain at least one of a metal such as titanium, nickel, copper, aluminum, silver, gold and tungsten, or a conductive metal nitride such as titanium nitride.
  • the source electrode 30 may be formed by using the same material as the gate electrode 20. In this case, the source electrode 30 and the gate electrode 20 can be formed in the same process.
  • the aspect ratio of the trench source structure 31 is defined by the ratio of the depth (length in the z-axis direction) of the trench source structure 31 to the width (length in the x-axis direction) of the trench source structure 31.
  • the width of the trench source structure 31 is, for example, the sum of the width of the source trench 32 and the width of the side wall portion 15a of the deep well region 15 located on both sides of the source trench 32.
  • the width of the trench source structure 31 is, for example, 0.6 ⁇ m or more and 2.4 ⁇ m or less.
  • the width of the trench source structure 31 may be about 0.8 ⁇ m.
  • the depth of the trench source structure 31 is the sum of the depth of the source trench 32 and the thickness of the bottom wall portion 15b of the deep well region 15.
  • the depth of the trench source structure 31 is, for example, 1.5 ⁇ m or more and 11 ⁇ m or less.
  • the depth of the trench source structure 31 may be about 2.5 ⁇ m.
  • the aspect ratio of the trench source structure 31 is larger than the aspect ratio of the trench gate structure 21.
  • the aspect ratio of the trench source structure 31 is 1.5 or more and 4.0 or less.
  • the drain electrode 40 corresponds to the second electrode layer 103.
  • the drain electrode 40 may contain at least one of titanium, nickel, copper, aluminum, gold or silver.
  • the drain electrode 40 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer that are laminated in order from the second main surface 101b of the semiconductor layer 101.
  • the drain electrode 40 may have a four-layer structure including a Ti layer, an AlCu layer, a Ni layer, and an Au layer, which are laminated in order from the second main surface 101b of the semiconductor layer 101.
  • the AlCu layer is an alloy layer of aluminum and copper.
  • the drain electrode 40 may have a four-layer structure including a Ti layer, an AlSiCu layer, a Ni layer, and an Au layer, which are laminated in order from the second main surface 101b of the semiconductor layer 101.
  • the AlSiCu layer is an alloy layer of aluminum, silicon and copper.
  • the drain electrode 40 may include a single-layer structure composed of a TiN layer or a laminated structure including a Ti layer and a TiN layer instead of the Ti layer.
  • the semiconductor device 100 configured as described above can switch between an on state in which the drain current flows and an off state in which the drain current does not flow, according to the gate voltage applied to the gate electrode 20 of the vertical transistor 2. ..
  • the gate voltage is, for example, a voltage of 10 V or more and 50 V or less. As an example, the gate voltage may be 30V.
  • the source voltage applied to the source electrode 30 is a reference voltage such as a ground voltage (0V).
  • the drain voltage applied to the drain electrode 40 is a voltage having a magnitude greater than or equal to the source voltage.
  • the drain voltage is, for example, a voltage having a magnitude of 0 V or more and 10000 V or less.
  • the drain voltage may be a voltage having a magnitude of 1000 V or more.
  • a gate voltage is applied to the gate electrode 20 , a channel is formed in a portion of the p- shaped body region 16 in contact with the gate insulating layer 23.
  • a current path is formed from the source electrode 30 through the contact region 18, the source region 17, the channel of the body region 16, the epitaxial layer 101d, and the semiconductor substrate 101c in this order to reach the drain electrode 40.
  • the drain electrode 40 Since the drain electrode 40 has a higher potential than the source electrode 30, the drain current passes from the drain electrode 40 through the semiconductor substrate 101c, the epitaxial layer 101d, the channel of the body region 16, the source region 17, and the contact region 18 in this order. It flows to the electrode 30. In this way, the drain current flows along the thickness direction of the semiconductor device 100.
  • a pn junction is formed between the p- type deep well region 15 and the n -type epitaxial layer 101d.
  • the source voltage is applied to the p- type deep well region 15 via the source electrode 30, and the n - type epitaxial layer 101d is applied to the n-type epitaxial layer 101d via the drain electrode 40 from the source voltage.
  • a large drain voltage is applied.
  • a reverse bias voltage is applied to the pn junction between the deep well region 15 and the epitaxial layer 101d. Since the n-type impurity concentration of the epitaxial layer 101d is lower than the p-type impurity concentration of the deep well region 15, the depletion layer spreads from the interface between the deep well region 15 and the epitaxial layer 101d toward the drain electrode 40. Thereby, the withstand voltage of the vertical transistor 2 can be increased.
  • the source electrode 30 is electrically connected to the first electrode layer 102s provided on the source electrode 30.
  • the gate electrode 20 is insulated from the first electrode layer 102s by the insulating layer 61, and is provided via a gate finger (for example, the gate finger 102a in FIG. 3) provided above the outer peripheral portion of the semiconductor layer 101. It is electrically connected to 102 g of the first electrode layer.
  • the insulating layer 61 contains, for example, silicon oxide or silicon nitride as a main component.
  • 5A to 5G are cross-sectional views showing a method of manufacturing the semiconductor device 100.
  • the semiconductor layer 101 is formed, and the first electrode layer 102 is formed on the first main surface 101a of the semiconductor layer 101.
  • various existing methods are used.
  • the first electrode layer 102 is formed by, for example, a sputtering method, a vapor deposition method, or the like.
  • the insulating film 104 is formed through, for example, a coating step and an exposure development step.
  • the coating step the liquid photosensitive resin material that is the source of the insulating film 104 is coated on the first electrode layer 102 by the spin coating method.
  • the exposure development step after the photosensitive resin material is cured by exposure, unnecessary portions of the photosensitive resin material are removed by an ashing method, a wet etching method, or the like. As a result, the insulating film 104 is formed.
  • the plating layer 105 is formed on the first electrode layer 102.
  • the plating layer 105 is formed on the first electrode layer 102 by, for example, an electrolytic plating method or an electroless plating method.
  • the plating layer 105 is selectively formed on at least a part of the portion of the first electrode layer 102 that is not covered with the insulating film 104.
  • the liquid resin material 106a (for example, a thermosetting resin) that is the source of the mold layer 106 is applied or printed on the entire surface of the semiconductor layer 101 on the first main surface 101a side.
  • the insulating film 104 and the plating layer 105 are covered with the resin material 106a.
  • the resin material 106a also penetrates between the plating layer 105 on the first electrode layer 102g and the plating layer 105 on the first electrode layer 102s.
  • the coated or printed resin material 106a is cured by heating, for example.
  • the upper surface (surface) of the resin material 106a is ground until the plating layer 105 is exposed.
  • the upper surface (surface) of the plating layer 105 and the upper surface (surface) of the mold layer 106 are flush with each other. That is, the upper surface (surface) of the plating layer 105 and the upper surface (surface) of the mold layer 106 are ground surfaces that are continuous with each other.
  • the second main surface 101b side (that is, the semiconductor substrate 101c) of the semiconductor layer 101 is ground, and the thickness of the semiconductor layer 101 is reduced.
  • the method of grinding the semiconductor layer 101 will be described later.
  • the second electrode layer 103 is formed on the second main surface 101b of the semiconductor layer 101.
  • the second electrode layer 103 is formed by, for example, a sputtering method, a vapor deposition method, or the like.
  • the wafer is fragmented by cutting the wafer along the scribe line SL with a dicing blade.
  • the dicing blade cuts the semiconductor layer 101 and the mold layer 106 at the same time.
  • the side surface of the semiconductor layer 101 and the side surface of the mold layer 106 are flush with each other. That is, the side surface of the semiconductor layer 101 and the side surface of the mold layer 106 are ground surfaces that are continuous with each other.
  • the semiconductor device 100 as shown in FIG. 2 is obtained.
  • the lower surface of the second electrode layer 103, the upper surface of the plating layer 105, the side surface of the plating layer 105, and the upper surface of the mold layer 106 constitute the outer surface of the semiconductor device 100 (chip).
  • FIG. 5F is a cross-sectional views showing a method of grinding the semiconductor substrate 101c.
  • the glass plate 150 is attached to the first main surface 101a side of the semiconductor layer 101.
  • a glass plate 150 having a protective tape 151 attached to the upper surface is prepared, and a plating layer 105 and a mold layer 106 of a work-in-process (wafer of a semiconductor device 100 in the process of being manufactured) are placed on the protective tape 151 side of the glass plate 150.
  • the top surface of the glass is glued.
  • the second main surface 101b side of the semiconductor layer 101 is ground in this state.
  • a diamond grindstone is used for grinding. Grinding is performed until the thickness of the semiconductor substrate 101c of the semiconductor layer 101 is 5 ⁇ m or more and 20 ⁇ m or less.
  • the protective tape 151 is irradiated with laser light. It is preferable that the laser beam is applied to the protective tape 151 from the first main surface 101a side via the glass plate 150. In this step, the work-in-process is turned upside down to irradiate the laser beam. As a result, the protective tape 151 is altered and the glass plate 150 is removed. After that, the protective tape 151 remaining on the wafer (semiconductor layer 101) is removed.
  • the semiconductor substrate 101c may warp after the glass plate 150 that is the support of the semiconductor substrate 101c is removed, or the semiconductor substrate 101c may become uncomfortable. There is a problem that it breaks. That is, there is a limit to the thinning of the semiconductor substrate 101c in a general semiconductor device. In particular, the SiC substrate is more likely to be cracked or chipped than the Si substrate.
  • the semiconductor substrate 101c may warp even after the glass plate 150 is removed, or the semiconductor substrate 101c may be disengaged. It is suppressed that it breaks. That is, according to the plating layer 105 and the mold layer 106, the thickness of the semiconductor substrate 101c can be made extremely thin. As described above, the thickness of the semiconductor substrate 101c is, for example, 5 ⁇ m or more and 20 ⁇ m or less, which is thinner than both the thickness t2 of the plating layer 105 and the thickness t3 of the mold layer 106. It is also possible to make the thickness of the semiconductor substrate 101c the same as or thinner than the thickness of the epitaxial layer 101d.
  • FIG. 7 shows the relationship between the thickness of the semiconductor substrate 101c (350 ⁇ m, 150 ⁇ m, 20 ⁇ m) and the on-resistance. It is a figure which shows. In FIG. 7, in addition to the resistance value of the semiconductor substrate 101c, the on-resistance of the epitaxial layer 101d is also shown.
  • the semiconductor layer 101 is a SiC semiconductor layer
  • the semiconductor device 100 can have a withstand voltage of 600 V to 1200 V. Since the semiconductor substrate 101c does not contribute to the withstand voltage, there is no problem in the device characteristics even if the semiconductor substrate 101c is made thin. From this point of view, there is no problem even if the thickness of the semiconductor substrate 101c is 5 ⁇ m or less, and the semiconductor substrate 101c may be completely removed. That is, the semiconductor layer 101 may have a single-layer structure composed of the epitaxial layer 101d.
  • the glass plate 150 was attached to the work-in-process.
  • the plating layer 105 and the mold layer 106 can also be used as a support for grinding instead of the glass plate 150.
  • a step of adhering the work-in-process to the glass plate 150 by using the plating layer 105 and the mold layer 106 as a support for grinding (FIG. 6A) and a step of removing the work-in-process from the glass plate 150 (FIG. 6C) are performed. It can be omitted. That is, the manufacturing process of the semiconductor device 100 can be simplified.
  • a wafer support system be used for grinding the semiconductor substrate 101c, and other existing methods may be used. Further, in the above example, an example of thinning by grinding the back surface of the SiC substrate has been described, but the present invention is not limited to this. For example, an unnecessary portion of the SiC substrate may be peeled off (specifically, cleavage) by irradiating a laser at a predetermined depth position of the SiC substrate. As a result, the SiC substrate, which is difficult to process, can be easily thinned.
  • FIG. 8 is a plan view of the semiconductor device according to the second embodiment.
  • FIG. 9 is a cross-sectional view of the semiconductor device shown in FIG. 8 (cross-sectional view taken along the line IX-IX of FIG. 8).
  • the semiconductor device 200 shown in FIG. 8 is a semiconductor chip that functions as a vertical Schottky barrier diode by utilizing the Schottky barrier generated by the bonding of the semiconductor layer 201 and the first electrode layer 202.
  • the semiconductor device 200 is, for example, a power semiconductor device used for supplying and controlling electric power.
  • the semiconductor device 200 includes a semiconductor layer 201, a first electrode layer 202, a second electrode layer 203, an insulating film 204, a plating layer 205, and a mold layer 206.
  • the semiconductor layer 201 is a SiC semiconductor layer containing a SiC (silicon carbide) single crystal as an example of a wide bandgap semiconductor.
  • the entire semiconductor layer 201 corresponds to a semiconductor substrate (for example, the semiconductor substrate 101c).
  • the conductive type of the semiconductor layer 201 is, for example, an n type.
  • the semiconductor layer 201 is formed in a rectangular plate shape in a plan view.
  • the length of one side of the semiconductor layer 201 is, for example, 1 mm or more and 10 mm or less, but may be 2 mm or more and 5 mm or less.
  • the semiconductor layer 201 has a first main surface 201a and a second main surface 201b that faces the first main surface 201a.
  • the thickness t4 of the semiconductor layer 201 is, for example, 5 ⁇ m or more and 40 ⁇ m or less, and more preferably 5 ⁇ m or more and 20 ⁇ m or less.
  • the semiconductor layer 201 is not limited to the SiC semiconductor layer, and may be a semiconductor layer made of another wide bandgap semiconductor such as GaN, or may be a Si semiconductor layer.
  • the semiconductor layer 201 may have a laminated structure including the above-mentioned semiconductor substrate 101c and the above-mentioned epitaxial layer 101d.
  • the first electrode layer 202 is formed on the first main surface 201a.
  • the first electrode layer 202 functions as an anode of the Schottky barrier diode.
  • the first electrode layer 202 is formed of, for example, aluminum.
  • the first electrode layer 202 may be formed of other materials such as titanium, nickel, copper, silver, gold, titanium nitride, and tungsten.
  • the second electrode layer 203 is formed on the second main surface 201b.
  • the second electrode layer 203 functions as a cathode of the Schottky barrier diode.
  • the second electrode layer 203 is formed of, for example, a laminated film of titanium, nickel, and gold.
  • the second electrode layer 203 may be formed of other materials such as aluminum, copper, silver, titanium nitride, and tungsten.
  • the insulating film 204 covers the entire circumference of the outer peripheral portion of the first electrode layer 202 (that is, both ends in the X-axis direction and both ends in the Y-axis direction).
  • the insulating film 204 includes a first portion 204a and a second portion 204b.
  • the first portion 204a rides on the first electrode layer 202. More specifically, the first portion 204a rides on the peripheral edge portion of the first electrode layer 202.
  • the second portion 204b is located outside the first portion 204a and covers a region other than the first electrode layer 202. That is, the second portion 204b does not ride on the first electrode layer 202.
  • the first portion 204a further includes an inner end portion 204a1 and a flat portion 204a2.
  • the inner end portion 204a1 is an end portion of a portion of the first portion 204a located on the inner side of the semiconductor layer 201 in a plan view.
  • the inner end portion 204a1 is obliquely inclined downward toward the inner portion of the first electrode layer 202 in a cross-sectional view.
  • the flat portion 104a2 is located on the outer side of the inner end portion 204a1 (peripheral side of the semiconductor layer 101) and has a substantially uniform thickness.
  • the insulating film 204 is, for example, an organic film containing a photosensitive resin.
  • the insulating film 204 is formed of, for example, polyimide, PBO (polybenzoxazole), or the like.
  • the insulating film 204 may be an inorganic film formed of silicon nitride, silicon oxide, or the like.
  • the insulating film 204 may have a single-layer structure or may have a laminated structure in which a plurality of types of materials are laminated.
  • the insulating film 204 may include both an organic film and an inorganic film.
  • the insulating film 204 preferably includes an inorganic film and an organic film laminated in this order from the first main surface 201a side.
  • the thickness of the insulating film 204 is about 10 ⁇ m at the maximum.
  • the plating layer 205 is a metal layer that covers at least a part of the first electrode layer 202.
  • the plating layer 205 covers at least a part of the first electrode layer 202 other than the end portion (that is, the portion covered with the insulating film 204).
  • the plating layer 205 is surrounded by the mold layer 206.
  • the plating layer 205 formed on the first electrode layer 202 functions as a pad having a rectangular shape in a plan view.
  • the pad is a portion to which the bonding wire is bonded when the semiconductor device 200 is packaged.
  • the plating layer 205 also functions as a support member for the mold layer 206.
  • the plating layer 205 is formed of, for example, a material different from that of the first electrode layer 202.
  • the plating layer 205 is formed of, for example, copper or a copper alloy containing copper as a main component.
  • the plating layer 205 may be formed of another metal material.
  • the thickness t5 of the plating layer 205 is larger than the thickness of the insulating film 204. More specifically, the thickness t5 of the plating layer 205 is larger than the maximum thickness of the insulating film 204 located on the first electrode layer 202. As a result, the top of the plating layer 205 is higher than the top of the insulating film 204.
  • the thickness t5 of the plating layer 205 is, for example, 30 ⁇ m or more and 100 ⁇ m or less.
  • the thickness t5 of the plating layer 205 may be 100 ⁇ m or more and 200 ⁇ m or less.
  • the side surface 205a of the plating layer 205 extends vertically or substantially vertically.
  • the side surface 205a does not necessarily have to extend linearly in a cross-sectional view and may include curves and irregularities.
  • the side surface 205a is located in a region where both the first electrode layer 202 and the insulating film 204 overlap each other. More specifically, the side surface 205a is located on the flat portion 204a2 of the insulating film 204. That is, the plating layer 205 covers the inner end portion 204a1 and the flat portion 204a2 of the first portion 204a. By locating the side surface 205a on the flat portion 204a2, the plating layer 205 can be formed more stably than in the case where the side surface 205a is positioned on the inner end portion 204a1 having a relatively large variation in thickness.
  • the mold layer 206 is a resin layer that covers a part of the insulating film 204. In this form, the mold layer 206 also covers a part of the first main surface 201a.
  • the mold layer 206 is located on the outer peripheral portion of the semiconductor layer 201 on the first main surface 201a side. In a plan view, the mold layer 206 is a rectangular ring along the outer peripheral portion of the semiconductor layer 201.
  • the inner surface of the mold layer 206 is in direct contact with the side surface 205a of the plating layer 205.
  • the mold layer 206 is formed only on the first main surface 201a of the semiconductor layer 201, and exposes the second main surface 201b and the side surface of the semiconductor layer 201.
  • the mold layer 206 is formed of, for example, a thermosetting resin (epoxy resin).
  • the mold layer 106 may be formed of an epoxy resin containing carbon, glass fiber and the like.
  • the thickness t6 of the mold layer 206 is, for example, 30 ⁇ m or more and 100 ⁇ m or less, but may be 100 ⁇ m or more and 200 ⁇ m or less.
  • the upper surface of the mold layer 206 and the upper surface of the plating layer 205 are flush with each other or substantially flush with each other.
  • FIG. 10 is a view showing a detailed configuration of the outer peripheral portion of the semiconductor device 200 (a cross-sectional view showing the details of the region X in FIG. 9).
  • the end of the first electrode layer 202 is covered with the insulating film 204.
  • the insulating film 204 is provided under the first insulating film 204c located on the first electrode layer 202, the second insulating film 204d located on the first insulating film 204c, and the first electrode layer 202.
  • the first insulating film 204c is an inorganic film formed of silicon nitride, silicon oxide, or the like.
  • the second insulating film 204d is an organic film formed of polyimide, PBO, or the like.
  • the third insulating film 204e is an inorganic film formed of silicon nitride, silicon oxide, or the like.
  • such an insulating film 204 is provided to suppress the invasion of moisture into the end of the first electrode layer 202 and the occurrence of ion migration.
  • a durability test in a high temperature and high humidity environment or a reliability test such as a temperature cycle test is performed, the insulating film 204 deteriorates, moisture invades from the deteriorated part, and ion migration occurs at the deteriorated part. May occur. That is, the deterioration of the insulating film 204 may cause a failure of the semiconductor device.
  • the insulating film 204 is further covered with the mold layer 206. As a result, deterioration of the insulating film 204 is suppressed, and the reliability of the semiconductor device 200 is improved. As shown in FIG. 10, the end end portion of the first electrode layer 202 is covered with the second insulating film 204d, and the first insulating film 204c is omitted. With such a configuration, the stress is relaxed. Since the manufacturing method of the semiconductor device 200 is the same as the manufacturing method of the semiconductor device 100, detailed description of the manufacturing method of the semiconductor device 200 is omitted. It can be said that the semiconductor device 200 is also a semiconductor device with reduced on-resistance.
  • FIG. 11 and 12 are diagrams showing an example of the semiconductor package according to the third embodiment.
  • FIG. 12 is a diagram showing the internal structure of the semiconductor package 300 shown in FIG. 11 when viewed from the side opposite to that of FIG.
  • the semiconductor package 300 is a so-called TO (Transistor Outline) type semiconductor package.
  • the semiconductor package 300 includes a package body 301, terminals 302d, terminals 302g, terminals 302s, bonding wires 303g, bonding wires 303s, and a semiconductor device 100.
  • the package body 301 has a rectangular parallelepiped shape, and terminals 302d, 302g, and 302s project from the bottom of the package body 301. Further, the package main body 301 incorporates the semiconductor device 100. In other words, the package body 301 is a sealing body that seals the semiconductor device 100.
  • the package body 301 is formed of, for example, an epoxy resin.
  • the package body 301 may be formed of an epoxy resin containing carbon, glass fiber and the like.
  • Each of the terminal 302d, the terminal 302g, and the terminal 302s protrudes from the bottom of the package body 301 and is arranged side by side in a row.
  • the terminal 302d, the terminal 302g, and the terminal 302s are each formed of, for example, aluminum.
  • the terminals 302d, 302g, and 302s may each be formed of another metal material such as copper.
  • the gate pad (plating layer 105 on the first electrode layer 102g) included in the semiconductor device 100 is electrically connected to the terminal 302g by the bonding wire 303g.
  • the source pad (plating layer 105 on the first electrode layer 102s) included in the semiconductor device 100 is electrically connected to the terminal 302s by the bonding wire 303s.
  • the drain electrode (second electrode layer 103) included in the semiconductor device 100 is bonded to a wide portion of the terminal 302d located in the package main body 301 by solder, a sintered layer made of silver or copper, or the like.
  • the semiconductor package 300 may include the semiconductor device 200 instead of the semiconductor device 100.
  • the semiconductor package 300 includes two terminals, and inside the package body 301, the anode (first electrode layer 202) included in the semiconductor device 200 is electrically connected to one of the two terminals by a bonding wire or the like.
  • the cathode (second electrode layer 203) is connected to the other of the two terminals, a wide portion located in the package body 401, by solder, a sintered layer made of silver or copper, or the like.
  • the semiconductor package 300 as described above has higher reliability than the case where the general semiconductor device is included. Further, the semiconductor package 300 has a reduced on-resistance as compared with the case where the semiconductor package 300 includes a general semiconductor device.
  • FIG. 13 is a diagram showing another example of the semiconductor package according to the third embodiment.
  • the semiconductor package 400 shown in FIG. 13 is a so-called DIP (Dual In-line Package) type semiconductor package.
  • the semiconductor package 400 includes a package body 401, a plurality of terminals 402, and a semiconductor device 100.
  • the package body 401 has a rectangular parallelepiped shape, and a plurality of terminals 402 project from the package body 401. Further, the package body 401 incorporates the semiconductor device 100. In other words, the package body 401 is a sealing body that seals the semiconductor device 100.
  • the package body 401 is formed of, for example, an epoxy resin containing carbon, glass fiber, and the like.
  • the plurality of terminals 402 are arranged side by side along the long side of the package body 401.
  • the plurality of terminals 402 are each formed of, for example, aluminum.
  • the plurality of terminals 402 may each be formed of another metal material such as copper.
  • the semiconductor package 400 may include a plurality of semiconductor devices 100. That is, the package main body 401 may include a plurality of semiconductor devices 100.
  • the semiconductor package 400 may include the semiconductor device 200 in place of the semiconductor device 100 or in addition to the semiconductor device 100.
  • each of the anode (first electrode layer 202) and the cathode (second electrode layer 203) included in the semiconductor device 200 is electrically connected to the corresponding terminal 402 by a bonding wire or the like. Connected to.
  • the semiconductor package 400 as described above has higher reliability than the case where the general semiconductor device is included. Further, the semiconductor package 400 has a reduced on-resistance as compared with the case where the semiconductor package 400 includes a general semiconductor device.
  • a bonding wire is used for electrical connection between the terminal included in the semiconductor package 300 or the semiconductor package 400 and the semiconductor device 100 (or the semiconductor device 200).
  • the bonding wire is a wire made of aluminum
  • FIG. 14 is a cross-sectional view of a semiconductor device 100 having a structure in which a nickel layer is formed on a plating layer 105.
  • the bonding wire 303g and the bonding wire 303s are also shown.
  • the nickel layer 107 is an example of a metal layer formed of a metal material different from the metal material forming the plating layer 105. Although not shown, a nickel layer may be formed on the plating layer 205 in the semiconductor device 200 as well.
  • the plating layer 105 may be composed of a first plating layer 1051 made of copper and a second plating layer 1052 made of nickel.
  • FIG. 15 is a cross-sectional view of the semiconductor device 100 including a plating layer having a two-layer structure. This eliminates the need to form an additional nickel layer as in the example of FIG. In the example of FIG. 15, the upper surface of the second plating layer 1052 and the upper surface of the mold layer are flush with each other.
  • a nickel layer is formed on the outermost surface of the plating layer 105, which is a bonding portion with the bonding wire made of aluminum, but the nickel layer is formed on the outermost surface of the plating layer 105.
  • the outermost surface of the plating layer 105 may have a two-layer structure (that is, a NiPd layer) in which a palladium layer is formed on a nickel layer.
  • the outermost surface of the plating layer 105 may have a three-layer structure (for example, a NiPdAu layer) in which another metal layer is formed on the palladium layer.
  • a NiPdAu layer for example, NiPdAu layer
  • Such NiPd layer and NiPdAu layer are not limited to the case where the bonding wire is bonded to the plating layer 105 which functions as the source pad, but also when the external terminals are bonded to the plating layer 105 which functions as the source pad by silver sintering. It is also suitable for.
  • the form of the semiconductor package including the semiconductor device 100 is not limited to the forms such as the semiconductor package 300 and the semiconductor package 400.
  • Semiconductor packages include SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-). leaded Package) may be adopted. Further, various semiconductor packages similar to these may be adopted as the semiconductor package.
  • the semiconductor device 100 includes a semiconductor layer 101, a first electrode layer 102, a second electrode layer 103, an insulating film 104, a plating layer 105, and a mold layer 106.
  • the semiconductor layer 101 has a first main surface 101a and a second main surface 101b that faces the first main surface 101a.
  • the first electrode layer 102 is formed on the first main surface 101a.
  • the second electrode layer 103 is formed on the second main surface 101b.
  • the insulating film 104 covers the end portion of the first electrode layer 102.
  • the plating layer 105 covers at least a part of the first electrode layer 102 other than the end portion.
  • the mold layer 106 covers the insulating film 104.
  • the semiconductor layer 101 includes the semiconductor substrate 101c constituting the second main surface 101b, and the thickness of the semiconductor substrate 101c is thinner than the thickness of the plating layer 105.
  • the semiconductor device 100 since the insulating film 104 covering the end portion of the first electrode layer 102 is further covered with the mold layer 106, deterioration of the insulating film 104 can be suppressed. That is, it can be said that the semiconductor device 100 is a semiconductor device with improved reliability. Further, in the semiconductor device 100, the on-resistance is reduced because the thickness of the semiconductor substrate 101c is thinner than the thickness of the plating layer 105.
  • the thickness of the semiconductor substrate 101c is 5 ⁇ m or more and 20 ⁇ m or less.
  • the on-resistance is significantly reduced.
  • the mold layer 106 is an annular shape along the outer peripheral portion of the semiconductor layer 101. The reliability of such a semiconductor device 100 is further improved by covering the outer peripheral portion of the semiconductor layer 101 with the mold layer 106.
  • the surface of the plating layer 105 and the surface of the mold layer 106 are flush with each other.
  • Such a semiconductor device 100 can be manufactured by applying or printing a resin material 106a on the first main surface 101a side of the semiconductor layer 101 and then grinding until the plating layer 105 is exposed.
  • the plating layer 105 and the mold layer 106 are in direct contact with each other.
  • the plating layer 105 can be used as a support for the mold layer 106.
  • the semiconductor layer 101 is formed of SiC.
  • Such a semiconductor device 100 can obtain a relatively high dielectric breakdown electric field strength.
  • the semiconductor device 100 may function as a transistor.
  • the semiconductor layer 101 may include the semiconductor substrate 101c and the epitaxial layer 101d on the semiconductor substrate 101c.
  • the second electrode layer 103 may be the drain electrode of the transistor.
  • the first electrode layer 102 may include the source electrode of the transistor and the gate electrode of the transistor. In the first electrode layer 102, the gate electrode is insulated from the source electrode.
  • Such a semiconductor device 100 can function as a transistor.
  • the semiconductor device 200 functions as a Schottky barrier diode having the first electrode layer 202 as an anode and the second electrode layer 203 as a cathode.
  • Such a semiconductor device 100 can function as a Schottky barrier diode.
  • the manufacturing method of the semiconductor device 100 includes the first to seventh steps.
  • a semiconductor layer 101 having a first main surface 101a and a second main surface 101b facing back to the first main surface 101a, including a semiconductor substrate 101c constituting the second main surface 101b.
  • Layer 101 is prepared.
  • the first electrode layer 102 is formed on the first main surface 101a of the semiconductor layer 101.
  • the insulating film 104 covering the end portion of the first electrode layer 102 is formed.
  • a plating layer 105 that covers at least a part of the first electrode layer 102 other than the end portion is formed.
  • the mold layer 106 covering the insulating film 104 is formed.
  • the semiconductor substrate 101c is ground from the second main surface side until the thickness of the semiconductor substrate 101c becomes thinner than the thickness of the plating layer 105.
  • the second electrode layer 103 is formed on the second main surface 101b of the semiconductor layer 101 after the semiconductor substrate 101c is ground.
  • the semiconductor device 100 with improved reliability can be manufactured. Further, in the semiconductor device 100, the on-resistance is reduced because the thickness of the semiconductor substrate 101c is thinner than the thickness of the plating layer 105.
  • FIG. 16 is a plan view of a semiconductor device according to a modification having such a structure.
  • the semiconductor device 100a includes a gate pad 105 g (a plating layer 105 that functions as a gate pad; the same applies hereinafter), a source pad 105s, a current sense pad 105c (pad electrode), and a current sense pad 105c (pad electrode). Includes a pair of temperature sensing pads 105t (pad electrodes).
  • the semiconductor device 100a includes a first electrode layer 102s having a plurality of separated portions separated from each other.
  • the current sense pad 105c is a plating layer connected to a portion (separated portion) of the first electrode layer 102s included in the semiconductor device 100a.
  • the semiconductor device 100a includes a diode (temperature sensitive diode) provided on the first main surface 101a of the semiconductor layer 101.
  • One of the pair of temperature sensing pads 105t is a plating layer electrically connected to the anode of the diode (temperature sensitive diode) included in the semiconductor device 100a.
  • the other of the pair of temperature sensing pads 105t is a plating layer that is electrically connected to the cathode of the diode (temperature sensitive diode).
  • the temperature of the semiconductor device 100a can be detected by the magnitude of the voltage between the pair of temperature sensing pads 105t.
  • the present invention can also be realized as a semiconductor device 100a including a current sense pad 105c and a pair of temperature sense pads 105t.
  • the present invention may be realized as a semiconductor device including at least one of a current sense pad 105c and a pair of temperature sense pads 105t.
  • 17A to 17C are cross-sectional views for explaining a dicing step according to a modified example having such a two-step dicing step.
  • the first dicing blade DB1 having the first width w1 cuts the entire mold layer 106 and a part of the semiconductor layer 101.
  • the entire semiconductor substrate 101c is covered by the second dicing blade DB2 having the same rotation axis as the first dicing blade DB1 and having a second width w2 smaller than the first width w1. Be disconnected.
  • the side surface of the mold layer 106 is located inside the side surface of the semiconductor layer 101, and the boundary portion between the mold layer 106 and the semiconductor layer 101 is located. It has a step in the vicinity.
  • Dicing may be performed by turning the wafer upside down. That is, dicing may be performed with the back surface (carbon surface) of the semiconductor substrate 101c on the upper side.
  • the rotation direction of the dicing blade is preferably the direction of cutting from the carbon surface toward the silicon surface.
  • 18A to 18C are cross-sectional views for explaining a dicing step according to another modification having such a two-step dicing step.
  • the entire semiconductor layer 101 and a part of the mold layer 106 are cut by the first dicing blade DB1 having the first width w1.
  • the entire mold layer 106 is formed by the second dicing blade DB2 having the same rotation axis as the first dicing blade DB1 and having a second width w2 smaller than the first width w1. Be disconnected.
  • the side surface of the semiconductor layer 101 is located inside the side surface of the mold layer 106c, and the boundary portion between the mold layer 106 and the semiconductor layer 101 is located. It has a step in the vicinity.
  • the two-step dicing step shown in FIGS. 17A to 17C and the two-step dicing step shown in FIGS. 18A to 18C are not only a semiconductor device that functions as a transistor but also a semiconductor device that functions as a Schottky barrier diode. It is also applicable to.
  • the present invention is not limited to the above embodiment.
  • all the numbers used in the description in the above-described embodiment are exemplified for concrete explanation of the present invention, and the present invention is not limited to the illustrated numbers.
  • each layer of the laminated structure included in the semiconductor device is within a range in which the same functions as those of the laminated structure of the above-described embodiment can be realized.
  • Other materials may be included.
  • the corners and sides of each component are shown linearly, but the present invention also includes those having rounded corners and sides due to manufacturing reasons and the like.
  • the present invention also includes a semiconductor device having a structure in which the conductive type described in the above embodiment is reversed.
  • the present invention is not limited to these embodiments. As long as it does not deviate from the gist of the present invention, a form in which various modifications that can be conceived by those skilled in the art are applied to the embodiment and a form constructed by combining components in different embodiments are also included in the scope of the present invention. Is done.
  • a power semiconductor device using a SiC substrate has been described, but the present invention can also be applied to a power semiconductor device (IGBT or MOSFET) using a Si substrate.
  • the present invention can be applied to semiconductor devices, semiconductor packages, etc. as industrial applicability.
  • [A1] to [A9] provide a semiconductor device having reduced on-resistance and a method for manufacturing the semiconductor device.
  • a semiconductor layer (101, 201) having a first main surface (101a, 201a) and a second main surface (101b, 201b) opposite to the first main surface (101a, 201a), and the above.
  • the first electrode layer (102, 102 g, 102s, 202) formed on the first main surface (101a, 201a) and the second electrode layer (103, 203) formed on the second main surface (101b, 201b).
  • the insulating film (104, 204) covering the end of the first electrode layer (102, 102 g, 102s, 202), and the end of the first electrode layer (102, 102 g, 102s, 202).
  • the semiconductor layer (101, 201) includes a plating layer (105, 205) covering at least a part of the above, and a mold layer (106, 206) covering the insulating film (104, 204).
  • the semiconductor device (100, 201) includes the semiconductor substrates (101c, 201) constituting the surfaces (101b, 201b), and the thickness of the semiconductor substrate (101c, 201) is thinner than the thickness of the plating layer (105, 205). 100a, 100b, 100c, 200).
  • A2 The semiconductor device (100, 100a, 100b, 100c, 200) according to A1, wherein the thickness of the semiconductor substrate (101c, 201) is 5 ⁇ m or more and 40 ⁇ m or less.
  • the semiconductor device (100, 100a, 100b, 100c, 200) functions as a transistor, and the semiconductor layer (101, 201) is the semiconductor substrate (101c, 201) and the semiconductor substrate (101c, 201).
  • the second electrode layer (103, 203) is the drain electrode (40) of the transistor, and the first electrode layer (102, 102 g, 102s, 202) includes the epitaxial layer (101d).
  • the semiconductor device (100) according to any one of A1 to A6, which includes a source electrode (102s) of the transistor and a gate electrode (102g) of the transistor insulated from the source electrode (102s). , 100a, 100b, 100c, 200).
  • the first electrode layer (102, 102g, 102s, 202) is used as an anode and the second electrode layer (103, 203) is used as a cathode.
  • the semiconductor device (100, 100a, 100b, 100c, 200) according to any one of A1 to A7, which functions as a Schottky barrier diode.
  • the first electrode layer (102, 102 g, 102s, 202) is formed, an insulating film (104, 204) covering the end of the first electrode layer (102, 102g, 102s, 202) is formed, and the first electrode layer (102, 102g, 102s, 102s, A plating layer (105, 205) covering at least a part other than the end portion of 202) is formed, a mold layer (106, 206) covering the insulating film (104, 204) is formed, and the semiconductor substrate (101c) is formed.
  • the following [B1] to [B22] provide semiconductor devices capable of improving mechanical strength.
  • the following structures [B1] to [B22] are also effective in reducing the on-resistance.
  • a semiconductor layer (101, 201) including a semiconductor substrate (101c, 201) having a first thickness and having a main surface (101a, 201a) is arranged on the main surface (101a, 201a).
  • the first surface electrode (102, 102 g, 102 s, 202) having a second thickness less than the first thickness, and the first surface electrode (102, 102 g, 102 s, 202) arranged on the main surface electrode (102, 102 g, 102 s, 202).
  • Semiconductor devices (100, 100a, 100b, 100c, 200).
  • the pad electrode (105, 105c, 105g, 105s, 105t, 205) has an electrode surface
  • the resin (106, 206) has the pad electrode (105, 105c, 105g, 105s, 105t, 105t, 205)
  • the semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B2 to B7, which has an outer surface connected to the electrode surface.
  • the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205) is made of a ground surface, and the outer surface of the resin (106, 206) is made of a ground surface.
  • Semiconductor devices (100, 100a, 100b, 100c, 200).
  • the resin (106, 206) covers the insulating film (104, 204), according to any one of B2 to B9. 200).
  • the resin (106, 206) partially exposes the insulating film (104, 204) on the inner side of the main surface electrodes (102, 102 g, 102s, 202), and the pad electrode (102, 102 g, 102s, 202).
  • the 105, 105c, 105g, 105s, 105t, 205) are the main surface electrodes (102, 102g, 102s, 202) and the insulating film on the inner side of the main surface electrodes (102, 102g, 102s, 202). (104, 204) and the semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B10 to B13, which is in contact with the resin (106, 206).
  • the semiconductor layer (101, 201) includes an epitaxial layer (101d) laminated on the semiconductor substrate (101c, 201), and the pad electrodes (105, 105c, 105g, 105s, 105t, 205t, 205). ) Is the semiconductor device (100) according to any one of B1 to B14, which has the third thickness exceeding the total thickness of the semiconductor substrate (101c, 201) and the epitaxial layer (101d). , 100a, 100b, 100c, 200).
  • a fourth thickness that exceeds the third thickness by covering the peripheral edge of the main surface electrode (102, 102 g, 102s, 202) with the photosensitive resin layer (104, 204) sandwiched so as to expose the inner portion.
  • thermosetting resin layer (106, 206) partially exposes the photosensitive resin layer (104, 204) on the inner side of the main surface electrodes (102, 102 g, 102s, 202).
  • the pad electrodes (105, 105c, 105g, 105s, 105t, 205) are formed on the inner side of the main surface electrodes (102, 102g, 102s, 202).
  • the semiconductor device (100, 100a, 100b, 100c, 200) according to any one of B17 to B20, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) is made of a plating film. ..
  • the following [C1] to [C18] provide semiconductor devices capable of improving mechanical strength.
  • the following structures [C1] to [C18] are also effective in reducing the on-resistance.
  • a semiconductor layer (101, 201) including a semiconductor substrate (101c, 201) having a first thickness and having a main surface (101a, 201a) is arranged on the main surface (101a, 201a).
  • a semiconductor device (100, 100a) comprising a resin (106, 206) having a third thickness exceeding the first thickness, which covers the peripheral edge of the main surface electrode (102, 102 g, 102s, 202). , 100b, 100c, 200).
  • C5 Any of C1 to C4 further comprising pad electrodes (105, 105c, 105g, 105s, 105t, 205) arranged on the inner portion of the main surface electrodes (102, 102g, 102s, 202).
  • One of the semiconductor devices (100, 100a, 100b, 100c, 200).
  • the pad electrode (105, 105c, 105g, 105s, 105t, 205) has a fourth thickness exceeding the first thickness of the semiconductor substrate (101c, 201), C5 or C6. (100, 100a, 100b, 100c, 200).
  • the pad electrode (105, 105c, 105g, 105s, 105t, 205) has an electrode surface
  • the resin (106, 206) has the pad electrode (105, 105c, 105g, 105s, 105t, 105t, 205)
  • the semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C5 to C7, which has an outer surface connected to the electrode surface.
  • the electrode surface of the pad electrode (105, 105c, 105g, 105s, 105t, 205) is made of a ground surface, and the outer surface of the resin (106, 206) is made of a ground surface.
  • Semiconductor devices (100, 100a, 100b, 100c, 200).
  • the semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C5 to C9, wherein the pad electrode (105, 105c, 105g, 105s, 105t, 205) is made of a plating film. ..
  • the resin (106, 206) partially exposes the insulating film (104, 204) on the inner side of the main surface electrodes (102, 102 g, 102s, 202), C11 to The semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C14.
  • the semiconductor layer (101, 201) includes an epitaxial layer (101d) laminated on the semiconductor substrate (101c, 201), and the resin (106, 206) is the semiconductor substrate (101c, 101c, 201) and the semiconductor device (100, 100a, 100b, 100c, 200) according to any one of C1 to C15, which has the third thickness exceeding the total thickness of the epitaxial layer (101d). ..
  • the following [D1] to [D6] provide semiconductor devices capable of improving mechanical strength.
  • the following structures [D1] to [D6] are also effective in reducing the on-resistance.
  • a semiconductor device (100, 100a, 100b, 100c, 200) comprising a resin (106, 206) that partially covers 102s, 202) and has a third thickness that exceeds the first thickness.
  • [D4] The semiconductor device according to any one of D1 to D3, wherein the semiconductor layer (101, 201) has a laminated structure including a semiconductor substrate (101c, 201) and an epitaxial layer (101d). 100, 100a, 100b, 100c, 200).

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  • Electrodes Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
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US17/801,798 US12476162B2 (en) 2020-05-08 2021-04-30 Semiconductor device
JP2022519955A JP7656593B2 (ja) 2020-05-08 2021-04-30 半導体装置
CN202180032864.XA CN115516644A (zh) 2020-05-08 2021-04-30 半导体装置
DE212021000199.8U DE212021000199U1 (de) 2020-05-08 2021-04-30 Halbleiterbauteil
JP2025048467A JP2025085827A (ja) 2020-05-08 2025-03-24 半導体装置
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WO2024258445A1 (en) * 2023-06-14 2024-12-19 Microchip Technology Incorporated Electronic devices with substrates less than 50 micrometer thick and methods of manufacture

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JP2025085827A (ja) 2025-06-05
DE212021000199U1 (de) 2022-02-07
US12476162B2 (en) 2025-11-18
US20230082976A1 (en) 2023-03-16
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CN115516644A (zh) 2022-12-23
US20260047478A1 (en) 2026-02-12

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