CN115516644A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN115516644A CN115516644A CN202180032864.XA CN202180032864A CN115516644A CN 115516644 A CN115516644 A CN 115516644A CN 202180032864 A CN202180032864 A CN 202180032864A CN 115516644 A CN115516644 A CN 115516644A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
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- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
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- H10P54/00—Cutting or separating of wafers, substrates or parts of devices
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
- H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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- H—ELECTRICITY
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7416—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
- H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
- H10W72/07552—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in structures or sizes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/521—Structures or relative sizes of bond wires
- H10W72/527—Multiple bond wires having different sizes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/926—Multiple bond pads having different sizes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Electrodes Of Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Composite Materials (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020-082730 | 2020-05-08 | ||
| JP2020082730 | 2020-05-08 | ||
| PCT/JP2021/017272 WO2021225125A1 (ja) | 2020-05-08 | 2021-04-30 | 半導体装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115516644A true CN115516644A (zh) | 2022-12-23 |
Family
ID=78467970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180032864.XA Pending CN115516644A (zh) | 2020-05-08 | 2021-04-30 | 半导体装置 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US12476162B2 (https=) |
| JP (2) | JP7656593B2 (https=) |
| CN (1) | CN115516644A (https=) |
| DE (2) | DE212021000199U1 (https=) |
| WO (1) | WO2021225125A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115516643A (zh) * | 2020-05-08 | 2022-12-23 | 罗姆股份有限公司 | 半导体装置 |
| WO2024258445A1 (en) * | 2023-06-14 | 2024-12-19 | Microchip Technology Incorporated | Electronic devices with substrates less than 50 micrometer thick and methods of manufacture |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665996A (en) * | 1994-12-30 | 1997-09-09 | Siliconix Incorporated | Vertical power mosfet having thick metal layer to reduce distributed resistance |
| JPH10270370A (ja) * | 1997-03-26 | 1998-10-09 | Sharp Corp | 不純物の拡散方法ならびに半導体装置およびその製造方法 |
| JP4241284B2 (ja) * | 2003-09-19 | 2009-03-18 | カシオ計算機株式会社 | 半導体装置 |
| JP5339800B2 (ja) * | 2008-07-10 | 2013-11-13 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US8188482B2 (en) * | 2008-12-22 | 2012-05-29 | Infineon Technologies Austria Ag | SiC semiconductor device with self-aligned contacts, integrated circuit and manufacturing method |
| JP2010225648A (ja) * | 2009-03-19 | 2010-10-07 | Casio Computer Co Ltd | 半導体装置およびその製造方法 |
| JP5253455B2 (ja) | 2010-06-01 | 2013-07-31 | 三菱電機株式会社 | パワー半導体装置 |
| US9029200B2 (en) | 2010-07-15 | 2015-05-12 | Infineon Technologies Austria Ag | Method for manufacturing semiconductor devices having a metallisation layer |
| JP5547022B2 (ja) | 2010-10-01 | 2014-07-09 | トヨタ自動車株式会社 | 半導体装置 |
| JP5995518B2 (ja) * | 2012-05-11 | 2016-09-21 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
| JP2015222743A (ja) * | 2014-05-22 | 2015-12-10 | 三菱電機株式会社 | 半導体装置 |
| JP6233236B2 (ja) * | 2014-08-08 | 2017-11-22 | 三菱電機株式会社 | 半導体装置の製造方法 |
| CN115274855B (zh) | 2017-02-24 | 2025-10-28 | 三菱电机株式会社 | 碳化硅半导体装置以及电力变换装置 |
| JP6846687B2 (ja) * | 2017-09-12 | 2021-03-24 | パナソニックIpマネジメント株式会社 | 半導体装置およびその製造方法 |
| US11538728B2 (en) | 2017-12-20 | 2022-12-27 | Mitsubishi Electric Corporation | Semiconductor package comprising a heat dissipation structure and an outer peripheral frame used as a resin flow barrier |
| CN112189251B (zh) * | 2018-05-28 | 2023-12-26 | 三菱电机株式会社 | 半导体装置的制造方法 |
| JP7135445B2 (ja) * | 2018-05-29 | 2022-09-13 | 富士電機株式会社 | 半導体装置 |
-
2021
- 2021-04-30 DE DE212021000199.8U patent/DE212021000199U1/de active Active
- 2021-04-30 CN CN202180032864.XA patent/CN115516644A/zh active Pending
- 2021-04-30 JP JP2022519955A patent/JP7656593B2/ja active Active
- 2021-04-30 DE DE112021000398.4T patent/DE112021000398B4/de active Active
- 2021-04-30 WO PCT/JP2021/017272 patent/WO2021225125A1/ja not_active Ceased
- 2021-04-30 US US17/801,798 patent/US12476162B2/en active Active
-
2025
- 2025-03-24 JP JP2025048467A patent/JP2025085827A/ja active Pending
- 2025-10-21 US US19/363,687 patent/US20260047478A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021225125A1 (ja) | 2021-11-11 |
| JPWO2021225125A1 (https=) | 2021-11-11 |
| DE212021000199U8 (de) | 2022-03-31 |
| DE112021000398B4 (de) | 2024-09-26 |
| JP7656593B2 (ja) | 2025-04-03 |
| JP2025085827A (ja) | 2025-06-05 |
| DE212021000199U1 (de) | 2022-02-07 |
| US12476162B2 (en) | 2025-11-18 |
| US20230082976A1 (en) | 2023-03-16 |
| DE112021000398T5 (de) | 2022-10-13 |
| US20260047478A1 (en) | 2026-02-12 |
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