WO2021217800A1 - 一种显示面板 - Google Patents

一种显示面板 Download PDF

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Publication number
WO2021217800A1
WO2021217800A1 PCT/CN2020/095780 CN2020095780W WO2021217800A1 WO 2021217800 A1 WO2021217800 A1 WO 2021217800A1 CN 2020095780 W CN2020095780 W CN 2020095780W WO 2021217800 A1 WO2021217800 A1 WO 2021217800A1
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WIPO (PCT)
Prior art keywords
layer
display panel
thin film
phase retardation
phase
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Application number
PCT/CN2020/095780
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English (en)
French (fr)
Inventor
杨汉宁
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/979,883 priority Critical patent/US11963393B2/en
Priority to JP2021529023A priority patent/JP2022534459A/ja
Priority to EP20917292.3A priority patent/EP4145524A4/en
Priority to KR1020217005320A priority patent/KR20210134887A/ko
Publication of WO2021217800A1 publication Critical patent/WO2021217800A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B5/00—Optical elements other than lenses
    • G02B5/30—Polarising elements
    • G02B5/3016—Polarising elements involving passive liquid crystal elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H10K50/8445—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/85—Arrangements for extracting light from the devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K59/8792—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. black layers
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B5/00—Optical elements other than lenses
    • G02B5/30—Polarising elements
    • G02B5/3083—Birefringent or phase retarding elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/868—Arrangements for polarized light emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • This application relates to the field of display technology, and in particular to a display panel.
  • the thickness of the screen to realize the folding of the screen has become the development trend of the mobile phone screen in the future.
  • its polarizer is composed of a ⁇ /4 phase retardation film and a linear polarizer, which can effectively eliminate the reflected light generated by external light irradiating the surface of the display screen.
  • the thickness of the traditional polarizer is generally in the range of 100 microns, which limits the thickness of the screen and reduces the bending performance of the screen.
  • the present application provides a display panel, which can solve the problem that the thickness of the entire panel is limited due to the provision of a polarizer in the traditional display panel, and at the same time, the bending performance of the panel is reduced.
  • This application provides a display panel, including:
  • the thin film transistor array layer is arranged on the substrate;
  • the light emitting device layer is arranged on the thin film transistor array layer
  • a thin-film encapsulation layer disposed on the light-emitting device layer
  • the phase retardation layer is arranged in the thin film encapsulation layer
  • the linear offset layer is arranged in the thin film encapsulation layer.
  • the thin film encapsulation layer includes an inorganic layer and an organic layer that are stacked, and the phase retardation layer and the linear offset layer are located between the adjacent inorganic layer and the organic layer; Alternatively, the inorganic layer and/or the organic layer are provided between the phase retardation layer and the linear offset layer.
  • the linear offset layer is located on a side of the phase retardation layer away from the light emitting device layer.
  • the light-emitting device layer includes array-distributed light-emitting devices
  • the phase retardation layer includes phase-lag units corresponding to the light-emitting devices and arranged in an array
  • the display panel is configured to correspond to two adjacent phases.
  • a black retaining wall is set at the gap of the hysteresis unit.
  • the thin film transistor array layer includes an inorganic stacked layer and a thin film transistor
  • the display panel is further provided with an organic stacked layer on the inorganic stacked layer
  • the black barrier is located on the organic stacked layer.
  • the thin film encapsulation layer On or in the thin film encapsulation layer.
  • the linearly biased layer includes linearly biased units corresponding to the array of the phase lag unit, and the orthographic projection of the linearly biased unit on the substrate covers the phase lag unit on the substrate. Orthographic projection on the substrate.
  • the phase lag unit covers the light-emitting area of the light-emitting device layer.
  • the phase retardation layer is an anisotropic organic material.
  • the phase retardation layer is a liquid crystal material, and the surface of the phase retardation layer is provided with an alignment layer.
  • the phase difference of the phase retardation layer is a quarter wavelength.
  • the present application also provides a display panel, including:
  • the thin film transistor array layer is arranged on the substrate;
  • the light emitting device layer is arranged on the thin film transistor array layer
  • a thin-film encapsulation layer disposed on the light-emitting device layer
  • the phase retardation layer is arranged in the thin film encapsulation layer
  • the linear offset layer is arranged in the thin film encapsulation layer, and the phase retardation layer and the linear offset layer are laminated and arranged.
  • the thin film encapsulation layer includes an inorganic layer and an organic layer that are stacked, and the phase retardation layer and the linear offset layer are located between the adjacent inorganic layer and the organic layer; Alternatively, the inorganic layer and/or the organic layer are provided between the phase retardation layer and the linear offset layer.
  • the linear offset layer is located on a side of the phase retardation layer away from the light emitting device layer.
  • the light-emitting device layer includes array-distributed light-emitting devices
  • the phase retardation layer includes phase-lag units corresponding to the light-emitting devices and arranged in an array
  • the display panel is configured to correspond to two adjacent phases.
  • a black retaining wall is set at the gap of the hysteresis unit.
  • the thin film transistor array layer includes an inorganic stacked layer and a thin film transistor
  • the display panel is further provided with an organic stacked layer on the inorganic stacked layer
  • the black barrier is located on the organic stacked layer.
  • the thin film encapsulation layer On or in the thin film encapsulation layer.
  • the linearly biased layer includes linearly biased units corresponding to the array of the phase lag unit, and the orthographic projection of the linearly biased unit on the substrate covers the phase lag unit on the substrate. Orthographic projection on the substrate.
  • the phase lag unit covers the light-emitting area of the light-emitting device layer.
  • the phase retardation layer is an anisotropic organic material.
  • the phase retardation layer is a liquid crystal material, and the surface of the phase retardation layer is provided with an alignment layer.
  • the phase difference of the phase retardation layer is a quarter wavelength.
  • the display panel provided by the present application removes the traditional polarizer, and arranges the phase retardation layer and the linear polarization layer in the film encapsulation layer.
  • the display panel is greatly improved.
  • the thickness is reduced and the bending performance of the display panel is increased.
  • the combination of the phase retardation layer and the linear polarization layer can effectively eliminate the reflected light generated by external light irradiating the surface of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided in Embodiment 1 of the application;
  • FIG. 2 is a schematic diagram of the structure of a display panel provided in the second embodiment of the application.
  • FIG. 3 is a schematic structural diagram of a display panel provided in Embodiment 3 of the application.
  • FIG. 4 is a schematic structural diagram of a display panel provided in the fourth embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features.
  • “multiple” means two or more than two, unless otherwise specifically defined. In this application, “/” means “or”.
  • the present application provides a display panel, which includes: a substrate 10, the substrate 10 can be a flexible substrate, but not limited to this; a thin film transistor array layer 20, provided On the substrate 10; a light emitting device layer 40, which is disposed on the thin film transistor array layer 20; a thin film encapsulation layer 50, which is disposed on the light emitting device layer 40; and a phase retardation layer 60, which is disposed on the film In the encapsulation layer 50; the linear offset layer 70 is disposed in the thin film encapsulation layer 50, and the phase retardation layer 60 and the linear offset layer 70 are laminated.
  • the current OLED display panel structure often uses an external polarizer, which is usually a composite film composed of multiple organic material layers, including a ⁇ /4 phase retardation film and a linear polarizer.
  • the two birefringent layers can achieve the screen’s resistance to Reflection function.
  • the ⁇ /4 phase retardation film and the linear polarizer need to be protected and connected by a multi-layer film, which in turn leads to a larger thickness of the polarizer.
  • the thickness of the traditional polarizer is generally in the range of 100 ⁇ m, which limits the thickness of the screen and reduces the bending performance of the screen.
  • the display panel of the present application removes the traditional polarizer structure, and only arranges the phase retardation layer and the linear polarization layer in the film encapsulation layer.
  • the combination of the phase retardation layer and the linear polarization layer can effectively eliminate the external light irradiating the surface of the display panel. Reflected light.
  • the thickness is greatly reduced, thereby increasing the bending performance of the display panel, which is beneficial to the development of the foldable display panel.
  • FIG. 1 is a schematic diagram of the structure of the display panel provided in the first embodiment of this application.
  • a thin film transistor array layer 20 is provided on the substrate 10, and the thin film transistor array layer 20 includes an inorganic stacked layer and a thin film transistor 204.
  • the inorganic stacked layer includes, but is not limited to, a first gate insulating layer 201, a second gate insulating layer 202, and an interlayer insulating layer 203 that are stacked.
  • the thin film transistor 204 includes an active layer 2041, a gate 2042, and a source/drain 2043.
  • An electrode layer 205 is provided on the gate 2042 to be insulated, and the electrode layer 205 and the gate 2042 form a capacitor.
  • the organic stacked layer 30 and a light-emitting device layer 40 are further provided on the inorganic stacked layer.
  • the organic stacked layer 30 includes, but is not limited to, a planarization layer 301 and a pixel definition layer 302 that are stacked.
  • the light-emitting device layer 40 includes an anode 401, a light-emitting layer 402, and a cathode 403 that are stacked.
  • the anode 401 is disposed on the planarization layer 301 and is electrically connected to the source/drain 2043 of the thin film transistor 204 through the via hole on the planarization layer 301.
  • the pixel defining layer 302 forms a pixel hole at a position corresponding to the anode 401, the light-emitting layer 402 is located in the pixel hole, and the cathode 403 is disposed on the light-emitting layer 402.
  • the thin film encapsulation layer 50 is disposed on the cathode 403, and the thin film encapsulation layer 50 at least includes a three-layer laminated inorganic layer 501, an organic layer 502 and an inorganic layer 501.
  • the thickness of the inorganic layer 501 is usually in the range of several hundred nanometers, and the thickness of the organic layer 502 is usually below 20 microns. effect.
  • the present application is to reduce the thickness of the entire display module, and integrate the external polarizer into the thin film encapsulation layer 50 of the display panel.
  • the thin film encapsulation layer 50 includes a phase retardation layer 60 and a linear offset layer 70, and the linear offset layer 70 is located on a side of the phase retardation layer 60 away from the light emitting device layer 40.
  • the phase retardation layer 60 and the linear offset layer 70 are disposed in the thin film encapsulation layer 50 over the entire surface.
  • the inorganic layer 501 and/or the organic layer 502 are provided between the phase retardation layer 60 and the linear offset layer 70.
  • the phase retardation layer 60 and the linear offset layer 70 are located between the adjacent inorganic layer 501 and the organic layer 502.
  • the phase retardation layer 60 is located on the first inorganic layer 501, an organic layer 502 is provided on the phase retardation layer 60, and the linearly biased layer 70 is provided on the organic layer 502.
  • a second inorganic layer 501 is provided on the linear offset layer 70.
  • the phase difference of the phase retardation layer 60 is a quarter wavelength, and the phase retardation layer 60 may be a quarter wave plate.
  • the linearly polarized light passes through the corresponding
  • the phase retardation layer 60 is then converted into circularly polarized light, which is reflected by the cathode 403 and anode 401 and then increases the phase of ⁇ (for example, from left-handed circularly polarized light to right-handed circularly polarized light, or from right-handed circularly polarized light to left-handed circularly polarized light)
  • the circularly polarized light with phase retardation passes through the phase retardation layer 60 again and then becomes linearly polarized light perpendicular to the incident ray polarization (for example, linearly polarized light in the vertical direction), so that it cannot pass through the linearly polarized layer 70 to achieve extinction.
  • the 1/4 wave plate layer of the traditional polarizer is mainly obtained by stretching a polymer material, in order to achieve a specific phase lag coefficient, a thickness of several tens of micrometers is usually required.
  • the phase retardation layer 60 can be a liquid crystal material or other anisotropic organic materials, and the thickness of the phase retardation layer 60 is in the range of one to several micrometers. Thus, the thickness is greatly reduced, and the bending performance of the display panel is increased.
  • FIG. 2 it is a schematic diagram of the structure of the display panel provided in the second embodiment of this application.
  • the display panel of this embodiment is the same as/similar to the display panel of the first embodiment. The difference is that: the light-emitting device layer 40 of this embodiment includes array-distributed light-emitting devices, that is, pixel points, and the phase retardation layer includes corresponding light-emitting devices.
  • the phase lag units 601 are arranged in an array.
  • the display panel is provided with a black retaining wall 80 at the gap between two adjacent phase lag units 601.
  • the black retaining wall 80 is a light-absorbing material, which can effectively absorb the phase Light is incident from the outside of the area outside the hysteresis unit 601. Therefore, the reflected light generated by the external light irradiating the surface of the display panel can be further eliminated.
  • the black barrier wall 80 is located on the organic stack layer 30 or in the thin film encapsulation layer 50, and the height of the black barrier wall 80 is in the range of several micrometers to more than ten micrometers.
  • the black retaining wall 80 is located on the pixel definition layer 302 and can be arranged around the pixel hole. Due to the arrangement of the black barrier wall 80, the cathode 403 and the inorganic layer 501 located on the black barrier wall 80 will form a recess at the position corresponding to the pixel hole, and the phase delay unit 601 is correspondingly located in the recess.
  • the phase delay unit 601 covers the light emitting area of the light emitting device layer 40, that is, the orthographic projection of the phase delay unit 601 on the substrate 10 covers the light emitting layer 402 on the substrate 10. Orthographic projection.
  • the phase lag unit 601 may extend to the periphery of the pixel hole.
  • the black barrier wall 80 may be located on the inorganic layer 501 or the organic layer 502 of the thin film encapsulation layer 50, and the external incident light incident on the area outside the phase delay unit 601 may be blocked by the black color. Wall 80 absorbs.
  • the black retaining wall 80 and the phase lag unit 601 may be located on the same layer, and the adjacent phase lag units 601 are separated by the black retaining wall 80.
  • the anti-reflection (extinction) principle of the phase lag unit 601 and the linear polarization layer 70 of this embodiment is the same as the anti-reflection principle of the first embodiment, and will not be repeated here.
  • FIG. 3 it is a schematic diagram of the structure of the display panel provided in the third embodiment of this application.
  • the display panel of this embodiment is the same as/similar to the display panel of the above-mentioned second embodiment.
  • the linear deflection layer of this embodiment includes linear deflection units 701 arranged in an array corresponding to the phase lag units 601, and the linear deflection units
  • the orthographic projection of 701 on the substrate 10 covers the orthographic projection of the phase delay unit 601 on the substrate 10.
  • the beneficial effects of this embodiment are the same as those of the second embodiment, and the anti-reflection (extinction) principle of the phase lag unit 601 and the linear polarization unit 701 of this embodiment is the same as the anti-reflection principle of the first embodiment. I won't repeat them here.
  • FIG. 4 it is a schematic diagram of the structure of the display panel provided in the fourth embodiment of this application.
  • the display panel of this embodiment is the same as/similar to the display panel of the third embodiment above.
  • the difference is that the phase lag unit 601 and the linear offset unit 701 of this embodiment are located between the adjacent inorganic layer 501 and the organic layer 502.
  • the phase retardation layer (phase retardation unit 601) is made of liquid crystal material, and the surface of the phase retardation layer is provided with an alignment layer 90.
  • the alignment layer 90 may be located on the side of the phase lag unit 601 away from the linear offset unit 701, or may be located on the side of the phase lag unit 601 facing the linear offset unit 701; or, The alignment layer 90 is provided on both surfaces of the phase lag unit 601.
  • the size of the alignment layer 90 can be adapted to the size of the phase retardation layer, and can be arranged in an entire layer or distributed in an array.
  • the phase lag unit 601 and the linear offset unit 701 can also be located on different layers of the thin film encapsulation layer.
  • the alignment layer 90 is used to align the liquid crystal material, so that the liquid crystal material generates a suitable phase difference, such as a quarter-wavelength phase difference.
  • a suitable phase difference such as a quarter-wavelength phase difference.
  • the liquid crystal material can be aligned according to actual needs.
  • this embodiment can cause the phase lag unit 601 to generate different phase differences by setting the alignment layer 90, and can flexibly eliminate the reflected light according to the actual situation.
  • the anti-reflection (extinction) principle of the phase lag unit 601 and the linear deflection unit 701 of this embodiment is the same as the anti-reflection principle of the first embodiment, and will not be repeated here.
  • the display panel provided by the present application removes the traditional polarizer and arranges the phase retardation layer and the linear polarization layer in the film encapsulation layer. Compared with the traditional display panel attached with the polarizer, the thickness is greatly reduced and the display is increased. The bending performance of the panel. At the same time, the combination of the phase retardation layer and the linear polarization layer can effectively eliminate the reflected light caused by external light irradiating the surface of the display panel. In addition, the black barrier wall with light absorption function can further eliminate the external light irradiating the surface of the display panel. reflected light.

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  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Inorganic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Electroluminescent Light Sources (AREA)
  • Polarising Elements (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请提供一种显示面板，包括：衬底；薄膜晶体管阵列层，设置于衬底上；发光器件层，设置于薄膜晶体管阵列层上；薄膜封装层，设置于发光器件层上；以及相位迟滞层，设置于薄膜封装层内；线偏层，设置于薄膜封装层内。本申请通过去除了传统的偏光片，从而解决传统的显示面板因设置偏光片而限制了面板整体的厚度，同时降低了面板弯折性能的问题。

Description

一种显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板。
 背景技术
随着科技发展以及人们对产品要求的提高，柔性显示屏成为日受关注的领域。目前，降低屏幕的厚度进而实现屏幕的可折叠已经成为未来手机屏幕的发展趋势。对于现行的OLED显示屏，其偏光片是由λ/4相位迟滞片和线偏振片构成，其可有效地消除外部光照射到显示屏表面产生的反射光。而传统的偏光片的厚度普遍在100微米的范围内，进而限制了屏幕的厚度，降低了屏幕的弯折性能。
因此，现有技术存在缺陷，急需解决。
 技术问题
本申请提供一种显示面板，能够解决传统的显示面板因设置偏光片而限制了面板整体的厚度，同时降低了面板弯折性能的问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种显示面板，包括：
衬底；
薄膜晶体管阵列层，设置于所述衬底上；
发光器件层，设置于所述薄膜晶体管阵列层上；
薄膜封装层，设置于所述发光器件层上；以及
相位迟滞层，设置于所述薄膜封装层内；
线偏层，设置于所述薄膜封装层内。
在本申请的显示面板中，所述薄膜封装层包括层叠设置的无机层和有机层，所述相位迟滞层和所述线偏层位于相邻的所述无机层和所述有机层之间；或者，所述相位迟滞层和所述线偏层之间设置有所述无机层和/或所述有机层。
在本申请的显示面板中，所述线偏层位于所述相位迟滞层背离所述发光器件层的一侧。
在本申请的显示面板中，所述发光器件层包括阵列分布的发光器件，所述相位迟滞层包括对应发光器件并呈阵列分布的相位迟滞单元，所述显示面板在对应相邻两所述相位迟滞单元的间隙处设置有黑色挡墙。
在本申请的显示面板中，所述薄膜晶体管阵列层包括无机堆叠层和薄膜晶体管，所述显示面板在所述无机堆叠层上还设置有机堆叠层，所述黑色挡墙位于所述有机堆叠层上或者位于所述薄膜封装层内。
在本申请的显示面板中，所述线偏层包括对应所述相位迟滞单元阵列分布的线偏单元，所述线偏单元在所述衬底上的正投影覆盖所述相位迟滞单元在所述衬底上的正投影。
在本申请的显示面板中，所述相位迟滞单元覆盖所述发光器件层的发光区域。
在本申请的显示面板中，所述相位迟滞层为各向异性有机材料。
在本申请的显示面板中，所述相位迟滞层为液晶材料，所述相位迟滞层的表面设置有配向层。
在本申请的显示面板中，所述相位迟滞层的相位差为四分之一波长。
为解决上述问题，本申请还提供一种显示面板，包括：
衬底；
薄膜晶体管阵列层，设置于所述衬底上；
发光器件层，设置于所述薄膜晶体管阵列层上；
薄膜封装层，设置于所述发光器件层上；以及
相位迟滞层，设置于所述薄膜封装层内；
线偏层，设置于所述薄膜封装层内，所述相位迟滞层与所述线偏层层叠设置。
在本申请的显示面板中，所述薄膜封装层包括层叠设置的无机层和有机层，所述相位迟滞层和所述线偏层位于相邻的所述无机层和所述有机层之间；或者，所述相位迟滞层和所述线偏层之间设置有所述无机层和/或所述有机层。
在本申请的显示面板中，所述线偏层位于所述相位迟滞层背离所述发光器件层的一侧。
在本申请的显示面板中，所述发光器件层包括阵列分布的发光器件，所述相位迟滞层包括对应发光器件并呈阵列分布的相位迟滞单元，所述显示面板在对应相邻两所述相位迟滞单元的间隙处设置有黑色挡墙。
在本申请的显示面板中，所述薄膜晶体管阵列层包括无机堆叠层和薄膜晶体管，所述显示面板在所述无机堆叠层上还设置有机堆叠层，所述黑色挡墙位于所述有机堆叠层上或者位于所述薄膜封装层内。
在本申请的显示面板中，所述线偏层包括对应所述相位迟滞单元阵列分布的线偏单元，所述线偏单元在所述衬底上的正投影覆盖所述相位迟滞单元在所述衬底上的正投影。
在本申请的显示面板中，所述相位迟滞单元覆盖所述发光器件层的发光区域。
在本申请的显示面板中，所述相位迟滞层为各向异性有机材料。
在本申请的显示面板中，所述相位迟滞层为液晶材料，所述相位迟滞层的表面设置有配向层。
在本申请的显示面板中，所述相位迟滞层的相位差为四分之一波长。
 有益效果
本申请的有益效果为：本申请提供的显示面板，通过去除传统的偏光片，并将相位迟滞层和线偏层设置于薄膜封装层内，相较于传统贴附偏光片的显示面板大大的缩减了厚度，增加了显示面板的弯折性能。同时，相位迟滞层和线偏层的组合可以有效地消除外部光照射到显示面板表面产生的反射光。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例一提供的显示面板的结构示意图；
图2为本申请实施例二提供的显示面板的结构示意图；
图3为本申请实施例三提供的显示面板的结构示意图；
图4为本申请实施例四提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“纵向”、“横向”、“长度”、“宽度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。在本申请中，“/”表示“或者”的意思。
本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。
请参照图1和图4所示，本申请提供一种显示面板，其包括：衬底10，所述衬底10可以为柔性衬底，但不以此为限；薄膜晶体管阵列层20，设置于所述衬底10上；发光器件层40，设置于所述薄膜晶体管阵列层20上；薄膜封装层50，设置于所述发光器件层40上；以及相位迟滞层60，设置于所述薄膜封装层50内；线偏层70，设置于所述薄膜封装层50内，所述相位迟滞层60与所述线偏层70层叠设置。
现行的OLED显示面板结构常采用外挂偏光片，偏光片通常为多层有机材料层组成的复合膜，其中包括λ/4相位迟滞片和线偏振片，该两层双折射层可实现屏幕的抗反射功能。但是λ/4相位迟滞片和线偏振片需要多层薄膜进行保护和连接，进而导致偏光片具有较大的厚度。传统的偏光片的厚度普遍在100μm的范围内，进而限制了屏幕的厚度，降低了屏幕的弯折性能。
本申请的显示面板通过去除传统的偏光片结构，只将相位迟滞层和线偏层设置于薄膜封装层内，相位迟滞层和线偏层组合后可以有效地消除外部光照射到显示面板表面产生的反射光。相较于传统贴附偏光片的显示面板大大的缩减了厚度，从而增加了显示面板的弯折性能，有利于可折叠显示面板的发展。
以下请结合具体实施例对本申请的所述显示面板进行详细描述。
实施例一
请参照图1所示，为本申请实施例一提供的显示面板的结构示意图。其中，衬底10上设置有薄膜晶体管阵列层20，所述薄膜晶体管阵列层20包括无机堆叠层和薄膜晶体管204。具体地，所述无机堆叠层包括但不限于层叠设置的第一栅绝缘层201、第二栅绝缘层202、层间绝缘层203。所述薄膜晶体管204包括有源层2041、栅极2042以及源/漏极2043。在所述栅极2042之上绝缘的设置有电极层205，所述电极层205与所述栅极2042形成电容。
所述无机堆叠层上还设置有机堆叠层30和发光器件层40，所述有机堆叠层30包括但不限于层叠设置的平坦化层301、像素定义层302。所述发光器件层40包括层叠设置的阳极401、发光层402、阴极403。
其中，所述阳极401设置于所述平坦化层301上，并通过平坦化层301上的过孔与薄膜晶体管204的源/漏极2043电连接。所述像素定义层302在对应所述阳极401的位置形成像素孔，所述发光层402位于所述像素孔内，所述阴极403设置于所述发光层402上。
薄膜封装层50设置于所述阴极403上，所述薄膜封装层50至少包括三层层叠的无机层501和有机层502以及无机层501。其中，所述无机层501的厚度通常在几百纳米的范围内，所述有机层502的厚度通常在20微米以下，所述有机层502既可用于阻隔水氧，也可起到平坦表面的作用。
其中，本申请为减薄显示屏全模组的厚度，将外挂偏光片集成到显示面板的薄膜封装层50内。所述薄膜封装层50中包括相位迟滞层60和线偏层70，所述线偏层70位于所述相位迟滞层60背离所述发光器件层40的一侧。
在本实施例中，所述相位迟滞层60和所述线偏层70整面的设置于所述薄膜封装层50中。具体地，所述相位迟滞层60和所述线偏层70之间设置有所述无机层501和/或所述有机层502。或者，所述相位迟滞层60和所述线偏层70位于相邻的所述无机层501和所述有机层502之间。
在图1中，所述相位迟滞层60位于第一层无机层501上，在所述相位迟滞层60上设置有机层502，在所述有机层502上设置所述线偏层70，在所述线偏层70上设置第二层无机层501。
在本实施例中，所述相位迟滞层60的相位差为四分之一波长，所述相位迟滞层60可以为1/4波片。
本实施例的显示面板，当外部入射光或自然光照射至显示面板表面后，会穿过所述线偏层70转变为线偏振光（例如水平方向的线偏振光），该线偏光经过相应的相位迟滞层60进而被转变为圆偏光，该圆偏光被阴极403及阳极401反射后进而增加π的相位（比如由左旋圆偏光变右旋圆偏光，或由右旋圆偏光变左旋圆偏光）；带相位延迟的圆偏光再次经过相位迟滞层60后转变为与入射线偏光垂直的线偏光（例如竖直方向的线偏振光），从而无法通过线偏层70，进而实现消光。
由于传统偏光片的1/4波片层主要通过高分子材料拉伸得到，故为达到特定相位迟滞系数，通常需要几十微米的厚度。而在本申请中，相位迟滞层60可为液晶材料或其他各向异性有机材料，且相位迟滞层60的厚度在一至几微米的范围内。从而大大的缩减了厚度，增加了显示面板的弯折性能。
实施例二
如图2所示，为本申请实施例二提供的显示面板的结构示意图。本实施例的显示面板与上述实施例一的显示面板相同/相似，区别在于：本实施例的所述发光器件层40包括阵列分布的发光器件即像素点，所述相位迟滞层包括对应发光器件并呈阵列分布的相位迟滞单元601，所述显示面板在对应相邻两所述相位迟滞单元601的间隙处设置有黑色挡墙80，黑色挡墙80为吸光材料，可有效地吸收所述相位迟滞单元601之外区域的外界入射光。因此，可以进一步消除外部光照射到显示面板表面产生的反射光。
其中，所述黑色挡墙80位于所述有机堆叠层30上或者位于所述薄膜封装层50内，所述黑色挡墙80的高度在几微米至十几微米的范围内。
具体地，所述黑色挡墙80位于所述像素定义层302上，可围绕像素孔设置。由于黑色挡墙80的设置，因此位于黑色挡墙80之上的阴极403以及无机层501会在对应像素孔的位置形成凹陷，所述相位迟滞单元601对应位于所述凹陷处。
其中，所述相位迟滞单元601覆盖所述发光器件层40的发光区域，即所述相位迟滞单元601在所述衬底10上的正投影覆盖所述发光层402在所述衬底10上的正投影。所述相位迟滞单元601可以向像素孔外围延伸。
在一种实施例中，所述黑色挡墙80可以位于所述薄膜封装层50的无机层501或有机层502上，入射至相位迟滞单元601之外区域的外界入射光可被所述黑色挡墙80吸收。
具体地，所述黑色挡墙80可以与所述相位迟滞单元601位于同一层，相邻的所述相位迟滞单元601以所述黑色挡墙80相隔。
其中，本实施例的相位迟滞单元601与线偏层70的抗反射（消光）原理与上述实施例一的抗反射原理相同，此处不再赘述。
实施例三
如图3所示，为本申请实施例三提供的显示面板的结构示意图。本实施例的显示面板与上述实施例二的显示面板相同/相似，区别在于：本实施例所述线偏层包括对应所述相位迟滞单元601阵列分布的线偏单元701，所述线偏单元701在所述衬底10上的正投影覆盖所述相位迟滞单元601在所述衬底10上的正投影。
其中，本实施例的有益效果与上述实施例二的有益效果相同，并且本实施例的相位迟滞单元601与线偏单元701的抗反射（消光）原理与上述实施例一的抗反射原理相同，此处不再赘述。
实施例四
如图4所示，为本申请实施例四提供的显示面板的结构示意图。本实施例的显示面板与上述实施例三的显示面板相同/相似，区别在于：本实施例的相位迟滞单元601和线偏单元701位于相邻的所述无机层501和所述有机层502之间，并且所述相位迟滞层（相位迟滞单元601）为液晶材料，所述相位迟滞层的表面设置有配向层90。
其中，所述配向层90可以位于所述相位迟滞单元601背离所述线偏单元701的一侧，或者可以位于所述相位迟滞单元601面向所述线偏单元701的一侧；或者，所述相位迟滞单元601的两侧表面均设置有所述配向层90。
在一种实施例中，所述配向层90的尺寸可以与相位迟滞层的尺寸相适应，可以整层设置也可以阵列分布。当然，相位迟滞单元601和线偏单元701也可以位于薄膜封装层的不同膜层上。
所述配向层90用于为所述液晶材料配向，从而使液晶材料产生合适的相位差，比如产生四分之一波长的相位差。当然，可根据实际需求对液晶材料配向。
本实施例相较于上述实施例三，可以通过对配向层90的设置而使相位迟滞单元601产生不同的相位差，可以根据实际情况灵活的消除反射光。
其中，本实施例的相位迟滞单元601与线偏单元701的抗反射（消光）原理与上述实施例一的抗反射原理相同，此处不再赘述。
本申请提供的显示面板，通过去除传统的偏光片，并将相位迟滞层和线偏层设置于薄膜封装层内，相较于传统贴附偏光片的显示面板大大的缩减了厚度，增加了显示面板的弯折性能。同时，相位迟滞层和线偏层的组合可以有效地消除外部光照射到显示面板表面产生的反射光，另外，通过设置具有吸光功能的黑色挡墙可以进一步消除外部光照射到显示面板表面产生的反射光。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括：
    衬底；
    薄膜晶体管阵列层，设置于所述衬底上；
    发光器件层，设置于所述薄膜晶体管阵列层上；
    薄膜封装层，设置于所述发光器件层上；以及
    相位迟滞层，设置于所述薄膜封装层内；
    线偏层，设置于所述薄膜封装层内。
  2. 根据权利要求1所述的显示面板，其中，所述薄膜封装层包括层叠设置的无机层和有机层，所述相位迟滞层和所述线偏层位于相邻的所述无机层和所述有机层之间；或者，所述相位迟滞层和所述线偏层之间设置有所述无机层和/或所述有机层。
  3. 根据权利要求2所述的显示面板，其中，所述线偏层位于所述相位迟滞层背离所述发光器件层的一侧。
  4. 根据权利要求1所述的显示面板，其中，所述发光器件层包括阵列分布的发光器件，所述相位迟滞层包括对应发光器件并呈阵列分布的相位迟滞单元，所述显示面板在对应相邻两所述相位迟滞单元的间隙处设置有黑色挡墙。
  5. 根据权利要求4所述的显示面板，其中，所述薄膜晶体管阵列层包括无机堆叠层和薄膜晶体管，所述显示面板在所述无机堆叠层上还设置有机堆叠层，所述黑色挡墙位于所述有机堆叠层上或者位于所述薄膜封装层内。
  6. 根据权利要求4所述的显示面板，其中，所述线偏层包括对应所述相位迟滞单元阵列分布的线偏单元，所述线偏单元在所述衬底上的正投影覆盖所述相位迟滞单元在所述衬底上的正投影。
  7. 根据权利要求6所述的显示面板，其中，所述相位迟滞单元覆盖所述发光器件层的发光区域。
  8. 根据权利要求1所述的显示面板，其中，所述相位迟滞层为各向异性有机材料。
  9. 根据权利要求8所述的显示面板，其中，所述相位迟滞层为液晶材料，所述相位迟滞层的表面设置有配向层。
  10. 根据权利要求1所述的显示面板，其中，所述相位迟滞层的相位差为四分之一波长。
  11. 一种显示面板，其包括：
    衬底；
    薄膜晶体管阵列层，设置于所述衬底上；
    发光器件层，设置于所述薄膜晶体管阵列层上；
    薄膜封装层，设置于所述发光器件层上；以及
    相位迟滞层，设置于所述薄膜封装层内；
    线偏层，设置于所述薄膜封装层内，所述相位迟滞层与所述线偏层层叠设置。
  12. 根据权利要求11所述的显示面板，其中，所述薄膜封装层包括层叠设置的无机层和有机层，所述相位迟滞层和所述线偏层位于相邻的所述无机层和所述有机层之间；或者，所述相位迟滞层和所述线偏层之间设置有所述无机层和/或所述有机层。
  13. 根据权利要求12所述的显示面板，其中，所述线偏层位于所述相位迟滞层背离所述发光器件层的一侧。
  14. 根据权利要求11所述的显示面板，其中，所述发光器件层包括阵列分布的发光器件，所述相位迟滞层包括对应发光器件并呈阵列分布的相位迟滞单元，所述显示面板在对应相邻两所述相位迟滞单元的间隙处设置有黑色挡墙。
  15. 根据权利要求14所述的显示面板，其中，所述薄膜晶体管阵列层包括无机堆叠层和薄膜晶体管，所述显示面板在所述无机堆叠层上还设置有机堆叠层，所述黑色挡墙位于所述有机堆叠层上或者位于所述薄膜封装层内。
  16. 根据权利要求14所述的显示面板，其中，所述线偏层包括对应所述相位迟滞单元阵列分布的线偏单元，所述线偏单元在所述衬底上的正投影覆盖所述相位迟滞单元在所述衬底上的正投影。
  17. 根据权利要求16所述的显示面板，其中，所述相位迟滞单元覆盖所述发光器件层的发光区域。
  18. 根据权利要求11所述的显示面板，其中，所述相位迟滞层为各向异性有机材料。
  19. 根据权利要求18所述的显示面板，其中，所述相位迟滞层为液晶材料，所述相位迟滞层的表面设置有配向层。
  20. 根据权利要求11所述的显示面板，其中，所述相位迟滞层的相位差为四分之一波长。
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