WO2021214933A1 - Procédé de production d'un dispositif semiconducteur - Google Patents

Procédé de production d'un dispositif semiconducteur Download PDF

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WO2021214933A1
WO2021214933A1 PCT/JP2020/017454 JP2020017454W WO2021214933A1 WO 2021214933 A1 WO2021214933 A1 WO 2021214933A1 JP 2020017454 W JP2020017454 W JP 2020017454W WO 2021214933 A1 WO2021214933 A1 WO 2021214933A1
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layer
forming
semiconductor layer
etching stop
gan
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Japanese (ja)
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佑樹 吉屋
拓也 星
杉山　弘樹
松崎　秀昭
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日本電信電話株式会社
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Priority to PCT/JP2020/017454 priority Critical patent/WO2021214933A1/fr
Priority to JP2022516571A priority patent/JP7388545B2/ja
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device using GaN.
  • ICP-RIE inductively coupled plasma reactive ion etching
  • chlorine-based ICP-RIE is dry etching using plasma, and the plasma is guided to the sample surface by the bias voltage at the time of etching. After etching, this plasma forms a damaged layer with many defects on the surface of the GaN layer to be etched.
  • the thickness of the damage layer depends on the bias voltage, and the larger the bias voltage, the thicker the damage layer is formed, which deteriorates the characteristics of the device.
  • Non-Patent Document 1 Non-Patent Document 1
  • Non-Patent Document 2 A multi-stage bias etching technique has been reported as a technique for solving the above-mentioned problems (Non-Patent Document 2).
  • the bias voltage is gradually lowered during etching to remove the damaged layer generated by etching with a high bias voltage, and the etching proceeds while suppressing the formation of a new damaged layer.
  • the bias voltage is lowered, the etching rate decreases. Therefore, it is necessary to proceed with etching while adjusting a plurality of etching rates, which is technically difficult.
  • Another problem with this type of dry etching is that the controllability of the etching amount is not high.
  • the etching amount is controlled by time. This is because a high selectivity selective etching technique has not been established in ICP-RIE. Control by time has problems such as large variation in each etching process and difficulty in stopping etching at the heterojunction interface.
  • Non-Patent Document 3 a method has been reported in which a small amount of oxygen is added to a chlorine-based etching gas to increase the difference in etching rates between GaN and AlGaN and increase the selectivity.
  • AlGaN is more easily oxidized than GaN and AlGaN, and AlGaN is used as an etch stop layer for GaN etching by utilizing the fact that the etching rate of the oxide is small.
  • AlGaN with a high Al composition of 28%.
  • AlGaN having a high Al composition becomes a large barrier to electrons in the device using GaN, so that the structure of the device using this etch stop layer is greatly limited.
  • the AlGaN surface after etching stop is covered with an oxide as a layer for suppressing etching, and it is necessary to remove the oxide with hydrofluoric acid after etching.
  • the conventional technique has a problem that it is not easy to manufacture a GaN device by etching GaN with good controllability without limiting the structure of the device by dry etching processing.
  • the present invention has been made to solve the above problems, and enables a GaN device to be manufactured by etching GaN with good controllability by a dry etching process without limiting the structure of the device.
  • the purpose is.
  • the semiconductor device has a first step of forming a channel layer made of GaN on a substrate, a second step of forming a barrier layer made of AlGaN on the channel layer, and a barrier layer.
  • a source electrode and a drain electrode that make ohmic contact with the two-dimensional electron gas formed near the interface between the channel layer and the barrier layer are formed.
  • the seventh step is provided, and the thickness of the etching stop layer and the composition ratio of Al are within the range in which the void formed by the gate pattern acts on the two-dimensional electron gas.
  • the semiconductor device has a first step of forming a channel layer made of GaN on a substrate, a second step of forming a barrier layer made of AlGaN on the channel layer, and a barrier layer.
  • a seventh step of forming an electrode is provided, and the thickness of the etching stop layer and the composition ratio of Al are within the range in which the gate electric field generated by the gate electrode acts on the two-dimensional electron gas.
  • the semiconductor device has a first step of forming a first semiconductor layer made of a first conductive type GaN on a substrate, and an etching stop layer made of AlGaN on the first semiconductor layer. From the second step of forming the second semiconductor layer composed of the first conductive type GaN on the etching stop layer, and the second step of forming the second semiconductor layer composed of the first conductive type GaN on the second semiconductor layer.
  • the etching stop layer is formed by patterning the second semiconductor layer and the third semiconductor layer using the fourth step of forming the configured third semiconductor layer and the etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN.
  • a seventh step of forming a second electrode that makes ohmic contact with the third semiconductor layer is provided on the three semiconductor layers, and the thickness of the etching stop layer and the composition ratio of Al are the same as those of the first electrode and the first semiconductor layer. It is said that the range where the ohmic contact can be obtained.
  • the semiconductor device is composed of a first step of forming a first semiconductor layer which is composed of a first conductive type GaN and serves as a drain on a substrate, and an AlGaN on the first semiconductor layer.
  • the second semiconductor layer and the second semiconductor layer using the fourth step of forming the third semiconductor layer which is composed of the first conductive type GaN and the source, and the etching by thermal decomposition which selectively decomposes GaN with respect to AlGaN.
  • the eighth step of forming the electrode and the ninth step of forming the source electrode electrically connected to the third semiconductor layer are provided, and the thickness of the etching stop layer and the composition ratio of Al are the channel and the first semiconductor layer. It is said that it is within the range where the carrier can move between and.
  • the semiconductor device has a first step of forming a first semiconductor layer made of GaN on a substrate and a second step of forming an etching stop layer made of AlGaN on the first semiconductor layer.
  • a second semiconductor layer using a step a third step of forming a second semiconductor layer composed of GaN on an etching stop layer, and etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN.
  • the GaN device can be manufactured by etching GaN with good controllability by the dry etching process without limiting the structure of the device. ..
  • FIG. 1A is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1D is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1A is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a state of the semiconductor device in the intermediate
  • FIG. 1E is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1F is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
  • FIG. 2B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 2C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 3A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 3B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 4A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4D is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4E is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4D is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method
  • FIG. 5A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 5B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 5C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.
  • a channel layer 102 composed of GaN is formed on the substrate 101 (first step). Between the substrate 101 and the channel layer 102, for example, a buffer layer composed of one or more of GaN, AlGaN, AlN, and AlON as a nucleation layer, and a back barrier layer for confining carriers of the channel layer.
  • a buffer layer composed of one or more of GaN, AlGaN, AlN, and AlON as a nucleation layer
  • a back barrier layer for confining carriers of the channel layer.
  • a layer made of AlGaN or InGaN, a superlattice structure for reducing the dislocation density, and the like can be inserted.
  • a barrier layer 103 composed of AlGaN is formed on the channel layer 102 (second step). Therefore, as shown in FIG. 1C, an etching stop layer 104 composed of AlGaN is formed on the barrier layer 103 (third step). Next, as shown in FIG. 1D, a p-type semiconductor layer 105 composed of p-type GaN is formed on the etching stop layer 104 (fourth step). As is well known, GaN into which p-type impurities have been introduced becomes p-type GaN by being activated by heat treatment.
  • the substrate 101 is made of, for example, Al 2 O 3 (sapphire), and the plane orientation of the main surface is, for example, (0001).
  • the substrate 101 is made of a material capable of crystal growth of a nitride semiconductor such as GaN, AlGaN, and InGaN.
  • the barrier layer 103 is composed of, for example, AlGaN having an Al composition of about 25%, and is formed to have a layer thickness of about 20 nm.
  • the p-type semiconductor layer 105 is formed, for example, to have a layer thickness of about 100 nm.
  • the etching stop layer 104 has, for example, an Al composition of 5%.
  • the Al composition of the etching stop layer 104 can be 5% or more, or 5% or less. Since the influence on the device characteristics differs depending on the Al composition of the etching stop layer 104 and the thickness required for the function for stopping the etching also differs, care must be taken when designing the device.
  • the etching stop layer 104 made of AlGaN having a different composition is arranged on the barrier layer 103. Therefore, when increasing the Al composition of the etching stop layer 104, the overall thickness of the layer made of AlGaN in consideration of the thickness of the barrier layer 103 and the thickness of the etching stop layer 104 determines the device characteristics. Will be done. If the composition of Al in the etching stop layer 104 is small, such an effect can be ignored to some extent.
  • Each semiconductor layer described above is epitaxially grown in this order, for example, with the main surface having group III polarity (in the + c-axis direction).
  • Nitride semiconductors such as GaN have a hexagonal wurtzite structure as a stable phase, and polarization occurs in the c-axis direction. By utilizing this effect, a high-concentration two-dimensional electron gas serving as a channel can be formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103.
  • Each of the above-mentioned layers can be formed by the well-known metalorganic vapor phase growth method.
  • Each layer can also be formed (epitaxially grown) by molecular beam epitaxy (which may be classified into gas source, RF plasma source, laser, etc.), hydride vapor phase growth method, etc., for each of the above-mentioned semiconductor layers. Is.
  • the gate pattern 106 is placed on the etching stop layer 104.
  • a mask pattern (not shown) is formed on the p-type semiconductor layer 105 by a known lithography technique, the formed mask pattern is used as a mask, and the p-type semiconductor layer 105 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the gate pattern 106.
  • the etching target (p-type semiconductor layer 105) is heated to a high temperature (for example, 1000 ° C.), and etching is performed by utilizing thermal decomposition of a GaN-based material. Proceed. Since the energy required for thermal decomposition of AlGaN is larger than the energy required for thermal decomposition of GaN, GaN can be etched with a high selectivity for AlGaN in the above-mentioned etching process. As shown in Non-Patent Document 4, if the Al composition of about 5% AlGaN, etching selectivity of the GaN exceeds 10 2, obtained a value close to 10 3.
  • the etching rate of GaN is selected to be 10 2 nm / min (5 ⁇ 10 2 nm / min or more in Non-Patent Document 4, and about 10 nm / min under the experimental conditions of the inventors)
  • the Al composition 5 The etching rate of% AlGaN is 1 nm / min or less. Therefore, if an etching stop layer 104 having a thickness of 1 nm made of AlGaN having an Al composition of 5% is provided under the p-type semiconductor layer 105 having a thickness of 100 nm, the overetching time of the etching stop layer 104 can be set to the p-type semiconductor layer. It is possible to take about the time (1 minute) required for etching the thickness of 105 of 100 nm, and it is possible to completely flatten the unevenness of the surface caused by the etching.
  • the thickness of the p-type semiconductor layer 105 is larger than 100 nm, the time required for etching increases and the unevenness generated during etching also increases. Therefore, in order to obtain a flat surface in the etching stop layer 104, it is necessary to increase the overetching time, and it is necessary to make the etching stop layer 104 thicker. However, it is not necessary to increase the layer thickness of the etching stop layer 104 in proportion to the layer thickness of the p-type semiconductor layer 105.
  • the overetching time required for flattening also changes depending on the conditions. Therefore, in order to etch the p-type semiconductor layer 105 at 500 nm, the thickness of the etching stop layer 104 having an Al composition of 5% is not required to be 5 nm. Similarly, if the p-type semiconductor layer 105 to be etched becomes thinner, the overetching time can be shortened, so that the etching stop layer 104 can be further thinned. However, it is not desirable to use the etching stop layer 104 with a layer thickness of 1 nm or less because it is difficult to control the composition and the layer thickness of the etching stop layer 104 having a thickness of less than 1 nm.
  • the composition and thickness of the etching stop layer 104 are determined by the thickness and etching conditions of the p-type semiconductor layer 105 to be etched. However, regarding the thickness of the etching stop layer 104 and the composition ratio of Al, the depletion formed by the gate pattern 106 via the etching stop layer 104 remaining after the gate pattern 106 is formed becomes the above-mentioned two-dimensional electron gas. It is important that it is within the range of action.
  • the gate electrode 107 arranged on the gate pattern 106 is formed (sixth step).
  • the gate electrode 107 can be formed after the gate pattern 106 is formed. It is also possible to form the gate electrode 107 on the p-type semiconductor layer 105 and use the gate electrode 107 as a mask to carry out the patterning of the p-type semiconductor layer 105 described above to form the gate pattern 106.
  • the gate electrode 107 is finally formed so as to be arranged on the gate pattern 106.
  • a source electrode 108 and a drain electrode 109 that make ohmic contact with the two-dimensional electron gas formed near the interface between the channel layer 102 and the barrier layer 103 are formed.
  • heat treatment is generally performed.
  • the gate pattern 106 can be formed, then the source electrode 108 and the drain electrode 109 can be formed and the above-mentioned heat treatment can be performed, and then the gate electrode 107 can be formed.
  • the gate electrode 107 By forming the gate electrode 107 after the heat treatment for ohmic contact, the influence of the heat treatment on the gate electrode 107 can be prevented.
  • a normally-off field effect transistor high electron mobility transistor
  • the etching stop layer composed of AlGaN is used, the GaN is etched with good controllability by the dry etching process without limiting the structure of the device, and the GaN device. (Field effect transistor) can be manufactured.
  • a channel layer 102 composed of GaN is formed on the substrate 101 (first step).
  • a barrier layer 103 composed of AlGaN is formed on the channel layer 102 (second step). Therefore, as shown in FIG. 1C, an etching stop layer 104 composed of AlGaN is formed on the barrier layer 103 (third step).
  • a two-dimensional electron gas is formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103.
  • a cap layer 111 composed of GaN is formed on the etching stop layer 104 (fourth step).
  • the cap layer 111 is formed to have a thickness of, for example, about 3 nm.
  • the cap layer 111 is a layer for preventing natural oxidation of the surface of the layer of the nitride semiconductor containing Al.
  • the surface of the etching stop layer 104 penetrates the cap layer 111.
  • the exposed gate opening 112 is formed (fifth step).
  • a mask pattern is formed on the cap layer 111 by a known lithography technique, the formed mask pattern is used as a mask, and the cap layer 111 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the gate opening 112.
  • the etching by thermal decomposition described above is the same as that of the first embodiment described above.
  • the etching target (cap layer 111) is heated to a high temperature and the thermal decomposition of the GaN-based material is utilized. And proceed with etching.
  • the layer thickness of the cap layer 111 is as thin as 3 nm, it is desirable to adjust the etching conditions and reduce the etching rate of GaN. For example, the etching rate can be lowered by lowering the temperature during etching.
  • the etching stop layer 104 is preferably having a thickness of 1 nm or more because the controllability of the composition and the layer thickness is lowered when the thickness is made smaller than 1 nm.
  • the thickness of the etching stop layer 104 is determined from the viewpoint of reducing the influence of the etching stop layer 104 on the device characteristics. It is desirable that the content is equal to or less than that of the cap layer 111. Since the layer thicknesses of the etching stop layer 104 and the cap layer 111 are about the same, a sufficient overetching time can be taken and a flat surface morphology can be surely obtained.
  • the gate electric field by the gate electrode described later acts on the above-mentioned two-dimensional electron gas through the etching stop layer 104 remaining after the gate opening 112 is formed. It is important that the range is set.
  • the gate electrode 113 is formed on the etching stop layer 104 exposed to the gate opening 112 (sixth step). Further, the source electrode 114 and the drain electrode 115 are formed on the cap layer 111 on the side of the gate electrode 113. The source electrode 114 and the drain electrode 115 are formed so as to make ohmic contact with the two-dimensional electron gas formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103 (7th step). Further, an opening penetrating the cap layer 111 may be formed to expose the etching stop layer 104, and the source electrode 114 may be formed therein. Similarly, an opening penetrating the cap layer 111 may be formed to expose the etching stop layer 104, and the drain electrode 115 may be formed therein. A field effect transistor (high electron mobility transistor) can be obtained by the above manufacturing method.
  • the etching stop layer composed of AlGaN is used, the GaN is etched with good controllability by the dry etching process without limiting the structure of the device, and the GaN device (the GaN device). Field effect transistor) can be manufactured.
  • the first semiconductor layer 202, the etching stop layer 203, the second semiconductor layer 204, and the third semiconductor layer 205 are formed on the substrate 201 in this order (first step, step 1. 2nd step, 3rd step, 4th step).
  • the first semiconductor layer 202 is composed of a first conductive type (n type) GaN and has a thickness of 300 nm.
  • the first semiconductor layer 202 can be made of GaN having a high concentration of n-type.
  • the etching stop layer 203 is made of AlGaN.
  • the second semiconductor layer 204 is composed of the first conductive type GaN.
  • the second semiconductor layer 204 is composed of GaN having a low concentration of n-type and has a thickness of 3 ⁇ m.
  • the third semiconductor layer 205 is made of a second conductive type (p type) GaN. Since the thickness of the second semiconductor layer 204 affects the withstand voltage characteristic of the diode, it can be made thicker.
  • the second semiconductor layer 204 and the third semiconductor layer 205 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 3B, one of the etching stop layers 203.
  • the surface of the portion is exposed to form the electrode forming surface 206 (fifth step).
  • a mask pattern is formed on the third semiconductor layer 205 by a known lithography technique, the formed mask pattern is used as a mask, and the third semiconductor layer 205 and the second semiconductor layer 204 are etched by an etching process by thermal decomposition.
  • the mask pattern is removed after forming the electrode forming surface 206.
  • the first electrode 207 that makes ohmic contact with the first semiconductor layer 202 is formed on the electrode forming surface 206 of the etching stop layer 203 (sixth step). Further, a second electrode 208 that makes ohmic contact with the third semiconductor layer 205 is formed on the third semiconductor layer 205 (7th step).
  • the thickness of the etching stop layer 203 and the composition ratio of Al are within a range in which ohmic contact between the first electrode 207 and the first semiconductor layer 202 can be obtained after the electrode forming surface 206 is formed. is important.
  • the etching by thermal decomposition for forming the electrode forming surface 206 is the same as that of the first and second embodiments described above.
  • the etching stop layer 203 made of AlGaN is inserted in the place where it is originally composed of only GaN. Since it is difficult for AlGaN to function as a barrier against electrons when the Al composition is low, it is desirable that the etching stop layer 203 has a low Al composition.
  • the second semiconductor layer 204 on the etching stop layer 203 is as thick as 3 ⁇ m, and the etching process takes a long time, so that it is considered that the unevenness generated during the etching becomes large. Therefore, it is important to take a long overetching time in the etching stop layer 203 in order to obtain a flat surface.
  • the thickness of the etching stop layer 203 is designed.
  • the etching stop layer 203 having an Al composition of 5% is etched at 1 nm or more under these etching conditions. Therefore, it is desirable that the thickness of the etching stop layer 203 is 2 nm or more.
  • the thickness of the etching stop layer 203 should be as thick as several tens of nm in order to sufficiently reduce the influence of AlGaN. Is not desirable.
  • the etching stop layer 203 is exposed by an etching process in order to expose the surface of the first semiconductor layer 202 originally made of n + type GaN, and the first electrode 207 is formed therein. Therefore, it is desirable that the etching stop layer 203 is doped in the same degree as the first semiconductor layer 202. The effect of doping is considered to be small, and the above discussion is the same even when the etching stop layer 203 composed of n + type AlGaN is used.
  • the GaN device is etched with good controllability by the dry etching process without limiting the structure of the device.
  • a diode can be manufactured.
  • the first semiconductor layer 302, the etching stop layer 303, the second semiconductor layer 304, and the third semiconductor layer 305 are formed in this order on the substrate 301 (first step, step 1. 2nd step, 3rd step, 4th step).
  • the first semiconductor layer 302 is made of a first conductive type (n type) GaN and has a thickness of about 300 nm.
  • the first semiconductor layer 302 serves as a drain for the MOS transistor.
  • the etching stop layer 303 is made of AlGaN.
  • the second semiconductor layer 304 is made of a second conductive type (p type) GaN and has a thickness of about 500 nm.
  • the second semiconductor layer 304 is a region where a channel of a MOS transistor is formed.
  • the third semiconductor layer 305 is composed of a first conductive type (n type) GaN and has a thickness of about 300 nm.
  • the third semiconductor layer 305 serves as a source for the MOS transistor.
  • the second semiconductor layer 304 and the third semiconductor layer 305 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 4B, the second semiconductor layer 304 and An opening 306 that penetrates the third semiconductor layer 305 and reaches the etching stop layer 303 is formed (fifth step).
  • a mask pattern is formed on the third semiconductor layer 305 by a known lithography technique, the formed mask pattern is used as a mask, and the third semiconductor layer 305 and the second semiconductor layer 304 are etched by an etching process by thermal decomposition. The mask pattern is removed after forming the opening 306.
  • an insulating layer 307 covering the bottom surface and the side surface of the opening 306 is formed (sixth step).
  • the insulating layer 307 can be formed by depositing an insulating material to form an insulating film by a well-known deposition technique and then patterning the insulating film by a known lithography technique and etching technique.
  • a gate electrode 308 for applying a gate electric field to the channel is formed inside the opening 306 whose bottom surface and side surfaces are covered with the insulating layer 307 (7th step).
  • a mask pattern having an opening is formed in the gate electrode forming region, and the gate electrode material is deposited on the mask pattern.
  • the gate electrode 308 can be formed by leaving the gate electrode material in the gate forming region.
  • a drain electrode (not shown) electrically connected to the first semiconductor layer 302 is formed (step 8) and a source electrode (not shown) electrically connected to the third semiconductor layer 305 is formed (not shown).
  • a so-called trench type MOS transistor is obtained.
  • the substrate 301 is made of a conductive material (for example, conductive GaN)
  • the above-mentioned drain electrode can be formed on the back surface of the substrate 301.
  • each electrode can also be formed via a contact layer in which a predetermined impurity is introduced to a higher concentration to form a predetermined conductive type.
  • the thickness of the etching stop layer 303 and the composition ratio of Al are set within a range in which carriers can be moved between the channel and the first semiconductor layer 302 after the opening 306 is formed. is important.
  • the etching by thermal decomposition for forming the opening 306 is the same as that of the first and second embodiments described above.
  • the etching stop layer 303 made of AlGaN is inserted in the place where it is originally composed of only GaN. Since it is difficult for AlGaN to function as a barrier against electrons (carriers) when the Al composition is low, it is desirable that the etching stop layer 303 has a low Al composition.
  • the thickness of the GaN layer to be etched (the second semiconductor layer 304 and the third semiconductor layer 305) is 1 ⁇ m or less, and the unevenness generated during the etching of GaN is considered to be about several tens of nm.
  • the unevenness generated during the etching of GaN is considered to be about several tens of nm.
  • the etching stop layer 303 having a thickness of about 2 nm as in the above-described third embodiment. ..
  • the etching stop layer 303 is located above the first semiconductor layer 302 made of n-type GaN, the etching stop layer 303 is doped to etch the first semiconductor layer 302. The influence of using the stop layer 303 can be reduced.
  • the trench-type MOSFET may have a structure in which an etching stop layer 303a made of AlGaN is inserted in the middle of the source first semiconductor layer 302 in the thickness direction.
  • an etching stop layer 303a made of AlGaN is inserted in the middle of the source first semiconductor layer 302 in the thickness direction.
  • the first semiconductor layer 402, the etching stop layer 403, and the second semiconductor layer 404 are formed in this order on the substrate 401 (first step, second step, third step). Process).
  • the first semiconductor layer 402 is made of, for example, an n-type GaN and has a thickness of about 300 nm.
  • the etching stop layer 403 is made of AlGaN.
  • the second semiconductor layer 404 is composed of, for example, an n-type GaN and has a thickness of about 300 nm.
  • the etching stop layer penetrates the second semiconductor layer 404.
  • the opening 405 that reaches 403 is formed (fourth step).
  • a mask pattern is formed on the second semiconductor layer 404 by a known lithography technique, the formed mask pattern is used as a mask, and the second semiconductor layer 404 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the opening 405.
  • p-type GaN is re-grown on the etching stop layer 403 exposed to the opening 405 to form the third semiconductor layer 406 as shown in FIG. 5C.
  • the layer thickness for regrowth is 300 nm.
  • the layer thickness of the second semiconductor layer 404 to be etched is 300 nm, and the unevenness generated during etching by thermal decomposition of GaN is considered to be about several tens of nm.
  • the unevenness of about 50 nm is flattened by over-etching the etching stop layer 403, it is desirable that the thickness of the etching stop layer 403 is about 2 nm.
  • the etching stop layer 403 is arranged in the layer made of GaN, the influence of the insertion of the AlGaN layer into the layer made of GaN is reduced by doping the etching stop layer 403. can do.
  • etching by thermal decomposition can be carried out by the above-mentioned apparatus for growing the nitride semiconductor.
  • a growth apparatus that carries out metalorganic vapor phase growth
  • the third semiconductor layer 406 can be continuously regrown without being exposed to the atmosphere.
  • the GaN device is manufactured by etching GaN with good controllability by the dry etching process without limiting the structure of the device. become able to.

Abstract

Selon la présente invention, un motif de grille (106) est formé au-dessus d'une couche d'arrêt de gravure (104) par formation d'un motif sur une couche en semiconducteur de type P (105) au moyen d'une gravure par décomposition thermique dans laquelle du GaN est décomposé sélectivement sur de l'AlGaN. Dans la gravure par décomposition thermique, la gravure est effectuée, par exemple, en utilisant une décomposition thermique d'un matériau à base de GaN par chauffage de la couche en semiconducteur de type P (105) à une température élevée dans une atmosphère sous NH3/H2. Du fait que l'énergie nécessaire à la décomposition thermique de l'AlGaN est supérieure à l'énergie nécessaire à la décomposition thermique du GaN, le GaN peut être gravé sélectivement sur l'AlGaN avec une sélectivité élevée dans le processus de gravure décrit ci-dessus.
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JP2000252265A (ja) * 1999-03-03 2000-09-14 Hitachi Ltd 化合物半導体材料のエッチング方法および化合物半導体装置
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