WO2021214933A1 - Method for producing semiconductor device - Google Patents

Method for producing semiconductor device Download PDF

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Publication number
WO2021214933A1
WO2021214933A1 PCT/JP2020/017454 JP2020017454W WO2021214933A1 WO 2021214933 A1 WO2021214933 A1 WO 2021214933A1 JP 2020017454 W JP2020017454 W JP 2020017454W WO 2021214933 A1 WO2021214933 A1 WO 2021214933A1
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layer
forming
semiconductor layer
etching stop
gan
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PCT/JP2020/017454
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French (fr)
Japanese (ja)
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佑樹 吉屋
拓也 星
杉山　弘樹
松崎　秀昭
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日本電信電話株式会社
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Priority to JP2022516571A priority Critical patent/JP7388545B2/en
Priority to PCT/JP2020/017454 priority patent/WO2021214933A1/en
Publication of WO2021214933A1 publication Critical patent/WO2021214933A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device using GaN.
  • ICP-RIE inductively coupled plasma reactive ion etching
  • chlorine-based ICP-RIE is dry etching using plasma, and the plasma is guided to the sample surface by the bias voltage at the time of etching. After etching, this plasma forms a damaged layer with many defects on the surface of the GaN layer to be etched.
  • the thickness of the damage layer depends on the bias voltage, and the larger the bias voltage, the thicker the damage layer is formed, which deteriorates the characteristics of the device.
  • Non-Patent Document 1 Non-Patent Document 1
  • Non-Patent Document 2 A multi-stage bias etching technique has been reported as a technique for solving the above-mentioned problems (Non-Patent Document 2).
  • the bias voltage is gradually lowered during etching to remove the damaged layer generated by etching with a high bias voltage, and the etching proceeds while suppressing the formation of a new damaged layer.
  • the bias voltage is lowered, the etching rate decreases. Therefore, it is necessary to proceed with etching while adjusting a plurality of etching rates, which is technically difficult.
  • Another problem with this type of dry etching is that the controllability of the etching amount is not high.
  • the etching amount is controlled by time. This is because a high selectivity selective etching technique has not been established in ICP-RIE. Control by time has problems such as large variation in each etching process and difficulty in stopping etching at the heterojunction interface.
  • Non-Patent Document 3 a method has been reported in which a small amount of oxygen is added to a chlorine-based etching gas to increase the difference in etching rates between GaN and AlGaN and increase the selectivity.
  • AlGaN is more easily oxidized than GaN and AlGaN, and AlGaN is used as an etch stop layer for GaN etching by utilizing the fact that the etching rate of the oxide is small.
  • AlGaN with a high Al composition of 28%.
  • AlGaN having a high Al composition becomes a large barrier to electrons in the device using GaN, so that the structure of the device using this etch stop layer is greatly limited.
  • the AlGaN surface after etching stop is covered with an oxide as a layer for suppressing etching, and it is necessary to remove the oxide with hydrofluoric acid after etching.
  • the conventional technique has a problem that it is not easy to manufacture a GaN device by etching GaN with good controllability without limiting the structure of the device by dry etching processing.
  • the present invention has been made to solve the above problems, and enables a GaN device to be manufactured by etching GaN with good controllability by a dry etching process without limiting the structure of the device.
  • the purpose is.
  • the semiconductor device has a first step of forming a channel layer made of GaN on a substrate, a second step of forming a barrier layer made of AlGaN on the channel layer, and a barrier layer.
  • a source electrode and a drain electrode that make ohmic contact with the two-dimensional electron gas formed near the interface between the channel layer and the barrier layer are formed.
  • the seventh step is provided, and the thickness of the etching stop layer and the composition ratio of Al are within the range in which the void formed by the gate pattern acts on the two-dimensional electron gas.
  • the semiconductor device has a first step of forming a channel layer made of GaN on a substrate, a second step of forming a barrier layer made of AlGaN on the channel layer, and a barrier layer.
  • a seventh step of forming an electrode is provided, and the thickness of the etching stop layer and the composition ratio of Al are within the range in which the gate electric field generated by the gate electrode acts on the two-dimensional electron gas.
  • the semiconductor device has a first step of forming a first semiconductor layer made of a first conductive type GaN on a substrate, and an etching stop layer made of AlGaN on the first semiconductor layer. From the second step of forming the second semiconductor layer composed of the first conductive type GaN on the etching stop layer, and the second step of forming the second semiconductor layer composed of the first conductive type GaN on the second semiconductor layer.
  • the etching stop layer is formed by patterning the second semiconductor layer and the third semiconductor layer using the fourth step of forming the configured third semiconductor layer and the etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN.
  • a seventh step of forming a second electrode that makes ohmic contact with the third semiconductor layer is provided on the three semiconductor layers, and the thickness of the etching stop layer and the composition ratio of Al are the same as those of the first electrode and the first semiconductor layer. It is said that the range where the ohmic contact can be obtained.
  • the semiconductor device is composed of a first step of forming a first semiconductor layer which is composed of a first conductive type GaN and serves as a drain on a substrate, and an AlGaN on the first semiconductor layer.
  • the second semiconductor layer and the second semiconductor layer using the fourth step of forming the third semiconductor layer which is composed of the first conductive type GaN and the source, and the etching by thermal decomposition which selectively decomposes GaN with respect to AlGaN.
  • the eighth step of forming the electrode and the ninth step of forming the source electrode electrically connected to the third semiconductor layer are provided, and the thickness of the etching stop layer and the composition ratio of Al are the channel and the first semiconductor layer. It is said that it is within the range where the carrier can move between and.
  • the semiconductor device has a first step of forming a first semiconductor layer made of GaN on a substrate and a second step of forming an etching stop layer made of AlGaN on the first semiconductor layer.
  • a second semiconductor layer using a step a third step of forming a second semiconductor layer composed of GaN on an etching stop layer, and etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN.
  • the GaN device can be manufactured by etching GaN with good controllability by the dry etching process without limiting the structure of the device. ..
  • FIG. 1A is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1D is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1A is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 1B is a cross-sectional view showing a state of the semiconductor device in the intermediate
  • FIG. 1E is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1F is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
  • FIG. 2B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 2C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 3A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 3B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 4A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4D is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4E is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 4D is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method
  • FIG. 5A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 5B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 5C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.
  • a channel layer 102 composed of GaN is formed on the substrate 101 (first step). Between the substrate 101 and the channel layer 102, for example, a buffer layer composed of one or more of GaN, AlGaN, AlN, and AlON as a nucleation layer, and a back barrier layer for confining carriers of the channel layer.
  • a buffer layer composed of one or more of GaN, AlGaN, AlN, and AlON as a nucleation layer
  • a back barrier layer for confining carriers of the channel layer.
  • a layer made of AlGaN or InGaN, a superlattice structure for reducing the dislocation density, and the like can be inserted.
  • a barrier layer 103 composed of AlGaN is formed on the channel layer 102 (second step). Therefore, as shown in FIG. 1C, an etching stop layer 104 composed of AlGaN is formed on the barrier layer 103 (third step). Next, as shown in FIG. 1D, a p-type semiconductor layer 105 composed of p-type GaN is formed on the etching stop layer 104 (fourth step). As is well known, GaN into which p-type impurities have been introduced becomes p-type GaN by being activated by heat treatment.
  • the substrate 101 is made of, for example, Al 2 O 3 (sapphire), and the plane orientation of the main surface is, for example, (0001).
  • the substrate 101 is made of a material capable of crystal growth of a nitride semiconductor such as GaN, AlGaN, and InGaN.
  • the barrier layer 103 is composed of, for example, AlGaN having an Al composition of about 25%, and is formed to have a layer thickness of about 20 nm.
  • the p-type semiconductor layer 105 is formed, for example, to have a layer thickness of about 100 nm.
  • the etching stop layer 104 has, for example, an Al composition of 5%.
  • the Al composition of the etching stop layer 104 can be 5% or more, or 5% or less. Since the influence on the device characteristics differs depending on the Al composition of the etching stop layer 104 and the thickness required for the function for stopping the etching also differs, care must be taken when designing the device.
  • the etching stop layer 104 made of AlGaN having a different composition is arranged on the barrier layer 103. Therefore, when increasing the Al composition of the etching stop layer 104, the overall thickness of the layer made of AlGaN in consideration of the thickness of the barrier layer 103 and the thickness of the etching stop layer 104 determines the device characteristics. Will be done. If the composition of Al in the etching stop layer 104 is small, such an effect can be ignored to some extent.
  • Each semiconductor layer described above is epitaxially grown in this order, for example, with the main surface having group III polarity (in the + c-axis direction).
  • Nitride semiconductors such as GaN have a hexagonal wurtzite structure as a stable phase, and polarization occurs in the c-axis direction. By utilizing this effect, a high-concentration two-dimensional electron gas serving as a channel can be formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103.
  • Each of the above-mentioned layers can be formed by the well-known metalorganic vapor phase growth method.
  • Each layer can also be formed (epitaxially grown) by molecular beam epitaxy (which may be classified into gas source, RF plasma source, laser, etc.), hydride vapor phase growth method, etc., for each of the above-mentioned semiconductor layers. Is.
  • the gate pattern 106 is placed on the etching stop layer 104.
  • a mask pattern (not shown) is formed on the p-type semiconductor layer 105 by a known lithography technique, the formed mask pattern is used as a mask, and the p-type semiconductor layer 105 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the gate pattern 106.
  • the etching target (p-type semiconductor layer 105) is heated to a high temperature (for example, 1000 ° C.), and etching is performed by utilizing thermal decomposition of a GaN-based material. Proceed. Since the energy required for thermal decomposition of AlGaN is larger than the energy required for thermal decomposition of GaN, GaN can be etched with a high selectivity for AlGaN in the above-mentioned etching process. As shown in Non-Patent Document 4, if the Al composition of about 5% AlGaN, etching selectivity of the GaN exceeds 10 2, obtained a value close to 10 3.
  • the etching rate of GaN is selected to be 10 2 nm / min (5 ⁇ 10 2 nm / min or more in Non-Patent Document 4, and about 10 nm / min under the experimental conditions of the inventors)
  • the Al composition 5 The etching rate of% AlGaN is 1 nm / min or less. Therefore, if an etching stop layer 104 having a thickness of 1 nm made of AlGaN having an Al composition of 5% is provided under the p-type semiconductor layer 105 having a thickness of 100 nm, the overetching time of the etching stop layer 104 can be set to the p-type semiconductor layer. It is possible to take about the time (1 minute) required for etching the thickness of 105 of 100 nm, and it is possible to completely flatten the unevenness of the surface caused by the etching.
  • the thickness of the p-type semiconductor layer 105 is larger than 100 nm, the time required for etching increases and the unevenness generated during etching also increases. Therefore, in order to obtain a flat surface in the etching stop layer 104, it is necessary to increase the overetching time, and it is necessary to make the etching stop layer 104 thicker. However, it is not necessary to increase the layer thickness of the etching stop layer 104 in proportion to the layer thickness of the p-type semiconductor layer 105.
  • the overetching time required for flattening also changes depending on the conditions. Therefore, in order to etch the p-type semiconductor layer 105 at 500 nm, the thickness of the etching stop layer 104 having an Al composition of 5% is not required to be 5 nm. Similarly, if the p-type semiconductor layer 105 to be etched becomes thinner, the overetching time can be shortened, so that the etching stop layer 104 can be further thinned. However, it is not desirable to use the etching stop layer 104 with a layer thickness of 1 nm or less because it is difficult to control the composition and the layer thickness of the etching stop layer 104 having a thickness of less than 1 nm.
  • the composition and thickness of the etching stop layer 104 are determined by the thickness and etching conditions of the p-type semiconductor layer 105 to be etched. However, regarding the thickness of the etching stop layer 104 and the composition ratio of Al, the depletion formed by the gate pattern 106 via the etching stop layer 104 remaining after the gate pattern 106 is formed becomes the above-mentioned two-dimensional electron gas. It is important that it is within the range of action.
  • the gate electrode 107 arranged on the gate pattern 106 is formed (sixth step).
  • the gate electrode 107 can be formed after the gate pattern 106 is formed. It is also possible to form the gate electrode 107 on the p-type semiconductor layer 105 and use the gate electrode 107 as a mask to carry out the patterning of the p-type semiconductor layer 105 described above to form the gate pattern 106.
  • the gate electrode 107 is finally formed so as to be arranged on the gate pattern 106.
  • a source electrode 108 and a drain electrode 109 that make ohmic contact with the two-dimensional electron gas formed near the interface between the channel layer 102 and the barrier layer 103 are formed.
  • heat treatment is generally performed.
  • the gate pattern 106 can be formed, then the source electrode 108 and the drain electrode 109 can be formed and the above-mentioned heat treatment can be performed, and then the gate electrode 107 can be formed.
  • the gate electrode 107 By forming the gate electrode 107 after the heat treatment for ohmic contact, the influence of the heat treatment on the gate electrode 107 can be prevented.
  • a normally-off field effect transistor high electron mobility transistor
  • the etching stop layer composed of AlGaN is used, the GaN is etched with good controllability by the dry etching process without limiting the structure of the device, and the GaN device. (Field effect transistor) can be manufactured.
  • a channel layer 102 composed of GaN is formed on the substrate 101 (first step).
  • a barrier layer 103 composed of AlGaN is formed on the channel layer 102 (second step). Therefore, as shown in FIG. 1C, an etching stop layer 104 composed of AlGaN is formed on the barrier layer 103 (third step).
  • a two-dimensional electron gas is formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103.
  • a cap layer 111 composed of GaN is formed on the etching stop layer 104 (fourth step).
  • the cap layer 111 is formed to have a thickness of, for example, about 3 nm.
  • the cap layer 111 is a layer for preventing natural oxidation of the surface of the layer of the nitride semiconductor containing Al.
  • the surface of the etching stop layer 104 penetrates the cap layer 111.
  • the exposed gate opening 112 is formed (fifth step).
  • a mask pattern is formed on the cap layer 111 by a known lithography technique, the formed mask pattern is used as a mask, and the cap layer 111 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the gate opening 112.
  • the etching by thermal decomposition described above is the same as that of the first embodiment described above.
  • the etching target (cap layer 111) is heated to a high temperature and the thermal decomposition of the GaN-based material is utilized. And proceed with etching.
  • the layer thickness of the cap layer 111 is as thin as 3 nm, it is desirable to adjust the etching conditions and reduce the etching rate of GaN. For example, the etching rate can be lowered by lowering the temperature during etching.
  • the etching stop layer 104 is preferably having a thickness of 1 nm or more because the controllability of the composition and the layer thickness is lowered when the thickness is made smaller than 1 nm.
  • the thickness of the etching stop layer 104 is determined from the viewpoint of reducing the influence of the etching stop layer 104 on the device characteristics. It is desirable that the content is equal to or less than that of the cap layer 111. Since the layer thicknesses of the etching stop layer 104 and the cap layer 111 are about the same, a sufficient overetching time can be taken and a flat surface morphology can be surely obtained.
  • the gate electric field by the gate electrode described later acts on the above-mentioned two-dimensional electron gas through the etching stop layer 104 remaining after the gate opening 112 is formed. It is important that the range is set.
  • the gate electrode 113 is formed on the etching stop layer 104 exposed to the gate opening 112 (sixth step). Further, the source electrode 114 and the drain electrode 115 are formed on the cap layer 111 on the side of the gate electrode 113. The source electrode 114 and the drain electrode 115 are formed so as to make ohmic contact with the two-dimensional electron gas formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103 (7th step). Further, an opening penetrating the cap layer 111 may be formed to expose the etching stop layer 104, and the source electrode 114 may be formed therein. Similarly, an opening penetrating the cap layer 111 may be formed to expose the etching stop layer 104, and the drain electrode 115 may be formed therein. A field effect transistor (high electron mobility transistor) can be obtained by the above manufacturing method.
  • the etching stop layer composed of AlGaN is used, the GaN is etched with good controllability by the dry etching process without limiting the structure of the device, and the GaN device (the GaN device). Field effect transistor) can be manufactured.
  • the first semiconductor layer 202, the etching stop layer 203, the second semiconductor layer 204, and the third semiconductor layer 205 are formed on the substrate 201 in this order (first step, step 1. 2nd step, 3rd step, 4th step).
  • the first semiconductor layer 202 is composed of a first conductive type (n type) GaN and has a thickness of 300 nm.
  • the first semiconductor layer 202 can be made of GaN having a high concentration of n-type.
  • the etching stop layer 203 is made of AlGaN.
  • the second semiconductor layer 204 is composed of the first conductive type GaN.
  • the second semiconductor layer 204 is composed of GaN having a low concentration of n-type and has a thickness of 3 ⁇ m.
  • the third semiconductor layer 205 is made of a second conductive type (p type) GaN. Since the thickness of the second semiconductor layer 204 affects the withstand voltage characteristic of the diode, it can be made thicker.
  • the second semiconductor layer 204 and the third semiconductor layer 205 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 3B, one of the etching stop layers 203.
  • the surface of the portion is exposed to form the electrode forming surface 206 (fifth step).
  • a mask pattern is formed on the third semiconductor layer 205 by a known lithography technique, the formed mask pattern is used as a mask, and the third semiconductor layer 205 and the second semiconductor layer 204 are etched by an etching process by thermal decomposition.
  • the mask pattern is removed after forming the electrode forming surface 206.
  • the first electrode 207 that makes ohmic contact with the first semiconductor layer 202 is formed on the electrode forming surface 206 of the etching stop layer 203 (sixth step). Further, a second electrode 208 that makes ohmic contact with the third semiconductor layer 205 is formed on the third semiconductor layer 205 (7th step).
  • the thickness of the etching stop layer 203 and the composition ratio of Al are within a range in which ohmic contact between the first electrode 207 and the first semiconductor layer 202 can be obtained after the electrode forming surface 206 is formed. is important.
  • the etching by thermal decomposition for forming the electrode forming surface 206 is the same as that of the first and second embodiments described above.
  • the etching stop layer 203 made of AlGaN is inserted in the place where it is originally composed of only GaN. Since it is difficult for AlGaN to function as a barrier against electrons when the Al composition is low, it is desirable that the etching stop layer 203 has a low Al composition.
  • the second semiconductor layer 204 on the etching stop layer 203 is as thick as 3 ⁇ m, and the etching process takes a long time, so that it is considered that the unevenness generated during the etching becomes large. Therefore, it is important to take a long overetching time in the etching stop layer 203 in order to obtain a flat surface.
  • the thickness of the etching stop layer 203 is designed.
  • the etching stop layer 203 having an Al composition of 5% is etched at 1 nm or more under these etching conditions. Therefore, it is desirable that the thickness of the etching stop layer 203 is 2 nm or more.
  • the thickness of the etching stop layer 203 should be as thick as several tens of nm in order to sufficiently reduce the influence of AlGaN. Is not desirable.
  • the etching stop layer 203 is exposed by an etching process in order to expose the surface of the first semiconductor layer 202 originally made of n + type GaN, and the first electrode 207 is formed therein. Therefore, it is desirable that the etching stop layer 203 is doped in the same degree as the first semiconductor layer 202. The effect of doping is considered to be small, and the above discussion is the same even when the etching stop layer 203 composed of n + type AlGaN is used.
  • the GaN device is etched with good controllability by the dry etching process without limiting the structure of the device.
  • a diode can be manufactured.
  • the first semiconductor layer 302, the etching stop layer 303, the second semiconductor layer 304, and the third semiconductor layer 305 are formed in this order on the substrate 301 (first step, step 1. 2nd step, 3rd step, 4th step).
  • the first semiconductor layer 302 is made of a first conductive type (n type) GaN and has a thickness of about 300 nm.
  • the first semiconductor layer 302 serves as a drain for the MOS transistor.
  • the etching stop layer 303 is made of AlGaN.
  • the second semiconductor layer 304 is made of a second conductive type (p type) GaN and has a thickness of about 500 nm.
  • the second semiconductor layer 304 is a region where a channel of a MOS transistor is formed.
  • the third semiconductor layer 305 is composed of a first conductive type (n type) GaN and has a thickness of about 300 nm.
  • the third semiconductor layer 305 serves as a source for the MOS transistor.
  • the second semiconductor layer 304 and the third semiconductor layer 305 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 4B, the second semiconductor layer 304 and An opening 306 that penetrates the third semiconductor layer 305 and reaches the etching stop layer 303 is formed (fifth step).
  • a mask pattern is formed on the third semiconductor layer 305 by a known lithography technique, the formed mask pattern is used as a mask, and the third semiconductor layer 305 and the second semiconductor layer 304 are etched by an etching process by thermal decomposition. The mask pattern is removed after forming the opening 306.
  • an insulating layer 307 covering the bottom surface and the side surface of the opening 306 is formed (sixth step).
  • the insulating layer 307 can be formed by depositing an insulating material to form an insulating film by a well-known deposition technique and then patterning the insulating film by a known lithography technique and etching technique.
  • a gate electrode 308 for applying a gate electric field to the channel is formed inside the opening 306 whose bottom surface and side surfaces are covered with the insulating layer 307 (7th step).
  • a mask pattern having an opening is formed in the gate electrode forming region, and the gate electrode material is deposited on the mask pattern.
  • the gate electrode 308 can be formed by leaving the gate electrode material in the gate forming region.
  • a drain electrode (not shown) electrically connected to the first semiconductor layer 302 is formed (step 8) and a source electrode (not shown) electrically connected to the third semiconductor layer 305 is formed (not shown).
  • a so-called trench type MOS transistor is obtained.
  • the substrate 301 is made of a conductive material (for example, conductive GaN)
  • the above-mentioned drain electrode can be formed on the back surface of the substrate 301.
  • each electrode can also be formed via a contact layer in which a predetermined impurity is introduced to a higher concentration to form a predetermined conductive type.
  • the thickness of the etching stop layer 303 and the composition ratio of Al are set within a range in which carriers can be moved between the channel and the first semiconductor layer 302 after the opening 306 is formed. is important.
  • the etching by thermal decomposition for forming the opening 306 is the same as that of the first and second embodiments described above.
  • the etching stop layer 303 made of AlGaN is inserted in the place where it is originally composed of only GaN. Since it is difficult for AlGaN to function as a barrier against electrons (carriers) when the Al composition is low, it is desirable that the etching stop layer 303 has a low Al composition.
  • the thickness of the GaN layer to be etched (the second semiconductor layer 304 and the third semiconductor layer 305) is 1 ⁇ m or less, and the unevenness generated during the etching of GaN is considered to be about several tens of nm.
  • the unevenness generated during the etching of GaN is considered to be about several tens of nm.
  • the etching stop layer 303 having a thickness of about 2 nm as in the above-described third embodiment. ..
  • the etching stop layer 303 is located above the first semiconductor layer 302 made of n-type GaN, the etching stop layer 303 is doped to etch the first semiconductor layer 302. The influence of using the stop layer 303 can be reduced.
  • the trench-type MOSFET may have a structure in which an etching stop layer 303a made of AlGaN is inserted in the middle of the source first semiconductor layer 302 in the thickness direction.
  • an etching stop layer 303a made of AlGaN is inserted in the middle of the source first semiconductor layer 302 in the thickness direction.
  • the first semiconductor layer 402, the etching stop layer 403, and the second semiconductor layer 404 are formed in this order on the substrate 401 (first step, second step, third step). Process).
  • the first semiconductor layer 402 is made of, for example, an n-type GaN and has a thickness of about 300 nm.
  • the etching stop layer 403 is made of AlGaN.
  • the second semiconductor layer 404 is composed of, for example, an n-type GaN and has a thickness of about 300 nm.
  • the etching stop layer penetrates the second semiconductor layer 404.
  • the opening 405 that reaches 403 is formed (fourth step).
  • a mask pattern is formed on the second semiconductor layer 404 by a known lithography technique, the formed mask pattern is used as a mask, and the second semiconductor layer 404 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the opening 405.
  • p-type GaN is re-grown on the etching stop layer 403 exposed to the opening 405 to form the third semiconductor layer 406 as shown in FIG. 5C.
  • the layer thickness for regrowth is 300 nm.
  • the layer thickness of the second semiconductor layer 404 to be etched is 300 nm, and the unevenness generated during etching by thermal decomposition of GaN is considered to be about several tens of nm.
  • the unevenness of about 50 nm is flattened by over-etching the etching stop layer 403, it is desirable that the thickness of the etching stop layer 403 is about 2 nm.
  • the etching stop layer 403 is arranged in the layer made of GaN, the influence of the insertion of the AlGaN layer into the layer made of GaN is reduced by doping the etching stop layer 403. can do.
  • etching by thermal decomposition can be carried out by the above-mentioned apparatus for growing the nitride semiconductor.
  • a growth apparatus that carries out metalorganic vapor phase growth
  • the third semiconductor layer 406 can be continuously regrown without being exposed to the atmosphere.
  • the GaN device is manufactured by etching GaN with good controllability by the dry etching process without limiting the structure of the device. become able to.

Abstract

According to the present invention, a gate pattern (106) is formed on top of an etching stop layer (104) by patterning a p-type semiconductor layer (105) by means of thermal decomposition etching wherein GaN is selectively decomposed over AlGaN. In the thermal decomposition etching, etching is carried out, for example, by utilizing thermal decomposition of a GaN-based material by heating the p-type semiconductor layer (105) to a high temperature in an NH3/H2 atmosphere. Since the energy required for thermal decomposition of AlGaN is larger than the energy required for thermal decomposition of GaN, GaN is able to be selectively etched over AlGaN with a high selectivity in the above-described etching process.

Description

半導体装置の製造方法Manufacturing method of semiconductor devices
　本発明は、ＧａＮを用いた半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device using GaN.
　現在のＧａＮデバイスの作製において、エッチングのプロセスでは、一般的に、塩素系のエッチングガスを用いた誘導結合型プラズマ反応性イオンエッチング（Inductively Coupled Plasma Reactive Ion Etching：ＩＣＰ－ＲＩＥ）が用いられている。しかしながら、塩素系のＩＣＰ－ＲＩＥでは、プラズマを使用したドライエッチングであり、エッチングの際にはバイアス電圧によってプラズマを試料表面へと導くこととなる。このプラズマによって、エッチング後に、エッチング対象のＧａＮ層の表面に欠陥の多いダメージ層が形成される。ダメージ層の厚さはバイアス電圧によって異なり、バイアス電圧が大きいほど厚いダメージ層が形成され、デバイスの特性を劣化させる。 In the current fabrication of GaN devices, inductively coupled plasma reactive ion etching (ICP-RIE) using a chlorine-based etching gas is generally used in the etching process. .. However, the chlorine-based ICP-RIE is dry etching using plasma, and the plasma is guided to the sample surface by the bias voltage at the time of etching. After etching, this plasma forms a damaged layer with many defects on the surface of the GaN layer to be etched. The thickness of the damage layer depends on the bias voltage, and the larger the bias voltage, the thicker the damage layer is formed, which deteriorates the characteristics of the device.
　また、このようなドライエッチングでは、エッチング対象のＧａＮ層の表面粗さが、ＧａＮ層の成長後の表面に比べて大きくなるという問題もある。このエッチング後の表面粗さは、成長直後のＧａＮ層の表面に比べて大きくなり、表面平坦性も劣化していることも分かっている（非特許文献１）。 Further, in such dry etching, there is also a problem that the surface roughness of the GaN layer to be etched becomes larger than the surface after the growth of the GaN layer. It is also known that the surface roughness after this etching is larger than that of the surface of the GaN layer immediately after growth, and the surface flatness is also deteriorated (Non-Patent Document 1).
　上述した問題を解決する技術として、多段バイアスエッチング技術が報告されている（非特許文献２）。この技術では、エッチング中にバイアス電圧を少しずつ下げていくことによって、高いバイアス電圧のエッチングで発生したダメージ層を除去し、かつ新たなダメージ層の形成を抑制しながらエッチングを進める。しかし、バイアス電圧を下げていくとエッチングレートが下がっていく。このため、複数のエッチングレートを調整しながらエッチングを進めることが必要となり、技術的な難しさを有している。 A multi-stage bias etching technique has been reported as a technique for solving the above-mentioned problems (Non-Patent Document 2). In this technique, the bias voltage is gradually lowered during etching to remove the damaged layer generated by etching with a high bias voltage, and the etching proceeds while suppressing the formation of a new damaged layer. However, as the bias voltage is lowered, the etching rate decreases. Therefore, it is necessary to proceed with etching while adjusting a plurality of etching rates, which is technically difficult.
　また、この種のドライエッチングでは、エッチング量の制御性が高くないことも問題となる。現在一般的なＩＣＰ－ＲＩＥのエッチングでは、エッチング量の制御を時間で行っている。これは、ＩＣＰ－ＲＩＥにおいて高選択比の選択エッチング技術が確立していないことによる。時間による制御では、エッチング処理ごとのバラつきが大きくなったり、ヘテロ接合界面でエッチングを止めることが難しかったりといった課題がある。 Another problem with this type of dry etching is that the controllability of the etching amount is not high. In the current general ICP-RIE etching, the etching amount is controlled by time. This is because a high selectivity selective etching technique has not been established in ICP-RIE. Control by time has problems such as large variation in each etching process and difficulty in stopping etching at the heterojunction interface.
　この課題を解決する技術として塩素系のエッチングガスに少量の酸素を加えることでＧａＮとＡｌＧａＮのエッチングレートの差を大きくし、選択比を上げる手法が報告されている（非特許文献３）。この技術では、ＧａＮとＡｌＧａＮとではＡｌＧａＮの方が酸化しやすく、またその酸化物のエッチングレートが小さいことを利用して、ＧａＮエッチングに対してＡｌＧａＮをエッチストップ層としている。 As a technique for solving this problem, a method has been reported in which a small amount of oxygen is added to a chlorine-based etching gas to increase the difference in etching rates between GaN and AlGaN and increase the selectivity (Non-Patent Document 3). In this technique, AlGaN is more easily oxidized than GaN and AlGaN, and AlGaN is used as an etch stop layer for GaN etching by utilizing the fact that the etching rate of the oxide is small.
　しかし、この技術は現在２８％と高いＡｌ組成のＡｌＧａＮを用いた報告しかない。Ａｌ組成の高いＡｌＧａＮは、ＧａＮを用いたデバイスの中で電子に対する大きなバリアとなってしまうため、このエッチストップ層を用いるデバイスの構造は大きく制限されてしまう。また、エッチストップ後のＡｌＧａＮ表面は、エッチングを抑制する層として酸化物で覆われており、エッチング後にフッ酸によって酸化物を除去することが必要である。 However, this technology is currently only reported using AlGaN with a high Al composition of 28%. AlGaN having a high Al composition becomes a large barrier to electrons in the device using GaN, so that the structure of the device using this etch stop layer is greatly limited. Further, the AlGaN surface after etching stop is covered with an oxide as a layer for suppressing etching, and it is necessary to remove the oxide with hydrofluoric acid after etching.
　上述したように、従来の技術では、ドライエッチング処理により、デバイスの構造を制限することなく、ＧａＮを制御性よくエッチングしてＧａＮデバイスを作製することが容易ではないという問題があった。 As described above, the conventional technique has a problem that it is not easy to manufacture a GaN device by etching GaN with good controllability without limiting the structure of the device by dry etching processing.
　本発明は、以上のような問題点を解消するためになされたものであり、デバイスの構造を制限することなく、ドライエッチング処理によりＧａＮを制御性よくエッチングしてＧａＮデバイスが作製できるようにすることを目的とする。 The present invention has been made to solve the above problems, and enables a GaN device to be manufactured by etching GaN with good controllability by a dry etching process without limiting the structure of the device. The purpose is.
　本発明に係る半導体装置は、基板の上にＧａＮから構成されたチャネル層を形成する第１工程と、チャネル層の上に、ＡｌＧａＮから構成された障壁層を形成する第２工程と、障壁層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第３工程と、エッチングストップ層の上にｐ型のＧａＮから構成されたｐ型半導体層を形成する第４工程と、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、ｐ型半導体層のパターニングにより、エッチングストップ層の上に、ゲートパターンを形成する第５工程と、ゲートパターンの上に配置されるゲート電極を形成する第６工程と、エッチングストップ層の上のゲートパターンの側方に、チャネル層と障壁層との界面近傍に形成される２次元電子ガスにオーミックコンタクトするソース電極およびドレイン電極を形成する第７工程とを備え、エッチングストップ層の厚さおよびＡｌの組成比は、ゲートパターンにより形成される空乏が２次元電子ガスに作用する範囲とされている。 The semiconductor device according to the present invention has a first step of forming a channel layer made of GaN on a substrate, a second step of forming a barrier layer made of AlGaN on the channel layer, and a barrier layer. A third step of forming an etching stop layer made of AlGaN on the top, a fourth step of forming a p-type semiconductor layer made of p-type GaN on the etching stop layer, and the case of AlGaN. A fifth step of forming a gate pattern on the etching stop layer by patterning a p-type semiconductor layer using etching by thermal decomposition that selectively decomposes GaN, and a gate electrode arranged on the gate pattern. On the side of the gate pattern on the etching stop layer, a source electrode and a drain electrode that make ohmic contact with the two-dimensional electron gas formed near the interface between the channel layer and the barrier layer are formed. The seventh step is provided, and the thickness of the etching stop layer and the composition ratio of Al are within the range in which the void formed by the gate pattern acts on the two-dimensional electron gas.
　本発明に係る半導体装置は、基板の上にＧａＮから構成されたチャネル層を形成する第１工程と、チャネル層の上に、ＡｌＧａＮから構成された障壁層を形成する第２工程と、障壁層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第３工程と、エッチングストップ層の上にＧａＮから構成されたキャップ層を形成する第４工程と、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、キャップ層のパターニングにより、キャップ層を貫通してエッチングストップ層の表面が露出するゲート開口を形成する第５工程と、ゲート開口に露出するエッチングストップ層の上に、ゲート電極を形成する第６工程と、エッチングストップ層の上のゲート電極の側方に、チャネル層と障壁層との界面近傍に形成される２次元電子ガスにオーミックコンタクトするソース電極およびドレイン電極を形成する第７工程とを備え、エッチングストップ層の厚さおよびＡｌの組成比は、ゲート電極によるゲート電界が２次元電子ガスに作用する範囲とされている。 The semiconductor device according to the present invention has a first step of forming a channel layer made of GaN on a substrate, a second step of forming a barrier layer made of AlGaN on the channel layer, and a barrier layer. A third step of forming an etching stop layer composed of AlGaN on the top, a fourth step of forming a cap layer composed of GaN on the etching stop layer, and selectively selecting GaN with respect to AlGaN. A fifth step of forming a gate opening that penetrates the cap layer and exposes the surface of the etching stop layer by patterning the cap layer using etching by thermal decomposition that decomposes, and above the etching stop layer that is exposed to the gate opening. In addition, the sixth step of forming the gate electrode, and the source electrode and drain that ohmically contact the two-dimensional electron gas formed near the interface between the channel layer and the barrier layer on the side of the gate electrode on the etching stop layer. A seventh step of forming an electrode is provided, and the thickness of the etching stop layer and the composition ratio of Al are within the range in which the gate electric field generated by the gate electrode acts on the two-dimensional electron gas.
　本発明に係る半導体装置は、基板の上に第１導電型のＧａＮから構成された第１半導体層を形成する第１工程と、第１半導体層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第２工程と、エッチングストップ層の上に第１導電型のＧａＮから構成された第２半導体層を形成する第３工程と、第２半導体層の上に第２導電型のＧａＮから構成された第３半導体層を形成する第４工程と、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、第２半導体層および第３半導体層のパターニングによりエッチングストップ層の一部の表面を露出させて電極形成面を形成する第５工程と、エッチングストップ層の電極形成面の上に、第１半導体層にオーミックコンタクトする第１電極を形成する第６工程と、第３半導体層の上に、第３半導体層にオーミックコンタクトする第２電極を形成する第７工程とを備え、エッチングストップ層の厚さおよびＡｌの組成比は、第１電極と第１半導体層とのオーミックコンタクトが得られる範囲とされている。 The semiconductor device according to the present invention has a first step of forming a first semiconductor layer made of a first conductive type GaN on a substrate, and an etching stop layer made of AlGaN on the first semiconductor layer. From the second step of forming the second semiconductor layer composed of the first conductive type GaN on the etching stop layer, and the second step of forming the second semiconductor layer composed of the first conductive type GaN on the second semiconductor layer. The etching stop layer is formed by patterning the second semiconductor layer and the third semiconductor layer using the fourth step of forming the configured third semiconductor layer and the etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN. A fifth step of exposing a part of the surface to form an electrode forming surface, a sixth step of forming a first electrode in ohmic contact with the first semiconductor layer on the electrode forming surface of the etching stop layer, and a third step. A seventh step of forming a second electrode that makes ohmic contact with the third semiconductor layer is provided on the three semiconductor layers, and the thickness of the etching stop layer and the composition ratio of Al are the same as those of the first electrode and the first semiconductor layer. It is said that the range where the ohmic contact can be obtained.
　本発明に係る半導体装置は、基板の上に第１導電型のＧａＮから構成されてドレインとなる第１半導体層を形成する第１工程と、第１半導体層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第２工程と、エッチングストップ層の上に第２導電型のＧａＮから構成されてチャネルが形成される第２半導体層を形成する第３工程と、第２半導体層の上に第１導電型のＧａＮから構成されてソースとなる第３半導体層を形成する第４工程と、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、第２半導体層および第３半導体層のパターニングにより、第２半導体層および第３半導体層を貫通してエッチングストップ層に到達する開口を形成する第５工程と、開口の底面および側面を覆う絶縁層を形成する第６工程と、絶縁層で底面および側面が覆われた開口の内部に、チャネルに対してゲート電界を作用させるためのゲート電極を形成する第７工程と、第１半導体層に電気的に接続するドレイン電極を形成する第８工程と、第３半導体層に電気的に接続するソース電極を形成する第９工程とを備え、エッチングストップ層の厚さおよびＡｌの組成比は、チャネルと第１半導体層との間のキャリアの移動が可能となる範囲とされている。 The semiconductor device according to the present invention is composed of a first step of forming a first semiconductor layer which is composed of a first conductive type GaN and serves as a drain on a substrate, and an AlGaN on the first semiconductor layer. The second step of forming the etching stop layer, the third step of forming the second semiconductor layer composed of the second conductive type GaN and forming the channel on the etching stop layer, and the upper part of the second semiconductor layer. The second semiconductor layer and the second semiconductor layer using the fourth step of forming the third semiconductor layer which is composed of the first conductive type GaN and the source, and the etching by thermal decomposition which selectively decomposes GaN with respect to AlGaN. A fifth step of forming an opening that penetrates the second semiconductor layer and the third semiconductor layer and reaches the etching stop layer by patterning the third semiconductor layer, and a sixth step of forming an insulating layer that covers the bottom surface and the side surface of the opening. The process, the seventh step of forming a gate electrode for applying a gate electric field to the channel inside the opening whose bottom surface and side surfaces are covered with an insulating layer, and the drain electrically connected to the first semiconductor layer. The eighth step of forming the electrode and the ninth step of forming the source electrode electrically connected to the third semiconductor layer are provided, and the thickness of the etching stop layer and the composition ratio of Al are the channel and the first semiconductor layer. It is said that it is within the range where the carrier can move between and.
　本発明に係る半導体装置は、基板の上にＧａＮから構成された第１半導体層を形成する第１工程と、第１半導体層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第２工程と、エッチングストップ層の上にＧａＮから構成された第２半導体層を形成する第３工程と、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、第２半導体層のパターニングにより、第２半導体層を貫通してエッチングストップ層に到達する開口を形成する第４工程と、開口に露出するエッチングストップ層の上に、ＧａＮを再成長させて第３半導体層を形成する第５工程とを備える。 The semiconductor device according to the present invention has a first step of forming a first semiconductor layer made of GaN on a substrate and a second step of forming an etching stop layer made of AlGaN on the first semiconductor layer. A second semiconductor layer using a step, a third step of forming a second semiconductor layer composed of GaN on an etching stop layer, and etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN. A fourth step of forming an opening that penetrates the second semiconductor layer and reaches the etching stop layer by patterning, and a third semiconductor layer is formed by regrowth of GaN on the etching stop layer exposed to the opening. It includes a fifth step.
　以上説明したように、本発明によれば、ＡｌＧａＮから構成されたエッチングストップ層を用いるので、デバイスの構造を制限することなく、ドライエッチング処理によりＧａＮを制御性よくエッチングしてＧａＮデバイスが作製できる。 As described above, according to the present invention, since the etching stop layer composed of AlGaN is used, the GaN device can be manufactured by etching GaN with good controllability by the dry etching process without limiting the structure of the device. ..
図１Ａは、本発明の実施の形態１に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 1A is a cross-sectional view showing a state of a semiconductor device in an intermediate process for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図１Ｂは、本発明の実施の形態１に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 1B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図１Ｃは、本発明の実施の形態１に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 1C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention. 図１Ｄは、本発明の実施の形態１に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 1D is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention. 図１Ｅは、本発明の実施の形態１に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 1E is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention. 図１Ｆは、本発明の実施の形態１に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 1F is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the first embodiment of the present invention. 図２Ａは、本発明の実施の形態２に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 2A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention. 図２Ｂは、本発明の実施の形態２に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 2B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the second embodiment of the present invention. 図２Ｃは、本発明の実施の形態２に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 2C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the second embodiment of the present invention. 図３Ａは、本発明の実施の形態３に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the third embodiment of the present invention. 図３Ｂは、本発明の実施の形態３に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 3B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the third embodiment of the present invention. 図４Ａは、本発明の実施の形態４に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 4A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention. 図４Ｂは、本発明の実施の形態４に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 4B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention. 図４Ｃは、本発明の実施の形態４に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 4C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention. 図４Ｄは、本発明の実施の形態４に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 4D is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention. 図４Ｅは、本発明の実施の形態４に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 4E is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention. 図５Ａは、本発明の実施の形態５に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 5A is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention. 図５Ｂは、本発明の実施の形態５に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 5B is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the manufacturing method of the semiconductor device according to the fifth embodiment of the present invention. 図５Ｃは、本発明の実施の形態５に係る半導体装置の製造方法を説明するための途中工程の半導体装置の状態を示す断面図である。FIG. 5C is a cross-sectional view showing a state of the semiconductor device in the intermediate process for explaining the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.
　以下、本発明の実施の形態に係る半導体装置の製造方法について説明する。 Hereinafter, a method for manufacturing a semiconductor device according to the embodiment of the present invention will be described.
［実施の形態１］
　はじめに、本発明の実施の形態１に係る半導体装置の製造方法について、図１Ａ～図１Ｆを参照して説明する。 [Embodiment 1]
First, a method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1F.
　まず、図１Ａに示すように、基板１０１の上にＧａＮから構成されたチャネル層１０２を形成する（第１工程）。なお、基板１０１とチャネル層１０２との間には、例えば核形成層となるＧａＮやＡｌＧａＮ、ＡｌＮ、ＡｌＯＮのうち１つ以上からなるバッファー層や、チャネル層のキャリアを閉じ込めるためのバックバリア層となるＡｌＧａＮやＩｎＧａＮからなる層、転位密度を低減するための超格子構造などを挿入することができる。 First, as shown in FIG. 1A, a channel layer 102 composed of GaN is formed on the substrate 101 (first step). Between the substrate 101 and the channel layer 102, for example, a buffer layer composed of one or more of GaN, AlGaN, AlN, and AlON as a nucleation layer, and a back barrier layer for confining carriers of the channel layer. A layer made of AlGaN or InGaN, a superlattice structure for reducing the dislocation density, and the like can be inserted.
　次いで、図１Ｂに示すように、チャネル層１０２の上に、ＡｌＧａＮから構成された障壁層１０３を形成する（第２工程）。ついて、図１Ｃに示すように、障壁層１０３の上に、ＡｌＧａＮから構成されたエッチングストップ層１０４を形成する（第３工程）。次いで、図１Ｄに示すように、エッチングストップ層１０４の上にｐ型のＧａＮから構成されたｐ型半導体層１０５を形成する（第４工程）。なお、よく知られているように、ｐ型不純物が導入されたＧａＮは、加熱処理により活性化することで、ｐ型のＧａＮとなる。 Next, as shown in FIG. 1B, a barrier layer 103 composed of AlGaN is formed on the channel layer 102 (second step). Therefore, as shown in FIG. 1C, an etching stop layer 104 composed of AlGaN is formed on the barrier layer 103 (third step). Next, as shown in FIG. 1D, a p-type semiconductor layer 105 composed of p-type GaN is formed on the etching stop layer 104 (fourth step). As is well known, GaN into which p-type impurities have been introduced becomes p-type GaN by being activated by heat treatment.
　基板１０１は、例えば、Ａｌ2Ｏ3（サファイア）から構成し、例えば、主表面の面方位を（０００１）とする。基板１０１は、ＧａＮ、ＡｌＧａＮ、およびＩｎＧａＮなどの窒化物半導体の結晶成長が実施できる材料から構成する。障壁層１０３は、例えば、Ａｌ組成は２５％程度としたＡｌＧａＮから構成し、層厚２０ｎｍ程度に形成する。ｐ型半導体層１０５は、例えば、層厚１００ｎｍ程度に形成する。 The substrate 101 is made of, for example, Al 2 O 3 (sapphire), and the plane orientation of the main surface is, for example, (0001). The substrate 101 is made of a material capable of crystal growth of a nitride semiconductor such as GaN, AlGaN, and InGaN. The barrier layer 103 is composed of, for example, AlGaN having an Al composition of about 25%, and is formed to have a layer thickness of about 20 nm. The p-type semiconductor layer 105 is formed, for example, to have a layer thickness of about 100 nm.
　エッチングストップ層１０４は、例えばＡｌ組成を５％とする。なお、エッチングストップ層１０４のＡｌ組成は、５％以上、あるいは５％以下とすることもできる。エッチングストップ層１０４のＡｌ組成によって、デバイス特性に与える影響が異なり、またエッチングの停止のための機能に必要な厚さも異なるため、デバイス設計時の注意を必要とする。 The etching stop layer 104 has, for example, an Al composition of 5%. The Al composition of the etching stop layer 104 can be 5% or more, or 5% or less. Since the influence on the device characteristics differs depending on the Al composition of the etching stop layer 104 and the thickness required for the function for stopping the etching also differs, care must be taken when designing the device.
　実施の形態１では、障壁層１０３の上に、組成の異なるＡｌＧａＮからなるエッチングストップ層１０４を配置している。このため、エッチングストップ層１０４のＡｌ組成を大きくする場合には、障壁層１０３の厚さにエッチングストップ層１０４の厚さを考慮した、ＡｌＧａＮからなる層の全体の厚さが、デバイス特性を決定することになる。エッチングストップ層１０４におけるＡｌの組成が小さければ、こうした影響をある程度無視することも可能である。 In the first embodiment, the etching stop layer 104 made of AlGaN having a different composition is arranged on the barrier layer 103. Therefore, when increasing the Al composition of the etching stop layer 104, the overall thickness of the layer made of AlGaN in consideration of the thickness of the barrier layer 103 and the thickness of the etching stop layer 104 determines the device characteristics. Will be done. If the composition of Al in the etching stop layer 104 is small, such an effect can be ignored to some extent.
　上述した各半導体層は、例えば、主表面をＩＩＩ族極性とした状態で（＋ｃ軸方向に）、これらの順にエピタキシャル成長する。ＧａＮなどの窒化物半導体は、安定相として六方晶ウルツ鉱構造となり、ｃ軸方向に分極が発生する。この効果を利用することで、チャネルとなる高濃度の２次元電子ガスを、チャネル層１０２と障壁層１０３との界面近傍に形成することができる。 Each semiconductor layer described above is epitaxially grown in this order, for example, with the main surface having group III polarity (in the + c-axis direction). Nitride semiconductors such as GaN have a hexagonal wurtzite structure as a stable phase, and polarization occurs in the c-axis direction. By utilizing this effect, a high-concentration two-dimensional electron gas serving as a channel can be formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103.
　上述した各層は、よく知られた有機金属気相成長法により形成することができる。各層は、また、上述した各半導体層は、分子線エピタキシ（ガスソース、ＲＦプラズマソース、レーザなどの分類があるがいずれでもよい）、ハイドライド気相成長方法などによって形成（エピタキシャル成長）することも可能である。 Each of the above-mentioned layers can be formed by the well-known metalorganic vapor phase growth method. Each layer can also be formed (epitaxially grown) by molecular beam epitaxy (which may be classified into gas source, RF plasma source, laser, etc.), hydride vapor phase growth method, etc., for each of the above-mentioned semiconductor layers. Is.
　次に、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用い、ｐ型半導体層１０５をパターニングすることで、図１Ｅに示すように、エッチングストップ層１０４の上に、ゲートパターン１０６を形成する（第５工程）。例えば、公知のリソグラフィー技術によりｐ型半導体層１０５の上にマスクパターン（不図示）を形成し、形成したマスクパターンをマスクとし、ｐ型半導体層１０５を熱分解によるエッチング処理によりエッチングする。マスクパターンは、ゲートパターン１０６を形成した後で除去する。 Next, by patterning the p-type semiconductor layer 105 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 1E, the gate pattern 106 is placed on the etching stop layer 104. (Fifth step). For example, a mask pattern (not shown) is formed on the p-type semiconductor layer 105 by a known lithography technique, the formed mask pattern is used as a mask, and the p-type semiconductor layer 105 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the gate pattern 106.
　上述した熱分解によるエッチングは、例えば、ＮＨ3／Ｈ2雰囲気において、エッチング対象（ｐ型半導体層１０５）を高温（例えば１０００℃）に加熱し、ＧａＮ系材料の熱分解を利用してエッチングを進める。ＧａＮの熱分解に要するエネルギーに対し、ＡｌＧａＮの熱分解に要するエネルギーが大きいため、上述したエッチング処理では、ＡｌＧａＮに対して高い選択比でＧａＮがエッチングできる。非特許文献４に示されるように、ＡｌＧａＮのＡｌ組成が５％程度あれば、ＧａＮとのエッチング選択比は１０2を超え、１０3に近い値が得られる。 In the above-mentioned etching by thermal decomposition, for example, in an NH 3 / H 2 atmosphere, the etching target (p-type semiconductor layer 105) is heated to a high temperature (for example, 1000 ° C.), and etching is performed by utilizing thermal decomposition of a GaN-based material. Proceed. Since the energy required for thermal decomposition of AlGaN is larger than the energy required for thermal decomposition of GaN, GaN can be etched with a high selectivity for AlGaN in the above-mentioned etching process. As shown in Non-Patent Document 4, if the Al composition of about 5% AlGaN, etching selectivity of the GaN exceeds 10 2, obtained a value close to 10 3.
　例えばＧａＮのエッチングレートを１０2ｎｍ／ｍｉｎ（非特許文献４では５×１０2ｎｍ／ｍｉｎ以上、発明者らの実験条件では１０ｎｍ／ｍｉｎ程度）とするような条件を選べば、Ａｌ組成５％のＡｌＧａＮのエッチングレートは１ｎｍ／ｍｉｎ以下になる。このため、厚さ１００ｎｍあるｐ型半導体層１０５の下に、Ａｌ組成５％のＡｌＧａＮからなる厚さ１ｎｍのエッチングストップ層１０４を設けると、エッチングストップ層１０４のオーバーエッチング時間を、ｐ型半導体層１０５の厚さ１００ｎｍをエッチングするのに要する時間（１分）程度取ることが可能になり、エッチングで生じる表面の凹凸を完全に平坦化することができる。 For example, if the etching rate of GaN is selected to be 10 2 nm / min (5 × 10 2 nm / min or more in Non-Patent Document 4, and about 10 nm / min under the experimental conditions of the inventors), the Al composition 5 The etching rate of% AlGaN is 1 nm / min or less. Therefore, if an etching stop layer 104 having a thickness of 1 nm made of AlGaN having an Al composition of 5% is provided under the p-type semiconductor layer 105 having a thickness of 100 nm, the overetching time of the etching stop layer 104 can be set to the p-type semiconductor layer. It is possible to take about the time (1 minute) required for etching the thickness of 105 of 100 nm, and it is possible to completely flatten the unevenness of the surface caused by the etching.
　ｐ型半導体層１０５の厚さが１００ｎｍより大きい場合には、エッチングに要する時間が増え、かつエッチング中に生じる凹凸も大きくなる。このため、エッチングストップ層１０４で平坦な表面を得るためには、オーバーエッチング時間を増やす必要があり、エッチングストップ層１０４を厚くする必要がある。ただし、ｐ型半導体層１０５の層厚に比例してエッチングストップ層１０４の層厚を増やす必要はない。 When the thickness of the p-type semiconductor layer 105 is larger than 100 nm, the time required for etching increases and the unevenness generated during etching also increases. Therefore, in order to obtain a flat surface in the etching stop layer 104, it is necessary to increase the overetching time, and it is necessary to make the etching stop layer 104 thicker. However, it is not necessary to increase the layer thickness of the etching stop layer 104 in proportion to the layer thickness of the p-type semiconductor layer 105.
　エッチング中に生じる凹凸は、エッチング条件によってサイズが大きく異なるため、平坦化に要するオーバーエッチング時間は条件によっても変化する。このため、ｐ型半導体層１０５を５００ｎｍエッチングするために、Ａｌ組成５％としたエッチングストップ層１０４の厚さが５ｎｍ必要となるわけではない。同様に、エッチングされるｐ型半導体層１０５が薄くなれば、オーバーエッチング時間が短くて済むため、エッチングストップ層１０４を更に薄くすることが可能である。しかしながら、１ｎｍを下回るエッチングストップ層１０４は組成や層厚の制御が困難になることから、１ｎｍ以下の層厚でエッチングストップ層１０４を用いることは望ましくない。 Since the size of the unevenness generated during etching varies greatly depending on the etching conditions, the overetching time required for flattening also changes depending on the conditions. Therefore, in order to etch the p-type semiconductor layer 105 at 500 nm, the thickness of the etching stop layer 104 having an Al composition of 5% is not required to be 5 nm. Similarly, if the p-type semiconductor layer 105 to be etched becomes thinner, the overetching time can be shortened, so that the etching stop layer 104 can be further thinned. However, it is not desirable to use the etching stop layer 104 with a layer thickness of 1 nm or less because it is difficult to control the composition and the layer thickness of the etching stop layer 104 having a thickness of less than 1 nm.
　なお、エッチングストップ層１０４の組成や厚さは、エッチングされるｐ型半導体層１０５の厚さやエッチング条件によって決定されるものである。ただし、エッチングストップ層１０４の厚さおよびＡｌの組成比は、ゲートパターン１０６が形成された後に残るエッチングストップ層１０４を介して、ゲートパターン１０６により形成される空乏が、上述した２次元電子ガスに作用する範囲とされていることが重要となる。 The composition and thickness of the etching stop layer 104 are determined by the thickness and etching conditions of the p-type semiconductor layer 105 to be etched. However, regarding the thickness of the etching stop layer 104 and the composition ratio of Al, the depletion formed by the gate pattern 106 via the etching stop layer 104 remaining after the gate pattern 106 is formed becomes the above-mentioned two-dimensional electron gas. It is important that it is within the range of action.
　次に、図１Ｆに示すように、ゲートパターン１０６の上に配置されるゲート電極１０７を形成する（第６工程）。ゲート電極１０７は、ゲートパターン１０６を形成した後に形成することができる。なお、ｐ型半導体層１０５の上にゲート電極１０７を形成し、ゲート電極１０７をマスクとして、上述したｐ型半導体層１０５のパターニングを実施し、ゲートパターン１０６を形成することもできる。ゲート電極１０７は、最終的にゲートパターン１０６の上に配置される状態に形成されるものである。 Next, as shown in FIG. 1F, the gate electrode 107 arranged on the gate pattern 106 is formed (sixth step). The gate electrode 107 can be formed after the gate pattern 106 is formed. It is also possible to form the gate electrode 107 on the p-type semiconductor layer 105 and use the gate electrode 107 as a mask to carry out the patterning of the p-type semiconductor layer 105 described above to form the gate pattern 106. The gate electrode 107 is finally formed so as to be arranged on the gate pattern 106.
　また、エッチングストップ層１０４の上のゲートパターン１０６の側方に、チャネル層１０２と障壁層１０３との界面近傍に形成される２次元電子ガスにオーミックコンタクトするソース電極１０８およびドレイン電極１０９を形成する（第７工程）。なお、ソース電極１０８およびドレイン電極１０９を、２次元電子ガスにオーミックコンタクトさせるために、一般に加熱処理が実施される。この場合、ゲートパターン１０６を形成し、次いで、ソース電極１０８およびドレイン電極１０９を形成して上述した加熱処理を実施し、この後、ゲート電極１０７を形成することができる。オーミックコンタクトのための加熱処理の後にゲート電極１０７を形成することで、加熱処理によるゲート電極１０７への影響が防げる。以上の製造方法により、ノーマリーオフの電界効果トランジスタ（高電子移動度トランジスタ）が得られる。 Further, on the side of the gate pattern 106 on the etching stop layer 104, a source electrode 108 and a drain electrode 109 that make ohmic contact with the two-dimensional electron gas formed near the interface between the channel layer 102 and the barrier layer 103 are formed. (7th step). In order to make the source electrode 108 and the drain electrode 109 ohmic contact with the two-dimensional electron gas, heat treatment is generally performed. In this case, the gate pattern 106 can be formed, then the source electrode 108 and the drain electrode 109 can be formed and the above-mentioned heat treatment can be performed, and then the gate electrode 107 can be formed. By forming the gate electrode 107 after the heat treatment for ohmic contact, the influence of the heat treatment on the gate electrode 107 can be prevented. By the above manufacturing method, a normally-off field effect transistor (high electron mobility transistor) can be obtained.
　以上に説明したように、実施の形態１によれば、ＡｌＧａＮから構成されたエッチングストップ層を用いるので、デバイスの構造を制限することなく、ドライエッチング処理によりＧａＮを制御性よくエッチングしてＧａＮデバイス（電界効果トランジスタ）が作製できる。 As described above, according to the first embodiment, since the etching stop layer composed of AlGaN is used, the GaN is etched with good controllability by the dry etching process without limiting the structure of the device, and the GaN device. (Field effect transistor) can be manufactured.
［実施の形態２］
　次に、本発明の実施の形態１に係る半導体装置の製造方法について、図１Ａ～図１Ｃ，図２Ａ～図２Ｂを参照して説明する。 [Embodiment 2]
Next, a method of manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1C and FIGS. 2A to 2B.
　まず、図１Ａに示すように、基板１０１の上にＧａＮから構成されたチャネル層１０２を形成する（第１工程）。次いで、図１Ｂに示すように、チャネル層１０２の上に、ＡｌＧａＮから構成された障壁層１０３を形成する（第２工程）。ついて、図１Ｃに示すように、障壁層１０３の上に、ＡｌＧａＮから構成されたエッチングストップ層１０４を形成する（第３工程）。これらの工程は、前述した実施の形態１と同様である。チャネル層１０２と障壁層１０３との界面近傍には、２次元電子ガスが形成される。 First, as shown in FIG. 1A, a channel layer 102 composed of GaN is formed on the substrate 101 (first step). Next, as shown in FIG. 1B, a barrier layer 103 composed of AlGaN is formed on the channel layer 102 (second step). Therefore, as shown in FIG. 1C, an etching stop layer 104 composed of AlGaN is formed on the barrier layer 103 (third step). These steps are the same as those in the first embodiment described above. A two-dimensional electron gas is formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103.
　次に、図２Ａに示すように、エッチングストップ層１０４の上にＧａＮから構成されたキャップ層１１１を形成する（第４工程）。キャップ層１１１は、例えば、厚さ３ｎｍ程度に形成する。キャップ層１１１は、Ａｌを含む窒化物半導体の層の表面の自然酸化などを防止するための層である。 Next, as shown in FIG. 2A, a cap layer 111 composed of GaN is formed on the etching stop layer 104 (fourth step). The cap layer 111 is formed to have a thickness of, for example, about 3 nm. The cap layer 111 is a layer for preventing natural oxidation of the surface of the layer of the nitride semiconductor containing Al.
　次に、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、キャップ層１１１のパターニングにより、図２Ｂに示すように、キャップ層１１１を貫通してエッチングストップ層１０４の表面が露出するゲート開口１１２を形成する（第５工程）。例えば、公知のリソグラフィー技術によりキャップ層１１１の上にマスクパターンを形成し、形成したマスクパターンをマスクとし、キャップ層１１１を熱分解によるエッチング処理によりエッチングする。マスクパターンは、ゲート開口１１２を形成した後で除去する。 Next, by patterning the cap layer 111 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 2B, the surface of the etching stop layer 104 penetrates the cap layer 111. The exposed gate opening 112 is formed (fifth step). For example, a mask pattern is formed on the cap layer 111 by a known lithography technique, the formed mask pattern is used as a mask, and the cap layer 111 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the gate opening 112.
　上述した熱分解によるエッチングは、前述した実施の形態１と同様であり、例えば、ＮＨ3／Ｈ2雰囲気において、エッチング対象（キャップ層１１１）を高温に加熱し、ＧａＮ系材料の熱分解を利用してエッチングを進める。 The etching by thermal decomposition described above is the same as that of the first embodiment described above. For example, in an NH 3 / H 2 atmosphere, the etching target (cap layer 111) is heated to a high temperature and the thermal decomposition of the GaN-based material is utilized. And proceed with etching.
　ただし、実施の形態２では、キャップ層１１１の層厚が３ｎｍと薄いため、エッチング条件を調整し、ＧａＮのエッチングレートを下げることが望ましい。例えば、エッチング中の温度を下げることで、エッチングレートを下げることができる。エッチングストップ層１０４は、実施の形態１の説明でも示したように、厚さを１ｎｍより薄くすると組成や層厚の制御性が低下することから、厚さ１ｎｍ以上であることが望ましい。 However, in the second embodiment, since the layer thickness of the cap layer 111 is as thin as 3 nm, it is desirable to adjust the etching conditions and reduce the etching rate of GaN. For example, the etching rate can be lowered by lowering the temperature during etching. As shown in the description of the first embodiment, the etching stop layer 104 is preferably having a thickness of 1 nm or more because the controllability of the composition and the layer thickness is lowered when the thickness is made smaller than 1 nm.
　実施の形態２では、エッチング対象のキャップ層１１１の厚さが３ｎｍ程度と薄いことから、デバイス特性へのエッチングストップ層１０４の影響を小さくするという観点からも、エッチングストップ層１０４の厚さは、キャップ層１１１と同程度かそれ以下とすることが望ましい。エッチングストップ層１０４とキャップ層１１１の層厚が同程度になるため、オーバーエッチング時間を十分に取り、確実に平坦な表面モフォロジーを得ることができる。 In the second embodiment, since the thickness of the cap layer 111 to be etched is as thin as about 3 nm, the thickness of the etching stop layer 104 is determined from the viewpoint of reducing the influence of the etching stop layer 104 on the device characteristics. It is desirable that the content is equal to or less than that of the cap layer 111. Since the layer thicknesses of the etching stop layer 104 and the cap layer 111 are about the same, a sufficient overetching time can be taken and a flat surface morphology can be surely obtained.
　なお、エッチングストップ層１０４の厚さおよびＡｌの組成比は、ゲート開口１１２が形成された後に残るエッチングストップ層１０４を介して、後述するゲート電極によるゲート電界が、上述した２次元電子ガスに作用する範囲とされていることが重要となる。 Regarding the thickness of the etching stop layer 104 and the composition ratio of Al, the gate electric field by the gate electrode described later acts on the above-mentioned two-dimensional electron gas through the etching stop layer 104 remaining after the gate opening 112 is formed. It is important that the range is set.
　次に、図２Ｃに示すように、ゲート開口１１２に露出するエッチングストップ層１０４の上に、ゲート電極１１３を形成する（第６工程）。また、ゲート電極１１３の側方のキャップ層１１１の上に、ソース電極１１４およびドレイン電極１１５を形成する。ソース電極１１４およびドレイン電極１１５は、チャネル層１０２と障壁層１０３との界面近傍に形成される２次元電子ガスにオーミックコンタクトするように形成する（第７工程）。また、キャップ層１１１を貫通する開口を形成してエッチングストップ層１０４を露出させ、ここにソース電極１１４を形成することもできる。同様に、キャップ層１１１を貫通する開口を形成してエッチングストップ層１０４を露出させ、ここにドレイン電極１１５を形成することもできる。以上の製造方法により、電界効果トランジスタ（高電子移動度トランジスタ）が得られる。 Next, as shown in FIG. 2C, the gate electrode 113 is formed on the etching stop layer 104 exposed to the gate opening 112 (sixth step). Further, the source electrode 114 and the drain electrode 115 are formed on the cap layer 111 on the side of the gate electrode 113. The source electrode 114 and the drain electrode 115 are formed so as to make ohmic contact with the two-dimensional electron gas formed in the vicinity of the interface between the channel layer 102 and the barrier layer 103 (7th step). Further, an opening penetrating the cap layer 111 may be formed to expose the etching stop layer 104, and the source electrode 114 may be formed therein. Similarly, an opening penetrating the cap layer 111 may be formed to expose the etching stop layer 104, and the drain electrode 115 may be formed therein. A field effect transistor (high electron mobility transistor) can be obtained by the above manufacturing method.
　以上に説明したように、実施の形態２においても、ＡｌＧａＮから構成されたエッチングストップ層を用いるので、デバイスの構造を制限することなく、ドライエッチング処理によりＧａＮを制御性よくエッチングしてＧａＮデバイス（電界効果トランジスタ）が作製できる。 As described above, also in the second embodiment, since the etching stop layer composed of AlGaN is used, the GaN is etched with good controllability by the dry etching process without limiting the structure of the device, and the GaN device (the GaN device). Field effect transistor) can be manufactured.
［実施の形態３］
　次に、本発明の実施の形態３に係る半導体装置の製造方法について、図３Ａ，図３Ｂを参照して説明する。以下では、半導体装置して、ダイオードを例に説明する。 [Embodiment 3]
Next, a method of manufacturing the semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 3A and 3B. In the following, a semiconductor device will be described using a diode as an example.
　まず、図３Ａに示すように、基板２０１の上に、第１半導体層２０２、エッチングストップ層２０３、第２半導体層２０４、および第３半導体層２０５を、これらの順に形成する（第１工程、第２工程、第３工程、第４工程）。第１半導体層２０２は、第１導電型（ｎ型）のＧａＮから構成され、厚さ３００ｎｍである。第１半導体層２０２は、高濃度にｎ型とされたＧａＮから構成することができる。 First, as shown in FIG. 3A, the first semiconductor layer 202, the etching stop layer 203, the second semiconductor layer 204, and the third semiconductor layer 205 are formed on the substrate 201 in this order (first step, step 1. 2nd step, 3rd step, 4th step). The first semiconductor layer 202 is composed of a first conductive type (n type) GaN and has a thickness of 300 nm. The first semiconductor layer 202 can be made of GaN having a high concentration of n-type.
　エッチングストップ層２０３は、ＡｌＧａＮから構成されている。第２半導体層２０４は、第１導電型のＧａＮから構成されている。第２半導体層２０４は、低濃度にｎ型とされたＧａＮから構成され、厚さ３μｍである。第３半導体層２０５は、第２導電型（ｐ型）のＧａＮから構成されている。第２半導体層２０４の厚さは、ダイオードの耐圧特性に影響するため、より厚くすることもできる。 The etching stop layer 203 is made of AlGaN. The second semiconductor layer 204 is composed of the first conductive type GaN. The second semiconductor layer 204 is composed of GaN having a low concentration of n-type and has a thickness of 3 μm. The third semiconductor layer 205 is made of a second conductive type (p type) GaN. Since the thickness of the second semiconductor layer 204 affects the withstand voltage characteristic of the diode, it can be made thicker.
　次に、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、第２半導体層２０４および第３半導体層２０５のパターニングにより、図３Ｂに示すように、エッチングストップ層２０３の一部の表面を露出させて、電極形成面２０６を形成する（第５工程）。例えば、公知のリソグラフィー技術により第３半導体層２０５の上にマスクパターンを形成し、形成したマスクパターンをマスクとし、第３半導体層２０５および第２半導体層２０４を熱分解によるエッチング処理によりエッチングする。マスクパターンは、電極形成面２０６を形成した後で除去する。 Next, by patterning the second semiconductor layer 204 and the third semiconductor layer 205 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 3B, one of the etching stop layers 203. The surface of the portion is exposed to form the electrode forming surface 206 (fifth step). For example, a mask pattern is formed on the third semiconductor layer 205 by a known lithography technique, the formed mask pattern is used as a mask, and the third semiconductor layer 205 and the second semiconductor layer 204 are etched by an etching process by thermal decomposition. The mask pattern is removed after forming the electrode forming surface 206.
　次いで、エッチングストップ層２０３の電極形成面２０６の上に、第１半導体層２０２にオーミックコンタクトする第１電極２０７を形成する（第６工程）。また、第３半導体層２０５の上に、第３半導体層２０５にオーミックコンタクトする第２電極２０８を形成する（第７工程）。 Next, the first electrode 207 that makes ohmic contact with the first semiconductor layer 202 is formed on the electrode forming surface 206 of the etching stop layer 203 (sixth step). Further, a second electrode 208 that makes ohmic contact with the third semiconductor layer 205 is formed on the third semiconductor layer 205 (7th step).
　ここで、エッチングストップ層２０３の厚さおよびＡｌの組成比は、電極形成面２０６を形成した後において、第１電極２０７と第１半導体層２０２とのオーミックコンタクトが得られる範囲とされていることが重要である。 Here, the thickness of the etching stop layer 203 and the composition ratio of Al are within a range in which ohmic contact between the first electrode 207 and the first semiconductor layer 202 can be obtained after the electrode forming surface 206 is formed. is important.
　実施の形態３において、電極形成面２０６の形成のための熱分解によるエッチングは、前述した実施の形態１，２と同様である。ただし、この例で示す半導体装置（ダイオード）では、本来、ＧａＮのみで構成されるところに、ＡｌＧａＮからなるエッチングストップ層２０３を挿入している。ＡｌＧａＮは、Ａｌ組成が低い方が電子に対してバリアとして機能しにくいことから、エッチングストップ層２０３は、低Ａｌ組成である方が望ましい。 In the third embodiment, the etching by thermal decomposition for forming the electrode forming surface 206 is the same as that of the first and second embodiments described above. However, in the semiconductor device (diode) shown in this example, the etching stop layer 203 made of AlGaN is inserted in the place where it is originally composed of only GaN. Since it is difficult for AlGaN to function as a barrier against electrons when the Al composition is low, it is desirable that the etching stop layer 203 has a low Al composition.
　また、実施の形態３では、エッチングストップ層２０３の上の第２半導体層２０４が、厚さ３μｍと厚く、エッチング処理の時間が長くなるため、エッチング中に生じる凹凸が大きくなると考えられる。このため、エッチングストップ層２０３でのオーバーエッチング時間を長めに取ることが平坦な表面を得るために重要となる。発明者らの実験では、厚さ１μｍ程度のＧａＮの層をエッチングした際に、数十ｎｍ程度の凹凸が観察されており、厚さ３μｍのエッチングでは、１００ｎｍ程度の凹凸が生じると推定される。これらのことを考慮して、エッチングストップ層２０３の厚さを設計する。 Further, in the third embodiment, the second semiconductor layer 204 on the etching stop layer 203 is as thick as 3 μm, and the etching process takes a long time, so that it is considered that the unevenness generated during the etching becomes large. Therefore, it is important to take a long overetching time in the etching stop layer 203 in order to obtain a flat surface. In the experiments of the inventors, when a GaN layer having a thickness of about 1 μm was etched, unevenness of about several tens of nm was observed, and it is estimated that etching of a thickness of 3 μm causes unevenness of about 100 nm. .. Taking these things into consideration, the thickness of the etching stop layer 203 is designed.
　ＧａＮのエッチングレートを１０2ｎｍ／ｍｉｎとした場合には、ＧａＮの凹凸を消すためには１分以上のオーバーエッチングが必要である。１分以上のオーバーエッチングを実施した場合、このエッチング条件ではＡｌ組成５％のエッチングストップ層２０３が１ｎｍ以上はエッチングされるため、エッチングストップ層２０３の厚さは２ｎｍ以上としておくことが望ましい。一方で、ＧａＮで構成されるデバイスに、ＡｌＧａＮの層を挿入する形を取ることから、ＡｌＧａＮの影響を十分に小さくするためにもエッチングストップ層２０３の厚さは、数十ｎｍと厚くすることは望ましくない。 When the GaN etching rate and 10 2 nm / min, the to erase GaN of irregularities it is required more than one minute over-etching. When over-etching is performed for 1 minute or more, the etching stop layer 203 having an Al composition of 5% is etched at 1 nm or more under these etching conditions. Therefore, it is desirable that the thickness of the etching stop layer 203 is 2 nm or more. On the other hand, since the AlGaN layer is inserted into the device composed of GaN, the thickness of the etching stop layer 203 should be as thick as several tens of nm in order to sufficiently reduce the influence of AlGaN. Is not desirable.
　実施の形態３では、本来、ｎ+型のＧａＮによる第１半導体層２０２の表面を露出させるためエッチング処理で、エッチングストップ層２０３を露出させ、ここに第１電極２０７を形成している。このため、エッチングストップ層２０３に、第１半導体層２０２と同程度のドーピングを実施することが望ましい。ドーピングによる影響は小さいと考えられ、上記の議論は、ｎ+型ＡｌＧａＮから構成したエッチングストップ層２０３を用いても同様である。 In the third embodiment, the etching stop layer 203 is exposed by an etching process in order to expose the surface of the first semiconductor layer 202 originally made of n + type GaN, and the first electrode 207 is formed therein. Therefore, it is desirable that the etching stop layer 203 is doped in the same degree as the first semiconductor layer 202. The effect of doping is considered to be small, and the above discussion is the same even when the etching stop layer 203 composed of n + type AlGaN is used.
　以上に説明したように、実施の形態３においても、ＡｌＧａＮから構成されたエッチングストップ層を用いるので、デバイスの構造を制限することなく、ドライエッチング処理によりＧａＮを制御性よくエッチングしてＧａＮデバイス（ダイオード）が作製できる。 As described above, also in the third embodiment, since the etching stop layer composed of AlGaN is used, the GaN device is etched with good controllability by the dry etching process without limiting the structure of the device. A diode) can be manufactured.
［実施の形態４］
　次に、本発明の実施の形態４に係る半導体装置の製造方法について、図４Ａ～図４Ｅを参照して説明する。以下では、半導体装置して、ＭＯＳトランジスタを例に説明する。 [Embodiment 4]
Next, a method of manufacturing the semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIGS. 4A to 4E. Hereinafter, a MOS transistor will be described as an example of a semiconductor device.
　まず、図４Ａに示すように、基板３０１の上に、第１半導体層３０２、エッチングストップ層３０３、第２半導体層３０４、および第３半導体層３０５を、これらの順に形成する（第１工程、第２工程、第３工程、第４工程）。第１半導体層３０２は、第１導電型（ｎ型）のＧａＮから構成され、厚さ３００ｎｍ程度である。第１半導体層３０２は、ＭＯＳトランジスタのドレインとなる。 First, as shown in FIG. 4A, the first semiconductor layer 302, the etching stop layer 303, the second semiconductor layer 304, and the third semiconductor layer 305 are formed in this order on the substrate 301 (first step, step 1. 2nd step, 3rd step, 4th step). The first semiconductor layer 302 is made of a first conductive type (n type) GaN and has a thickness of about 300 nm. The first semiconductor layer 302 serves as a drain for the MOS transistor.
　エッチングストップ層３０３は、ＡｌＧａＮから構成されている。第２半導体層３０４は、第２導電型（ｐ型）のＧａＮから構成され、厚さ５００ｎｍ程度である。第２半導体層３０４は、ＭＯＳトランジスタのチャネルが形成される領域となる。第３半導体層３０５は、第１導電型（ｎ型）のＧａＮから構成され、厚さ３００ｎｍ程度である。第３半導体層３０５は、ＭＯＳトランジスタのソースとなる。 The etching stop layer 303 is made of AlGaN. The second semiconductor layer 304 is made of a second conductive type (p type) GaN and has a thickness of about 500 nm. The second semiconductor layer 304 is a region where a channel of a MOS transistor is formed. The third semiconductor layer 305 is composed of a first conductive type (n type) GaN and has a thickness of about 300 nm. The third semiconductor layer 305 serves as a source for the MOS transistor.
　次に、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、第２半導体層３０４および第３半導体層３０５のパターニングにより、図４Ｂに示すように、第２半導体層３０４および第３半導体層３０５を貫通してエッチングストップ層３０３に到達する開口３０６を形成する（第５工程）。 Next, by patterning the second semiconductor layer 304 and the third semiconductor layer 305 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 4B, the second semiconductor layer 304 and An opening 306 that penetrates the third semiconductor layer 305 and reaches the etching stop layer 303 is formed (fifth step).
 例えば、公知のリソグラフィー技術により第３半導体層３０５の上にマスクパターンを形成し、形成したマスクパターンをマスクとし、第３半導体層３０５および第２半導体層３０４を熱分解によるエッチング処理によりエッチングする。マスクパターンは、開口３０６を形成した後で除去する。 For example, a mask pattern is formed on the third semiconductor layer 305 by a known lithography technique, the formed mask pattern is used as a mask, and the third semiconductor layer 305 and the second semiconductor layer 304 are etched by an etching process by thermal decomposition. The mask pattern is removed after forming the opening 306.
　次に、図４Ｃに示すように、開口３０６の底面および側面を覆う絶縁層３０７を形成する（第６工程）。例えば、よく知られた堆積技術により、絶縁材料を堆積して絶縁膜を形成した後、この絶縁膜を、公知のリソグラフィー技術およびエッチング技術によりパターニングすることで、絶縁層３０７が形成できる。 Next, as shown in FIG. 4C, an insulating layer 307 covering the bottom surface and the side surface of the opening 306 is formed (sixth step). For example, the insulating layer 307 can be formed by depositing an insulating material to form an insulating film by a well-known deposition technique and then patterning the insulating film by a known lithography technique and etching technique.
　次に、図４Ｄに示すように、絶縁層３０７で底面および側面が覆われた開口３０６の内部に、チャネルに対してゲート電界を作用させるためのゲート電極３０８を形成する（第７工程）。例えば、ゲート電極形成領域に開口を備えるマスクパターンを形成し、この上からゲート電極材料を堆積する。この後、マスクパターンを除去（リフトオフ）することで、ゲート形成領域にゲート電極材料を残せば、ゲート電極３０８が形成できる。また、第１半導体層３０２に電気的に接続するドレイン電極（不図示）を形成し（第８工程）、第３半導体層３０５に電気的に接続するソース電極（不図示）を形成すれば（第９工程）、いわゆるトレンチ型のＭＯＳトランジスタが得られる。例えば、基板３０１を導電性材料（例えば導電性のＧａＮ）から構成すれば、基板３０１の裏面に上述したドレイン電極を形成することができる。また、各電極は、より高濃度に所定の不純物が導入されて所定の導電型とされたコンタクト層を介して形成することもできる。 Next, as shown in FIG. 4D, a gate electrode 308 for applying a gate electric field to the channel is formed inside the opening 306 whose bottom surface and side surfaces are covered with the insulating layer 307 (7th step). For example, a mask pattern having an opening is formed in the gate electrode forming region, and the gate electrode material is deposited on the mask pattern. After that, by removing (lifting off) the mask pattern, the gate electrode 308 can be formed by leaving the gate electrode material in the gate forming region. Further, if a drain electrode (not shown) electrically connected to the first semiconductor layer 302 is formed (step 8) and a source electrode (not shown) electrically connected to the third semiconductor layer 305 is formed (not shown). 9th step), a so-called trench type MOS transistor is obtained. For example, if the substrate 301 is made of a conductive material (for example, conductive GaN), the above-mentioned drain electrode can be formed on the back surface of the substrate 301. Further, each electrode can also be formed via a contact layer in which a predetermined impurity is introduced to a higher concentration to form a predetermined conductive type.
　ここで、エッチングストップ層３０３の厚さおよびＡｌの組成比は、開口３０６を形成した後において、チャネルと第１半導体層３０２との間のキャリアの移動が可能となる範囲とされていることが重要である。 Here, the thickness of the etching stop layer 303 and the composition ratio of Al are set within a range in which carriers can be moved between the channel and the first semiconductor layer 302 after the opening 306 is formed. is important.
　実施の形態３において、開口３０６の形成のための熱分解によるエッチングは、前述した実施の形態１，２と同様である。ただし、この例で示す半導体装置（ＭＯＳトランジスタ）では、本来、ＧａＮのみで構成されるところに、ＡｌＧａＮからなるエッチングストップ層３０３を挿入している。ＡｌＧａＮは、Ａｌ組成が低い方が電子（キャリア）に対してバリアとして機能しにくいことから、エッチングストップ層３０３は、低Ａｌ組成である方が望ましい。 In the third embodiment, the etching by thermal decomposition for forming the opening 306 is the same as that of the first and second embodiments described above. However, in the semiconductor device (MOS transistor) shown in this example, the etching stop layer 303 made of AlGaN is inserted in the place where it is originally composed of only GaN. Since it is difficult for AlGaN to function as a barrier against electrons (carriers) when the Al composition is low, it is desirable that the etching stop layer 303 has a low Al composition.
　実施の形態４において、エッチングされるＧａＮの層（第２半導体層３０４および第３半導体層３０５）の厚さが１μｍ以下であり、ＧａＮのエッチング中に生じる凹凸は数十ｎｍ程度と考えられる。例えば、５０ｎｍ程度の凹凸をエッチングストップ層３０３のＡｌＧａＮをオーバーエッチングすることで平坦にする場合には、前述した実施の形態３と同様に、厚さ２ｎｍ程度のエッチングストップ層３０３を用いることが望ましい。 In the fourth embodiment, the thickness of the GaN layer to be etched (the second semiconductor layer 304 and the third semiconductor layer 305) is 1 μm or less, and the unevenness generated during the etching of GaN is considered to be about several tens of nm. For example, when flattening unevenness of about 50 nm by over-etching AlGaN of the etching stop layer 303, it is desirable to use the etching stop layer 303 having a thickness of about 2 nm as in the above-described third embodiment. ..
　また、実施の形態４において、エッチングストップ層３０３は、ｎ型ＧａＮからなる第１半導体層３０２の上部に位置するため、エッチングストップ層３０３にドーピングを行うことで、第１半導体層３０２へのエッチングストップ層３０３を用いたことによる影響を低減することができる。 Further, in the fourth embodiment, since the etching stop layer 303 is located above the first semiconductor layer 302 made of n-type GaN, the etching stop layer 303 is doped to etch the first semiconductor layer 302. The influence of using the stop layer 303 can be reduced.
　また、トレンチ型ＭＯＳＦＥＴでは、図４Ｅに示すように、ソースとなる第１半導体層３０２の厚さ方向の途中にＡｌＧａＮからなるエッチングストップ層３０３ａを挿入した構造とすることもできる。この場合にも、組成，層厚、ドーピング濃度について上と同様の議論が成り立つ。 Further, as shown in FIG. 4E, the trench-type MOSFET may have a structure in which an etching stop layer 303a made of AlGaN is inserted in the middle of the source first semiconductor layer 302 in the thickness direction. In this case as well, the same discussion as above holds for composition, layer thickness, and doping concentration.
［実施の形態５］
　次に、本発明の実施の形態５に係る半導体装置の製造方法について、図５Ａ～図５Ｃを参照して説明する。 [Embodiment 5]
Next, a method of manufacturing the semiconductor device according to the fifth embodiment of the present invention will be described with reference to FIGS. 5A to 5C.
　まず、図５Ａに示すように、基板４０１の上に、第１半導体層４０２、エッチングストップ層４０３、および第２半導体層４０４を、これらの順に形成する（第１工程、第２工程、第３工程）。第１半導体層４０２は、例えばｎ型のＧａＮから構成され、厚さ３００ｎｍ程度である。エッチングストップ層４０３は、ＡｌＧａＮから構成されている。第２半導体層４０４は、例えばｎ型のＧａＮから構成され、厚さ３００ｎｍ程度である。 First, as shown in FIG. 5A, the first semiconductor layer 402, the etching stop layer 403, and the second semiconductor layer 404 are formed in this order on the substrate 401 (first step, second step, third step). Process). The first semiconductor layer 402 is made of, for example, an n-type GaN and has a thickness of about 300 nm. The etching stop layer 403 is made of AlGaN. The second semiconductor layer 404 is composed of, for example, an n-type GaN and has a thickness of about 300 nm.
　次に、ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、第２半導体層４０４のパターニングにより、図５Ｂに示すように、第２半導体層４０４を貫通してエッチングストップ層４０３に到達する開口４０５を形成する（第４工程）。例えば、公知のリソグラフィー技術により第２半導体層４０４の上にマスクパターンを形成し、形成したマスクパターンをマスクとし、第２半導体層４０４を熱分解によるエッチング処理によりエッチングする。マスクパターンは、開口４０５を形成した後で除去する。 Next, by patterning the second semiconductor layer 404 using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, as shown in FIG. 5B, the etching stop layer penetrates the second semiconductor layer 404. The opening 405 that reaches 403 is formed (fourth step). For example, a mask pattern is formed on the second semiconductor layer 404 by a known lithography technique, the formed mask pattern is used as a mask, and the second semiconductor layer 404 is etched by an etching process by thermal decomposition. The mask pattern is removed after forming the opening 405.
　次に、開口４０５に露出するエッチングストップ層４０３の上に、例えばｐ型のＧａＮを再成長させて、図５Ｃに示すように、第３半導体層４０６を形成する。再成長の層厚は、３００ｎｍである。 Next, for example, p-type GaN is re-grown on the etching stop layer 403 exposed to the opening 405 to form the third semiconductor layer 406 as shown in FIG. 5C. The layer thickness for regrowth is 300 nm.
　実施の形態５では、エッチングされる第２半導体層４０４の層厚が３００ｎｍであり、ＧａＮの熱分解によるエッチング中に生じる凹凸は、数十ｎｍ程度と考えられる。例えば、５０ｎｍ程度の凹凸をエッチングストップ層４０３をオーバーエッチングすることで平坦にする場合には、エッチングストップ層４０３の厚さを２ｎｍ程度とすることが望ましい。また、この例においても、エッチングストップ層４０３は、ＧａＮからなる層の中に配置するため、エッチングストップ層４０３にドーピングを行うことで、ＧａＮからなる層へのＡｌＧａＮの層の挿入の影響を低減することができる。 In the fifth embodiment, the layer thickness of the second semiconductor layer 404 to be etched is 300 nm, and the unevenness generated during etching by thermal decomposition of GaN is considered to be about several tens of nm. For example, when the unevenness of about 50 nm is flattened by over-etching the etching stop layer 403, it is desirable that the thickness of the etching stop layer 403 is about 2 nm. Further, also in this example, since the etching stop layer 403 is arranged in the layer made of GaN, the influence of the insertion of the AlGaN layer into the layer made of GaN is reduced by doping the etching stop layer 403. can do.
　ところで、熱分解によるエッチングは、上述した窒化物半導体の成長を実施する装置で実施できる。例えば、有機金属気相成長を実施する成長装置では、成長室内にＮＨ3ガスおよびＨ2ガスを供給することが可能であり、また、成長室内に配置した基板４０１を、１０００℃程度に加熱することができる。このような成長装置を用いることで、上述した開口４０５を形成した後、第３半導体層４０６の再成長を、大気に曝すことなく連続して実施できる。このように同一装置内で連続して処理することで、再成長させる面に対する不純物の付着などが防げる。 By the way, etching by thermal decomposition can be carried out by the above-mentioned apparatus for growing the nitride semiconductor. For example, in a growth apparatus that carries out metalorganic vapor phase growth, it is possible to supply NH 3 gas and H 2 gas to the growth chamber, and the substrate 401 arranged in the growth chamber is heated to about 1000 ° C. be able to. By using such a growth device, after the above-mentioned opening 405 is formed, the third semiconductor layer 406 can be continuously regrown without being exposed to the atmosphere. By continuously treating in the same apparatus in this way, it is possible to prevent impurities from adhering to the surface to be regrown.
　以上に説明したように、本発明によれば、ＡｌＧａＮから構成されたエッチングストップ層を用いるので、デバイスの構造を制限することなく、ドライエッチング処理によりＧａＮを制御性よくエッチングしてＧａＮデバイスが作製できるようになる。 As described above, according to the present invention, since the etching stop layer composed of AlGaN is used, the GaN device is manufactured by etching GaN with good controllability by the dry etching process without limiting the structure of the device. become able to.
　なお、本発明は以上に説明した実施の形態に限定されるものではなく、本発明の技術的思想内で、当分野において通常の知識を有する者により、多くの変形および組み合わせが実施可能であることは明白である。 The present invention is not limited to the embodiments described above, and many modifications and combinations can be carried out by a person having ordinary knowledge in the art within the technical idea of the present invention. That is clear.
　１０１…基板、１０２…チャネル層、１０３…障壁層、１０４…エッチングストップ層、１０５…ｐ型半導体層、１０６…ゲートパターン、１０７…ゲート電極、１０８…ソース電極、１０９…ドレイン電極。 101 ... substrate, 102 ... channel layer, 103 ... barrier layer, 104 ... etching stop layer, 105 ... p-type semiconductor layer, 106 ... gate pattern, 107 ... gate electrode, 108 ... source electrode, 109 ... drain electrode.

Claims (5)

  1. 　基板の上にＧａＮから構成されたチャネル層を形成する第１工程と、
    　前記チャネル層の上に、ＡｌＧａＮから構成された障壁層を形成する第２工程と、
    　前記障壁層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第３工程と、
    　前記エッチングストップ層の上にｐ型のＧａＮから構成されたｐ型半導体層を形成する第４工程と、
    　ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、前記ｐ型半導体層のパターニングにより、前記エッチングストップ層の上に、ゲートパターンを形成する第５工程と、
    　前記ゲートパターンの上に配置されるゲート電極を形成する第６工程と、
    　前記エッチングストップ層の上の前記ゲートパターンの側方に、前記チャネル層と前記障壁層との界面近傍に形成される２次元電子ガスにオーミックコンタクトするソース電極およびドレイン電極を形成する第７工程と
    　を備え、
    　前記エッチングストップ層の厚さおよびＡｌの組成比は、前記ゲートパターンにより形成される空乏が前記２次元電子ガスに作用する範囲とされている
    　ことを特徴とする半導体装置の製造方法。     The first step of forming a channel layer composed of GaN on the substrate, and
    A second step of forming a barrier layer made of AlGaN on the channel layer, and
    A third step of forming an etching stop layer made of AlGaN on the barrier layer, and
    A fourth step of forming a p-type semiconductor layer composed of p-type GaN on the etching stop layer, and
    A fifth step of forming a gate pattern on the etching stop layer by patterning the p-type semiconductor layer using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN.
    The sixth step of forming the gate electrode arranged on the gate pattern and
    A seventh step of forming a source electrode and a drain electrode that make ohmic contact with a two-dimensional electron gas formed in the vicinity of the interface between the channel layer and the barrier layer on the side of the gate pattern on the etching stop layer. With
    A method for manufacturing a semiconductor device, wherein the thickness of the etching stop layer and the composition ratio of Al are within a range in which the depletion formed by the gate pattern acts on the two-dimensional electron gas.
  2. 　基板の上にＧａＮから構成されたチャネル層を形成する第１工程と、
    　前記チャネル層の上に、ＡｌＧａＮから構成された障壁層を形成する第２工程と、
    　前記障壁層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第３工程と、
    　前記エッチングストップ層の上にＧａＮから構成されたキャップ層を形成する第４工程と、
    　ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、前記キャップ層のパターニングにより、前記キャップ層を貫通して前記エッチングストップ層の表面が露出するゲート開口を形成する第５工程と、
    　前記ゲート開口に露出する前記エッチングストップ層の上に、ゲート電極を形成する第６工程と、
    　前記エッチングストップ層の上の前記ゲート電極の側方に、前記チャネル層と前記障壁層との界面近傍に形成される２次元電子ガスにオーミックコンタクトするソース電極およびドレイン電極を形成する第７工程と
    　を備え、
    　前記エッチングストップ層の厚さおよびＡｌの組成比は、前記ゲート電極によるゲート電界が前記２次元電子ガスに作用する範囲とされている
    　ことを特徴とする半導体装置の製造方法。     The first step of forming a channel layer composed of GaN on the substrate, and
    A second step of forming a barrier layer made of AlGaN on the channel layer, and
    A third step of forming an etching stop layer made of AlGaN on the barrier layer, and
    A fourth step of forming a cap layer composed of GaN on the etching stop layer, and
    Fifth step of forming a gate opening that penetrates the cap layer and exposes the surface of the etching stop layer by patterning the cap layer using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN. When,
    A sixth step of forming a gate electrode on the etching stop layer exposed to the gate opening, and
    A seventh step of forming a source electrode and a drain electrode that make ohmic contact with a two-dimensional electron gas formed in the vicinity of the interface between the channel layer and the barrier layer on the side of the gate electrode on the etching stop layer. With
    A method for manufacturing a semiconductor device, wherein the thickness of the etching stop layer and the composition ratio of Al are within a range in which the gate electric field generated by the gate electrode acts on the two-dimensional electron gas.
  3. 　基板の上に第１導電型のＧａＮから構成された第１半導体層を形成する第１工程と、
    　前記第１半導体層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第２工程と、
    　前記エッチングストップ層の上に第１導電型のＧａＮから構成された第２半導体層を形成する第３工程と、
    　前記第２半導体層の上に第２導電型のＧａＮから構成された第３半導体層を形成する第４工程と、
    　ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、前記第２半導体層および前記第３半導体層のパターニングにより前記エッチングストップ層の一部の表面を露出させて電極形成面を形成する第５工程と、
    　前記エッチングストップ層の前記電極形成面の上に、前記第１半導体層にオーミックコンタクトする第１電極を形成する第６工程と、
    　前記第３半導体層の上に、前記第３半導体層にオーミックコンタクトする第２電極を形成する第７工程と
    　を備え、
    　前記エッチングストップ層の厚さおよびＡｌの組成比は、前記第１電極と前記第１半導体層とのオーミックコンタクトが得られる範囲とされている
    　ことを特徴とする半導体装置の製造方法。     The first step of forming the first semiconductor layer composed of the first conductive type GaN on the substrate, and
    A second step of forming an etching stop layer made of AlGaN on the first semiconductor layer, and
    A third step of forming a second semiconductor layer composed of a first conductive type GaN on the etching stop layer, and
    A fourth step of forming a third semiconductor layer composed of a second conductive type GaN on the second semiconductor layer, and
    By patterning the second semiconductor layer and the third semiconductor layer using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, a part of the surface of the etching stop layer is exposed to expose the electrode forming surface. The fifth step of forming and
    A sixth step of forming a first electrode that makes ohmic contact with the first semiconductor layer on the electrode forming surface of the etching stop layer.
    A seventh step of forming a second electrode that makes ohmic contact with the third semiconductor layer is provided on the third semiconductor layer.
    A method for manufacturing a semiconductor device, wherein the thickness of the etching stop layer and the composition ratio of Al are within a range in which ohmic contact between the first electrode and the first semiconductor layer can be obtained.
  4. 　基板の上に第１導電型のＧａＮから構成されてドレインとなる第１半導体層を形成する第１工程と、
    　前記第１半導体層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第２工程と、
    　前記エッチングストップ層の上に第２導電型のＧａＮから構成されてチャネルが形成される第２半導体層を形成する第３工程と、
    　前記第２半導体層の上に第１導電型のＧａＮから構成されてソースとなる第３半導体層を形成する第４工程と、
    　ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、前記第２半導体層および前記第３半導体層のパターニングにより、前記第２半導体層および前記第３半導体層を貫通して前記エッチングストップ層に到達する開口を形成する第５工程と、
    　前記開口の底面および側面を覆う絶縁層を形成する第６工程と、
    　前記絶縁層で底面および側面が覆われた前記開口の内部に、前記チャネルに対してゲート電界を作用させるためのゲート電極を形成する第７工程と、
    　前記第１半導体層に電気的に接続するドレイン電極を形成する第８工程と、
    　前記第３半導体層に電気的に接続するソース電極を形成する第９工程と
    　を備え、
    　前記エッチングストップ層の厚さおよびＡｌの組成比は、前記チャネルと前記第１半導体層との間のキャリアの移動が可能となる範囲とされている
    　ことを特徴とする半導体装置の製造方法。     The first step of forming a first semiconductor layer which is composed of a first conductive type GaN and serves as a drain on a substrate, and
    A second step of forming an etching stop layer made of AlGaN on the first semiconductor layer, and
    A third step of forming a second semiconductor layer composed of a second conductive type GaN and forming a channel on the etching stop layer, and
    A fourth step of forming a third semiconductor layer as a source, which is composed of a first conductive type GaN, on the second semiconductor layer.
    By patterning the second semiconductor layer and the third semiconductor layer using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN, the second semiconductor layer and the third semiconductor layer are penetrated and said. The fifth step of forming an opening reaching the etching stop layer, and
    The sixth step of forming an insulating layer covering the bottom surface and the side surface of the opening, and
    A seventh step of forming a gate electrode for applying a gate electric field to the channel inside the opening whose bottom surface and side surfaces are covered with the insulating layer.
    The eighth step of forming the drain electrode electrically connected to the first semiconductor layer, and
    A ninth step of forming a source electrode electrically connected to the third semiconductor layer is provided.
    A method for manufacturing a semiconductor device, characterized in that the thickness of the etching stop layer and the composition ratio of Al are within a range in which carriers can be moved between the channel and the first semiconductor layer.
  5. 　基板の上にＧａＮから構成された第１半導体層を形成する第１工程と、
    　前記第１半導体層の上に、ＡｌＧａＮから構成されたエッチングストップ層を形成する第２工程と、
    　前記エッチングストップ層の上にＧａＮから構成された第２半導体層を形成する第３工程と、
    　ＡｌＧａＮに対してＧａＮを選択的に分解する熱分解によるエッチングを用いた、前記第２半導体層のパターニングにより、前記第２半導体層を貫通して前記エッチングストップ層に到達する開口を形成する第４工程と、
    　前記開口に露出する前記エッチングストップ層の上に、ＧａＮを再成長させて第３半導体層を形成する第５工程と
    　を備える半導体装置の製造方法。     The first step of forming the first semiconductor layer composed of GaN on the substrate, and
    A second step of forming an etching stop layer made of AlGaN on the first semiconductor layer, and
    A third step of forming a second semiconductor layer composed of GaN on the etching stop layer, and
    A fourth patterning of the second semiconductor layer using etching by thermal decomposition that selectively decomposes GaN with respect to AlGaN forms an opening that penetrates the second semiconductor layer and reaches the etching stop layer. Process and
    A method for manufacturing a semiconductor device, comprising a fifth step of regrowth of GaN to form a third semiconductor layer on the etching stop layer exposed to the opening.
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252265A (en) * 1999-03-03 2000-09-14 Hitachi Ltd Etching method of compound semiconductor material and compound semiconductor device
JP2006080378A (en) * 2004-09-10 2006-03-23 Toshiba Corp Semiconductor substrate, semiconductor element, method for manufacturing semiconductor element, and method for manufacturing semiconductor substrate
JP2006339561A (en) * 2005-06-06 2006-12-14 Matsushita Electric Ind Co Ltd Field-effect transistor and its manufacturing method
JP2012156321A (en) * 2011-01-26 2012-08-16 Toshiba Corp Nitride semiconductor device and method of manufacturing the same
JP2012231081A (en) * 2011-04-27 2012-11-22 Sharp Corp Semiconductor device manufacturing method
JP2013065612A (en) * 2011-09-15 2013-04-11 Rohm Co Ltd Nitride semiconductor device and manufacturing method of the same
JP2013225621A (en) * 2012-04-23 2013-10-31 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
JP2015165530A (en) * 2014-03-03 2015-09-17 三菱電機株式会社 Semiconductor device and semiconductor device manufacturing method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014090033A (en) 2012-10-29 2014-05-15 Fujitsu Ltd Compound semiconductor device and manufacturing method of the same

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000252265A (en) * 1999-03-03 2000-09-14 Hitachi Ltd Etching method of compound semiconductor material and compound semiconductor device
JP2006080378A (en) * 2004-09-10 2006-03-23 Toshiba Corp Semiconductor substrate, semiconductor element, method for manufacturing semiconductor element, and method for manufacturing semiconductor substrate
JP2006339561A (en) * 2005-06-06 2006-12-14 Matsushita Electric Ind Co Ltd Field-effect transistor and its manufacturing method
JP2012156321A (en) * 2011-01-26 2012-08-16 Toshiba Corp Nitride semiconductor device and method of manufacturing the same
JP2012231081A (en) * 2011-04-27 2012-11-22 Sharp Corp Semiconductor device manufacturing method
JP2013065612A (en) * 2011-09-15 2013-04-11 Rohm Co Ltd Nitride semiconductor device and manufacturing method of the same
JP2013225621A (en) * 2012-04-23 2013-10-31 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
JP2015165530A (en) * 2014-03-03 2015-09-17 三菱電機株式会社 Semiconductor device and semiconductor device manufacturing method

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