JP4876927B2 - Method for forming a semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor device which can reduce contamination from a mask material and deposit formed along the edge of a mask. <P>SOLUTION: A lamination 19 comprising films 15, 17 is formed on a group III nitride region 13. The film 15 is composed of an inorganic compound which comprises either oxygen or nitrogen as a constituent element and is different from a group III nitride. The film 17 is composed of a group III nitride. A mask 19a is formed by etching the films 15, 17 of the lamination 19. The mask 19a comprises a lowermost layer 15a and an uppermost layer 17a. The mask 19a has an opening 19b positioned in a second region 13b, the second region 13b is exposed in the opening 19b, and a second region 13b is covered with the lowermost layer 15a. A group III nitride is formed again by an MOCVD furnace on the major surface 13c of the group III nitride region 13 by using the mask 19a, and film formation gas is also consumed on the mask 19a, thus generating a deposit 25 also on the mask 19a. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a method of forming a semiconductor device.

Non-Patent Document 1 describes selective growth or buried growth used for a mask. This mask is either a single layer of SiO ₂ or AlN. An electron beam method is used for forming the SiO ₂ film.
Jpn. J. Appl. Phys. Vol.42 (2003) pp.6276

When growing a GaN epitaxial film using the metal organic vapor phase epitaxy method, high-temperature hydrogen and ammonia are used in a growth furnace. However, since these etch the mask material SiO ₂ and SiN, silicon is desorbed into the growth furnace and diffused. The silicon is taken into the GaN epitaxial film, and as a result, the resistance of the GaN epitaxial film is lowered. Therefore, it is difficult to produce a low-doped epitaxial film, a high-resistance epitaxial film, and a p-type epitaxial film using a mask made of such a material. Low-doped epitaxial films, high-resistance epitaxial films, and p-type epitaxial films are used for power devices, for example. In addition, when a mask made of the mask material is used, GaN does not substantially grow on the mask. For this reason, the raw material supplied to the growth furnace is not consumed on the mask, and protruding GaN grows along the edge of the mask.

Further, when used for a SiO ₂ mask manufactured by an electron beam (EB) method, silicon desorbed from the SiO _{2 of} the mask is mixed into the epitaxial layer. Due to the mixing of Si, the resistance of the epitaxial layer is lowered. Therefore, it becomes difficult to grow an epitaxial layer having a low Si concentration.

On the other hand, when a mask material made of a group III nitride that does not contain silicon, for example, AlN produced by sputtering, is used as a mask, the decrease in the resistance of the epitaxial layer is small compared to the growth used for the SiO ₂ mask. . However, although the SiO ₂ mask can be removed using buffered hydrofluoric acid, hot ammonia water is used to remove the AlN mask.

  According to the inventors' knowledge, when AlN is removed using ammonia water, damage remains on the surface of a group III nitride semiconductor such as GaN. For example, after removing the AlN mask on the surface of the GaN region, a Schottky electrode is formed on the GaN surface. When the reverse current was measured, the leakage current increased significantly, and the on-resistance increased significantly.

  The present invention has been made in view of such circumstances, and it is possible to reduce the contamination from the mask material, to reduce the deposits grown along the edge of the mask, and to remove the mask. An object of the present invention is to provide a method of forming a semiconductor device that can prevent the subsequent introduction of damage.

  The invention according to one aspect of the present invention is a method of forming a semiconductor device using a group III nitride semiconductor. The method includes: (a) forming a mask on a group III nitride region having first and second regions; (b) growing a group III nitride semiconductor using the mask; c) removing the mask. The mask is composed of a plurality of layers, the uppermost layer of the plurality of layers of the mask is made of group III nitride, and the lowermost layer of the plurality of layers of the mask is at least one of oxygen and nitrogen It is made of an inorganic compound containing one element as a constituent element and different from the group III nitride, the lowermost layer covers the second region, and the mask has an opening located in the first region.

  According to this method, since the uppermost layer of the mask is made of group III nitride, protruding deposits grown along the edge of the mask opening can be reduced, and contamination from the upper mask material can be reduced. . Further, since the uppermost layer of the mask is provided on the lowermost layer, it is possible to reduce contamination from the material of the lowermost layer.

  In the method according to the present invention, the uppermost layer of the mask is preferably made of GaN. Since the top layer of the mask is composed of GaN, contamination from the mask that may occur during growth is reduced. Further, when the group III nitride is grown, since the raw material is consumed also on the GaN layer, the rising at the edge of the mask is reduced.

  In the method according to the present invention, the uppermost layer of the mask is preferably made of AlN. Since the top layer of the mask is made of AlN, contamination from the mask that may occur during growth is reduced. Further, since the raw material is consumed also on the AlN layer when the group III nitride is grown, the swell at the edge of the mask is reduced.

  In the method according to the present invention, the uppermost layer of the mask is preferably made of AlGaN. Since the top layer of the mask consists of AlGaN, contamination from the mask that may occur during growth is reduced. Further, when the group III nitride is grown, since the raw material is consumed also on the AlGaN layer, the rising at the edge of the mask is reduced.

  In the method according to the present invention, the uppermost layer of the mask is preferably made of a group III nitride containing Al and In as constituent elements. Since the top layer of the mask is made of AlInGaN or AlInN, contamination from the mask that may occur during growth is reduced. Further, when the group III nitride is grown, since the raw material is consumed also on the group III nitride layer containing Al and In, the rise at the edge of the mask is reduced.

  In the method according to the present invention, the lowermost layer of the mask is preferably made of aluminum oxide. As the aluminum oxide, for example, alumina or the like can be used. Since the lowermost layer material is made of aluminum oxide, processing with very little damage to the group III nitride region is possible.

  In the method according to the present invention, the lowermost layer of the mask is preferably made of a silicon inorganic compound. As this silicon inorganic compound, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like can be used. Since the lowermost layer material is made of a silicon inorganic compound, it is possible to perform processing with very little damage to the group III nitride region.

  In the method according to the present invention, the group III nitride semiconductor may have p conductivity. According to this method, since the influence of contamination from the mask material can be reduced, it is easy to control the conductivity in the group III nitride semiconductor having p conductivity.

In the method according to the present invention, the group III nitride semiconductor may have a silicon concentration of 1 × 10 ¹⁷ cm ⁻³ or less. According to this method, since the influence of contamination from the mask material is reduced, the silicon concentration in the group III nitride semiconductor can be easily controlled. When using an organic metal vapor phase growth furnace, silicon contamination from a mask material or the like can occur. However, since the uppermost layer is made of group III nitride, the influence from this lower layer can be reduced even when a silicon compound is used for the lower layer.

  The method according to the present invention may further include the step of etching the group III nitride region using the mask to form a recess in the second region of the group III nitride region. The group III nitride semiconductor is embedded and grown in the recess of the group III nitride region using the mask. According to this method, it is possible to reduce contamination from the mask material in buried growth, and it is possible to reduce deposits grown along the edge of the mask. Alternatively, the method according to the present invention further includes a step of forming a group III nitride layer having a main surface prior to the formation of the mask. The group III nitride region includes the group III nitride layer, the mask is formed on the main surface of the group III nitride layer, and the group III nitride semiconductor is formed using the mask. Regrown on the III-nitride layer. According to this method, in the regrowth, contamination from the mask material can be reduced, and deposits grown along the edge of the mask can be reduced.

  In the method according to the present invention, the semiconductor device is a Schottky barrier diode. The method may further include a step of forming a Schottky electrode on the group III nitride region after removing the mask. The group III nitride region includes an n-type drift layer for the Schottky barrier diode, and the group III nitride semiconductor includes a p-type guard ring layer regrown on the group III nitride region.

  According to this method, a Schottky barrier diode including a regrown p-type guard ring layer can be manufactured, and the p-type guard ring layer is raised on the group III nitride region. Further, since the uppermost layer of the mask is made of group III nitride, it is possible to reduce the protruding deposits grown along the edge of the mask opening and to reduce contamination from the upper mask material. In addition, unlike the group III nitride, the uppermost layer of the mask is provided on the lowermost layer made of an inorganic compound, so that contamination from the inorganic compound can be reduced. Since the influence of contamination from the mask material can be reduced, it becomes easy to control the p conductivity of the group III nitride semiconductor.

  In the method according to the present invention, the semiconductor device is a Schottky barrier diode. The group III nitride region includes an n-type drift layer for the Schottky barrier diode. The method includes a step of forming a recess in the second region of the group III nitride region by etching the group III nitride region using the mask prior to growing the group III nitride semiconductor. And a step of forming a Schottky electrode on the group III nitride region after removing the mask. The group III nitride semiconductor includes a p-type guard ring region embedded and grown in the recess of the group III nitride region.

  According to this method, a Schottky barrier diode including a buried p-type guard ring region can be manufactured, and this p-type guard ring region is buried in the group III nitride region. Further, since the uppermost layer of the mask is made of group III nitride, it is possible to reduce the protruding deposits grown along the edge of the mask opening and to reduce contamination from the upper mask material. In addition, unlike the group III nitride, the uppermost layer of the mask is provided on the lowermost layer made of an inorganic compound, so that contamination from the inorganic compound can be reduced. Since contamination from the mask material can be reduced, it becomes easy to control the p conductivity of the group III nitride semiconductor.

  In the method according to the present invention, the semiconductor device is a vertical transistor. The III-nitride region includes an n-type drift layer for the vertical transistor. The group III nitride semiconductor is formed for a p-type well region embedded and grown in the group III nitride region. The method includes a step of forming a recess in the second region of the group III nitride region by etching the group III nitride region using the mask prior to growing the group III nitride semiconductor. And a step of forming a gate insulating film on the p-type well region after removing the mask.

  According to this method, a transistor including a buried p-type well region can be manufactured, and the p-type well region is buried in the group III nitride region. Further, since the uppermost layer of the mask is made of group III nitride, it is possible to reduce the protruding deposits grown along the edge of the mask opening and to reduce contamination from the upper mask material. In addition, unlike the group III nitride, the uppermost layer of the mask is provided on the lowermost layer made of an inorganic compound, so that contamination from the inorganic compound can be reduced. Since the influence of contamination from the mask material can be reduced, it becomes easy to control the p conductivity of the group III nitride semiconductor.

  In the method according to the present invention, the semiconductor device is a vertical transistor. The method includes forming a group III nitride layer having a main surface and forming a p-type well region of the vertical transistor prior to forming the mask, and growing the group III nitride semiconductor. Prior to, etching the group III nitride region using the mask to form a recess in the second region of the group III nitride region, and after removing the mask, the p-type And a step of forming a gate insulating film on the well region. The group III nitride semiconductor is formed for an n-type drift region embedded and grown in the group III nitride layer, the group III nitride region includes the group III nitride layer, and the mask And formed on the main surface of the group III nitride layer.

  According to this method, a transistor including an embedded n-type drift region can be manufactured, and the n-type drift region is embedded in the group III nitride region. Further, since the uppermost layer of the mask is made of group III nitride, it is possible to reduce the protruding deposits grown along the edge of the mask opening and to reduce contamination from the upper mask material. In addition, unlike the group III nitride, the uppermost layer of the mask is provided on the lowermost layer made of an inorganic compound, so that contamination from the inorganic compound can be reduced. Since the influence of contamination from the mask material can be reduced, the carrier concentration of the group III nitride semiconductor can be easily controlled.

  The method according to the present invention includes various configurations without being limited to the above configuration. The lowermost mask thickness is preferably larger than the uppermost mask thickness. In the method according to the present invention, it is preferable that the thickness of the group III nitride semiconductor grown using the mask is smaller than the thickness of the mask.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, it is possible to reduce contamination from the mask material, to reduce deposits grown along the edge of the mask, and to introduce damage after removing the mask. A method for forming a semiconductor device is provided.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the method for forming a semiconductor device of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

(First embodiment)
1 to 3 are drawings schematically showing a manufacturing process in a method of forming a semiconductor device according to an embodiment of the present invention. In the following description, a method for manufacturing a Schottky barrier diode as an example of a semiconductor device will be described. Referring to FIG. 1A, a group III nitride region 13 is grown on the substrate 11. As the substrate 11, a group III nitride substrate such as GaN, AlGaN, or AlN can be used. However, the semiconductor device according to the present embodiment is not limited to the group III nitride substrate, for example, a sapphire substrate, A Si substrate, a SiC substrate, a ZrB ₂ substrate, or the like can also be used. The group III nitride region 13 can be, for example, a group III nitride such as AlN and a gallium nitride semiconductor, and GaN, AlGaN, InGaN, AlInGaN, or the like is used as the gallium nitride semiconductor.

  Next, a mask is formed on the group III nitride region 13. As will be understood from the following description, the mask is composed of a plurality of layers. In the step shown in FIG. 1B, a film 15 for the lowermost layer among a plurality of layers constituting the mask is formed. The film 15 is made of an inorganic compound containing at least one of oxygen and nitrogen as a constituent element, and this inorganic compound is different from the group III nitride. The inorganic compound of the film 15 can be, for example, aluminum oxide. As the aluminum oxide, for example, alumina or the like can be used. Illustrative alumina can be formed by, for example, EB vapor deposition or sputtering. Since the lowermost layer material is made of aluminum oxide, processing with very little damage to the group III nitride region is possible. Alternatively, the inorganic compound of the film 15 is preferably made of, for example, a silicon inorganic compound. As this silicon inorganic compound, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like can be used. These exemplified silicon inorganic compounds can be grown by, for example, vapor phase epitaxy, EB vapor deposition, plasma CVD, sputtering, or the like. Since the lowermost layer material is made of a silicon inorganic compound, damage to the group III nitride region can be reduced.

  Subsequently, in the step shown in FIG. 1C, a film 17 for the uppermost layer among a plurality of layers constituting the mask is formed. The film 17 for the top layer is made of group III nitride. The group III nitride can be, for example, a group III nitride such as AlN and a gallium nitride based semiconductor. As the gallium nitride based semiconductor, GaN, AlGaN, InAlN, InAlGaN, or the like is used. Through these steps, the stack 19 for the mask was formed. If necessary, another film may be formed between the film 15 for the lowermost layer and the film 17 for the uppermost layer.

As shown in FIG. 2A, a mask 21 is formed in order to form a pattern in the stack 19. The mask 21 is made of a resist, for example, and is patterned using photolithography. The resist mask 21 has an opening 21 a provided in the second region 13 b of the group III nitride region 13.

  As shown in FIG. 2B, the stack 19 is etched using a resist mask 21 to form a mask 19a. The mask 19a includes a lowermost layer 15a and an uppermost layer 17a. The mask 19a has an opening 19b located in the second region 13b. The second region 13b is exposed in the opening 19b, and the second region 13b is covered with the lowermost layer 15a. In this etching, the films 15 and 17 of the stacked layer 19 are removed by dry etching, for example, and the lowermost layer 15a and the uppermost layer 17a having the openings 19b can be formed. After the etching of the stacked layer 19, the mask 21 is removed.

  Thereafter, as shown in FIG. 2C, a group III nitride semiconductor 23 is grown using a mask 19a. This growth can be performed, for example, using a metal organic chemical vapor deposition (MOCVD) furnace. According to this step, since the uppermost layer 17a of the mask 19a is made of group III nitride, the deposit 25 is also generated on the mask 19a, and the film forming gas is consumed also on the mask 19a. For this reason, protruding deposits grown along the edge of the opening 19b of the mask 19a can be reduced. Further, contamination from the mask material of the upper layer 17a can be reduced. Furthermore, since the uppermost layer 17a of the mask 19a is provided on the lowermost layer 15a made of an inorganic compound, unlike the group III nitride, contamination from the inorganic compound can be reduced. A group III nitride semiconductor 23 is grown in the opening 19b, and a deposit 25 is grown on the mask 19a. In this embodiment, the group III nitride region 13 includes a group III nitride layer that provides a major surface 13c on which a mask 19a is formed, the major surface 13c being substantially flat. Therefore, the group III nitride semiconductor 23 is regrown on the main surface 13c of the group III nitride region 13 using the mask 19a. The film thickness of the group III nitride semiconductor 23 is thinner than the thickness of the mask 19a. The film thickness of the group III nitride semiconductor 23 may be thinner than the lowermost layer 15a.

  After this growth is completed, the mask 19a is removed. As a result of this removal, the deposit 25 disappears with the removal of the mask 19a. More specifically, as shown in FIG. 3A, the uppermost layer 17a of the mask 19a is made of a group III nitride, and the deposit 25 is removed by etching or the like of the uppermost layer 17a. Further, when the uppermost layer 17a is removed, the surface 13d of the group III nitride region 13 is covered with the group III nitride 23 and the lowermost layer 15a. Therefore, the main surface 13c of the group III nitride region 13 is protected during the removal of the mask 17a.

  Next, as shown in FIG. 3B, the lowermost layer 15a of the mask 19a is removed. This removal is performed, for example, by wet etching or the like. Since the lowermost layer 15a of the mask 19a is made of an inorganic compound containing at least one of oxygen and nitrogen as a constituent element and different from the group III nitride, the lower layer 15a is removed even when the group III nitride region 13 is removed. Damage to the surface 13d is reduced. When the film thickness of the group III nitride semiconductor 23 is thinner than the lowermost layer 15a, the uppermost layer 17a and the deposit 25 on the lowermost layer 15a can be removed simultaneously by only wet etching the lowermost layer 15a. .

  As shown in FIG. 3C, the Schottky electrode 27 is formed on the group III nitride region 13 after removing the mask 19a. In addition, the ohmic electrode 29 is formed on the back surface 11 b of the substrate 11. This manufacturing process provides the Schottky barrier diode 31 including the regrown p-type guard ring layer. The group III nitride region 13 includes an n-type drift layer for the Schottky barrier diode, and the group III nitride semiconductor 23 includes a p-type guard ring layer regrown on the group III nitride region 13. This p-type guard ring layer is raised on the group III nitride region. The Schottky electrode 27 forms a Schottky junction with the protected front surface 13b and also contacts the p-type guard ring layer. Moreover, since the uppermost layer 17a is provided on the lowermost layer 15a made of an inorganic compound, unlike the group III nitride, the influence of contamination from the inorganic compound can be reduced. Therefore, the p conductivity of the group III nitride semiconductor 23 can be easily controlled.

When a group III nitride semiconductor is grown using an MOCVD furnace, silicon contamination from a mask material or the like can occur. However, since the uppermost layer 17a is made of group III nitride, the influence from this lower layer can be reduced even when a silicon compound is used for the lower layer. For this reason, the silicon concentration of the group III nitride semiconductor 23 can be 1 × 10 ¹⁷ cm ⁻³ or less. Since the influence of contamination from the mask material can be reduced, the silicon concentration in the group III nitride semiconductor can be easily controlled.

  The uppermost layer 17a of the mask 19a is preferably made of GaN, AlN, AlGaN, AlInN, AlInGaN, or the like. Contamination from the mask that can occur during growth is reduced. Further, when the group III nitride is grown, since the raw material is consumed also on the mask layer 17a, the bulge at the edge of the mask 19a is reduced.

  The constituent element of the group III nitride semiconductor 23 is preferably the same as the constituent element of the group III nitride of the uppermost layer 17a. This is because, when the same kind of material as that of the uppermost layer 17a is grown, the deposit 23 is easily formed, and the group III nitride semiconductor 23 is flattened. The constituent element of the group III nitride of the uppermost layer 17a is preferably the same as the constituent element of the group III nitride region 13. This is because, since the thermal expansion coefficients are the same, stress is reduced when the temperature is lowered after growth.

(Example 1) Method for creating guard ring structure using regrowth A GaN epitaxial layer of 6 μm was grown on a low dislocation GaN substrate by MOCVD. A 1 μm SiN layer was grown on the GaN epitaxial layer using a plasma CVD (pCVD) apparatus, and then 0.1 μm AlN was grown using sputtering. After forming a resist mask and etching AlN using ammonia water, the SiN film was etched using (110) buffered hydrofluoric acid (hereinafter referred to as “BHF (110)”). After removing the resist, selective growth of p-type GaN was performed. The average film thickness of the selectively grown p-type GaN film was 0.3 μm. Then, after removing the selective growth mask (AlN / SiN mask) using BHF (110), an Au electrode (Schottky electrode) was deposited. Through these steps, a Schottky barrier diode having a guard ring structure using regrowth was completed.

  The method for forming a semiconductor device according to this embodiment is not limited to the above-described embodiment, and can be applied to a method for manufacturing a Schottky barrier diode having another structure. 4 to 5 are drawings schematically showing manufacturing steps in a method of forming a shot barrier diode having another structure.

  As shown in FIG. 4A, a mask 33 is formed in order to form a pattern in the stack 19. Unlike the previous example, the mask 33 is used not only for the stack 19 but also for forming a pattern on the group III nitride region 13. The mask 33 is made of, for example, a resist. The mask 33 has an opening 33 a provided in the second region 13 b of the group III nitride region 13.

  As shown in FIG. 4B, similarly to the example shown in FIG. 2B, the stack 19 is etched using the mask 33 to form a mask 19a. The mask 19a includes a lowermost layer 15a and an uppermost layer 17a. After the production of the mask 19a, the second region 13b of the group III nitride region 13 is etched without removing the mask 33. By this etching, as shown in FIG. 4C, an opening 13e for buried growth is formed in the second region 13a. Thereafter, the mask 33 is removed. The opening 13e is a recess formed by etching.

  Next, as shown in FIG. 5A, a group III nitride semiconductor 35 is grown using a mask 33a. This growth can be performed using, for example, a MOCVD furnace. According to this step, since the uppermost layer 17a of the mask 19a is made of group III nitride, the deposit 25 is also generated on the mask 19a, and the film forming gas is consumed also on the mask 19a. For this reason, protruding deposits grown along the edge of the opening 19b of the mask 19a can be reduced. Further, contamination from the mask material of the upper layer 17a can be reduced. Furthermore, since the uppermost layer 17a of the mask 19a is provided on the lowermost layer 15a, contamination from the inorganic compound in the lowermost layer can be reduced. A group III nitride semiconductor 35 is grown in the opening 19b, and a deposit 25 is grown on the mask 19a. In this embodiment, a group III nitride semiconductor 35 is formed in the recess of the second region 13b of the group III nitride region 13 by burying growth using the mask 19a.

  After this growth is completed, the mask 19a is removed. As a result of this removal, the deposit 25 disappears with the removal of the mask 19a, as in the previous example. More specifically, as shown in FIG. 5A, the uppermost layer 17a of the mask 19a is made of a group III nitride, and the deposit 25 is removed by etching or the like of the uppermost layer 17a. Further, as shown in FIG. 5B, the lowermost layer 15a of the mask 19a is removed. This removal is performed, for example, by wet etching or the like. Since the lowermost layer 15a of the mask 19a is made of an inorganic compound containing at least one of oxygen and nitrogen as a constituent element and different from the group III nitride, the group III nitride region 13 is removed even when the lowermost layer 15a is removed. Damage to the surface 13f is reduced.

  As shown in FIG. 5C, after the mask 19 a is removed, a Schottky electrode 39 is formed on the group III nitride region 13. In addition, the ohmic electrode 29 is formed on the back surface 11 b of the substrate 11. This manufacturing process provides the Schottky barrier diode 41 including the buried p-type guard ring region. The group III nitride region 13 includes an n-type drift layer for the Schottky barrier diode 41, and the group III nitride semiconductor 23 includes a p-type guard ring region embedded and grown in the group III nitride region 13. This p-type guard ring region is grown so as to correspond to the position of the surface 13f of the group III nitride region. The Schottky electrode 39 forms a Schottky junction with the protected surface 13f and also contacts the p-type guard ring region. Further, according to this manufacturing method, the influence of contamination from the inorganic compound in the lowermost layer 15a can be reduced, so that the p conductivity of the group III nitride semiconductor 23 can be easily controlled.

(Example 2) Manufacturing method of guard ring structure using buried growth A GaN epitaxial layer of 6 μm was grown on a low dislocation GaN substrate by MOCVD. A 1 μm SiN layer was grown on the GaN epitaxial layer using a pCVD apparatus, and then a 0.1 μm AlN layer was grown using a sputtering apparatus. A resist mask was formed by photolithography, the AlN layer was etched using ammonia water, and then the SiN film was etched using BHF (110). Furthermore, the 0.3 μm n-type GaN layer was etched by dry etching (using Cl ₂ gas, output 100 W). After removing the resist mask, selective growth of p-type GaN was performed. The average film thickness of the selectively grown p-type GaN was 0.3 μm. Then, after removing the selective growth mask (AlN / SiN mask) using BHF (110), an Au electrode (Schottky electrode) was deposited. Through these steps, a guard ring structure using buried growth was completed.

(Second Embodiment)
The method for forming a semiconductor device according to the present embodiment is not limited to the method for manufacturing a shot barrier diode, but can be applied to a method for manufacturing a vertical transistor having another structure that will be described later. 6 to 8 are drawings schematically showing manufacturing steps in the method of forming a vertical transistor according to the embodiment of the present invention.

  Referring again to FIGS. 1A to 1C, a stack 19 including a film 15 and a film 17 for a mask is formed on the group III nitride region 13. In the subsequent description of fabricating the vertical transistor, film 15, film 17 and stack 19 are referred to as film 45, film 47 and stack 49, respectively. As shown in FIG. 6A, a mask 43 for the p-type well region is formed. This formation is performed in the same manner as the mask 33 shown in FIG. The mask 43 has an opening 43 a provided in the second region 13 b of the group III nitride region 13.

  In the same manner as the example shown in FIG. 4B, the stack 49 is etched using the mask 43 to form a mask 49a as shown in FIG. 6B. The mask 49a includes a lowermost layer 45a and an uppermost layer 47a. After the production of the mask 49a, the second region 13b of the group III nitride region 13 is etched without removing the mask 43. By this etching, as shown in FIG. 6C, an opening 13g for buried growth of the p-type well is formed in the second region 13a. The opening 13 g is a recess provided in the second region 13 b of the group III nitride region 13. Thereafter, the mask 43 is removed.

  Next, as shown in FIG. 7A, a group III nitride semiconductor 51 is grown using a mask 49a. This growth can be performed using, for example, a MOCVD furnace. According to this step, since the uppermost layer 47a of the mask 49a is made of group III nitride, the deposit 25 is also generated on the mask 49a, and the film forming gas is also consumed on the mask 49a. For this reason, protruding deposits grown along the edge of the group III nitride semiconductor 51 for the p-type well can be reduced. Further, contamination from the mask material of the upper layer 47a can be reduced. Furthermore, since the uppermost layer 47a is provided on the lowermost layer 45a made of an inorganic compound, unlike the group III nitride, contamination from the inorganic compound can be reduced. A group III nitride semiconductor 35 is grown in the opening 49b, and a deposit 25 is grown on the mask 49a. In this embodiment, the opening 13g provided in the second region 13b of the group III nitride region 13 is buried and grown using the mask 19a.

  After this growth is completed, the mask 49a is removed as shown in FIG. The uppermost layer 47a of the mask 49a is made of a group III nitride, and the deposit 25 is removed by etching or the like of the uppermost layer 47a. Further, the lowermost layer 15a of the mask 49a is removed. Since the lowermost layer 45a of the mask 49a is made of an inorganic compound containing at least one of oxygen and nitrogen as a constituent element and different from the group III nitride, the lower layer 45a is removed even when the group III nitride region 13 is removed. Damage to the surface 13h is reduced.

Subsequent manufacturing steps include steps unique to the fabrication of the vertical transistor. As shown in FIG. 7C, a source region 53 made of an n-type group III nitride _{semiconductor} is formed in a group III nitride _{semiconductor} 51 for a p-type well. This formation can be performed by, for example, an ion implantation method or a buried selective growth method. When the buried selective growth method is adopted, the growth for forming the p-type well can be similarly used, and the same technical advantages can be obtained.

As shown in FIG. 8A, after the mask is removed, the gate insulating film is formed on the surface 13h of the source region 53, the group III nitride semiconductor (p-type well region) 51, and the group III nitride region 13, and on the surface 13h. 55 is formed. The gate insulating film 55 is made of, for example, silicon nitride (for example, SiN), silicon oxide (for example, SiO ₂ ), aluminum nitride (AlN), or the like. Next, as shown in FIG. 8B, a gate electrode 57 a is formed on the gate insulating film 55 and the group III nitride semiconductor (p-type well region) 51, and a source electrode 57 b is formed on the source region 53. The drain electrode 57c is formed on the back surface 11b of the substrate 11. Through these steps, the vertical transistor 59 including the buried p-type well region is manufactured. The group III nitride region 13 includes an n-type drift layer for the vertical transistor 59, and the group III nitride semiconductor 51 is provided for a p-type well region embedded and grown in the group III nitride region 13.

Example 3 A 6 μm GaN epitaxial layer was grown on a low dislocation GaN substrate by using a vertical transistor MOCVD method using buried growth of a p-type GaN well layer. A 1 μm SiN layer was grown thereon using a pCVD apparatus, and then a 1 μm AlN layer was grown using a sputtering apparatus. A resist mask was formed, the AlN layer was etched using ammonia water, and then the SiN film was etched using BHF (110). Further, the 0.3 μm n-type GaN layer was etched by dry etching (Cl ₂ gas, output 100 watts). After removing the resist, selective growth of the p-type GaN well layer was performed. The average film thickness of the selectively grown p-type GaN film was 0.3 μm. Thereafter, the selective growth mask (AlN / SiN mask) was removed using BHF (110). Thereafter, Si ion implantation and activation annealing were performed to form an n ⁺ GaN contact layer. A gate insulating film was formed on the p-type well layer, and a drain electrode, a source electrode, and a gate electrode were further formed. Through these steps, a vertical transistor structure using buried growth of a p-type well layer is completed.

  The method for forming a semiconductor device according to this embodiment mode is not limited to the above embodiment mode, and can be applied to a method for manufacturing a vertical transistor having another structure to be described later. 9 to 10 are drawings schematically showing manufacturing steps in the method of forming a vertical transistor according to the embodiment of the present invention.

  Referring to FIG. 9A, the group III nitride region 60 includes a p-type group III nitride semiconductor layer 61 for the p-type well and an n-type group III nitride semiconductor layer 63 for the drift region. Including. Group III nitride semiconductor layer 61 and group III nitride semiconductor layer 63 are provided on substrate 11. In the subsequent description of the method for manufacturing the vertical transistor, the stack 19 for the mask including the film 15 and the film 17 is referred to as the stack 69 for the mask including the film 65 and the film 67. As shown in FIG. 9A, a mask 71 for the p-type well region is formed. This formation is performed in the same manner as the mask 33 shown in FIG. The mask 71 has an opening 71 a provided in the first region 60 a of the group III nitride region 60.

  As shown in FIG. 9B, similarly to the example shown in FIG. 4B, the stack 69 is etched using the mask 71 to form a mask 69a. The mask 69a includes a lowermost layer 65a and an uppermost layer 67a. After the production of the mask 69a, the second region 13b of the group III nitride region 13 is etched without removing the mask 71. By this etching, as shown in FIG. 9C, an opening 13j for n-type drift buried growth is formed in the second region 13b. The opening 13j is a recess that penetrates the p-type group III nitride semiconductor layer 61 for the p-type well and reaches the n-type group III nitride semiconductor layer 63 for the drift region. As a result, the p-type group III nitride semiconductor layer 61a and the n-type group III nitride semiconductor layer 63a patterned for the p-type well are formed in the group III nitride region 13. For this reason, the p-type group III nitride semiconductor layers 63a are separated from each other.

  As shown in FIG. 10A, the mask 71 is removed. Thereafter, as shown in FIG. 10B, an n-type group III nitride semiconductor 73 for the drift region is grown using the mask 69a. This growth is performed using, for example, an MOCVD furnace. According to this step, since the uppermost layer 67a of the mask 69a is made of group III nitride, the deposit 25 is also generated on the mask 67a, and the film forming gas is also consumed on the mask 69a. Therefore, protruding deposits grown along the edge of the n-type group III nitride semiconductor 73 for the n-type drift region can be reduced. In addition, contamination from the mask material of the uppermost layer 67a can be reduced. Furthermore, since the uppermost layer 67a is provided on the lowermost layer 65a, contamination from inorganic compounds in the lowermost layer 65a can be reduced. A group III nitride semiconductor 73 is grown in the opening 69b, and a deposit 25 is grown on the mask 69a.

  After this growth is completed, the mask 69a is removed as shown in FIG. The uppermost layer 67a of the mask 69a is made of group III nitride, and the deposit 25 is removed by etching or the like of the uppermost layer 67a. Further, the lowermost layer 65a of the mask 69a is removed. Since the lowermost layer 65a of the mask 69a is made of an inorganic compound containing at least one of oxygen and nitrogen as a constituent element and different from the group III nitride, the group III nitride region 13 is also removed when the lowermost layer 65a is removed. Damage to the surface 13k is reduced.

  Subsequently, the source region 53 is formed in the group III nitride semiconductor 63a for the p-type well in the same manner as the embodiment shown in FIGS. 7C, 8A, and 8B. . Next, a gate insulating film 55, a gate electrode 57a, a source electrode 57b, and a drain electrode 57c are formed. Through these steps, a vertical transistor including an embedded n-type drift region was manufactured. The group III nitride region 13 includes a p-type well layer 63a for a vertical transistor, and the group III nitride semiconductor 73 is embedded and grown in the group III nitride region 13 and provided for the n-type drift layer.

Example 4 Using a vertical transistor structure MOCVD furnace using embedded growth of an n-type drift layer, a 6 μm n-type GaN epitaxial layer and a 0.3 μm p-type GaN epitaxial layer are formed on a low-dislocation GaN substrate. grown. On this layer, a 1 μm SiN layer was grown using a pCVD apparatus, and then a 0.1 μm AlN layer was grown using a sputtering apparatus. A resist mask was formed, the AlN layer was etched using ammonia water, and then the SiN film was etched using BHF (110). Further, the p-type GaN layer and the n-type GaN layer were etched by dry etching (Cl ₂ gas, output 100 watts) to form a groove having a depth of 0.5 μm. After removing the resist, an n-type GaN drift layer was selectively grown. The average film thickness of the selectively grown n-type GaN was 0.5 μm. Thereafter, the selective growth mask (AlN / SiN mask) was removed using BHF (110). Silicon ion implantation / activation annealing was performed to form an n ⁺ -type GaN contact layer. After forming the gate insulating film, a drain electrode, a source electrode, a gate electrode, and the like are formed. Through these steps, a vertical transistor using buried growth of an n-type GaN drift layer was completed.

  In the semiconductor device manufactured according to Example 1-4, the amount of silicon mixed in can be greatly suppressed by using a multilayer mask such as an AlN / SiN mask without using a single-layer SiN mask for selective growth and regrowth. Improved device characteristics such as breakdown voltage.

(Example 5)
Using the MOCVD method, a 6 μm-thick GaN epitaxial layer was grown on a sapphire substrate (hereinafter referred to as “Sap substrate”). At that time, the flow rate of the Si dopant (for example, SiH ₄ ) was adjusted so that the silicon (Si) concentration in the epitaxial layer was 1 × 10 ¹⁶ cm ⁻³ . For the epitaxial layer, 12 kinds of evaluation samples were prepared as follows:
Sample 1: A SiO ₂ film having a thickness of 1 μm was formed using an electron beam (EB) method. A resist mask was formed on the SiO ₂ film using photolithography, and the SiO ₂ film was selectively etched using BHF (110).
Sample 2: A 1 μm SiN film was formed using the EB method. A resist mask was formed on the SiN film, and selective etching of the SiN film was performed using BHF (110).
Sample 3: 1 μm of SiO ₂ film was formed using the EB method, and then 0.1 μm of AlN was formed using sputtering. A resist mask was formed on the AlN film, AlN was selectively etched using ammonia water, and then the SiO ₂ film was selectively etched using BHF (110).
Sample 4: 1 μm of SiO ₂ film was formed using a pCVD apparatus. A resist was formed on the SiO ₂ film, and the SiO ₂ film was selectively etched using BHF (110).
Sample 5: A SiN film having a thickness of 1 μm was formed using a pCVD apparatus. A resist mask was formed on the SiN film, and selective etching of the SiN film was performed using BHF (110).
Sample 6: A 1 μm SiO ₂ film was formed using a pCVD apparatus, and then 0.1 μm AlN was formed using sputtering. A resist mask was formed on the AlN film, and selective etching of AlN was performed using ammonia water, and then the SiO ₂ film was etched using BHF (110).
Sample 7: A SiN film having a thickness of 1 μm was formed using a pCVD apparatus, and then an AlN film having a thickness of 0.1 μm was formed by sputtering. After forming a resist mask on the AlN film, selective etching of AlN was performed using ammonia water, and thereafter, the SiN film was etched using BHF (110).
Sample 8: An AlN film having a thickness of 1 μm was formed by sputtering. A resist mask was formed on the AlN film, and selective etching of AlN was performed using ammonia water.
Further, with respect to the embedded growth, the GaN epitaxial layer was further etched by 0.5 μm with respect to Sample 9: Sample 4 using an etching gas Cl ₂ using a resist mask.
Sample 10: The GaN epitaxial layer was further etched by 0.5 μm with respect to the sample 6 using an etching gas Cl ₂ using a resist mask.
Sample 11: The GaN epitaxial layer was further etched by 0.5 μm with respect to Sample 8 using an etching gas Cl ₂ using a resist mask.
Sample 12 for reference: no treatment (no mask at all, as grown)
Prepared. After removing the photoresist mask, a GaN epitaxial layer was grown on these samples by MOCVD. The film formation conditions were the same as the previous growth conditions, and the SiH ₄ flow rate was adjusted so that the Si concentration was 1 × 10 ¹⁶ cm ⁻³ .

The Si concentration of the epitaxial layer selectively grown (embedded growth or regrowth) on these 12 types of samples was measured using SIMS analysis. as a result,
Sample number Si concentration (cm ^-3 )
Sample 1: 5.2 × 10 ¹⁸ (SiO ₂ : EB)
Sample 2: 7.5 × 10 ¹⁸ (SiN: EB)
Sample 3: 8.2 × 10 ¹⁶ (AlN / SiO ₂ : EB)
Sample 4: 4.2 × 10 ¹⁷ (SiO ₂ : pCVD)
Sample 5: 5.3 × 10 ¹⁷ (SiN: pCVD)
Sample 6: 1.6 × 10 ¹⁶ (AlN / SiO ₂ : pCVD)
Sample 7: 1.8 × 10 ¹⁶ (AlN / SiN: pCVD)
Sample 8: 1.4 × 10 ¹⁶ (AlN)
Sample 9: 5.1 × 10 ¹⁷ (embedded growth of sample 4)
Sample 10: 1.9 × 10 ¹⁶ (embedded growth of sample 6)
Sample 11: 1.7 × 10 ¹⁶ (embedded growth of sample 8)
Sample 12: 1.0 × 10 ¹⁶ (nothing)
It became. By using an AlN film on the outermost surface of the selective growth mask (SiO ₂ or SiN), it has become possible to further suppress Si contamination. Furthermore, by changing the SiO ₂ film formation from the EB method to the pCVD method capable of forming a denser film, silicon contamination in the epitaxial layer can be greatly suppressed.

Next, the shape of the epitaxial layer produced by selective growth was evaluated. As a result of SEM observation using a scanning electron microscope, when AlN was used as the outermost surface of the selective growth mask, GaN polycrystals were grown on AlN. As a result, the rise of the edge portion (end portion) of the selective growth epitaxial layer was reduced (compared to the case where only SiN and SiO ₂ were used as a mask). When SiN or SiO ₂ is used for the mask, the raw material is not consumed on the mask, so that the raw material is concentrated and consumed at the edge portion of the opening (window region) of the mask, and the deposit rises. On the other hand, in the case of a mask material (for example, AlN) in which the raw material is consumed on the mask, the concentration of the raw material on the edge portion does not occur. Therefore, a flat epitaxial layer can be grown.

Next, the SiO ₂ , SiN, AlN, AlN / SiO ₂ , and AlN / SiN masks are removed after selective growth, and a Schottky electrode is formed on the removed portions of the masks. Evaluation was performed. At this time, no Schottky electrode is formed in the selectively grown portion. This is to evaluate the damage on the epi surface caused by removing the mask. Specifically, BHF (110) was used to remove the SiO ₂ , SiN, AlN / SiO ₂ , and AlN / SiN masks, and ammonia water heated and boiled was used to remove AlN. Thereafter, photolithography was performed and pretreatment was performed with dilute hydrochloric acid (for example, 10-fold dilution), and then an Au electrode was deposited to form a Schottky barrier diode. The IV characteristics in the reverse direction of this sample were evaluated. As a result, after removing the SiO ₂ , SiN, AlN / SiO ₂ , and AlN / SiN masks, the Schottky barrier diode fabricated on the n-type GaN surface leaks compared to the epitaxial layer of the sample 12 that does nothing. The current and withstand voltage are almost the same, and no deterioration in the characteristics is observed. According to this, it is considered that the GaN surface covered with the mask is not substantially damaged. On the other hand, the Schottky barrier diode fabricated on the n-type GaN surface from which the AlN mask has been removed has a large increase in leakage current and a significant decrease in breakdown voltage. That is, it is considered that some damage was applied to the surface of the GaN epitaxial layer grown after removing AlN. From this experiment, it can be understood that there are the following advantages by using an AlN / SiN, AlN / SiO mask or the like.
(1) Silicon can be significantly suppressed from being selectively grown in the epitaxial layer.
(2) The step of the edge portion of the selectively grown epitaxial layer can be reduced.
(3) No damage to the epitaxial layer surface after mask removal.
In particular, the silicon during selective growth can be greatly reduced (for example, less than 1 × 10 ¹⁷ cm ⁻³ ), and a wide control of the electrical characteristics of the selectively grown epitaxial layer is possible. That is, by significantly reducing the residual silicon, it is possible to provide growth of an epitaxial layer having a low carrier concentration and growth of a high resistance epitaxial layer that are indispensable for power devices. In addition, a p-type epitaxial layer can be easily manufactured. In this example, AlN / SiO ₂ and AlN / SiN were used as masks. However, the present embodiment is not limited to such a specific example, and GaN / SiO ₂ , GaN / SiN. , AlGaN / SiO ₂ , AlGaN / SiN, or the like can be used, and similar effects are obtained. Further, not only a two-layer mask but also AlN / GaN / SiO ₂ , AlN / GaN / SiN, or the like can be used. Further, the present embodiment is not limited to a Schottky barrier diode or a vertical transistor, but is also applied to a HEMT contact layer or the like.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1 is a drawing schematically showing a manufacturing process in the method of forming a semiconductor device according to the first embodiment. FIG. 2 is a drawing schematically showing a manufacturing process in the method of forming the semiconductor device according to the first embodiment. FIG. 3 is a drawing schematically showing a manufacturing process in the method of forming the semiconductor device according to the first embodiment. FIG. 4 is a drawing schematically showing a manufacturing process in the method for forming the shot barrier diode according to the second embodiment. FIG. 5 is a drawing schematically showing a manufacturing process in the method of forming the shot barrier diode according to the second embodiment. FIG. 6 is a drawing schematically showing a manufacturing process in the method for forming a vertical transistor according to the third embodiment. FIG. 7 is a drawing schematically showing a manufacturing process in the method of forming a vertical transistor according to the third embodiment. FIG. 8 is a drawing schematically showing a manufacturing process in the method of forming a vertical transistor according to the third embodiment. FIG. 9 is a drawing schematically showing a manufacturing process in the method of forming a vertical transistor according to the fourth embodiment. FIG. 10 is a drawing schematically showing a manufacturing process in the method of forming a vertical transistor according to the fourth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Substrate, 13 ... Group III nitride region, 13a, 13b ... Group III nitride region, 13c ... Main surface of group III nitride region, 13d ... Surface of group III nitride region, 13e ... Group III nitride Opening of the material region, 13g ... opening of the group III nitride region, 13h ... surface of the group III nitride region, 15, 17, 45, 47, 65, 67 ... film, 15a, 45a, 65a ... bottom layer, 17a, 47a, 67a ... top layer, 19, 49, 69 ... stacked, 21 ... mask, 19a, 49a, 69a ... mask, 19b ... mask opening, 23, 35, 51, 73 ... group III nitride semiconductor, 25 ... deposition 27 ... Schottky electrode, 29 ... Ohmic electrode, 31 ... Schottky barrier diode, 33 ... Mask, 39 ... Schottky electrode, 41 ... Schottky barrier diode, 43 ... Mask, 43a ... Mask opening, 51 ... p Group III nitride semiconductor for well, 53 ... source region, 55 ... gate insulating film, 57a ... gate electrode, 57b ... source electrode, 57c ... drain electrode, 59 ... vertical transistor, 61, 61a ... p-type well P-type group III nitride semiconductor layer 63, 63a ... n-type group III nitride semiconductor layer for drift region 71 ... mask 71a ... opening of mask

Claims (17)

A method of forming a semiconductor device using a group III nitride semiconductor,
Growing a group III nitride region having first and second regions on a substrate;
The III-nitride region, and forming a laminate comprising a plurality of layers for the mask in the first region,
Growing a group III nitride semiconductor using the mask;
And a step of removing the mask after growing the group III nitride semiconductor ,
In the step of removing the mask, the plurality of layers of the mask are removed,
The uppermost layer of the plurality of layers of the mask is made of group III nitride,
The lowermost layer of the plurality of layers of the mask is made of an inorganic compound different from the group III nitride containing at least one of oxygen and nitrogen as a constituent element,
The bottom layer covers the first region;
The method, wherein the mask has an opening located in the second region.   The method of claim 1, wherein the top layer of the mask comprises GaN.   The method of claim 1, wherein the top layer of the mask comprises AlN.   The method of claim 1, wherein the top layer of the mask comprises AlGaN.   The method according to claim 1, wherein the uppermost layer of the mask is made of a group III nitride containing at least Al and In as constituent elements.   The method according to claim 1, wherein the lowermost layer of the mask is made of aluminum oxide.   6. The method according to claim 1, wherein the lowermost layer of the mask is made of a silicon inorganic compound.   The method according to claim 1, wherein the group III nitride semiconductor exhibits p conductivity. 9. The method according to claim 7, wherein the group III nitride semiconductor exhibits a silicon concentration of 1 × 10 ¹⁷ cm ⁻³ or less. Etching the group III nitride region using the mask to further form a recess in the second region of the group III nitride region;
The method according to claim 1, wherein the group III nitride semiconductor is embedded and grown in the recess of the group III nitride region using the mask. Prior to the formation of the mask, further comprising the step of forming a group III nitride layer having a main surface,
The group III nitride region includes the group III nitride layer;
The mask is formed on the main surface of the group III nitride layer,
The method according to claim 1, wherein the group III nitride semiconductor is regrown on the group III nitride layer using the mask. The semiconductor device is a Schottky barrier diode,
The method includes forming a Schottky electrode on the group III nitride region after removing the mask; and
Forming an electrode on the back surface of the substrate;
Further comprising
The III-nitride region includes an n-type drift layer for the Schottky barrier diode;
The method according to claim 1, wherein the group III nitride semiconductor includes a p-type guard ring layer regrown on the group III nitride region. The semiconductor device is a Schottky barrier diode,
The III-nitride region includes an n-type drift layer for the Schottky barrier diode;
The method is
Prior to growing the group III nitride semiconductor, etching the group III nitride region using the mask to form a recess in the second region of the group III nitride region; and
Forming a Schottky electrode on the III-nitride region after removing the mask; and
Forming an electrode on the back surface of the substrate;
Further comprising
The method according to any one of claims 1 to 7, wherein the group III nitride semiconductor includes a p-type guard ring region embedded and grown in the recess of the group III nitride region. . The semiconductor device is a vertical transistor;
The III-nitride region includes an n-type drift layer for the vertical transistor;
The group III nitride semiconductor is formed for a p-type well region embedded and grown in the group III nitride region,
The method is
Prior to growing the group III nitride semiconductor, etching the group III nitride region using the mask to form a recess in the second region of the group III nitride region; and
Forming a gate insulating film on the p-type well region after removing the mask ;
Forming an electrode on the back surface of the substrate;
The method according to claim 1, further comprising: The semiconductor device is a vertical transistor;
The method is
Prior to the formation of the mask, forming a group III nitride layer having a main surface and for the p-type well region of the vertical transistor;
Prior to growing the group III nitride semiconductor, etching the group III nitride region using the mask to form a recess in the second region of the group III nitride region; and
Forming a gate insulating film on the p-type well region after removing the mask ;
Forming an electrode on the back surface of the substrate;
Further comprising
The group III nitride semiconductor is formed for an n-type drift region embedded and grown in the group III nitride layer,
The group III nitride region includes the group III nitride layer;
The method according to claim 1, wherein the mask is formed on the main surface of the group III nitride layer. The mask consists of two layers,
The method according to claim 1, wherein the lowermost mask thickness is greater than the uppermost mask thickness.   The method according to claim 1, wherein a film thickness of the group III nitride semiconductor grown using the mask is thinner than a thickness of the mask.

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