JP2011505064A - Electronic device fabrication process - Google Patents

Abstract

The present invention comprises the following continuous layers on the support layer (1): a layer (2, 3) configured to contain an electron gas, a barrier layer (4), a surface layer (7a), , And an etching method for at least a part of the surface layer (7a), and an electronic device made of a Group III / N material and a method for manufacturing the same. After the etching step, epitaxial regrowth is performed to grow a cover layer (7b) on the etched surface layer (7a). The material of the surface layer (7a) and the material of the covering layer (7b) contain at least one group III element and nitrogen.
[Selection] Figure 3D

Description

  The present invention relates to group III / N material based electronic devices such as rectifiers or field effect transistors such as, for example, high electron mobility transistors (HEMT) or insulated gate semiconductors (MIS). A Group III / N material is a material that includes at least one Group III element and nitrogen.

  Etching processes are often used in the production of electronic devices.

  FIG. 1C is a schematic diagram of a known type of electronic device. The electronic device typically includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a surface layer 7, an ohmic contact electrode 5, and a Schottky contact electrode from the base toward the surface. 8 and a passivation layer 9. In the case of a HEMT transistor or rectifier, the Schottky contact 8 is made in direct contact with the surface layer 7, whereas in the case of a MIS transistor, the Schottky contact 8 is deposited on the passivation layer 9.

  The essential function of the substrate layer 1 is to ensure the rigidity of the device.

  The substrate layer 1 is covered with a buffer layer 2 and a layer configured to contain an electron gas. These two layers may be separate, in which case the layer configured to contain the electron gas is commonly referred to as the “channel layer” 3. However, these two layers can be combined, and the buffer layer 2 can flow an electron gas by the heterojunction formed at the interface with the barrier layer 4. In this case, the channel does not belong to a layer separate from the buffer layer, but is defined on the top of the buffer layer by the heterojunction formed in the barrier layer.

  The buffer layer 2 exhibits good crystal quality and characteristics suitable for epitaxial growth of other layers covering the buffer layer. Therefore, this ensures a crystal transition between the substrate layer 1 and the layer formed on the buffer layer. The buffer layer 2 is made of, for example, a group III / N element binary, ternary, or quaternary alloy such as GaN.

  Also, if the buffer layer is configured to contain an electron gas, the buffer layer is made of a material having a smaller band gap than that of the barrier layer so that the electron gas can be formed and flowed. There must be.

  If there is a channel layer 3 separate from the buffer layer 2, the channel layer is binary, ternary, such as GaN, BGaN, InGaN, AlGaN, or another alloy with a smaller band gap than that of the barrier layer, Or made from Group III / N elements, which may be quaternary alloys.

  The role of the barrier layer 4 is to supply free electrons to the structure, ie the barrier layer 4 is called a donor layer. The barrier layer 4 includes a material composed of a binary, ternary, or quaternary alloy of Group III / N elements.

  If the band gap of the layer configured to contain the electron gas is always smaller than that of the barrier layer, the choice of the material of the barrier layer and the layer configured to contain the electron gas is free.

  The ohmic contact electrode 5 can inject or collect carriers. In the case of a transistor, there are two ohmic contact electrodes: the source is an electrode that injects carriers into the structure, while the drain is an electrode that collects carriers. In the case of a rectifier, there is only one ohmic contact electrode. The ohmic contact electrode 5 is generally composed of a surface layer of a metal layer deposited within the upper surface or thickness of the barrier layer 4 in order to ensure good ohmic contact.

  The barrier layer 4 may generally be covered with a surface layer 7 except for the position of the ohmic contact electrode. The surface layer 7 avoids deterioration of the structure and contributes to ensuring good Schottky contact with the Schottky contact electrode 8 deposited on the surface layer.

Finally, a passivation layer 9 made of, for example, ZnO, Si ₃ N ₄ or MgO is applied so as to encapsulate the device. Passivation generally protects the surface of the semiconductor.

  In making such devices, various etching steps are often utilized starting with the initial structure depicted in FIG. 1A. The initial structure has a structure in which a buffer layer 2, a channel layer 3, a barrier layer 4, and a surface layer 7 are continuously grown on the substrate layer 1.

  Referring to FIG. 1B, an isolation etch can be performed to form an isolation trench 10 between two devices to isolate devices fabricated in the same wafer. Such an etching depth passes through the barrier layer and the channel layer so as to reach the isolation buffer layer.

  In addition, in order to form the trench 11 under the ohmic contact electrode so as to deposit the ohmic contact electrode 5 in direct contact with the barrier layer 4 or the ohmic contact electrode 5 within the thickness of the barrier layer 4, the barrier layer 4 is formed. It is customary to etch the surface layer 7.

  It is also known that the trench 12 can be etched under the Schottky contact electrode 8. Such trenches, known as “gate recesses”, provide a shape effect on the surface layer 7 to help maintain high electron gas density by locally reducing the thickness of the surface layer 7. The closer the Schottky contact electrode 8 and the channel layer 3 are in the recess 12, the better the electronic control by the Schottky contact electrode.

  The gate recess 12 under the Schottky contact electrode 8 may be formed not only on the surface layer 7 but also on a part of the barrier layer 4. By increasing the depth of the gate recess 12 in this way, the proximity to the channel layer 3 is increased, and thus electronic control is further enhanced. However, since the barrier layer 4 constitutes a free electron storage part of the channel layer 3, it must have a thickness sufficient to maintain a sufficient electron gas density. Therefore, on the one hand, there is a compromise between the functional improvement obtained by bringing the Schottky contact electrode 8 closer to the channel layer 3 and the lowering of the electron gas density caused by the etching of the barrier layer 4. It is necessary to decide. In fact, it is considered that the thickness of the barrier layer 4 must be greater than 2 nm.

  However, in the etching process described above, the surface state after etching tends to be deteriorated as compared to the surface state of the material before etching. In particular, RIE (reactive ion etching) that is routinely used to form isolation trenches in devices is highly erodible and damages the surface. Prior to etching, the surface of the layer is defined by entanglements associated with entanglement of atomic steps and dislocations emerging from the crystal of the material. When this form is destroyed by etching, surface defects and “surface states” including localized electronic states may be formed on the surface acting as electron traps, and etching is preferentially performed around dislocations. Can happen.

  As a result, in particular, the density of crystal defects and electron traps increases, and a leakage current is generated at the interface between the surface layer 7 and the passivation layer 9, leading to a decrease in device performance.

  Therefore, surface damage due to etching is a problem that emerges when an electronic device is manufactured.

  In view of the above, one of the objects of the present invention is to provide a method that eliminates all these drawbacks by obtaining a device whose performance is not degraded by the etching operation. A further object of the present invention is to create an electronic device in which the leakage current associated with etching is controlled and maintained below a certain level.

According to the present invention, the following continuous layers on the support layer:
A layer configured to contain an electron gas;
A barrier layer;
A surface layer;
Epitaxially growing and etching to at least a portion of the surface layer, the process of making an electronic device made of a Group III / N material, after the etching step, on the etched surface layer In order to grow the cover layer, epitaxial regrowth is performed, and a process is provided wherein the surface layer material and the cover layer material comprise at least one Group III element and nitrogen.

  Etching at least part of the surface layer means etching part of the thickness of the surface layer and / or part of the surface of the surface layer. The expression “epitaxial regrowth is performed to grow a coating layer on the etched surface layer” means that the coating layer covers the entire surface of the resulting structure at the completion of the etching step. That is, if the surface layer is etched only a part of the thickness of the layer, the covering layer covers the entire surface layer, and the surface layer exposes the underlying layer to form one or more trenches. If etched locally over the entire thickness of the layer, the covering layer covers not only the surface layer of the remaining area, but also the underlying layer exposed in the trench.

  In certain embodiments, etching is performed over a portion of the thickness of the barrier layer.

  During epitaxial regrowth, the overlayer can be grown and doped.

  In a preferred method, etching of the surface layer is performed at the intended location relative to the Schottky contact electrode so as to form a trench under the Schottky contact electrode.

  After formation of the cover layer, the process preferably includes the following steps: forming a Schottky contact electrode in the trench and forming a passivation layer.

  In a variation of the embodiment, the coating layer and the surface layer so as to form an ohmic contact electrode on the barrier layer or within the thickness of the barrier layer at a predetermined location of the at least one ohmic contact electrode after formation of the coating layer. A trench having a depth equal to or greater than the thickness of is etched.

  A further subject matter of the present invention is a barrier layer comprising a substrate layer, a layer configured to contain an electron gas, a barrier layer, and at least one trench, continuously from the base of the electronic device to the surface. An electronic device made of a Group III / N material comprising a surface layer over at least a portion of the surface, wherein the surface layer and one or more of the trenches are separated by a plateau greater than 2 nm in width The invention relates to an electronic device, characterized in that it is covered by a covering layer having a surface exhibiting atomic steps, the surface layer material and the covering layer material comprising at least one group III element and nitrogen.

  The electronic device preferably includes an ohmic contact electrode disposed on the barrier layer or within the thickness of the barrier layer.

  The electronic device may also include a Schottky contact electrode disposed on the covering layer in the trench having a depth greater than or equal to the thickness of the surface layer.

  In a preferred embodiment, the surface layer is undoped and the cover layer is doped.

1 is a cross-sectional view of a known type of electronic device showing various fabrication steps of the electronic device. 1 is a cross-sectional view of a known type of electronic device showing various fabrication steps of the electronic device. 1 is a cross-sectional view of a known type of electronic device showing various fabrication steps of the electronic device. It is a photograph of the surface of a HEMT transistor. 1 is a cross-sectional view of an electronic device according to the present invention showing various fabrication steps of the electronic device. 1 is a cross-sectional view of an electronic device according to the present invention showing various fabrication steps of the electronic device. 1 is a cross-sectional view of an electronic device according to the present invention showing various fabrication steps of the electronic device. 1 is a cross-sectional view of an electronic device according to the present invention showing various fabrication steps of the electronic device.

  The invention will be better understood and other advantages and features of some embodiments and examples will become apparent from the following description with reference to the accompanying drawings.

Leakage Current In the prior art electronic device, a leakage current occurs at the interface between the surface layer 7 and the passivation layer 9. These currents contribute to the performance degradation of the electronic device.

Thus, in the case of a HEMT transistor, for example, a reverse leakage current of 10 ⁻⁹ to 10 ⁻⁸ A / mm was observed at a gate-source potential of −1 V (in this regard, T. Kikkawa, Fujitsu , Compound Semiconductor, July 2006, Vol. 12, No. 6, pages 23-25).

  FIG. 2 is a photograph of the surface of a HEMT transistor fabricated by molecular beam epitaxy (MBE) with a GaN surface layer on an AlGaN barrier layer and a GaN buffer layer. In this photograph, it was observed that the surface layer had dents D due to entanglement of atomic steps M and dislocations. The height of step M is approximately 0.25 nm.

  There are several phenomena as causes of the leakage current.

Interface state between the surface layer and the passivation layer. For example, in the case of a GaAs-based transistor, it is known that a native oxide Ga ₂ O ₃ formed from GaAs is unstable and causes trap formation at the interface.

Defects arising from crystals of semiconductor material on the surface layer. For example, GaN typically has 10 ⁷ to 10 ⁹ dislocations per cm ² in the thickness direction. This creates a dent on the surface where the stress varies locally. The combined effect of surface morphology and stress can affect the interface state with the passivation layer. For example, when the potential at the interface changes, the flow and presence of trapped electrons change.

  Etching (especially RIE) process that is somewhat erosive and can damage the surface. As shown in FIG. 2, when the initial shape of the surface is destroyed, the formation of a surface state occurs, and etching preferentially occurs around the dislocations, and a new phenomenon can occur.

DESCRIPTION OF THE INVENTION First, the initial structure of an electronic device according to the present invention will be described from the base to the surface.

  Referring to FIG. 3A, the initial structure of this device comprises a substrate layer 1, an optional buffer layer 2, a channel layer 3, a barrier layer 4, and a surface layer 7a.

  The substrate layer 1 may be made of, for example, silicon, SiC, GaN, or AlN.

  The buffer layer 2 is made of a material containing nitrogen and at least one element of Group III of the periodic table, for example, GaN, AlGaN or AlN, BGaN or InGaN.

  The channel layer 3 is formed of a material containing nitrogen and at least one element of group III of the periodic table. However, if this material is the same as that of the buffer layer, a material with a band gap of this material smaller than that of the barrier layer must be selected to collect the electron gas. If the material is different from that of the buffer layer, the band gap of this material needs to be smaller than that of the buffer layer material. The channel layer is preferably formed from GaN or InGaN.

  The barrier layer 4 comprises nitrogen and at least one element from group III of the periodic table and is formed from a material selected such that the band gap is greater than that of the channel layer material.

  The surface layer 7a is also formed from a material containing nitrogen and at least one element from group III of the periodic table. The surface layer 7a is preferably made of GaN, AlGaN or InGaN and should be selected such that the band gap is smaller than that of the barrier layer material. The barrier layer 4 may be made of, for example, AlGaN having an aluminum content of 50 to 70% of the group III element, and the surface layer 7a is made of AlGaN having an aluminum content of 20%. It may be. If the aluminum content of the AlGaN barrier layer 4 is approximately 20%, the aluminum content of the surface layer 7a is preferably 5% or less. The thickness of the surface layer 7a is in the range of 1 to 10 nm.

  The layer is grown by an epitaxy process (for example, MBE (molecular beam epitaxy)). It should be noted that epitaxy is a technique for growing two crystals having a certain number of common elements with symmetry of the crystal lattice, oriented in relation to each other. In addition to molecular beam epitaxy, there are various epitaxy techniques such as metal organic chemical vapor deposition (MOCVD), low pressure chemical vapor deposition (LPCVD), or hydride vapor phase epitaxy (HVPE).

  Referring to FIG. 3B, in the initial structure shown in FIG. 3A, at least one etching of the surface layer 7a is performed, for example, to form the trench 12 under the Schottky contact electrode or to form the isolation trench 10. Executed. From this, the surface layer 7a is etched all or part of its thickness.

  The present invention generally provides an epitaxial for forming a coating layer 7b on an etched surface layer 7a while performing an etching operation on the epitaxial surface layer 7a and covering one or more etched trenches. Includes regrowth.

  Epitaxial regrowth should be understood as meaning that the second epitaxy step is performed after an intermediate technical step (such as etching or cleaning) performed after the first epitaxy step.

  During this second epitaxy step, the same material as the first epitaxy step may be grown or a different material may be grown. Similarly, epitaxial regrowth may use the same technique as the first step or a different technique.

  For example, the cover layer 7b may be grown by MOCVD after the surface layer 7a is grown by MBE.

  The material of layer 7b includes nitrogen and at least one element from group III of the periodic table, i.e. may be the same as that of layer 7a.

  In order to improve the surface quality of the device, the lattice parameter of the material of the covering layer 7b is sufficiently close to that of the material of the surface layer 7a, for example, the mismatch of the lattice parameters is preferably less than 1%.

  This is because when the difference between the lattice parameters of the layers 7a and 7b is large, there is a risk of forming defects and / or cracks in the layer 7b if the layer 7b exceeds a certain thickness.

  Furthermore, in order to avoid stresses due to differences in thermal expansion coefficients, the temperature of the epitaxy of the material of the layers 7a and 7b is preferably not very different, for example this temperature difference is less than 400 ° C.

  Referring to FIG. 3C, since the covering layer 7b has a constant thickness over the entire surface of the covering layer, the profile of the covering layer is the profile of the surface layer 7a and the one or more trenches in which the surface layer 7a is formed. Follow the profile. The thickness of the coating layer 7b is in the range of 1 to 20 nm.

  Epitaxial regrowth has the effect of improving and repairing the crystal lattice of the surface layer 7a damaged by the etching process, thereby limiting the leakage current at the interface between the cover layer 7b and the passivation layer.

  In fact, it has been observed that the surface damaged by etching is characterized by successive atomic steps separated by less than 2 nm. Thus, a plateau with a width of less than 2 nm can be defined between two adjacent steps.

  On the other hand, the epitaxial growth on the damaged surface results in the growth of a coating layer whose surface contains atomic steps separated by at least 2 nm, ie a plateau having a width greater than 2 nm.

  The size of the plateau is directly related to the presence of leakage current at the interface between the surface layer and the passivation layer. In fact, the smaller the plateau, the greater the number of crystal defects, surface states, and electron traps, and the higher the probability that a leakage current will be formed.

  Thus, the surface layer 7 having a different structure depending on the region of the device has been formed on the surface of the electronic device. In detail

  In a region where the surface layer 7 a is not etched, the surface layer 7 is formed from both the surface layer 7 a and the covering layer 7 b, and this configuration is typically between the ohmic contact electrode 5 and the Schottky contact electrode 8. Occurs in the located area

  In the region where the surface layer 7a is partially etched, the surface layer 7 is composed of a residual surface layer and a coating layer 7b.

  Finally, in the region where the surface layer 7A is etched over the entire thickness, or in the region where the surface layer 7A is etched deeper into the barrier layer 4, the channel layer 3, or the buffer layer 2, the surface layer 7 is composed only of the covering layer 7b. . This situation is typically a Schottky contact trench (etch depth limited to a portion of the barrier thickness at most), or an isolation trench between devices (etching is performed on the surface of the isolation buffer layer or Stops within the thickness).

  The covering layer 7b formed by epitaxial regrowth may be made of the same material as that of the surface layer 7a, but may be doped with a different material.

Thus, the device may have an undoped surface layer 7a but has a coating layer 7b doped, for example, in the range of 5 × 10 ¹⁷ atoms / cm ^{3 to} 5 × 10 ¹⁹ atoms / cm ^3. May be.

  The dopant used is typically silicon or germanium.

The surface layer 7a may also be lightly doped in the range of 0-5 × 10 ¹⁷ atoms / cm ³ , thereby suitably reducing electron traps.

An example embodiment comprises a surface layer 7a doped at a concentration of 2 × 10 ¹⁵ atoms / cm ³ and a coating layer 7b more highly doped at a concentration of 5 × 10 ¹⁸ atoms / cm ^3. Also good.

  After the formation of the covering layer 7b, it is preferable to deposit the passivation layer 9 that covers the isolation trench 10 and the gate recess 12 as a result.

  Note that in certain areas of the device, it may be preferable to have no surface layer.

  In particular, it is easier to obtain a metal electrode alloy with AlGaN than the surface layer material (GaN), so that the ohmic contact electrode 5 is generally formed directly on the barrier layer 4 or within the thickness of the aluminum-rich barrier layer. Preferably formed, this improves ohmic contact where very low contact resistance is required.

  Therefore, after the formation of the covering layer 7b and the passivation layer 9, the etching is performed at the predetermined positions of the ohmic contact 5, at least the passivation layer 9, the covering layer 7b, and the surface layer 7a until the barrier layer 4 is reached.

  Referring now to FIG. 3D, the ohmic contact electrode 5 is deposited on the barrier layer 4 or within the thickness of the barrier layer 4, and the Schottky contact electrode 8 is deposited on the passivation layer 9 in the case of a MIS transistor. . In the case of a HEMT transistor, the Schottky contact electrode 8 is deposited in direct contact with the covering layer 7b, and then a passivation layer is deposited.

  From the above, the leakage current associated with the etching process is limited, so that the electronic devices described above are given higher performance than current state of the art devices.

  However, it should be noted that surface defects associated with the etching process are not the only cause of leakage current. Some of the leakage current is unique, in other words, it depends on the nature of the material. Leakage current due to causes other than etching may continue to exist in the device.

  The present invention preferably comprises a HEMT or MIS field effect transistor comprising a Schottky contact electrode and an ohmic contact electrode, or two ohmic contact electrodes (known as drain and source) and a Schottky contact electrode (known as gate). Applies to rectifiers including

Claims (11)

On the support layer (1), the following successive layers:
Layers (2, 3) configured to contain an electron gas;
A barrier layer (4);
A surface layer (7a);
Epitaxially growing, and
Etching to at least a portion of the surface layer (7a), and a process for making an electronic device made of a Group III / N material,
After the etching step, an epitaxial regrowth is performed to grow a coating layer (7b) on the etched surface layer (7a), the material of the surface layer (7a) and the coating layer (7b) A process, characterized in that the material comprises at least one group III element and nitrogen.   The etching process includes a step of forming at least one trench in the surface layer (7a), the depth of the trench is equal to or greater than the thickness of the surface layer (7a), and the covering layer (7b) 2. Process according to claim 1, characterized in that it covers the surface layer (7a) and the trench.   Process according to claim 1 or 2, characterized in that etching is carried out over a part of the thickness of the barrier layer (4).   4. Process according to any one of claims 1 to 3, characterized in that the coating layer (7b) is grown and doped during epitaxial regrowth.   Etching of the surface layer (7a) is performed at an intended position relative to the Schottky contact electrode (8) so as to form a trench (12) under the Schottky contact electrode, The process according to any one of claims 1 to 4. After the formation of the coating layer (7b), the following steps:
Forming a Schottky contact electrode (8) in the trench (12);
Forming a passivation layer (9);
The process of claim 5, comprising:   After the formation of the covering layer (7b), the ohmic contact electrode (5) is formed on the barrier layer (4) or within the thickness of the barrier layer at a predetermined position of the at least one ohmic contact electrode (5). A trench having a depth equal to or greater than the thickness of the covering layer (7b) and the surface layer (7a) is etched. The process described in Continuously from the base of the electronic device to the surface,
A substrate layer (1);
Layers (2, 3) configured to contain an electron gas;
A barrier layer (4);
A surface layer (7a) over at least part of the surface of the barrier layer (4), comprising at least one trench (10, 12);
An electronic device made of a Group III / N material, wherein the surface layer (7a) and one or more of the trenches exhibit a surface exhibiting atomic steps separated by a plateau having a width greater than 2 nm. An electronic device covered with a covering layer (7b) having the material of the surface layer (7a) and the material of the covering layer (7b) containing at least one group III element and nitrogen.   9. Electronic device according to claim 8, characterized in that it comprises an ohmic contact electrode (5) provided on the barrier layer (4) or within the thickness of the barrier layer (4).   The Schottky contact electrode (8) provided on the covering layer (7b) in the trench (12) having a depth equal to or greater than the thickness of the surface layer (7a). 9. The electronic device according to 9. 11. Electronic device according to any one of claims 8 to 10, characterized in that the surface layer (7a) is not doped and the covering layer (7b) is doped.

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