WO2021208322A1 - 一种多芯片散热封装结构及封装方法 - Google Patents

一种多芯片散热封装结构及封装方法 Download PDF

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Publication number
WO2021208322A1
WO2021208322A1 PCT/CN2020/111972 CN2020111972W WO2021208322A1 WO 2021208322 A1 WO2021208322 A1 WO 2021208322A1 CN 2020111972 W CN2020111972 W CN 2020111972W WO 2021208322 A1 WO2021208322 A1 WO 2021208322A1
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Prior art keywords
concave
chip
pads
formal
inverted
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PCT/CN2020/111972
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English (en)
French (fr)
Inventor
王栋
郑琦
曹权
汤荣耀
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烽火通信科技股份有限公司
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Priority to BR112022015064A priority Critical patent/BR112022015064A2/pt
Publication of WO2021208322A1 publication Critical patent/WO2021208322A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]

Definitions

  • the invention relates to the technical field of semiconductor packaging, in particular to a multi-chip heat dissipation packaging structure and packaging method.
  • the integration of devices has become higher and higher, and it has become a development trend to package multiple chips together to form highly integrated devices.
  • the heat dissipation problem of multi-chip integrated devices has become a major bottleneck in package design, especially the heat dissipation of high-frequency chips that are installed as a problem that needs to be solved urgently.
  • the traditional solution is to perform heat dissipation through the upper surface of the chip after flip-chip packaging. That is, by adding a heat dissipation cover on the flip chip, and then contacting the heat sink with thermally conductive glue on the heat dissipation cover, the heat generated when the chip is working is dissipated.
  • the heat dissipation of the formal chip also adopts a design structure in which a metal conductor is placed directly above the chip to dissipate the heat (as described in the patent CN102347293A), but for high-frequency chips, especially gallium arsenide and gallium nitride
  • high-frequency signal interconnection links will be designed on the surface.
  • the metal conductors in this package structure will directly contact or be very close to the signal link conductors on the top surface of the chip and the gold wire bonding wires, resulting in high-frequency signals. Problems such as crosstalk, resonance and antenna effect during transmission seriously affect the signal transmission performance of high-frequency chips, so the heat dissipation is limited to low-frequency formal chips.
  • the traditional solution is to design a thermally conductive hole or a thermally conductive metal block in the package carrier, and the heat generated by the chip can be dissipated through this channel.
  • this heat dissipation method also requires direct contact between the bottom of the device and the assembled circuit board to achieve better heat dissipation.
  • the contact surface with the assembled circuit board is very small (the contact surface between the chip and the circuit board is only shown on the BGA contact point), which increases the thermal resistance between the device and the circuit board, and its heat dissipation capacity is very good. limited.
  • Another way to dissipate heat is to remove the corresponding BGA directly below the inverted chip in the device during package design, so that the heat dissipation metal can directly contact the bottom of the package carrier through the high thermal conductivity adhesive , Thereby reducing the thermal resistance between the bottom of the chip and the external heat-dissipating metal conductor, and achieve high-efficiency heat dissipation.
  • the technical problem to be solved by the embodiment of the present invention is that the existing heat dissipation packaging method cannot effectively meet the requirements of the multi-chip scenario when applied to the multi-chip scenario; especially when the high-frequency forward rotation chip and/or the lower area of the chip are relatively large. Small formal chip occasions.
  • the present invention provides a multi-chip heat-dissipating package structure, including an inverted formal-mounted chip and at least one ordinary formal-mounted chip, specifically:
  • the inverted chip is arranged on the concave bottom of the concave pre-packaged carrier board, wherein the concave bottom of the concave pre-packaged carrier board is provided with a first set of pads, and the first set of pads is used to interact with the inverted front mounting
  • the pins of the chip are electrically connected; the first set of pads transmits electrical characteristics to the end area of the concave side wall through the concave side wall of the concave pre-packaged carrier board, so that the concave pre-packaged carrier board can be reversed When on the bottom plate, realize the electrical connection between the inverted chip and the bottom plate;
  • the outer surface of the concave bottom of the concave pre-packaged carrier board is further provided with a heat dissipation component, the heat dissipation component is coupled with the bottom of the inverted chip, and is used to drain away the heat generated when the inverted chip works;
  • the ordinary form-fitting chip is arranged on the bottom plate, and heat is dissipated through the bottom plate itself and the packaging cavity itself.
  • the concave pre-packaged carrier board realizes the electrical connection between the inverted chip and the bottom plate when the concave pre-packaged carrier board is upside down on the bottom plate, which specifically includes: a ball grid is provided at the end of the concave side wall of the concave pre-packaged carrier board The array bumps are soldered with the corresponding ball grid array pads on the bottom plate to complete the electrical connection between the inverted chip and the circuit on the bottom plate; or, the concave side wall of the concave pre-packaged carrier is provided with a second Set the pads, and complete the electrical connection between the inverted chip and the circuit on the bottom board by using gold wire bonding with the third set of pads on the bottom board located around the concave pre-packaged carrier board.
  • the concave pre-packaged carrier board is made of ceramic or semiconductor material, and the corresponding concave bottom for setting up the inverted positive chip is made with a through hole structure;
  • the heat dissipation component includes a thermal conductive glue and a thermal conductive metal gasket; specific:
  • the thermally conductive metal gasket is fixed on the outer side of the concave bottom of the concave pre-packaged carrier board, and the bottom of the inverted positive chip passes through the through hole of the concave bottom through the thermally conductive glue, and is connected to the thermally conductive metal gasket. fit.
  • the first set of pads transmits electrical characteristics to the end region of the concave side wall through the concave side wall of the concave pre-packaged carrier board, which specifically includes:
  • the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors, wherein electrical rails are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails between the layers are coupled with each other ;
  • a conductive medium is arranged in the electrical guide rail to complete the electrical connection between the first group of pads located at the bottom of the concave and the bumps of the ball grid array at the end; or to complete the first group of pads at the bottom of the concave Electrical connection with the second set of pads arranged on the concave sidewall.
  • the packaging structure further includes a metal cover, specifically:
  • the metal cover is fixed on the bottom plate, and the thermally conductive coupling between the thermally conductive metal gasket and the metal cover is completed by a TIM material.
  • the ordinary formal chip is arranged on the bottom plate, which specifically includes:
  • a set of heat dissipation holes are provided in the area where the ordinary formal chip is arranged, and the heat dissipation holes penetrate the bottom plate to provide a channel for heat dissipation at the bottom of the ordinary formal chip.
  • the packaging structure further includes:
  • the concave side wall of the concave pre-packaged carrier board is fixed on the bottom plate in the area of the bottom plate enclosed by the bottom plate, and at least one ordinary formal chip is arranged.
  • the packaging structure further includes:
  • a metal isolation cover plate for isolating high-frequency signals is provided in the concave area of the concave pre-packaged carrier board at a predetermined distance from the high-frequency front-mounted chip.
  • the packaging structure further includes:
  • a metal isolation layer is arranged inside the concave side wall or on the outside of the concave side wall of the concave pre-packaged carrier board.
  • At least one ordinary formal mounting chip is provided in the bottom plate area enclosed by the concave side wall of the concave pre-packaged carrier board fixed on the bottom plate, specifically for:
  • the ordinary formal-mounted chip that is more sensitive to high-frequency interference.
  • the power consumption density of the front-mounted chip (the power of the chip divided by the heat dissipation area at the bottom of the chip) is greater than 0.5 W/mm 2 , it is confirmed as the inverted front-mounted chip.
  • the present invention also provides a multi-chip heat dissipation packaging method, including:
  • the at least two formal chips involved in the package structure are analyzed, and the at least two formal chips are divided into an inverted formal chip and a normal formal chip according to the analysis result and a preset strategy; wherein the inverted formal chip is set in a customized A concave pre-packaged carrier board, on which the ordinary formal chip is arranged on the bottom board;
  • the concave pre-packaged carrier is fixed on the carrier. The designated position of the bottom plate;
  • the first set of pads on the concave bottom of the concave pre-packaged carrier board, the second set of pads on the matching concave sidewall, and the first set of pads and the second set of pads are designed.
  • the electrical connection includes:
  • the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors, wherein electrical rails are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails between the layers are coupled with each other ;
  • a conductive medium is arranged in the electrical rail to complete the electrical connection between the first set of pads at the bottom of the concave and the second set of pads on the sidewall of the concave.
  • the first set of pads on the concave bottom of the concave pre-packaged carrier board, the ball grid array bumps at the ends of the matching concave sidewalls, and the first set of pads and the ball grid array bumps are designed.
  • the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors, wherein electrical rails are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails between the layers are coupled with each other ;
  • a conductive medium is arranged in the electrical rail to complete the electrical connection between the first set of pads at the bottom of the concave and the bumps of the ball grid array at the end of the concave sidewall.
  • the present invention provides a multi-chip heat dissipation packaging structure and packaging method.
  • the packaging structure conducts the heat generated by the chip to the top of the device packaging metal cover through the heat dissipation component contacting the bottom of the chip, thereby realizing efficient heat dissipation of the chip and ensuring the Normal operation; compared with the prior art, in the packaging structure of the present invention, when the inverted formal mounting chip is a high-frequency formal mounting chip, there is no additional metal conductor on the upper surface of the high-frequency formal mounting chip, which will not affect the high-frequency formal mounting The signal transmission performance inside the chip and when the chip is interconnected with the package carrier.
  • FIG. 1 is a schematic cross-sectional view of a multi-chip heat dissipation package structure provided by an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view of a pre-packaged carrier in a multi-chip heat dissipation package structure provided by an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view of a multi-chip heat dissipation package structure provided by an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional view of a pre-packaged carrier in a multi-chip heat dissipation package structure provided by an embodiment of the present invention
  • FIG. 5 is a schematic cross-sectional view of a pre-packaged carrier in a multi-chip heat dissipation package structure provided by an embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional view of a multi-chip heat dissipation package structure provided by an embodiment of the present invention.
  • FIG. 7 is a schematic cross-sectional view of another multi-chip heat dissipation package structure provided by an embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of a multi-chip heat dissipation packaging method according to an embodiment of the present invention.
  • FIG. 9 is a schematic flowchart of a multi-chip heat dissipation packaging method according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of an assembly process of a concave pre-packaged carrier in a multi-chip heat dissipation package structure provided by an embodiment of the present invention
  • FIG. 11 is a schematic flowchart of a multi-chip heat dissipation packaging method provided by an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of the overall packaging process of a multi-chip heat dissipation packaging structure provided by an embodiment of the present invention.
  • FIG. 13 is a schematic flowchart of a multi-chip heat dissipation packaging method according to an embodiment of the present invention.
  • the terms “inner”, “outer”, “longitudinal”, “transverse”, “upper”, “lower”, “top”, “bottom”, etc. indicate the orientation or positional relationship based on the accompanying drawings.
  • the orientation or positional relationship shown is only for the convenience of describing the present invention and does not require that the present invention must be constructed and operated in a specific orientation, so it should not be understood as a limitation to the present invention.
  • Embodiment 1 of the present invention provides a multi-chip heat dissipation package structure.
  • FIG. 1 shows an exemplary structure diagram realized by an embodiment of the present invention.
  • the chip is arranged in a left-right position (in the cross-sectional view shown in FIG. 1, it is specifically represented as a left-right arrangement relationship), and the implementation of the present invention also includes the up and down stacking structure shown in FIG. 7 and the stacked structure shown in FIG. 1 and FIG. 7
  • the combination scheme of the structure, the feasible schemes that can be realized by the present invention will be described in detail in the subsequent specific expansion schemes and related embodiments.
  • the package structure includes an inverted formal chip 4 and at least one ordinary formal chip (labeled as 10 and 11 in FIG. 1, which are also exemplarily described as a first formal chip 10 and a second formal chip 11), specific:
  • the inverted chip 4 is arranged on the concave bottom of the concave pre-packaged carrier board 1, wherein the concave bottom of the concave pre-packaged carrier board is provided with a first set of pads (shown clearly in FIG.
  • the first set of pads are located in the concave bottom area associated with the gold wire bonding wire 5), and the first set of pads are used for electrical connection with the pins of the inverted formal chip 3;
  • the group pads transfer electrical characteristics to the end area of the concave side wall through the concave side wall of the concave pre-packaged carrier board (shown as the interconnection solder joint 7 on the end face of the concave side wall in Figure 2; in another scenario, in It is shown as the second set of pads on the concave sidewall in FIG. 3), so that when the concave pre-packaged carrier board is upside down on the bottom plate, the electrical connection between the inverted chip and the bottom plate can be realized;
  • the outer surface of the concave bottom of the concave pre-packaged carrier board is further provided with a heat dissipation component, the heat dissipation component is coupled with the bottom of the inverted chip, and is used to drain away the heat generated when the inverted chip works;
  • the ordinary form-fitting chip is arranged on the bottom plate, and heat is dissipated through the bottom plate itself and the packaging cavity itself.
  • the embodiment of the present invention provides a multi-chip heat dissipation package structure.
  • the package structure conducts the heat generated by the chip to the top of the device packaging metal cover through the heat dissipation component contacting the bottom of the chip, thereby realizing efficient heat dissipation of the chip and ensuring the normality of the chip Operation;
  • the packaging structure of the present invention when the inverted formal chip is a high-frequency formal chip, there is no additional metal conductor on the upper surface of the high-frequency formal chip, so that it will not affect the high-frequency formal chip Signal transmission performance inside and when the chip is interconnected with the package carrier.
  • the first set of pads transmits electrical characteristics to the end area of the concave side wall through the concave side wall of the concave pre-packaged carrier board, so that the concave pre-packaged carrier board is inverted on When it is on the bottom plate, at least two optional implementation methods are provided to realize the electrical connection between the inverted chip and the bottom plate.
  • the end of the concave side wall of the concave pre-packaged carrier board is provided with ball grid array bumps (that is, an example of the interconnection solder joints 7), and corresponding to the bottom plate Soldering of the ball grid array pads to complete the electrical connection between the inverted chip and the circuit on the bottom plate;
  • ball grid array bumps that is, an example of the interconnection solder joints 7
  • a second set of pads are provided on the concave side wall of the concave pre-packaged carrier board, and the third set of pads are connected to the bottom board and located around the concave pre-packaged carrier board.
  • the electrical connection between the inverted chip and the circuit on the bottom board is completed by means of gold wire bonding.
  • the number of pads in the second group of pads is determined according to the number of pins of the inverted chip.
  • the first method its integration degree is higher than that of the second method, and the manufacturing process complexity will be relatively high.
  • the first method has a larger area for the end of the concave side wall. Certain requirements, if the area of the end of the concave side wall is relatively small, higher process requirements are put forward for the formation of electrical connection channels inside the concave side wall.
  • the second method requires the introduction of gold wire bonding wire, and its overall cost will be higher, and the integration of the overall package structure is not as good as the first method.
  • the concave pre-packaged carrier board is usually processed from ceramic or semiconductor materials, and the corresponding concave bottom for setting up the inverted positive chip is made with a through-hole structure; then the heat dissipation component includes a thermal conductive glue 4 and thermally conductive metal gasket 2; as shown in Figure 2, specific:
  • the thermally conductive metal gasket 2 is fixed on the outer side of the concave bottom of the concave pre-packaged carrier board 1, and the bottom of the inverted positive chip 3 passes through the thermally conductive glue 4, passes through the through hole of the concave bottom, and is directly connected to the concave bottom.
  • the thermally conductive metal gasket 2 is attached.
  • FIG. 4 it is a schematic diagram corresponding to the electrical characteristic structure of the concave pre-packaged carrier board shown in FIG. 2 in the concave side wall.
  • a structural performance as shown in FIG. 4 is given.
  • the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors.
  • reference numerals 101, 102, and 103 respectively represent three-layer ceramic substrates or three-layer semiconductor structures, respectively.
  • Electrical rails 104 are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails 104 between the layers are coupled to each other;
  • the electrical guide rail 104 is provided with a conductive medium 105, which is used to complete the electrical connection between the first set of pads at the bottom of the concave shape and the bumps of the ball grid array at the end, that is, the structural diagram shown in FIG. 4; or, It is used to complete the electrical connection between the first set of pads located at the bottom of the recess and the second set of pads provided on the sidewall of the recess, as shown in FIG. 5, where part A in FIG. In the package carrier, the structure diagram of the multilayer ceramic substrate (or multilayer semiconductor stack) on the concave side wall on the left side, where part B in FIG. 5 is a left view of the structure corresponding to part A in FIG. 5 for Show the second group of pad structure more intuitively.
  • the package structure also includes a metal cover, as shown in Figure 1, specifically:
  • the metal cover 12 is fixed on the bottom plate 8, and the thermally conductive coupling between the thermally conductive metal gasket 2 and the metal cover 12 is completed by a TIM material 14.
  • a sealant 13 or solder is usually used to form a better sealing performance at the junction of the metal cover 12 and the bottom plate 8.
  • the heat dissipation structure after the ordinary formal chip is placed on the bottom plate may adopt the structure shown in FIG.
  • a set of heat dissipation holes 9 are provided in the area of the front-mounted chip shown in 10 and 11, and the heat-dissipating holes 9 penetrate through the bottom plate to provide a channel for heat dissipation at the bottom of the ordinary front-mounted chip.
  • the embodiment of the present invention also provides an optional implementation solution to improve the above-mentioned high-frequency interference problem.
  • Metal isolation layer 106 in order to prevent the inverted positive-mounting chip set on the concave pre-packaged carrier from affecting the electrical pathways on the bottom plate, a metal isolation cover can also be used to set the concave area of the concave pre-packaged carrier in the high-frequency area. Between the front-mounted chip and the bottom plate, and thus with the metal isolation layer 106, can completely isolate the high-frequency interference of the high-frequency front-mounted chip.
  • the present invention is a technical solution for instantiating expressions of partial characteristic structures based on consideration of specific application scenarios among the many realizable manners of Embodiment 1.
  • the package structure includes:
  • the inverted chip is arranged on the concave bottom of the concave pre-packaged carrier board, wherein the concave bottom of the concave pre-packaged carrier board is provided with a first set of pads, and the first set of pads is used to interact with the inverted front mounting
  • the pins of the chip are electrically connected; the first set of pads transmits electrical characteristics to the end area of the concave side wall through the concave side wall of the concave pre-packaged carrier board, so that the concave pre-packaged carrier board can be reversed When on the bottom plate, realize the electrical connection between the inverted chip and the bottom plate;
  • the outer surface of the concave bottom of the concave pre-packaged carrier board is further provided with a heat dissipation component, the heat dissipation component is coupled with the bottom of the inverted chip, and is used to drain away the heat generated when the inverted chip works;
  • the ordinary form-fitting chip is arranged on the bottom plate, and heat is dissipated through the bottom plate itself and the packaging cavity itself; and the concave side wall of the concave pre-packaged carrier board is fixed on the bottom plate and is surrounded by In the bottom plate area, there is at least one ordinary formal chip.
  • the ordinary formal chip and the inverted formal chip are designed to be stacked up and down, that is, there are both inverted formal chips.
  • the normal form-fitting chip is located in the concave area of the concave pre-packaged carrier board.
  • the structure proposed by the embodiment of the present invention has at least the following two considerations, and can be effectively improved by the embodiment of the present invention:
  • the heat of the front-mounted chip described here is greater than the first preset temperature, and the bottom area of the front-mounted chip is less than the first preset area is selected as the condition for the inverted front-mounted chip, that is, the heat dissipation hole that can be made by the current process cannot effectively complete the heat dissipation
  • One or more front-mounted chips are completed by adopting the structure of using the concave pre-packaged carrier board to invert the front-mounted chips proposed in the embodiment of the present invention.
  • the inverted formal mounting chip when selecting the inverted formal mounting chip and In the case of the ordinary formal mounting chip located in the recessed area of the recessed pre-packaged carrier board, it is preferable to select one or more ordinary formal mounting chips whose initial chip temperature rise rate is higher than that of the inverted formal mounting chip to be placed on the bottom plate in the recessed area , Thereby improving the working environment temperature of the inverted formal chip.
  • the reason is that the relative heat dissipation effect of the concave pre-packaged carrier board structure where the inverted formal chip is located is much higher than that of the ordinary formal chip set on the bottom plate, so in an extremely low temperature environment, the inverted formal chip is also affected by the extreme low temperature environment.
  • the working environment temperature of the inverted front-mounted chip can be improved through the faster heating capacity of the ordinary front-mounted chip located in the concave area.
  • the main controller chip is selected as the ordinary formal-mounted chip arranged on the bottom plate and located in the concave area, because the main controller is the first chip to be activated in the package structure and has a faster temperature rise characteristic.
  • Case 2 Although the embodiment of the present invention considers the problem of high frequency interference to the ordinary formal chip in the scenario where the inverted formal chip is specifically a high frequency formal chip, and provides an improved solution as shown in FIG. 6. However, it is not difficult to see from FIG. 6 that a metal isolation layer 106 needs to be fabricated on the concave pre-packaged carrier board, and even a metal isolation cover plate needs to be added to improve the interference problem.
  • the structure proposed in the embodiment of the present invention can prevent high-frequency interference effects similar to that shown in FIG. 6, and can also effectively reduce the processing cost and processing complexity of the concave pre-packaged carrier board.
  • the high-frequency formal mounting chip is under the performance of the inverted formal mounting chip in a specific example), and the two are separated by the metal isolation cover plate 6.
  • the metal isolation layer 106 As shown in FIG. 6 to achieve the expected high-frequency signal anti-interference effect, which reduces the processing difficulty and processing cost of the entire package structure.
  • the ordinary formal-mounted chip that is more sensitive to high-frequency interference.
  • the packaging structure further includes: The concave area of the concave pre-packaged carrier board is at a predetermined distance from the high-frequency front-mounted chip, and a metal isolation cover plate for isolating high-frequency signals is provided.
  • a preset distance is to comprehensively consider the thermal conductivity of both parties.
  • the metal isolation cover is set Too close to the ordinary formal chip located on the bottom plate, the normal formal chip located in the recessed area considered in the above case will reduce the effect of improving the working environment of the inverted formal chip in the extreme case, because at this time the ordinary formal chip located in the recessed area The heat of the chip will be more dissipated through the heat dissipation holes in the bottom plate, and the corresponding metal isolation cover will play a certain role in blocking the heat of the ordinary formal chip in the concave area from spreading to the area where the inverted formal chip is located.
  • the metal isolation cover is set too close to the inverted front-mounted chip, it will affect the heat dissipation effect of the inverted front-mounted chip in the rapid heating scenario, because after the metal isolation cover is close to the inverted front-mounted chip, it will be relatively close.
  • the recessed area space of the inverted formal chip will be compressed, which will reduce the effect of the recessed area space to alleviate the heating rate in the context of rapid heating of the inverted formal chip. Therefore, the preset distance is set after comprehensively considering the above two factors.
  • the parameter value of the specific preset distance will be set specifically according to the difference of the specific chip and the use environment. Therefore, in the implementation of the present invention The examples do not give examples of specific parameter values, but those skilled in the art are sufficient to obtain the preset distance of a specific application scenario through a limited number of test experiments based on the above analysis content.
  • the embodiment of the present invention provides a multi-chip heat dissipation packaging method, which is used to realize the packaging structure shown in Embodiment 1 and Embodiment 2. As it is a method-side embodiment based on a common inventive concept, it is correspondingly described in the embodiment
  • the structural improvement schemes based on specific examples in Embodiment 1 and Embodiment 2 are also applicable to the packaging method process of the embodiment of the present invention. In order to simplify the description of the method process of this embodiment, the extensions developed in Embodiment 1 and Embodiment 2 are similar.
  • the related content of the solution is not repeatedly described in the embodiment of the present invention.
  • the packaging method of the embodiment of the present invention includes:
  • step 201 the at least two formal-mounted chips involved in the package structure are analyzed, and the at least two formal-mounted chips are divided into an inverted formal-mounted chip and a normal formal-mounted chip according to the analysis result and a preset strategy; wherein, the inverted formal-mounted chip It is set on a custom recessed pre-packaged carrier board, and the ordinary formal chip is set on the bottom plate.
  • step 202 the first set of pads on the concave bottom of the concave pre-packaged carrier board, the second set of pads on the matching concave sidewalls, and the first set of pads are designed according to the pin characteristics of the selected inverted formal chip. The electrical connection between one set of pads and the second set of pads.
  • the second set of pads can also be replaced by the ball grid array bumps. Point; but for the sake of simplicity of description, in the method of the embodiment of the present invention, only the second set of pads are used as an example for description.
  • step 203 after the inverted formal chip is set on the concave pre-packaged carrier and the pins of the inverted formal chip are electrically connected to the first set of pads, the concave pre-packaged The carrier board is fixed at a designated position of the bottom plate; the second group of pads are electrically connected to the corresponding third group of pads on the bottom plate.
  • step 204 the electrical connection of the ordinary formal chip on the bottom plate is completed.
  • the embodiment of the present invention provides a multi-chip heat dissipation packaging method.
  • the packaging method conducts the heat generated by the chip to the top of the device packaging metal cover through the heat dissipation component contacting the bottom of the chip, thereby realizing efficient heat dissipation of the chip and ensuring the normality of the chip Operation;
  • the inverted formal chip is a high-frequency formal chip
  • FIG. 9 which specifically includes:
  • the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors, wherein electrical rails are arranged between each layer of ceramic substrate or each layer of semiconductor, and between the layers The electrical rails are coupled with each other.
  • the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors.
  • reference numerals 101, 102, and 103 respectively represent three-layer ceramic substrates or three-layer semiconductor structures, respectively.
  • Electrical rails 104 are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails 104 between the layers are coupled to each other;
  • the electrical guide rail 104 is provided with a conductive medium 105, which is used to complete the electrical connection between the first set of pads at the bottom of the concave shape and the bumps of the ball grid array at the end, that is, the structural diagram shown in FIG. 4; or, Used to complete the electrical connection between the first set of pads located at the bottom of the recess and the second set of pads on the sidewall of the recess, as shown in Figure 5, where part A in Figure 5 is located in the recessed pre-packaged carrier
  • the specific layering relationship is not necessarily limited to the structure shown in Figure 4 or Figure 5.
  • the number of layers is usually adapted according to the complexity of the graphic structure to be presented in the concave area. Adjusted, but similar to those shown in Figures 4 and 5, it is a preferred electrical connection structure, especially the ceramic substrate 102 and ceramic substrate 103 (or described as semiconductor 102 and semiconductor 103) in Figure 4 can be a single ceramic substrate, thus Further compress the number of layers of the ceramic substrate.
  • the fewer ceramic substrate layers that constitute the concave sidewalls the better the corresponding electrical connection characteristics, because the fewer the turning or connecting nodes in the electrical connection, the better the electrical characteristics.
  • a conductive medium is provided in the electrical rail to complete the electrical connection between the first set of pads at the bottom of the concave shape and the second set of pads provided at the end.
  • the embodiment of the present invention provides for the processing process of the related components of the concave pre-packaged carrier board in step 203, refer to the structure assembly process diagram shown in FIG. 10, and refer to the label relationship shown in FIG. 1, as shown in FIG. 11, the assembly method include:
  • step 2031 the pre-packaged carrier 1 and the thermally conductive metal pad 2 are welded together by a reflow or eutectic process; the reflow or eutectic process is characterized in that the solder joints formed can withstand subsequent assembly of ⁇ BGA, ball grid array bump Point, metal isolation cover and BGA welding temperature.
  • step 2032 the inverted front-mounted chip 3 is bonded to the thermally conductive metal gasket 2 by using the thermally conductive glue 4.
  • step 2033 the gold wire bonding wire 5 is used to realize the signal interconnection between the inverted formal chip 3 and the pre-packaged carrier board 1.
  • step 2034 the metal isolation cover 6 is adhered to the pre-packaged carrier 1.
  • step 2035 interconnect solder joints 7 are planted on the pre-packaged carrier board 1.
  • the embodiment of the present invention has been designed since the concave pre-packaged carrier board has been designed, and the implementation process of the embodiment of the present invention is explained only from the perspective of assembly.
  • Refer to the structural assembly process diagram shown in FIG. 12 and the method flowchart shown in FIG. 13 for details include:
  • step 301 the concave pre-packaged carrier 1 is flip-mounted on the bottom plate 8.
  • the concave pre-packaged carrier board is a complete assembly after performing the method steps shown in FIG. 11.
  • step 302 ordinary formal-mounted chips (for example, the first formal-mounted chip 10 and the second formal-mounted chip 11 in FIG. 1) are bonded in the cavity of the bottom plate 8.
  • TIM14 is coated on the top of the concave pre-packaged carrier.
  • the TIM14 has certain fluidity and high thermal conductivity, and can achieve close contact between the thermally conductive metal gasket and the metal cover.
  • step 304 the metal cover 12 is adhered to the bottom plate 8 through sealant or solder 13.
  • the sealant or solder 13 is characterized in that it can achieve an air-tight or quasi-air-sealed packaging inside the device, and effectively protect the chip.
  • step 305 a BGA 15 is planted at the bottom of the bottom plate 8 to realize the input and output of the device signal.
  • the BGA 15 is characterized in that the melting temperature is lower than the welding temperature of the aforementioned reflow or eutectic process, ⁇ BGA, ball grid array bumps, and metal isolation cover plate, and can meet the requirements of the subsequent SMT process.
  • the program can be stored in a computer-readable storage medium.
  • the storage medium can include: Read memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc.

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Abstract

本发明涉及半导体封装技术领域，提供了一种多芯片散热封装结构及封装方法。结构中倒置芯片被设置在凹型预封装载板的凹型底部，其中，凹型预封装载板的凹型底部设置有第一组焊盘，第一组焊盘用于与倒置正装芯片的引脚进行电气连接；第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域，以便于凹型预封装载板在倒扣在底板上时，实现倒置芯片与底板之间的电气连接；凹型预封装载板的凹型底部的外表面还设置有散热组件，散热组件与倒置芯片的底部耦合，用于将倒置芯片工作时产生的热量疏导出去；其中，普通正装芯片被设置在底板上，并通过底板自身和封装腔体自身进行散热。本发明实现芯片的高效散热，确保了芯片的正常运行。

Description

一种多芯片散热封装结构及封装方法 【技术领域】
本发明涉及半导体封装技术领域，特别是涉及一种多芯片散热封装结构及封装方法。
【背景技术】
近年来，器件集成度越来越高，将多个芯片封装在一起形成功能高度集成的器件成为一种发展趋势。而多芯片集成器件的散热问题成为封装设计的主要瓶颈，特别是正装高频芯片的散热成为亟需解决的问题。对于倒装芯片封装的散热问题，传统的解决方案是通过芯片倒装后通过上表面进行散热的。即通过在倒装芯片上面加散热盖，再在散热盖上用导热胶与散热片接触，将芯片工作时产生的热量散出。同理，正装芯片的散热，也有采用在芯片上方直接放置金属导体将热量散出的设计结构(如专利CN102347293A中所述)，但对于高频芯片来讲，尤其是砷化镓、氮化镓等芯片，其表层会设计高频信号互连链路，此种封装结构中的金属导体会与芯片上表面的信号链路导体以及金丝焊线直接接触或者距离很近，导致高频信号在传输时出现串扰，谐振以及天线效应等问题，严重影响高频芯片的信号传输性能，因此仅限于低频正装芯片的散热。
而对于正装高频芯片的散热，传统的解决方法是在封装载板中设计导热孔或者导热金属块，芯片产生的热量可以通过此种通道散出。但是此种散热方式还需要将器件底部与组装电路板直接接触才能起到更佳散热的作用。而对于BGA封装的器件，与组装电路板的接触面 积极小(芯片与电路板的接触面，仅仅表现在BGA接触点上)，加大了器件与电路板间的热阻，其散热能力很有限。为了降低器件与电路板间的热阻，还有一种散热方式是在封装设计时，将器件中倒置芯片正下方对应的BGA去除，这样可以将散热金属通过高导热胶与封装载板底部直接接触，从而减小了芯片底部与外界散热金属导体间的热阻，达到高效散热。由于散热区域不能再布BGA,其数量会减少，所以此种结构会降低BGA封装器件的I/O端口数量，影响其集成度；在器件与模块电路板组装时，需要在电路板相应的区域设计贯通空腔，同时在器件底部涂覆导热材料等，增加了产品后续设计自由度和组装复杂度。
另一方面，在多芯片封装的场景下，不同大小的正装芯片都会遇到，随着芯片加工集成度越来越高，采用现有导热孔技术来实现散热效果会越来越差，因为芯片底面积本身就小的情况下，更不可能在有限的面积下设置足以满足导热需求的导热孔。
因此，对于BGA封装类型的多芯片集成器件，在不影响正装高频芯片的信号传输性能的前提下，实现高效散热成为一个亟需解决的技术问题。
【发明内容】
本发明实施例要解决的技术问题是现有的散热封装方式，在应用到多芯片场景中，无法有效的应对多芯片场景需求；尤其是在涉及高频正转芯片和/或芯片底部面积较小的正装芯片场合。
本发明实施例采用如下技术方案：
第一方面，本发明提供了一种多芯片散热封装结构，包括倒置正装芯片和至少一个普通正装芯片，具体的：
所述倒置芯片被设置在凹型预封装载板的凹型底部，其中，所述 凹型预封装载板的凹型底部设置有第一组焊盘，所述第一组焊盘用于与所述倒置正装芯片的引脚进行电气连接；所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域，以便于所述凹型预封装载板在倒扣在底板上时，实现倒置芯片与底板之间的电气连接；
所述凹型预封装载板的凹型底部的外表面还设置有散热组件，所述散热组件与所述倒置芯片的底部耦合，用于将所述倒置芯片工作时产生的热量疏导出去；
其中，所述普通正装芯片被设置在所述底板上，并通过所述底板自身和封装腔体自身进行散热。
优选的，所述凹型预封装载板在倒扣在底板上时，实现倒置芯片与底板之间的电气连接，具体包括：所述凹型预封装载板的凹型侧壁的端部设置有球栅阵列凸点，并通过与底板上对应的球栅阵列焊盘进行焊接，完成所述倒置芯片与底板上电路的电气连接；或者，所述凹型预封装载板的凹型侧壁上设置有第二组焊盘，并通过与底板上位于所述凹型预封装载板四周的第三组焊盘，利用金丝焊线的方式完成倒置芯片与底板上电路的电气连接。
优选的，所述凹型预封装载板由陶瓷或者半导体材料加工而成，相应的用于设置倒置正装芯片的凹型底部制作有通孔结构；则所述散热组件包括导热胶和导热金属垫片；具体的：
所述导热金属垫片固定在所述凹型预封装载板的凹型底部外侧，所述倒置正装芯片的底部经由所述导热胶，穿过所述凹型底部的通孔，与所述导热金属垫片贴合。
优选的，所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域，具体包括：
所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨，并且，层与层之间的电气导轨相互耦合；
所述电气导轨内设置有导电介质，用于完成位于凹型底部第一组焊盘与端部设置的球栅阵列凸点之间的电气连接；或者，用于完成位于凹型底部第一组焊盘与凹型侧壁上设置的第二组焊盘之间的电气连接。
优选的，所述封装结构还包括金属封盖，具体的：
所述金属封盖固定在所述底板上，并且，所述导热金属垫片与所述金属封盖之间通过TIM材料完成导热耦合。
优选的，所述普通正装芯片被设置在所述底板上，具体包括：
所述底板上，位于设置所述普通正装芯片的区域设置有一组散热孔，所述散热孔贯穿所述底板，用于为所述普通正装芯片的底部散热提供渠道。
优选的，所述封装结构还包括：
所述凹型预封装载板的凹型侧壁固定在底板上后所围成的底板区域中，设置有至少一个普通正装芯片。
优选的，在所述倒置正装芯片具体为高频正装芯片时，所述封装结构还包括：
在所述凹型预封装载板的凹型区域，且与高频正装芯片相差预设距离处，设置有隔离高频信号用的金属隔离盖板。
优选的，在凹型预封装载板所在底板外围区域上，还设置有普通正装芯片时，所述封装结构还包括：
所述凹型预封装载板的凹型侧壁内部或者凹型侧壁外部上设置有金属隔离层。
优选的，在所述普通正装芯片数量至少有两个时，由所述凹型预封装载板的凹型侧壁固定在底板上后所围成的底板区域中，设置有至少一个普通正装芯片，具体为：
至少两个普通正装芯片中，相对高频干扰更为敏感的普通正装芯片。
优选的，正常工作下，正装芯片功耗密度(芯片的功率除以芯片底部的散热面积)大于0.5W/mm 2时，则确认作为所述倒置正装芯片。
第二方面，本发明还提供了一种多芯片散热封装方法，包括：
分析封装结构中所涉及的至少两个正装芯片，根据分析结果和预设策略将所述至少两个正装芯片分为倒置正装芯片和普通正装芯片；其中，所述倒置正装芯片被设置在定制的凹型预封装载板上，所述普通正装芯片被设置在底板上；
根据选定的倒置正装芯片的管脚特性，设计所述凹型预封装载板的凹型底部的第一组焊盘，配套的凹型侧壁上的第二组焊盘，以及第一组焊盘与第二组焊盘之间的电气连接；或者，设计所述凹型预封装载板的凹型底部的第一组焊盘，配套的凹型侧壁端部的球栅阵列凸点，以及第一组焊盘与球栅阵列凸点之间的电气连接；
在将所述倒置正装芯片设置在所述凹型预封装载板上，并完成倒置正装芯片的管脚与所述第一组焊盘的电气连接后，将所述凹型预封装载板固定在所述底板的指定位置；
将所述第二组焊盘与底板上的相应的第三组焊盘进行电气连接；或者，将所述凹型侧壁端部的球栅阵列凸点与底板上的球栅阵列焊盘进行电气连接；
完成普通正装芯片在所述底板上的电气连接。
优选的，所述设计所述凹型预封装载板的凹型底部的第一组焊盘， 配套的凹型侧壁上的第二组焊盘，以及第一组焊盘与第二组焊盘之间的电气连接，具体包括：
所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨，并且，层与层之间的电气导轨相互耦合；
所述电气导轨内设置有导电介质，用于完成位于凹型底部第一组焊盘与凹型侧壁上的第二组焊盘的电器连接。
优选的，所述设计所述凹型预封装载板的凹型底部的第一组焊盘，配套的凹型侧壁端部的球栅阵列凸点，以及第一组焊盘与球栅阵列凸点之间的电气连接，具体包括：
所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨，并且，层与层之间的电气导轨相互耦合；
所述电气导轨内设置有导电介质，用于完成位于凹型底部第一组焊盘与凹型侧壁端部的球栅阵列凸点的电器连接。
与现有技术相比，本发明实施例的有益效果在于：
本发明提供了一种多芯片散热封装结构及封装方法，该封装结构通过与芯片底部接触的散热组件将芯片产生的热量传导至器件封装金属封盖上面，实现芯片的高效散热，确保了芯片的正常运行；相比较现有技术，本发明在封装结构中，在所述倒置正装芯片具体为高频正装芯片时，高频正装芯片上表面不存在额外的金属导体，从而不会影响高频正装芯片内部以及芯片与封装载板互连时的信号传输性能。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面 将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为本发明的实施例提供的一种多芯片散热封装结构的剖面示意图；
图2为本发明的实施例提供的一种多芯片散热封装结构中的预封装载板的剖面示意图；
图3为本发明的实施例提供的一种多芯片散热封装结构的剖面示意图；
图4为本发明的实施例提供的一种多芯片散热封装结构中的预封装载板的剖面示意图；
图5为本发明的实施例提供的一种多芯片散热封装结构中的预封装载板的剖面示意图；
图6为本发明的实施例提供的一种多芯片散热封装结构的剖面示意图；
图7为本发明的实施例提供的另一种多芯片散热封装结构的剖面示意图；
图8为本发明的实施例提供的一种多芯片散热封装方法的流程示意图；
图9为本发明的实施例提供的一种多芯片散热封装方法的流程示意图；
图10为本发明的实施例提供的一种多芯片散热封装结构中的凹型预封装载板的组装流程示意图；
图11为本发明的实施例提供的一种多芯片散热封装方法的流程 示意图；
图12为本发明的实施例提供的一种多芯片散热封装结构的整体封装过程示意图；
图13为本发明的实施例提供的一种多芯片散热封装方法的流程示意图；
附图中各部件的标记为：1、预封装载板，2、导热金属垫片，3、倒置正装芯片，4、导热胶，5、金丝焊线，6、金属隔离盖板，7、互连焊点，8、底板，9、散热孔，10、第一正装芯片，11、第二正装芯片，12、金属封盖，13、密封胶/焊料，14、导热材料(TIM)，15、BGA，101、第一层陶瓷基板，102、第二层陶瓷基板，103、第三层陶瓷基板，104、电气导轨，105、导电介质，106、金属隔离层。
【具体实施方式】
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
在本发明的描述中，术语“内”、“外”、“纵向”、“横向”、“上”、“下”、“顶”、“底”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明而不是要求本发明必须以特定的方位构造和操作，因此不应当理解为对本发明的限制。
此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
需要说明的是，在本发明实施例中，在具体配合附图示例性说明结构的时候，采用引述附图中的相关附图标号；而在一般普适性特征描述上，并没有去特别的引述附图的标号。
实施例1:
本发明实施例1提供了本发明提供了一种多芯片散热封装结构，如图1所示为本发明实施例实现的一种示例性结构图，图1给予了一种倒置正装芯片与普通正装芯片左右错位设置(在图1所示的剖视图中，具体表现为左右设置关系)，而在本发明的实现方式中还包括如图7所示的上下堆叠结构，以及图1和图7所示的结构的组合方案，本发明所能实现的各可行方案将在后续具体扩展方案和关联实施例中具体阐述。在本发明实施例中，将阐述几种可行方案的共性关键结构特征。在本发明实施例中，封装结构包括倒置正装芯片4和至少一个普通正装芯片(图1中被标注为标号10和标号11，也被示例性的描述为第一正装芯片10和第二正装芯片11)，具体的：
如图2所示，所述倒置芯片4被设置在凹型预封装载板1的凹型底部，其中，所述凹型预封装载板的凹型底部设置有第一组焊盘(图2中为明示，所述第一组焊盘位于图中金丝焊线5所关联的凹型底部区域)，所述第一组焊盘用于与所述倒置正装芯片3的引脚进行电气连接；所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域(在图2中表现为凹型侧壁端面上的互连焊点7；另一种场景，在图3中表现为凹型侧壁上的第二组焊盘)，以便于所述凹型预封装载板在倒扣在底板上时，实现倒置芯片与底板之间的电气连接；
所述凹型预封装载板的凹型底部的外表面还设置有散热组件，所述散热组件与所述倒置芯片的底部耦合，用于将所述倒置芯片工作时产生的热量疏导出去；
其中，所述普通正装芯片被设置在所述底板上，并通过所述底板自身和封装腔体自身进行散热。
本发明实施例提供了一种多芯片散热封装结构，该封装结构通过 与芯片底部接触的散热组件将芯片产生的热量传导至器件封装金属封盖上面，实现芯片的高效散热，确保了芯片的正常运行；相比较现有技术，本发明在封装结构中，在所述倒置正装芯片具体为高频正装芯片时，高频正装芯片上表面不存在额外的金属导体，从而不会影响高频正装芯片内部以及芯片与封装载板互连时的信号传输性能。
在本发明实施例中，所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域，以便于所述凹型预封装载板在倒扣在底板上时，实现倒置芯片与底板之间的电气连接，至少提供了两种可选的实现方式。
方式一，如图1所示，所述凹型预封装载板的凹型侧壁的端部设置有球栅阵列凸点(即互连焊点7的一种实例表现)，并通过与底板上对应的球栅阵列焊盘进行焊接，完成所述倒置芯片与底板上电路的电气连接；
方式二，如图3所示，所述凹型预封装载板的凹型侧壁上设置有第二组焊盘，并通过与底板上位于所述凹型预封装载板四周的第三组焊盘，利用金丝焊线的方式完成倒置芯片与底板上电路的电气连接。其中，第二组焊盘中焊盘数量根据倒置芯片的管脚数量而定。
上述两种方式各有优势，对于方式一而言，其相对于方式二的集成度更高，并且制作工艺复杂度相对要求会高些，尤其是，方式一对于凹型侧壁端部的面积有一定的要求，若凹型侧壁端部的面积相对较小，则对于所述凹型侧壁内部形成电气连接通道提出了较高的工艺要求。相对于方式一而言，方式二因为需要引入金丝焊线，其综合成本会更高，并且对于整体的封装结构的集成度，表现的并非如方式一那般优秀。
在本发明实施例中，所述凹型预封装载板通常是由陶瓷或者半导 体材料加工而成，相应的用于设置倒置正装芯片的凹型底部制作有通孔结构；则所述散热组件包括导热胶4和导热金属垫片2；如图2所示，具体的：
所述导热金属垫片2固定在所述凹型预封装载板1的凹型底部外侧，所述倒置正装芯片3的底部经由所述导热胶4，穿过所述凹型底部的通孔，直接与所述导热金属垫片2贴合。
如图4所示，为对应图2所示凹型预封装载板在呈现凹型侧壁中的电气特性结构的示意图。在本发明实施例中，对于所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域，给予了一种如图4所示实现结构表现，包括：
所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，在图4中，以标号101、102和103示例性的分别表示了三层陶瓷基板或者三层半导体结构，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨104，并且，层与层之间的电气导轨104相互耦合；
所述电气导轨104内设置有导电介质105，用于完成位于凹型底部第一组焊盘与端部设置的球栅阵列凸点之间的电气连接，即图4所示的结构图；或者，用于完成位于凹型底部第一组焊盘与凹型侧壁上设置的第二组焊盘之间的电气连接，如图5所示，其中图5中的A部分是图4所示的凹型预封装载板中，位于左侧的凹型侧壁的多层陶瓷基板(或多层半导体叠装)结构示意图，其中，图5中的B部分是相应图5中A部分结构的左视图，用以更直观的展现第二组焊盘结构。
为了起到对封装结构的保护作用，通常所述封装结构还包括金属封盖，如图1所示，具体的：
所述金属封盖12固定在所述底板8上，并且，所述导热金属垫片2与所述金属封盖12之间通过TIM材料14完成导热耦合。若要达 到更好的密封效果，通常也会在金属封盖12与底板8的衔接处通过密封胶13或者采用焊料的方式形成更好的密封性。
在本发明实施例中，所述普通正装芯片被设置在所述底板上之后的散热结构可以采用如图1所示结构，所述底板8上，位于设置所述普通正装芯片(图1中标号10和11所示的正装芯片)的区域设置有一组散热孔9，所述散热孔9贯穿所述底板，用于为所述普通正装芯片的底部散热提供渠道。
在本发明实施例中，例如图1所示的封装结构下，若所述倒置正装芯片是高频正装芯片，则进一步考虑到高频正装芯片对设置在底板上的普通正装芯片的干扰，结合本发明实施例还给予了一种可选的实现方案，用于改善上述高频干扰问题，如图6所示，所述凹型预封装载板的凹型侧壁内部或者凹型侧壁外部上设置有金属隔离层106。除此以外，为了防止设置在凹型预封装载板上的倒置正装芯片对底板上的电气通路的影响，还可以使用金属隔离盖板设置在凹型预封装载板的凹型区域中，且位于高频正装芯片和底板之间，从而和所述金属隔离层106起到完全隔离高频正装芯片高频干扰的效果。
实施例2：
本发明是实施例1的诸多可实现方式中，基于特定应用场景考虑做的部分特征结构实例化表现的技术方案。如图7所示，封装结构包括：
所述倒置芯片被设置在凹型预封装载板的凹型底部，其中，所述凹型预封装载板的凹型底部设置有第一组焊盘，所述第一组焊盘用于与所述倒置正装芯片的引脚进行电气连接；所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域，以便于所述凹型预封装载板在倒扣在底板上时，实现倒置芯片与底板之间 的电气连接；
所述凹型预封装载板的凹型底部的外表面还设置有散热组件，所述散热组件与所述倒置芯片的底部耦合，用于将所述倒置芯片工作时产生的热量疏导出去；
其中，所述普通正装芯片被设置在所述底板上，并通过所述底板自身和封装腔体自身进行散热；并且，所述凹型预封装载板的凹型侧壁固定在底板上后所围成的底板区域中，设置有至少一个普通正装芯片。
与图1所示的普通正装芯片和倒置正装芯片错位布局结构不同，本发明实施例所对应的图7结构中，普通正装芯片和倒置正装芯片被设计成上下堆叠结构，即同时存在倒置正装芯片和普通正装芯片处于凹型预封装载板的凹型区域范围中。
本发明实施例所提出的结构，至少存在以下两种情形的考虑，并且，能够通过本发明实施例得到有效的改善：
情形一、在多芯片封装的场景下，不同大小的正装芯片都会遇到，随着芯片加工集成度越来越高，同一功能作用的芯片，其相对大小会随着集成度的提高越来越小，采用现有导热孔技术来实现散热效果会越来越差，因为芯片底面积本身就小的情况下，更不可能在有限的面积下设置足以满足导热需求的导热孔。因此，在本发明实施例中，挑选正常工作下，正装芯片功耗密度(芯片的功率除以芯片底部的散热面积)大于0.5W/mm 2时，则确认作为所述倒置正装芯片。这里所描述的正装芯片发热大于第一预设温度，且正装芯片底部面积小于第一预设面积的是挑选作为倒置正装芯片的条件，即利用当前工艺所能制作的散热孔无法有效完成散热的一个或者多个正装芯片，则采用本发明实施例所提出的利用凹型预封装载板倒置正装芯片的结构完成。
需要强调的是，上述情形一的技术考虑同样适用于实施例1中的封装结构设计。而在本发明实施例中，除了上述技术考虑之外，还提出了一种特殊应用场景的考量。在一些极端恶劣场景下，例如极端低温场景中，虽然同样需要考虑散热问题，但是，同样要考虑到起始正装芯片工作的环境温度问题，因此，在本发明实施例，在挑选倒置正装芯片和位于凹型预封装载板凹型区域内的普通正装芯片时，优选的是，选择初始芯片温度升温速度高于所述倒置正装芯片的一个或者多个普通正装芯片设置在所述凹型区域内的底板上，从而改善所述倒置正装芯片的工作环境温度。其原因是，倒置正装芯片所在的凹型预封装载板结构，其相对散热效果远高于设置在底板上的普通正装芯片，那么在极端低温环境下，所述倒置正装芯片受极端低温环境影响也更大，通过上述优选方案的设计，能够通过位于凹型区域的普通正装芯片的更快速的升温能力，改善所述倒置正装芯片的工作环境温度。例如：选择主控制器芯片作为设置在底板上，且位于所述凹型区域内的普通正装芯片，因为主控制作为封装结构中最先启动的芯片，具有较快的升温特性。
情形二、虽然本发明实施例考虑到倒置正装芯片具体为高频正装芯片场景下的对普通正装芯片的高频干扰问题，并提供了如图6所示的改进方案。但是，从图6中不难看出需要对凹型预封装载板制作金属隔离层106，甚至于还需要增设金属隔离盖板来完善干扰问题。本发明实施例所提出的结构，能够在起到和图6类似防止高频干扰效果的同时，还能够有效的减少凹型预封装载板的加工成本和加工复杂度。
如图7所示，因为将易被高频干扰的一个或者多个普通正装芯片，设置在凹型预封装载板的凹型区域，具体为高频正装芯片(在本发明各实施例中也被描述为倒置正装芯片，所述高频正装芯片为所述倒置 正装芯片在具体实例下的表现)下方，并且，两者之间由所述金属隔离盖板6相隔离，在本发明实施例中，无需如图6所示的设置金属隔离层106，便可以达到预期的高频信号抗干扰效果，降低了封装结构整件的加工难度和加工成本。
基于上述第二情形的考虑，在所述普通正装芯片数量至少有两个时，由所述凹型预封装载板的凹型侧壁固定在底板上后所围成的底板区域中，设置有至少一个普通正装芯片，具体为：
至少两个普通正装芯片中，相对高频干扰更为敏感的普通正装芯片。
在本发明实施例中，在综合考虑上述情形一和情形二的因素后，还存在一种技术改良方案，在所述倒置正装芯片具体为高频正装芯片时，所述封装结构还包括：在所述凹型预封装载板的凹型区域，且与高频正装芯片相差预设距离处，设置有隔离高频信号用的金属隔离盖板。相比较上述的一般意义上设置金属隔离盖板，这里强调了需要与高频正装芯片相差预设距离，此处的预设距离是要综合考虑双方导热特性，若所述金属隔离盖板设置的过于靠近位于底板上的普通正装芯片，则上述情形一中考虑的利用位于凹型区域的普通正装芯片改善极端情况下倒置正装芯片工作环境的效果就会减弱，因为，此时位于凹型区域的普通正装芯片的发热会更多的通过底板中的散热孔消散出去，相应的金属隔离盖板会起到一定的阻隔凹型区域的普通正装芯片发热量向倒置正装芯片所在区域扩散的效果。然而，若所述金属隔离盖板设置的位置离倒置正装芯片太近，则会影响倒置正装芯片在快速升温情景下的散热效果，因为，金属隔离盖板距离倒置正装芯片近了之后，相对的倒置正装芯片所拥有的凹型区域空间就会被压缩，这样会降低倒置正装芯片在快速升温情境下，借由所述凹型区域空间来缓 解升温速度的效果。因此，所述的预设距离则是在综合考虑上述两个因素之后设定的，具体预设距离的参数值根据具体芯片的不同，使用环境不同会具体的设定，因此，在本发明实施例中并不给予具体参数值的实例，但是，本领域技术人员足以根据上述的分析内容，通过有限次的测试实验获取到具体应用场景的该预设距离。
实施例3：
本发明实施例提供了一种多芯片散热封装方法，用于实现如实施例1和实施例2所示的封装结构，由于是基于一个共同发明构思的方法侧实施例，因此，相应在实施例1和实施例2中基于特定实例所做的结构改进方案，同样适用于本发明实施例封装方法过程，为了简化本实施例方法过程的描述，相似在实施例1和实施例2中展开的扩展方案相关内容，不过多的在本发明实施例中重复描述。如图8所示，本发明实施例的封装方法包括：
在步骤201中，分析封装结构中所涉及的至少两个正装芯片，根据分析结果和预设策略将所述至少两个正装芯片分为倒置正装芯片和普通正装芯片；其中，所述倒置正装芯片被设置在定制的凹型预封装载板上，所述普通正装芯片被设置在底板上。
在步骤202中，根据选定的倒置正装芯片的管脚特性，设计所述凹型预封装载板的凹型底部的第一组焊盘，配套的凹型侧壁上的第二组焊盘，以及第一组焊盘与第二组焊盘之间的电气连接。
在本发明实施例中，仅表述了第二组焊盘的实现方式，而作为实施例1和实施例2中等同实现方案，所述第二组焊盘还可以替换为所述球栅阵列凸点；但是为了描述的简洁性考虑，本发明实施例的所述方法中，仅仅使用第二组焊盘作为示例性进行表述。
在步骤203中，在将所述倒置正装芯片设置在所述凹型预封装载 板上，并完成倒置正装芯片的管脚与所述第一组焊盘的电气连接后，将所述凹型预封装载板固定在所述底板的指定位置；将所述第二组焊盘与底板上的相应的第三组焊盘进行电气连接。
在步骤204中，完成普通正装芯片在所述底板上的电气连接。
本发明实施例提供了一种多芯片散热封装方法，该封装方法通过与芯片底部接触的散热组件将芯片产生的热量传导至器件封装金属封盖上面，实现芯片的高效散热，确保了芯片的正常运行；相比较现有技术，本发明在封装结构中，在所述倒置正装芯片具体为高频正装芯片时，高频正装芯片上表面不存在额外的金属导体，从而不会影响高频正装芯片内部以及芯片与封装载板互连时的信号传输性能。
在本发明实施例中，对应于图8中步骤202中涉及的所述设计所述凹型预封装载板的凹型底部的第一组焊盘，以及配套的凹型侧壁上的第二组焊盘，在本发明实施例中还给予了一种可行的实现方式，如图9所示，具体包括：
在步骤2021中，所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨，并且，层与层之间的电气导轨相互耦合。
所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，在图4中，以标号101、102和103示例性的分别表示了三层陶瓷基板或者三层半导体结构，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨104，并且，层与层之间的电气导轨104相互耦合；
所述电气导轨104内设置有导电介质105，用于完成位于凹型底部第一组焊盘与端部设置的球栅阵列凸点之间的电气连接，即图4所示的结构图；或者，用于完成位于凹型底部第一组焊盘与凹型侧壁上设置的第二组焊盘之间的电气连接，如图5所示，其中图5中的A部 分是凹型预封装载板中位于一侧凹型侧壁的多层陶瓷基板(或多层半导体叠装)结构示意图，其中，图5中的B部分是相应A部分结构的左视图，用以更直观的展现第二组焊盘结构。需要补充的是，具体的分层关系并不一定限定于图4或者图5所示的结构，在实际情况中分层的层数通常会根据凹型区域内所要呈现的图形结构复杂性进行适应性调整，但是类似图4和图5所示的为优选的电气连接结构，尤其是图4中的陶瓷基板102和陶瓷基板103(或者描述为半导体102和半导体103)可以是单一的陶瓷基板，从而进一步压缩陶瓷基板的层数。在具体实现过程中，构成凹型侧壁的陶瓷基板层数越少，相应的电气连接特性越好，因为，电气连接中转折或者衔接节点越少，电气特性会越好。
在步骤2022中，所述电气导轨内设置有导电介质，用于完成位于凹型底部第一组焊盘与端部设置的第二组焊盘之间的电气连接。
本发明的实施例提供的针对步骤203中凹型预封装载板相关组件的加工过程，参考图10所示结构组装过程图，并借鉴图1所示的标号关系，如图11所示，组装方法包括：
在步骤2031中，预封装载板1与导热金属垫片2通过回流或共晶工艺焊接在一起；所述回流或共晶工艺其特征在于形成的焊点能够承受后续组装μBGA、球栅阵列凸点、金属隔离盖板和BGA的焊接温度。
在步骤2032中，采用导热胶4将倒置正装芯片3粘接在导热金属垫片2上。
在步骤2033中，采用金丝焊线5实现倒置正装芯片3与预封装载板1的信号互连。
在步骤2034中，将金属隔离盖板6粘接到预封装载板1上。
在步骤2035中，在预封装载板1上植互连焊点7。
实施例4：
本发明实施例从凹型预封装载板已经设计完成，仅从组装的角度阐述本发明实施例的实现过程，参考图12所示的结构组装过程图，以及图13所示的方法流程图，具体包括：
在步骤301中，将凹型预封装载板1倒装在底板8上。
所述凹型预封装载板是执行完如图11所示的方法步骤之后完整组装体。
在步骤302中，将普通正装芯片(例如图1中的第一正装芯片10和第二正装芯片11)粘接在底板8的腔槽中。
在步骤303中，在凹型预封装载板顶部涂敷TIM14。
所述TIM14，具有一定的流动性和高导热率，能够实现导热金属垫片与金属封盖的紧密接触。
在步骤304中，将金属封盖12通过密封胶或焊料13粘接在底板8上。
所述的密封胶或焊料13，其特征在于能够实现对器件内部的气密或准气密封装，对芯片尽行有效保护。
在步骤305中，在底板8底部植BGA15，实现器件信号的输入输出。
所述的BGA15，其特征在于熔融温度低于上述回流或共晶工艺、μBGA、球栅阵列凸点和金属隔离盖板焊接温度，且能够满足后续SMT工艺要求。
值得说明的是，上述装置和系统内的模块、单元之间的信息交互、执行过程等内容，由于与本发明的处理方法实施例基于同一构思，具体内容可参见本发明方法实施例中的叙述，此处不再赘述。
本领域普通技术人员可以理解实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储介质中，存储介质可以包括：只读存储器(ROM，Read Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁盘或光盘等。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种多芯片散热封装结构，其特征在于，包括倒置正装芯片和至少一个普通正装芯片，具体的：
    所述倒置芯片被设置在凹型预封装载板的凹型底部，其中，所述凹型预封装载板的凹型底部设置有第一组焊盘，所述第一组焊盘用于与所述倒置正装芯片的引脚进行电气连接；所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域，以便于所述凹型预封装载板在倒扣在底板上时，实现倒置芯片与底板之间的电气连接；
    所述凹型预封装载板的凹型底部的外表面还设置有散热组件，所述散热组件与所述倒置芯片的底部耦合，用于将所述倒置芯片工作时产生的热量疏导出去；
    其中，所述普通正装芯片被设置在所述底板上，并通过所述底板自身和封装腔体自身进行散热。
  2. 根据权利要求1所述的多芯片散热封装结构，其特征在于，所述凹型预封装载板在倒扣在底板上时，实现倒置芯片与底板之间的电气连接，具体包括：
    所述凹型预封装载板的凹型侧壁的端部设置有球栅阵列凸点，并通过与底板上对应的球栅阵列焊盘进行焊接，完成所述倒置芯片与底板上电路的电气连接；或者，所述凹型预封装载板的凹型侧壁上设置有第二组焊盘，并通过与底板上位于所述凹型预封装载板四周的第三组焊盘，利用金丝焊线的方式完成倒置芯片与底板上电路的电气连接。
  3. 根据权利要求1所述的多芯片散热封装结构，其特征在于， 所述凹型预封装载板由陶瓷或者半导体材料加工而成，相应的用于设置倒置正装芯片的凹型底部制作有通孔结构；则所述散热组件包括导热胶和导热金属垫片；具体的：
    所述导热金属垫片固定在所述凹型预封装载板的凹型底部外侧，所述倒置正装芯片的底部经由所述导热胶，穿过所述凹型底部的通孔，与所述导热金属垫片贴合。
  4. 根据权利要求3所述的多芯片散热封装结构，其特征在于，所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域，具体包括：
    所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨，并且，层与层之间的电气导轨相互耦合；
    所述电气导轨内设置有导电介质，用于完成位于凹型底部第一组焊盘与端部设置的球栅阵列凸点之间的电气连接；或者，用于完成位于凹型底部第一组焊盘与凹型侧壁上设置的第二组焊盘之间的电气连接。
  5. 根据权利要求3所述的多芯片散热封装结构，其特征在于，所述封装结构还包括金属封盖，具体的：
    所述金属封盖固定在所述底板上，并且，所述导热金属垫片与所述金属封盖之间通过TIM材料完成导热耦合。
  6. 根据权利要求1所述的多芯片散热封装结构，其特征在于，所述普通正装芯片被设置在所述底板上，具体包括：
    所述底板上，位于设置所述普通正装芯片的区域设置有一组散热孔，所述散热孔贯穿所述底板，用于为所述普通正装芯片的底部散热提供渠道。
  7. 根据权利要求1-6任一所述的多芯片散热封装结构，其特征在于，所述封装结构还包括：
    所述凹型预封装载板的凹型侧壁固定在底板上后所围成的底板区域中，设置有至少一个普通正装芯片。
  8. 根据权利要求7所述的多芯片散热封装结构，其特征在于，在所述倒置正装芯片具体为高频正装芯片时，所述封装结构还包括：
    在所述凹型预封装载板的凹型区域，且与高频正装芯片相差预设距离处，设置有隔离高频信号用的金属隔离盖板。
  9. 根据权利要求8所述的多芯片散热封装结构，其特征在于，在凹型预封装载板所在底板外围区域上，还设置有普通正装芯片时，所述封装结构还包括：
    所述凹型预封装载板的凹型侧壁内部或者凹型侧壁外部上设置有金属隔离层。
  10. 根据权利要求8所述的多芯片散热封装结构，其特征在于，在所述普通正装芯片数量至少有两个时，由所述凹型预封装载板的凹型侧壁固定在底板上后所围成的底板区域中，设置有至少一个普通正装芯片，具体为：
    至少两个普通正装芯片中，相对高频干扰更为敏感的普通正装芯 片。
  11. 根据权利要求1-6任一所述的多芯片散热封装结构，其特征在于，正常工作下，正装芯片功耗密度大于等于0.5W/mm 2时，则确认作为所述倒置正装芯片。
  12. 一种多芯片散热封装方法，其特征在于，包括：
    分析封装结构中所涉及的至少两个正装芯片，根据分析结果和预设策略将所述至少两个正装芯片分为倒置正装芯片和普通正装芯片；其中，所述倒置正装芯片被设置在定制的凹型预封装载板上，所述普通正装芯片被设置在底板上；
    根据选定的倒置正装芯片的管脚特性，设计所述凹型预封装载板的凹型底部的第一组焊盘，配套的凹型侧壁上的第二组焊盘，以及第一组焊盘与第二组焊盘之间的电气连接；或者，设计所述凹型预封装载板的凹型底部的第一组焊盘，配套的凹型侧壁端部的球栅阵列凸点，以及第一组焊盘与球栅阵列凸点之间的电气连接；
    在将所述倒置正装芯片设置在所述凹型预封装载板上，并完成倒置正装芯片的管脚与所述第一组焊盘的电气连接后，将所述凹型预封装载板固定在所述底板的指定位置；
    将所述第二组焊盘与底板上的相应的第三组焊盘进行电气连接；或者，将所述凹型侧壁端部的球栅阵列凸点与底板上的球栅阵列焊盘进行电气连接；
    完成普通正装芯片在所述底板上的电气连接。
  13. 根据权利要求12所述的多芯片散热封装方法，其特征在于， 所述设计所述凹型预封装载板的凹型底部的第一组焊盘，配套的凹型侧壁上的第二组焊盘，以及第一组焊盘与第二组焊盘之间的电气连接，具体包括：
    所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨，并且，层与层之间的电气导轨相互耦合；
    所述电气导轨内设置有导电介质，用于完成位于凹型底部第一组焊盘与凹型侧壁上的第二组焊盘的电器连接。
  14. 根据权利要求12所述的多芯片散热封装方法，其特征在于，所述设计所述凹型预封装载板的凹型底部的第一组焊盘，配套的凹型侧壁端部的球栅阵列凸点，以及第一组焊盘与球栅阵列凸点之间的电气连接，具体包括：
    所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成，其中，各层陶瓷基板或者各层半导体之间设置有电气导轨，并且，层与层之间的电气导轨相互耦合；
    所述电气导轨内设置有导电介质，用于完成位于凹型底部第一组焊盘与凹型侧壁端部的球栅阵列凸点的电器连接。
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