WO2021208322A1 - 一种多芯片散热封装结构及封装方法 - Google Patents
一种多芯片散热封装结构及封装方法 Download PDFInfo
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- WO2021208322A1 WO2021208322A1 PCT/CN2020/111972 CN2020111972W WO2021208322A1 WO 2021208322 A1 WO2021208322 A1 WO 2021208322A1 CN 2020111972 W CN2020111972 W CN 2020111972W WO 2021208322 A1 WO2021208322 A1 WO 2021208322A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
Definitions
- the invention relates to the technical field of semiconductor packaging, in particular to a multi-chip heat dissipation packaging structure and packaging method.
- the integration of devices has become higher and higher, and it has become a development trend to package multiple chips together to form highly integrated devices.
- the heat dissipation problem of multi-chip integrated devices has become a major bottleneck in package design, especially the heat dissipation of high-frequency chips that are installed as a problem that needs to be solved urgently.
- the traditional solution is to perform heat dissipation through the upper surface of the chip after flip-chip packaging. That is, by adding a heat dissipation cover on the flip chip, and then contacting the heat sink with thermally conductive glue on the heat dissipation cover, the heat generated when the chip is working is dissipated.
- the heat dissipation of the formal chip also adopts a design structure in which a metal conductor is placed directly above the chip to dissipate the heat (as described in the patent CN102347293A), but for high-frequency chips, especially gallium arsenide and gallium nitride
- high-frequency signal interconnection links will be designed on the surface.
- the metal conductors in this package structure will directly contact or be very close to the signal link conductors on the top surface of the chip and the gold wire bonding wires, resulting in high-frequency signals. Problems such as crosstalk, resonance and antenna effect during transmission seriously affect the signal transmission performance of high-frequency chips, so the heat dissipation is limited to low-frequency formal chips.
- the traditional solution is to design a thermally conductive hole or a thermally conductive metal block in the package carrier, and the heat generated by the chip can be dissipated through this channel.
- this heat dissipation method also requires direct contact between the bottom of the device and the assembled circuit board to achieve better heat dissipation.
- the contact surface with the assembled circuit board is very small (the contact surface between the chip and the circuit board is only shown on the BGA contact point), which increases the thermal resistance between the device and the circuit board, and its heat dissipation capacity is very good. limited.
- Another way to dissipate heat is to remove the corresponding BGA directly below the inverted chip in the device during package design, so that the heat dissipation metal can directly contact the bottom of the package carrier through the high thermal conductivity adhesive , Thereby reducing the thermal resistance between the bottom of the chip and the external heat-dissipating metal conductor, and achieve high-efficiency heat dissipation.
- the technical problem to be solved by the embodiment of the present invention is that the existing heat dissipation packaging method cannot effectively meet the requirements of the multi-chip scenario when applied to the multi-chip scenario; especially when the high-frequency forward rotation chip and/or the lower area of the chip are relatively large. Small formal chip occasions.
- the present invention provides a multi-chip heat-dissipating package structure, including an inverted formal-mounted chip and at least one ordinary formal-mounted chip, specifically:
- the inverted chip is arranged on the concave bottom of the concave pre-packaged carrier board, wherein the concave bottom of the concave pre-packaged carrier board is provided with a first set of pads, and the first set of pads is used to interact with the inverted front mounting
- the pins of the chip are electrically connected; the first set of pads transmits electrical characteristics to the end area of the concave side wall through the concave side wall of the concave pre-packaged carrier board, so that the concave pre-packaged carrier board can be reversed When on the bottom plate, realize the electrical connection between the inverted chip and the bottom plate;
- the outer surface of the concave bottom of the concave pre-packaged carrier board is further provided with a heat dissipation component, the heat dissipation component is coupled with the bottom of the inverted chip, and is used to drain away the heat generated when the inverted chip works;
- the ordinary form-fitting chip is arranged on the bottom plate, and heat is dissipated through the bottom plate itself and the packaging cavity itself.
- the concave pre-packaged carrier board realizes the electrical connection between the inverted chip and the bottom plate when the concave pre-packaged carrier board is upside down on the bottom plate, which specifically includes: a ball grid is provided at the end of the concave side wall of the concave pre-packaged carrier board The array bumps are soldered with the corresponding ball grid array pads on the bottom plate to complete the electrical connection between the inverted chip and the circuit on the bottom plate; or, the concave side wall of the concave pre-packaged carrier is provided with a second Set the pads, and complete the electrical connection between the inverted chip and the circuit on the bottom board by using gold wire bonding with the third set of pads on the bottom board located around the concave pre-packaged carrier board.
- the concave pre-packaged carrier board is made of ceramic or semiconductor material, and the corresponding concave bottom for setting up the inverted positive chip is made with a through hole structure;
- the heat dissipation component includes a thermal conductive glue and a thermal conductive metal gasket; specific:
- the thermally conductive metal gasket is fixed on the outer side of the concave bottom of the concave pre-packaged carrier board, and the bottom of the inverted positive chip passes through the through hole of the concave bottom through the thermally conductive glue, and is connected to the thermally conductive metal gasket. fit.
- the first set of pads transmits electrical characteristics to the end region of the concave side wall through the concave side wall of the concave pre-packaged carrier board, which specifically includes:
- the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors, wherein electrical rails are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails between the layers are coupled with each other ;
- a conductive medium is arranged in the electrical guide rail to complete the electrical connection between the first group of pads located at the bottom of the concave and the bumps of the ball grid array at the end; or to complete the first group of pads at the bottom of the concave Electrical connection with the second set of pads arranged on the concave sidewall.
- the packaging structure further includes a metal cover, specifically:
- the metal cover is fixed on the bottom plate, and the thermally conductive coupling between the thermally conductive metal gasket and the metal cover is completed by a TIM material.
- the ordinary formal chip is arranged on the bottom plate, which specifically includes:
- a set of heat dissipation holes are provided in the area where the ordinary formal chip is arranged, and the heat dissipation holes penetrate the bottom plate to provide a channel for heat dissipation at the bottom of the ordinary formal chip.
- the packaging structure further includes:
- the concave side wall of the concave pre-packaged carrier board is fixed on the bottom plate in the area of the bottom plate enclosed by the bottom plate, and at least one ordinary formal chip is arranged.
- the packaging structure further includes:
- a metal isolation cover plate for isolating high-frequency signals is provided in the concave area of the concave pre-packaged carrier board at a predetermined distance from the high-frequency front-mounted chip.
- the packaging structure further includes:
- a metal isolation layer is arranged inside the concave side wall or on the outside of the concave side wall of the concave pre-packaged carrier board.
- At least one ordinary formal mounting chip is provided in the bottom plate area enclosed by the concave side wall of the concave pre-packaged carrier board fixed on the bottom plate, specifically for:
- the ordinary formal-mounted chip that is more sensitive to high-frequency interference.
- the power consumption density of the front-mounted chip (the power of the chip divided by the heat dissipation area at the bottom of the chip) is greater than 0.5 W/mm 2 , it is confirmed as the inverted front-mounted chip.
- the present invention also provides a multi-chip heat dissipation packaging method, including:
- the at least two formal chips involved in the package structure are analyzed, and the at least two formal chips are divided into an inverted formal chip and a normal formal chip according to the analysis result and a preset strategy; wherein the inverted formal chip is set in a customized A concave pre-packaged carrier board, on which the ordinary formal chip is arranged on the bottom board;
- the concave pre-packaged carrier is fixed on the carrier. The designated position of the bottom plate;
- the first set of pads on the concave bottom of the concave pre-packaged carrier board, the second set of pads on the matching concave sidewall, and the first set of pads and the second set of pads are designed.
- the electrical connection includes:
- the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors, wherein electrical rails are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails between the layers are coupled with each other ;
- a conductive medium is arranged in the electrical rail to complete the electrical connection between the first set of pads at the bottom of the concave and the second set of pads on the sidewall of the concave.
- the first set of pads on the concave bottom of the concave pre-packaged carrier board, the ball grid array bumps at the ends of the matching concave sidewalls, and the first set of pads and the ball grid array bumps are designed.
- the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors, wherein electrical rails are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails between the layers are coupled with each other ;
- a conductive medium is arranged in the electrical rail to complete the electrical connection between the first set of pads at the bottom of the concave and the bumps of the ball grid array at the end of the concave sidewall.
- the present invention provides a multi-chip heat dissipation packaging structure and packaging method.
- the packaging structure conducts the heat generated by the chip to the top of the device packaging metal cover through the heat dissipation component contacting the bottom of the chip, thereby realizing efficient heat dissipation of the chip and ensuring the Normal operation; compared with the prior art, in the packaging structure of the present invention, when the inverted formal mounting chip is a high-frequency formal mounting chip, there is no additional metal conductor on the upper surface of the high-frequency formal mounting chip, which will not affect the high-frequency formal mounting The signal transmission performance inside the chip and when the chip is interconnected with the package carrier.
- FIG. 1 is a schematic cross-sectional view of a multi-chip heat dissipation package structure provided by an embodiment of the present invention
- FIG. 2 is a schematic cross-sectional view of a pre-packaged carrier in a multi-chip heat dissipation package structure provided by an embodiment of the present invention
- FIG. 3 is a schematic cross-sectional view of a multi-chip heat dissipation package structure provided by an embodiment of the present invention.
- FIG. 4 is a schematic cross-sectional view of a pre-packaged carrier in a multi-chip heat dissipation package structure provided by an embodiment of the present invention
- FIG. 5 is a schematic cross-sectional view of a pre-packaged carrier in a multi-chip heat dissipation package structure provided by an embodiment of the present invention
- FIG. 6 is a schematic cross-sectional view of a multi-chip heat dissipation package structure provided by an embodiment of the present invention.
- FIG. 7 is a schematic cross-sectional view of another multi-chip heat dissipation package structure provided by an embodiment of the present invention.
- FIG. 8 is a schematic flowchart of a multi-chip heat dissipation packaging method according to an embodiment of the present invention.
- FIG. 9 is a schematic flowchart of a multi-chip heat dissipation packaging method according to an embodiment of the present invention.
- FIG. 10 is a schematic diagram of an assembly process of a concave pre-packaged carrier in a multi-chip heat dissipation package structure provided by an embodiment of the present invention
- FIG. 11 is a schematic flowchart of a multi-chip heat dissipation packaging method provided by an embodiment of the present invention.
- FIG. 12 is a schematic diagram of the overall packaging process of a multi-chip heat dissipation packaging structure provided by an embodiment of the present invention.
- FIG. 13 is a schematic flowchart of a multi-chip heat dissipation packaging method according to an embodiment of the present invention.
- the terms “inner”, “outer”, “longitudinal”, “transverse”, “upper”, “lower”, “top”, “bottom”, etc. indicate the orientation or positional relationship based on the accompanying drawings.
- the orientation or positional relationship shown is only for the convenience of describing the present invention and does not require that the present invention must be constructed and operated in a specific orientation, so it should not be understood as a limitation to the present invention.
- Embodiment 1 of the present invention provides a multi-chip heat dissipation package structure.
- FIG. 1 shows an exemplary structure diagram realized by an embodiment of the present invention.
- the chip is arranged in a left-right position (in the cross-sectional view shown in FIG. 1, it is specifically represented as a left-right arrangement relationship), and the implementation of the present invention also includes the up and down stacking structure shown in FIG. 7 and the stacked structure shown in FIG. 1 and FIG. 7
- the combination scheme of the structure, the feasible schemes that can be realized by the present invention will be described in detail in the subsequent specific expansion schemes and related embodiments.
- the package structure includes an inverted formal chip 4 and at least one ordinary formal chip (labeled as 10 and 11 in FIG. 1, which are also exemplarily described as a first formal chip 10 and a second formal chip 11), specific:
- the inverted chip 4 is arranged on the concave bottom of the concave pre-packaged carrier board 1, wherein the concave bottom of the concave pre-packaged carrier board is provided with a first set of pads (shown clearly in FIG.
- the first set of pads are located in the concave bottom area associated with the gold wire bonding wire 5), and the first set of pads are used for electrical connection with the pins of the inverted formal chip 3;
- the group pads transfer electrical characteristics to the end area of the concave side wall through the concave side wall of the concave pre-packaged carrier board (shown as the interconnection solder joint 7 on the end face of the concave side wall in Figure 2; in another scenario, in It is shown as the second set of pads on the concave sidewall in FIG. 3), so that when the concave pre-packaged carrier board is upside down on the bottom plate, the electrical connection between the inverted chip and the bottom plate can be realized;
- the outer surface of the concave bottom of the concave pre-packaged carrier board is further provided with a heat dissipation component, the heat dissipation component is coupled with the bottom of the inverted chip, and is used to drain away the heat generated when the inverted chip works;
- the ordinary form-fitting chip is arranged on the bottom plate, and heat is dissipated through the bottom plate itself and the packaging cavity itself.
- the embodiment of the present invention provides a multi-chip heat dissipation package structure.
- the package structure conducts the heat generated by the chip to the top of the device packaging metal cover through the heat dissipation component contacting the bottom of the chip, thereby realizing efficient heat dissipation of the chip and ensuring the normality of the chip Operation;
- the packaging structure of the present invention when the inverted formal chip is a high-frequency formal chip, there is no additional metal conductor on the upper surface of the high-frequency formal chip, so that it will not affect the high-frequency formal chip Signal transmission performance inside and when the chip is interconnected with the package carrier.
- the first set of pads transmits electrical characteristics to the end area of the concave side wall through the concave side wall of the concave pre-packaged carrier board, so that the concave pre-packaged carrier board is inverted on When it is on the bottom plate, at least two optional implementation methods are provided to realize the electrical connection between the inverted chip and the bottom plate.
- the end of the concave side wall of the concave pre-packaged carrier board is provided with ball grid array bumps (that is, an example of the interconnection solder joints 7), and corresponding to the bottom plate Soldering of the ball grid array pads to complete the electrical connection between the inverted chip and the circuit on the bottom plate;
- ball grid array bumps that is, an example of the interconnection solder joints 7
- a second set of pads are provided on the concave side wall of the concave pre-packaged carrier board, and the third set of pads are connected to the bottom board and located around the concave pre-packaged carrier board.
- the electrical connection between the inverted chip and the circuit on the bottom board is completed by means of gold wire bonding.
- the number of pads in the second group of pads is determined according to the number of pins of the inverted chip.
- the first method its integration degree is higher than that of the second method, and the manufacturing process complexity will be relatively high.
- the first method has a larger area for the end of the concave side wall. Certain requirements, if the area of the end of the concave side wall is relatively small, higher process requirements are put forward for the formation of electrical connection channels inside the concave side wall.
- the second method requires the introduction of gold wire bonding wire, and its overall cost will be higher, and the integration of the overall package structure is not as good as the first method.
- the concave pre-packaged carrier board is usually processed from ceramic or semiconductor materials, and the corresponding concave bottom for setting up the inverted positive chip is made with a through-hole structure; then the heat dissipation component includes a thermal conductive glue 4 and thermally conductive metal gasket 2; as shown in Figure 2, specific:
- the thermally conductive metal gasket 2 is fixed on the outer side of the concave bottom of the concave pre-packaged carrier board 1, and the bottom of the inverted positive chip 3 passes through the thermally conductive glue 4, passes through the through hole of the concave bottom, and is directly connected to the concave bottom.
- the thermally conductive metal gasket 2 is attached.
- FIG. 4 it is a schematic diagram corresponding to the electrical characteristic structure of the concave pre-packaged carrier board shown in FIG. 2 in the concave side wall.
- a structural performance as shown in FIG. 4 is given.
- the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors.
- reference numerals 101, 102, and 103 respectively represent three-layer ceramic substrates or three-layer semiconductor structures, respectively.
- Electrical rails 104 are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails 104 between the layers are coupled to each other;
- the electrical guide rail 104 is provided with a conductive medium 105, which is used to complete the electrical connection between the first set of pads at the bottom of the concave shape and the bumps of the ball grid array at the end, that is, the structural diagram shown in FIG. 4; or, It is used to complete the electrical connection between the first set of pads located at the bottom of the recess and the second set of pads provided on the sidewall of the recess, as shown in FIG. 5, where part A in FIG. In the package carrier, the structure diagram of the multilayer ceramic substrate (or multilayer semiconductor stack) on the concave side wall on the left side, where part B in FIG. 5 is a left view of the structure corresponding to part A in FIG. 5 for Show the second group of pad structure more intuitively.
- the package structure also includes a metal cover, as shown in Figure 1, specifically:
- the metal cover 12 is fixed on the bottom plate 8, and the thermally conductive coupling between the thermally conductive metal gasket 2 and the metal cover 12 is completed by a TIM material 14.
- a sealant 13 or solder is usually used to form a better sealing performance at the junction of the metal cover 12 and the bottom plate 8.
- the heat dissipation structure after the ordinary formal chip is placed on the bottom plate may adopt the structure shown in FIG.
- a set of heat dissipation holes 9 are provided in the area of the front-mounted chip shown in 10 and 11, and the heat-dissipating holes 9 penetrate through the bottom plate to provide a channel for heat dissipation at the bottom of the ordinary front-mounted chip.
- the embodiment of the present invention also provides an optional implementation solution to improve the above-mentioned high-frequency interference problem.
- Metal isolation layer 106 in order to prevent the inverted positive-mounting chip set on the concave pre-packaged carrier from affecting the electrical pathways on the bottom plate, a metal isolation cover can also be used to set the concave area of the concave pre-packaged carrier in the high-frequency area. Between the front-mounted chip and the bottom plate, and thus with the metal isolation layer 106, can completely isolate the high-frequency interference of the high-frequency front-mounted chip.
- the present invention is a technical solution for instantiating expressions of partial characteristic structures based on consideration of specific application scenarios among the many realizable manners of Embodiment 1.
- the package structure includes:
- the inverted chip is arranged on the concave bottom of the concave pre-packaged carrier board, wherein the concave bottom of the concave pre-packaged carrier board is provided with a first set of pads, and the first set of pads is used to interact with the inverted front mounting
- the pins of the chip are electrically connected; the first set of pads transmits electrical characteristics to the end area of the concave side wall through the concave side wall of the concave pre-packaged carrier board, so that the concave pre-packaged carrier board can be reversed When on the bottom plate, realize the electrical connection between the inverted chip and the bottom plate;
- the outer surface of the concave bottom of the concave pre-packaged carrier board is further provided with a heat dissipation component, the heat dissipation component is coupled with the bottom of the inverted chip, and is used to drain away the heat generated when the inverted chip works;
- the ordinary form-fitting chip is arranged on the bottom plate, and heat is dissipated through the bottom plate itself and the packaging cavity itself; and the concave side wall of the concave pre-packaged carrier board is fixed on the bottom plate and is surrounded by In the bottom plate area, there is at least one ordinary formal chip.
- the ordinary formal chip and the inverted formal chip are designed to be stacked up and down, that is, there are both inverted formal chips.
- the normal form-fitting chip is located in the concave area of the concave pre-packaged carrier board.
- the structure proposed by the embodiment of the present invention has at least the following two considerations, and can be effectively improved by the embodiment of the present invention:
- the heat of the front-mounted chip described here is greater than the first preset temperature, and the bottom area of the front-mounted chip is less than the first preset area is selected as the condition for the inverted front-mounted chip, that is, the heat dissipation hole that can be made by the current process cannot effectively complete the heat dissipation
- One or more front-mounted chips are completed by adopting the structure of using the concave pre-packaged carrier board to invert the front-mounted chips proposed in the embodiment of the present invention.
- the inverted formal mounting chip when selecting the inverted formal mounting chip and In the case of the ordinary formal mounting chip located in the recessed area of the recessed pre-packaged carrier board, it is preferable to select one or more ordinary formal mounting chips whose initial chip temperature rise rate is higher than that of the inverted formal mounting chip to be placed on the bottom plate in the recessed area , Thereby improving the working environment temperature of the inverted formal chip.
- the reason is that the relative heat dissipation effect of the concave pre-packaged carrier board structure where the inverted formal chip is located is much higher than that of the ordinary formal chip set on the bottom plate, so in an extremely low temperature environment, the inverted formal chip is also affected by the extreme low temperature environment.
- the working environment temperature of the inverted front-mounted chip can be improved through the faster heating capacity of the ordinary front-mounted chip located in the concave area.
- the main controller chip is selected as the ordinary formal-mounted chip arranged on the bottom plate and located in the concave area, because the main controller is the first chip to be activated in the package structure and has a faster temperature rise characteristic.
- Case 2 Although the embodiment of the present invention considers the problem of high frequency interference to the ordinary formal chip in the scenario where the inverted formal chip is specifically a high frequency formal chip, and provides an improved solution as shown in FIG. 6. However, it is not difficult to see from FIG. 6 that a metal isolation layer 106 needs to be fabricated on the concave pre-packaged carrier board, and even a metal isolation cover plate needs to be added to improve the interference problem.
- the structure proposed in the embodiment of the present invention can prevent high-frequency interference effects similar to that shown in FIG. 6, and can also effectively reduce the processing cost and processing complexity of the concave pre-packaged carrier board.
- the high-frequency formal mounting chip is under the performance of the inverted formal mounting chip in a specific example), and the two are separated by the metal isolation cover plate 6.
- the metal isolation layer 106 As shown in FIG. 6 to achieve the expected high-frequency signal anti-interference effect, which reduces the processing difficulty and processing cost of the entire package structure.
- the ordinary formal-mounted chip that is more sensitive to high-frequency interference.
- the packaging structure further includes: The concave area of the concave pre-packaged carrier board is at a predetermined distance from the high-frequency front-mounted chip, and a metal isolation cover plate for isolating high-frequency signals is provided.
- a preset distance is to comprehensively consider the thermal conductivity of both parties.
- the metal isolation cover is set Too close to the ordinary formal chip located on the bottom plate, the normal formal chip located in the recessed area considered in the above case will reduce the effect of improving the working environment of the inverted formal chip in the extreme case, because at this time the ordinary formal chip located in the recessed area The heat of the chip will be more dissipated through the heat dissipation holes in the bottom plate, and the corresponding metal isolation cover will play a certain role in blocking the heat of the ordinary formal chip in the concave area from spreading to the area where the inverted formal chip is located.
- the metal isolation cover is set too close to the inverted front-mounted chip, it will affect the heat dissipation effect of the inverted front-mounted chip in the rapid heating scenario, because after the metal isolation cover is close to the inverted front-mounted chip, it will be relatively close.
- the recessed area space of the inverted formal chip will be compressed, which will reduce the effect of the recessed area space to alleviate the heating rate in the context of rapid heating of the inverted formal chip. Therefore, the preset distance is set after comprehensively considering the above two factors.
- the parameter value of the specific preset distance will be set specifically according to the difference of the specific chip and the use environment. Therefore, in the implementation of the present invention The examples do not give examples of specific parameter values, but those skilled in the art are sufficient to obtain the preset distance of a specific application scenario through a limited number of test experiments based on the above analysis content.
- the embodiment of the present invention provides a multi-chip heat dissipation packaging method, which is used to realize the packaging structure shown in Embodiment 1 and Embodiment 2. As it is a method-side embodiment based on a common inventive concept, it is correspondingly described in the embodiment
- the structural improvement schemes based on specific examples in Embodiment 1 and Embodiment 2 are also applicable to the packaging method process of the embodiment of the present invention. In order to simplify the description of the method process of this embodiment, the extensions developed in Embodiment 1 and Embodiment 2 are similar.
- the related content of the solution is not repeatedly described in the embodiment of the present invention.
- the packaging method of the embodiment of the present invention includes:
- step 201 the at least two formal-mounted chips involved in the package structure are analyzed, and the at least two formal-mounted chips are divided into an inverted formal-mounted chip and a normal formal-mounted chip according to the analysis result and a preset strategy; wherein, the inverted formal-mounted chip It is set on a custom recessed pre-packaged carrier board, and the ordinary formal chip is set on the bottom plate.
- step 202 the first set of pads on the concave bottom of the concave pre-packaged carrier board, the second set of pads on the matching concave sidewalls, and the first set of pads are designed according to the pin characteristics of the selected inverted formal chip. The electrical connection between one set of pads and the second set of pads.
- the second set of pads can also be replaced by the ball grid array bumps. Point; but for the sake of simplicity of description, in the method of the embodiment of the present invention, only the second set of pads are used as an example for description.
- step 203 after the inverted formal chip is set on the concave pre-packaged carrier and the pins of the inverted formal chip are electrically connected to the first set of pads, the concave pre-packaged The carrier board is fixed at a designated position of the bottom plate; the second group of pads are electrically connected to the corresponding third group of pads on the bottom plate.
- step 204 the electrical connection of the ordinary formal chip on the bottom plate is completed.
- the embodiment of the present invention provides a multi-chip heat dissipation packaging method.
- the packaging method conducts the heat generated by the chip to the top of the device packaging metal cover through the heat dissipation component contacting the bottom of the chip, thereby realizing efficient heat dissipation of the chip and ensuring the normality of the chip Operation;
- the inverted formal chip is a high-frequency formal chip
- FIG. 9 which specifically includes:
- the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors, wherein electrical rails are arranged between each layer of ceramic substrate or each layer of semiconductor, and between the layers The electrical rails are coupled with each other.
- the concave pre-packaged carrier board is formed by stacking multilayer ceramic substrates or multilayer semiconductors.
- reference numerals 101, 102, and 103 respectively represent three-layer ceramic substrates or three-layer semiconductor structures, respectively.
- Electrical rails 104 are arranged between each layer of ceramic substrate or each layer of semiconductor, and the electrical rails 104 between the layers are coupled to each other;
- the electrical guide rail 104 is provided with a conductive medium 105, which is used to complete the electrical connection between the first set of pads at the bottom of the concave shape and the bumps of the ball grid array at the end, that is, the structural diagram shown in FIG. 4; or, Used to complete the electrical connection between the first set of pads located at the bottom of the recess and the second set of pads on the sidewall of the recess, as shown in Figure 5, where part A in Figure 5 is located in the recessed pre-packaged carrier
- the specific layering relationship is not necessarily limited to the structure shown in Figure 4 or Figure 5.
- the number of layers is usually adapted according to the complexity of the graphic structure to be presented in the concave area. Adjusted, but similar to those shown in Figures 4 and 5, it is a preferred electrical connection structure, especially the ceramic substrate 102 and ceramic substrate 103 (or described as semiconductor 102 and semiconductor 103) in Figure 4 can be a single ceramic substrate, thus Further compress the number of layers of the ceramic substrate.
- the fewer ceramic substrate layers that constitute the concave sidewalls the better the corresponding electrical connection characteristics, because the fewer the turning or connecting nodes in the electrical connection, the better the electrical characteristics.
- a conductive medium is provided in the electrical rail to complete the electrical connection between the first set of pads at the bottom of the concave shape and the second set of pads provided at the end.
- the embodiment of the present invention provides for the processing process of the related components of the concave pre-packaged carrier board in step 203, refer to the structure assembly process diagram shown in FIG. 10, and refer to the label relationship shown in FIG. 1, as shown in FIG. 11, the assembly method include:
- step 2031 the pre-packaged carrier 1 and the thermally conductive metal pad 2 are welded together by a reflow or eutectic process; the reflow or eutectic process is characterized in that the solder joints formed can withstand subsequent assembly of ⁇ BGA, ball grid array bump Point, metal isolation cover and BGA welding temperature.
- step 2032 the inverted front-mounted chip 3 is bonded to the thermally conductive metal gasket 2 by using the thermally conductive glue 4.
- step 2033 the gold wire bonding wire 5 is used to realize the signal interconnection between the inverted formal chip 3 and the pre-packaged carrier board 1.
- step 2034 the metal isolation cover 6 is adhered to the pre-packaged carrier 1.
- step 2035 interconnect solder joints 7 are planted on the pre-packaged carrier board 1.
- the embodiment of the present invention has been designed since the concave pre-packaged carrier board has been designed, and the implementation process of the embodiment of the present invention is explained only from the perspective of assembly.
- Refer to the structural assembly process diagram shown in FIG. 12 and the method flowchart shown in FIG. 13 for details include:
- step 301 the concave pre-packaged carrier 1 is flip-mounted on the bottom plate 8.
- the concave pre-packaged carrier board is a complete assembly after performing the method steps shown in FIG. 11.
- step 302 ordinary formal-mounted chips (for example, the first formal-mounted chip 10 and the second formal-mounted chip 11 in FIG. 1) are bonded in the cavity of the bottom plate 8.
- TIM14 is coated on the top of the concave pre-packaged carrier.
- the TIM14 has certain fluidity and high thermal conductivity, and can achieve close contact between the thermally conductive metal gasket and the metal cover.
- step 304 the metal cover 12 is adhered to the bottom plate 8 through sealant or solder 13.
- the sealant or solder 13 is characterized in that it can achieve an air-tight or quasi-air-sealed packaging inside the device, and effectively protect the chip.
- step 305 a BGA 15 is planted at the bottom of the bottom plate 8 to realize the input and output of the device signal.
- the BGA 15 is characterized in that the melting temperature is lower than the welding temperature of the aforementioned reflow or eutectic process, ⁇ BGA, ball grid array bumps, and metal isolation cover plate, and can meet the requirements of the subsequent SMT process.
- the program can be stored in a computer-readable storage medium.
- the storage medium can include: Read memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
Description
Claims (14)
- 一种多芯片散热封装结构,其特征在于,包括倒置正装芯片和至少一个普通正装芯片,具体的:所述倒置芯片被设置在凹型预封装载板的凹型底部,其中,所述凹型预封装载板的凹型底部设置有第一组焊盘,所述第一组焊盘用于与所述倒置正装芯片的引脚进行电气连接;所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域,以便于所述凹型预封装载板在倒扣在底板上时,实现倒置芯片与底板之间的电气连接;所述凹型预封装载板的凹型底部的外表面还设置有散热组件,所述散热组件与所述倒置芯片的底部耦合,用于将所述倒置芯片工作时产生的热量疏导出去;其中,所述普通正装芯片被设置在所述底板上,并通过所述底板自身和封装腔体自身进行散热。
- 根据权利要求1所述的多芯片散热封装结构,其特征在于,所述凹型预封装载板在倒扣在底板上时,实现倒置芯片与底板之间的电气连接,具体包括:所述凹型预封装载板的凹型侧壁的端部设置有球栅阵列凸点,并通过与底板上对应的球栅阵列焊盘进行焊接,完成所述倒置芯片与底板上电路的电气连接;或者,所述凹型预封装载板的凹型侧壁上设置有第二组焊盘,并通过与底板上位于所述凹型预封装载板四周的第三组焊盘,利用金丝焊线的方式完成倒置芯片与底板上电路的电气连接。
- 根据权利要求1所述的多芯片散热封装结构,其特征在于, 所述凹型预封装载板由陶瓷或者半导体材料加工而成,相应的用于设置倒置正装芯片的凹型底部制作有通孔结构;则所述散热组件包括导热胶和导热金属垫片;具体的:所述导热金属垫片固定在所述凹型预封装载板的凹型底部外侧,所述倒置正装芯片的底部经由所述导热胶,穿过所述凹型底部的通孔,与所述导热金属垫片贴合。
- 根据权利要求3所述的多芯片散热封装结构,其特征在于,所述第一组焊盘通过凹型预封装载板的凹型侧壁将电气特性传递到凹型侧壁的端部区域,具体包括:所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成,其中,各层陶瓷基板或者各层半导体之间设置有电气导轨,并且,层与层之间的电气导轨相互耦合;所述电气导轨内设置有导电介质,用于完成位于凹型底部第一组焊盘与端部设置的球栅阵列凸点之间的电气连接;或者,用于完成位于凹型底部第一组焊盘与凹型侧壁上设置的第二组焊盘之间的电气连接。
- 根据权利要求3所述的多芯片散热封装结构,其特征在于,所述封装结构还包括金属封盖,具体的:所述金属封盖固定在所述底板上,并且,所述导热金属垫片与所述金属封盖之间通过TIM材料完成导热耦合。
- 根据权利要求1所述的多芯片散热封装结构,其特征在于,所述普通正装芯片被设置在所述底板上,具体包括:所述底板上,位于设置所述普通正装芯片的区域设置有一组散热孔,所述散热孔贯穿所述底板,用于为所述普通正装芯片的底部散热提供渠道。
- 根据权利要求1-6任一所述的多芯片散热封装结构,其特征在于,所述封装结构还包括:所述凹型预封装载板的凹型侧壁固定在底板上后所围成的底板区域中,设置有至少一个普通正装芯片。
- 根据权利要求7所述的多芯片散热封装结构,其特征在于,在所述倒置正装芯片具体为高频正装芯片时,所述封装结构还包括:在所述凹型预封装载板的凹型区域,且与高频正装芯片相差预设距离处,设置有隔离高频信号用的金属隔离盖板。
- 根据权利要求8所述的多芯片散热封装结构,其特征在于,在凹型预封装载板所在底板外围区域上,还设置有普通正装芯片时,所述封装结构还包括:所述凹型预封装载板的凹型侧壁内部或者凹型侧壁外部上设置有金属隔离层。
- 根据权利要求8所述的多芯片散热封装结构,其特征在于,在所述普通正装芯片数量至少有两个时,由所述凹型预封装载板的凹型侧壁固定在底板上后所围成的底板区域中,设置有至少一个普通正装芯片,具体为:至少两个普通正装芯片中,相对高频干扰更为敏感的普通正装芯 片。
- 根据权利要求1-6任一所述的多芯片散热封装结构,其特征在于,正常工作下,正装芯片功耗密度大于等于0.5W/mm 2时,则确认作为所述倒置正装芯片。
- 一种多芯片散热封装方法,其特征在于,包括:分析封装结构中所涉及的至少两个正装芯片,根据分析结果和预设策略将所述至少两个正装芯片分为倒置正装芯片和普通正装芯片;其中,所述倒置正装芯片被设置在定制的凹型预封装载板上,所述普通正装芯片被设置在底板上;根据选定的倒置正装芯片的管脚特性,设计所述凹型预封装载板的凹型底部的第一组焊盘,配套的凹型侧壁上的第二组焊盘,以及第一组焊盘与第二组焊盘之间的电气连接;或者,设计所述凹型预封装载板的凹型底部的第一组焊盘,配套的凹型侧壁端部的球栅阵列凸点,以及第一组焊盘与球栅阵列凸点之间的电气连接;在将所述倒置正装芯片设置在所述凹型预封装载板上,并完成倒置正装芯片的管脚与所述第一组焊盘的电气连接后,将所述凹型预封装载板固定在所述底板的指定位置;将所述第二组焊盘与底板上的相应的第三组焊盘进行电气连接;或者,将所述凹型侧壁端部的球栅阵列凸点与底板上的球栅阵列焊盘进行电气连接;完成普通正装芯片在所述底板上的电气连接。
- 根据权利要求12所述的多芯片散热封装方法,其特征在于, 所述设计所述凹型预封装载板的凹型底部的第一组焊盘,配套的凹型侧壁上的第二组焊盘,以及第一组焊盘与第二组焊盘之间的电气连接,具体包括:所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成,其中,各层陶瓷基板或者各层半导体之间设置有电气导轨,并且,层与层之间的电气导轨相互耦合;所述电气导轨内设置有导电介质,用于完成位于凹型底部第一组焊盘与凹型侧壁上的第二组焊盘的电器连接。
- 根据权利要求12所述的多芯片散热封装方法,其特征在于,所述设计所述凹型预封装载板的凹型底部的第一组焊盘,配套的凹型侧壁端部的球栅阵列凸点,以及第一组焊盘与球栅阵列凸点之间的电气连接,具体包括:所述凹型预封装载板由多层陶瓷基板或者多层半导体叠装而成,其中,各层陶瓷基板或者各层半导体之间设置有电气导轨,并且,层与层之间的电气导轨相互耦合;所述电气导轨内设置有导电介质,用于完成位于凹型底部第一组焊盘与凹型侧壁端部的球栅阵列凸点的电器连接。
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US5650593A (en) * | 1994-05-26 | 1997-07-22 | Amkor Electronics, Inc. | Thermally enhanced chip carrier package |
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KR100266637B1 (ko) * | 1997-11-15 | 2000-09-15 | 김영환 | 적층형볼그리드어레이반도체패키지및그의제조방법 |
KR20020039010A (ko) * | 2000-11-20 | 2002-05-25 | 윤종용 | 방열판을 갖는 이중 칩 패키지 |
JP5197961B2 (ja) * | 2003-12-17 | 2013-05-15 | スタッツ・チップパック・インコーポレイテッド | マルチチップパッケージモジュールおよびその製造方法 |
JP5023604B2 (ja) * | 2006-08-09 | 2012-09-12 | 富士電機株式会社 | 半導体装置 |
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CN105789154A (zh) * | 2016-04-20 | 2016-07-20 | 广东工业大学 | 一种倒装芯片模组 |
CN109346442B (zh) * | 2018-10-10 | 2020-05-15 | 常熟市华通电子有限公司 | 一种易于散热的芯片封装结构及其封装方法 |
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- 2020-04-13 CN CN202010283622.5A patent/CN113539989B/zh active Active
- 2020-08-28 WO PCT/CN2020/111972 patent/WO2021208322A1/zh active Application Filing
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