WO2021208177A1 - 封装芯片电学性能的测试方法 - Google Patents

封装芯片电学性能的测试方法 Download PDF

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Publication number
WO2021208177A1
WO2021208177A1 PCT/CN2020/090699 CN2020090699W WO2021208177A1 WO 2021208177 A1 WO2021208177 A1 WO 2021208177A1 CN 2020090699 W CN2020090699 W CN 2020090699W WO 2021208177 A1 WO2021208177 A1 WO 2021208177A1
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wafer
metal layer
top metal
test
electrical performance
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PCT/CN2020/090699
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English (en)
French (fr)
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梅萌
史刚
王培春
李广峰
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澜起电子科技(昆山)有限公司
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Priority to US17/272,766 priority Critical patent/US11393732B2/en
Publication of WO2021208177A1 publication Critical patent/WO2021208177A1/zh

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    • H—ELECTRICITY
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    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
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    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
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    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
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Definitions

  • the present invention generally relates to the technical field of packaged chip testing, in particular to a manufacturing method of a packaged chip electrical performance test structure and a packaged chip electrical performance test method.
  • Semiconductor integrated circuit chip refers to a silicon chip containing an integrated circuit, which is small in size and is often part of a computer or other electronic equipment.
  • Chip packaging is the packaging of semiconductor integrated circuit chips with insulating materials, and the pins of the packaged chips are connected to other devices through a printed circuit board. In order to ensure the reliability of the chip shipped out of the factory, it is necessary to test the packaged chip before leaving the factory to ensure functional integrity and so on.
  • the current method of measuring the electrical performance of a packaged chip is to add a large amount of solder to the bump area of the packaged chip for short-circuiting, connect the packaged chip to the circuit board, and set up a conductive structure for testing on the other side of the circuit board. Then, the probe is used to contact the conductive structure and the electrical performance of the packaged chip is measured by a vector network analyzer. In this test method, since the area where the packaged chip is connected to the circuit board is covered with green oil, the effect of the solder short circuit is poor, resulting in deviations in the electrical performance test results.
  • the purpose of the present invention is to provide a test method for the electrical performance of a packaged chip, which enhances the short-circuiting effect of the bump, thereby enhancing the contact performance between the bump and the probe, and improving the reliability of the test.
  • An embodiment of the present application discloses a manufacturing method of a packaged chip electrical performance test structure, including:
  • the first wafer and the second wafer are respectively packaged to form first particles and second particles, the second particles are used as a test structure, and the electrical properties of the second particles are used as a measure of the electrical properties of the first particles. refer to.
  • the step of forming bumps on part of the top metal layer further includes:
  • the patterned photoresist is removed.
  • the bumps include one of copper, nickel, tin, and silver or any combination thereof.
  • the top metal layer is grown by a sputtering process, and the top metal layer includes one of copper, gold, silver, nickel, and tin or any combination thereof.
  • the first wafer includes a transistor, an interconnection structure, and a control circuit.
  • the step of separately packaging the first wafer and the second wafer to form the first particles and the second particles further includes: packaging the first wafer and the second wafer by the same packaging process. The second wafer.
  • test structure manufactured by the foregoing manufacturing method includes:
  • the bumps of the test structure are connected to the substrate, and the other side of the substrate relative to the test structure is provided with a conductive structure for testing;
  • a probe is used to contact the conductive structure to test the electrical performance of the test structure.
  • the electrical properties include resistance properties and inductance properties.
  • the substrate is a printed circuit board, a flexible circuit board, a ceramic substrate or an organic substrate.
  • the conductive structure includes solder balls.
  • the second particle is used as the test structure, the surface of the second particle has a complete top metal layer, and the connection performance between the top metal layer and the bumps is better, so that the short circuit is good during the test, thereby improving the reliability of the test.
  • the second particles of the present application and the first particles (having a control circuit, etc.) as a product adopt the same metal layer process and packaging process, no additional process is added, and the cost is lower.
  • FIG. 1 shows a flowchart of a manufacturing method of a packaged chip electrical performance test structure in an embodiment of the present application.
  • FIG. 2 shows a schematic diagram of the first wafer and the second wafer in an embodiment of the present application.
  • FIG. 3 shows a schematic diagram of forming a polyimide layer and a top metal layer in an embodiment of the present application.
  • FIG. 4 shows a schematic diagram of forming a patterned photoresist and bumps in an embodiment of the present application.
  • FIG. 5 shows a schematic diagram of removing the patterned photoresist and the top metal layer in an embodiment of the present application.
  • FIG. 6 shows a schematic diagram of a reflow soldering process for bumps in an embodiment of the present application.
  • FIG. 7 shows a flowchart of a method for testing the electrical performance of a packaged chip in an embodiment of the present application.
  • FIG. 8 shows a schematic diagram of the electrical performance test process in an embodiment of the present application.
  • the first embodiment of the present application discloses a manufacturing method of a packaged chip electrical performance test structure.
  • FIG. 1 shows a flow chart of the manufacturing method of the test structure
  • FIGS. 2 to 6 show schematic diagrams of the structure corresponding to each step. .
  • the method includes:
  • a first wafer 100 and a second wafer 200 are provided.
  • the wafer refers to a substrate on which a device can be formed, for example, a silicon substrate, a silicon germanium substrate A substrate, a gallium arsenide substrate, etc.
  • the device may refer to a CMOS circuit, for example, a structure that includes one or more transistors, an interconnection structure, and a control circuit, etc., for realizing specific functions.
  • Other device structures may also be formed in the wafer, such as amplifiers, digital/analog converters, analog processing circuits and/or digital processing circuits, interface circuits, etc.
  • the method for forming these device structures may all be CMOS processes.
  • the first wafer 100 is used to form normal chip products, that is, devices are formed in the first wafer 100
  • the second wafer 200 is used for testing, that is, no devices are formed in the second wafer 200 , Only the metal layer and bumps that need to be tested are formed, and the electrical performance of the chip product is measured according to the test result of the second wafer.
  • the first wafer 100 and the second wafer 200 are respectively formed with pads 112, 212 and passivation layers 114, 214, the passivation layers 114, 214 partially cover the pads 112, 212, and the passivation layers 114, 214 are nitrogen Silicon (SiN).
  • polyimide layers 116, 216 are formed on the substrates 110, 210, respectively, and the polyimide layers 116, 216 are used to release the stress of the underlying substrates 110, 210, respectively. It should be understood that the polyimide layers 116 and 216 are optional, and in other embodiments, the polyimide layers 116 and 216 may not be formed.
  • top metal layers 118 and 218 are formed on the first wafer 100 and the second wafer 200, respectively.
  • the top metal layer refers to the uppermost metal layer or the metal layer under bumps in the process (Under bump metellization).
  • a sputtering process is used to form the top metal layer.
  • the top metal layer 118, 218 may include one of copper (Cu), titanium (Ti), gold (Au), silver (Ag), nickel (Ni), tin (Sn) or any combination thereof, for example, sputtering Copper or titanium forms the top metal layer.
  • the thickness of the top metal layer 118, 218 may be 300 nm to 600 nm, such as 300 nm, 400 nm, 600 nm, and so on.
  • Step S105 referring to FIG. 4, bumps 122 and 222 are formed on part of the top metal layers 118 and 218, respectively.
  • the step of forming bumps on part of the top metal layer further includes:
  • a patterned photoresist (PR) 120, 220 is deposited on the top metal layer 118, 218, respectively, and the patterned photoresist 120, 220 exposes a portion of the top metal layer 118, 218, while exposing the solder Disk 112,212.
  • PR photoresist
  • the patterned photoresist can be formed by a process known in the art or known in the future, and will not be repeated here.
  • an electroplating deposition (ECD) process is used to grow bumps 122 and 222 on the top metal layers 118 and 218 that are not covered by the patterned photoresist, respectively.
  • the bumps 122 and 222 may include one of copper, nickel, tin, and silver or any combination thereof.
  • the thickness of the bumps 122 and 222 may be 38 ⁇ m to 95 ⁇ m, for example, 40 ⁇ m, 50 ⁇ m, 60 ⁇ m, 65 ⁇ m, 78 ⁇ m, 86 ⁇ m, 90 ⁇ m, etc.
  • the bumps 122, 222 include a first metal layer 1220, 2220, a second metal layer 1222, 2222, and a third metal layer 1224, 2224 that are sequentially stacked, and the first metal layer 1220, 2220 is a copper metal layer.
  • the second metal layers 1222 and 2222 are nickel metal layers.
  • the third metal layers 1224, 2224 are tin-silver solder layers.
  • the bumps 122, 222 include two metal layers, for example, a first metal layer and a second metal layer.
  • the first metal layer is a nickel metal layer
  • the second metal layer is a solder layer.
  • LF solder no lead solder layer
  • the patterned photoresist 120, 220 is removed, for example, the photoresist 120, 220 is removed by using a plasma etching process or an ashing process.
  • Step S107 continuing to refer to FIG. 5, remove the top metal layer 118 in the first wafer 100 outside the bumps 122, leaving the top metal layer 218 in the second wafer 200 completely.
  • the top metal layer 118 in the first wafer 100 located outside the bumps 122 is removed, the unremoved top metal layer 118 in the first wafer 100 is used for interconnection, and the second The top metal layer 218 in the wafer 200 does not need to be interconnected, and is only used for electrical performance testing, so it does not need to be removed.
  • a wet etching process may be used to remove the top metal layer.
  • the top metal layer in the second wafer is an unetched metal layer
  • the surface of the top metal layer in the second wafer is flat, and the contact performance between the top metal layer and the bumps is good .
  • the manufacturing method further includes performing a reflow process on the bumps 122 and 222.
  • step S109 the first wafer 100 and the second wafer 200 are respectively packaged to form a first die and a second die, the second die is used as a test structure, and the electrical properties of the second die are used as Reference for the electrical properties of the first particles.
  • the step of encapsulating the first wafer and the second wafer to form the first particles and the second particles further includes: encapsulating the first particles by the same packaging process.
  • the wafer can be packaged using a technology well known to those skilled in the art, which will not be repeated here.
  • the structure of the second particle is shown as 200' in FIG. 8.
  • the second particle 200' includes a substrate 210', a top metal layer 218' located on the substrate 210', and is connected to the top metal layer.
  • the second particle and the first particle (having a control circuit, etc.) as a chip product adopt the same metal layer process and packaging process, no additional process is added, and the cost of realizing the test is lower.
  • the second embodiment of the present application also discloses a method for testing the electrical performance of a packaged chip.
  • FIG. 7 shows a flowchart of the testing method for the electrical performance of a packaged chip. Steps S201 to S209 are similar to the aforementioned S101 to S109. The method includes:
  • Step S201 providing a first wafer and a second wafer
  • Step S203 forming a top metal layer on the first wafer and the second wafer respectively;
  • Step S205 forming bumps on part of the top metal layer of the first wafer and the second wafer respectively;
  • Step S207 removing the top metal layer in the first wafer that is located outside the bumps, and completely leaving the top metal layer in the second wafer;
  • Step S209 encapsulating the first wafer and the second wafer to form first particles and second particles respectively;
  • the second particles are arranged on a substrate, the bumps are connected to the substrate, and the other side of the substrate relative to the second particles is provided with a conductive structure for testing.
  • the substrate is a printed circuit board (PCB), a flexible circuit board (FPC) or an organic substrate, and a pad (PAD) for electrical connection is provided on the substrate, and the bump is connected to the The pad connection of the substrate.
  • an encapsulant is used to connect the test structure and the substrate to reinforce the connection between the particles and the substrate.
  • the conductive structure is a solder ball.
  • a probe is used to contact the conductive structure 310 to test the electrical performance of the second particle 200', and the electrical performance of the second particle 200' is used as a reference for the electrical performance of the first particle.
  • the electrical properties include resistance properties and inductance properties.
  • FIG. 8 shows a schematic diagram of the electrical performance test process in an embodiment.
  • the second particle 200' is inverted on the substrate 300, the bump 222' is electrically connected to the pad (not shown in the figure) on the substrate 300, and an encapsulant (not shown in the figure) is provided between the bump 222' and the substrate 300 Out), a solder ball 310 is provided on the other side of the substrate 300 relative to the second particle 200'.
  • two probes shown by the arrow in the figure
  • One end of the probe is grounded (G), and the other probe is connected to the signal end (S).
  • the vector network analyzer measures the resistance value and the inductance value of the particles respectively, and the vector network analyzer uses a method known to those skilled in the art to test the resistance value and the inductance value, which will not be repeated here.
  • the following table 1 shows the results of the resistance value (R) and inductance value (H) measured by the present application and the existing test methods.
  • R resistance value
  • H inductance value
  • only the signal DAC1 is used as an example, and the different 6 are tested respectively.
  • those skilled in the art can test other signals such as QACA13. It can be seen from Table 1 below that the test method of the present application has significantly improved the resistance value test, the standard deviation of the resistance value has been reduced from 38.5667 to 0.0568, and the inductance value test has also been improved to a certain extent.
  • an act is performed based on a certain element, it means that the act is performed at least based on that element, which includes two situations: performing the act only based on the element, and performing the act based on the element and Other elements perform the behavior.
  • Multiple, multiple, multiple, etc. expressions include two, two, two, and two or more, two or more, and two or more expressions.

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Abstract

一种封装芯片电学性能的测试方法，测试方法中包括封装芯片电学性能测试结构的制作方法，测试方法具体包括：提供第一晶圆（100）和第二晶圆（200）；分别在第一晶圆（100）和第二晶圆（200）上形成顶层金属层（118, 218, 218'）；分别在第一晶圆（100）和第二晶圆（200）的部分顶层金属层（118, 218, 218'）上形成凸块（122, 222, 222'）；去除第一晶圆（100）中位于凸块（122）下方之外的顶层金属层（118），完全保留第二晶圆（200）中的顶层金属层（218, 218'）；分别封装第一晶圆（100）和第二晶圆（200）形成第一颗粒和第二颗粒（200'），将第二颗粒（200'）设置于基板（300）上，凸块（222, 222'）与基板（300）连接，基板（300）相对于第二颗粒（200'）的另一侧设置有用于测试的导电结构（310）；采用探针与导电结构（310）接触，测试第二颗粒（200'）的电学性能，第二颗粒（200'）的电学性能作为第一颗粒电学性能的参考。该方法采用第二颗粒（200'）作为测试结构，第二颗粒（200'）表面具有完整的顶层金属层（218, 218'），顶层金属层（218, 218'）与凸块（222, 222'）的连接性能更好，使得测试过程中短接良好，从而提高测试的可靠性。

Description

封装芯片电学性能的测试方法 技术领域
本发明一般涉及封装芯片测试技术领域，特别涉及一种封装芯片电学性能测试结构的制作方法、封装芯片电学性能的测试方法。
背景技术
半导体集成电路芯片指内含集成电路的硅片，体积很小，常常是计算机或其他电子设备的一部分。芯片封装是将半导体集成电路芯片用绝缘材料进行打包，封装芯片的引脚通过印刷电路板与其他器件建立连接。为了保证出厂的芯片的可靠性，需要在出厂前对封装芯片进行测试以确保功能完整性等。
目前测量封装芯片电学性能的方法是在封装芯片的凸块(bump)区域添加大量的焊料(solder)进行短接，将封装芯片与电路板连接，电路板的另一侧设置测试用的导电结构，然后，用探针与导电结构接触并通过矢量网络分析仪测量封装芯片的电学性能。该测试方法中，由于封装芯片与电路板连接的区域上覆盖有绿油，使得焊料短接的效果差，导致电学性能测试结果存在偏差。
发明内容
本发明的目的在于提供一种封装芯片电学性能的测试方法，增强凸块的短接效果，从而增强凸块与探针的接触性能，提高测试的可靠性。
本申请的一实施例中公开了一种封装芯片电学性能测试结构的制作方法，包括：
提供第一晶圆和第二晶圆；
分别在所述第一晶圆和所述第二晶圆上形成顶层金属层；
分别在所述第一晶圆和所述第二晶圆的部分所述顶层金属层上形成凸块；
去除所述第一晶圆中位于所述凸块下方之外的顶层金属层，完全保留所述第二晶圆中的顶层金属层；
分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒，所述第二颗粒作为测试结构，所述第二颗粒的电学性能作为所述第一颗粒电学性能的参考。
在一优选例中，在部分所述顶层金属层上形成凸块的步骤，进一步包括：
在所述顶层金属层上沉积图案化的光阻，所述图案化的光阻暴露出部分的顶层金属层；
采用电镀沉积工艺在所述暴露的部分顶层金属层上生长所述凸块；
去除所述图案化的光阻。
在一优选例中，所述凸块包括铜、镍、锡、银中的一种或其任意组合。
在一优选例中，采用溅射工艺生长所述顶层金属层，所述顶层金属层包括铜、金、银、镍、锡中的一种或其任意组合。
在一优选例中，所述第一晶圆内包括有晶体管、互连结构和控制电路。
在一优选例中，分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒的步骤，进一步包括：采用相同的封装工艺封装所述第一晶圆和所述第二晶圆。
本申请的另一实施例还公开了一种封装芯片电学性能的测试方法，采用前文所述的制作方法制作的测试结构，包括：
将所述测试结构设置于基板上，所述测试结构的凸块与所述基板连接，所述基板相对于所述测试结构的另一侧设置有用于测试的导电结构；
采用探针与所述导电结构接触，测试所述测试结构的电学性能。
在一优选例中，所述电学性能包括电阻性能和电感性能。
在一优选例中，所述基板为印刷电路板、柔性电路板、陶瓷基板或有机 基板。
在一优选例中，所述导电结构包括锡球。
本申请中，采用第二颗粒作为测试结构，第二颗粒表面具有完整的顶层金属层，顶层金属层与凸块的连接性能更好，使得测试过程中短接良好，从而提高测试的可靠性。
此外，本申请的第二颗粒与作为产品的第一颗粒(具有控制电路等)采用相同的金属层工艺和封装工艺，没有额外增加工艺，成本较低。
附图说明
参考以下附图描述本申请的非限制性和非穷举性实施例，其中除非另有说明，否则相同的附图标记在各个附图中指代相同的部分。
图1示出了本申请一实施例中封装芯片电学性能测试结构的制作方法的流程图。
图2示出了本申请一实施例中第一晶圆和第二晶圆的示意图。
图3示出了本申请一实施例中形成聚酰亚胺层和顶层金属层的示意图。
图4示出了本申请一实施例中形成图案化的光阻和凸块的示意图。
图5示出了本申请一实施例中去除图案化的光阻和顶层金属层的示意图。
图6示出了本申请一实施例中凸块进行回流焊工艺的示意图。
图7示出了本申请一实施例中封装芯片电学性能的测试方法的流程图。
图8示出了本申请一实施例中电学性能测试过程的示意图。
具体实施方式
现在将描述本申请的各个方面和示例。以下描述提供了用于彻底理解和实现这些示例的描述的具体细节。然而，本领域技术人员将理解，可以在没有许多这些细节的情况下实践本申请。
另外，可能未详细示出或描述一些众所周知的结构或功能，以便简明扼 要并避免不必要地模糊相关描述。
在下面给出的描述中使用的术语旨在以其最广泛的合理方式解释，即使它与本申请的某些特定示例的详细描述一起使用。以下甚至可以强调某些术语，然而，任何旨在以任何受限制的方式解释的术语将在本详细描述部分中明确且具体地定义。
本申请的第一实施例中公开了一种封装芯片电学性能测试结构的制作方法，图1示出了测试结构的制作方法的流程图，图2至图6示出了各步骤对应的结构示意图。该方法包括：
步骤S101，提供第一晶圆(wafer)100和第二晶圆200，参考图2所示，所述晶圆指的是可以在其中形成器件的衬底，例如，硅衬底、锗硅衬底、砷化镓衬底等等，所述器件可以指的是CMOS电路，例如包括一个或多个晶体管、互连结构和控制电路等等，用于实现特定功能的结构。所述晶圆中还可以形成有其他器件结构，例如放大器、数/模转换器、模拟处理电路和/或数字处理电路、接口电路等，形成这些器件结构的方法均可以为CMOS工艺。其中，所述第一晶圆100用于形成正常的芯片产品，即在第一晶圆100中形成器件，所述第二晶圆200用于测试，即在第二晶圆200中不形成器件，仅形成需要实现测试的金属层和凸块，根据第二晶圆的测试结果衡量芯片产品的电学性能。所述第一晶圆100和所述第二晶圆200中分别形成焊盘112,212以及钝化层114,214，所述钝化层114,214分别部分覆盖所述焊盘112,212，所述钝化层114,214为氮化硅(SiN)。
在一实施例中，参考图3所示，分别在所述衬底110,210上形成聚酰亚胺(polyimide)层116,216，所述聚酰亚胺层116,216分别用于释放下方衬底110,210的应力。应当理解，所述聚酰亚胺层116,216是可选的，在其他实施例中，也可以不形成聚酰亚胺层116,216。
步骤S103，继续参考图3所示，分别在所述第一晶圆100和第二晶圆200上形成顶层金属层118,218。本领域技术人员应当公知的是，在芯片工艺 制程中，需要形成多层金属层，例如，3至5层金属层，以实现电连接。本实施例中，所述顶层金属层指的是工艺制程中的最上层金属层或凸块下方的金属层(Under bump metellization)。在一实施例中，采用溅射(sputtering)工艺形成所述顶层金属层。所述顶层金属层118,218可包括铜(Cu)、钛(Ti)、金(Au)、银(Ag)、镍(Ni)、锡(Sn)中的一种或其任意组合，例如，溅射铜或钛形成所述顶层金属层。所述顶层金属层118,218的厚度可以为300nm～600nm，例如300nm、400nm、600nm等。
步骤S105，参考图4所示，分别在部分所述顶层金属层118,218上形成凸块(bump)122,222。在一实施例中，步骤S105中，在在部分所述顶层金属层上形成凸块的步骤，进一步包括：
参考图4所示，分别在所述顶层金属层118,218上沉积图案化的光阻(PR)120,220，所述图案化的光阻120,220暴露出部分所述顶层金属层118,218，同时暴露出所述焊盘112,212。应当理解，图案化的光阻可以采用本领域已知或未来可知的工艺形成，在此不做赘述。
之后，采用电镀沉积(ECD)工艺分别在所述图案化的光阻未覆盖的所述顶层金属层118,218上生长凸块122,222。在一实施例中，所述凸块122,222可包括铜、镍、锡、银中的一种或其任意组合。所述凸块122,222的厚度可以为38μm～95μm，例如，40μm、50μm、60μm、65μm、78μm、86μm、90μm等。例如，凸块122,222包括依次层叠的第一金属层1220,2220、第二金属层1222,2222和第三金属层1224,2224，所述第一金属层1220,2220为铜金属层。所述第二金属层1222,2222为镍金属层。所述第三金属层1224,2224为锡银焊料层。
在另一实施例中，所述凸块122,222包括两层金属层，例如，第一金属层和第二金属层，所述第一金属层为镍金属层，所述第二金属层为焊料层，例如，不含铅焊料层(LF solder)。
接着，参考图5所示，去除所述图案化的光阻120,220，例如，采用等离 子体蚀刻工艺或灰化工艺去除所述光阻120,220。
步骤S107，继续参考图5所示，去除所述第一晶圆100中位于所述凸块122下方之外的顶层金属层118，完全保留所述第二晶圆200中的顶层金属层218。本实施例中，去除所述第一晶圆100中位于所述凸块122下方之外的顶层金属层118，第一晶圆100中未去除的顶层金属层118用于实现互连，第二晶圆200中的顶层金属层218不需要实现互连，仅用于电学性能测试，因而不需要去除。本实施例中，可以采用湿法蚀刻工艺去除所述顶层金属层。
本实施例中，由于第二晶圆中的顶层金属层是未经蚀刻的金属层，因此第二晶圆中的顶层金属层的表面平整，该顶层金属层与凸块之间的接触性能良好。
参考图6所示，在一实施例中，所述制作方法还包括对所述凸块122,222进行回流焊(reflow)工艺。
步骤S109，分别封装所述第一晶圆100和所述第二晶圆200形成第一颗粒(die)和第二颗粒，所述第二颗粒作为测试结构，所述第二颗粒的电学性能作为所述第一颗粒电学性能的参考。在一实施例中，在步骤S109中，分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒的步骤，进一步包括：采用相同的封装工艺封装所述第一晶圆和所述第二晶圆。本实施例中，可以采用本领域技术人员公知的技术对晶圆进行封装，在此不做赘述。本实施例中，第二颗粒的结构参考图8中200’所示，第二颗粒200’包括衬底210’、位于所述衬底210’上的顶层金属层218’以及与顶层金属层连接的凸块222’。本实施例中，第二颗粒与作为芯片产品的第一颗粒(具有控制电路等)采用相同的金属层工艺和封装工艺，没有额外增加工艺，实现测试的成本较低。
本申请的第二实施例还公开了一种封装芯片电学性能的测试方法，图7示出了封装芯片电学性能的测试方法的流程图，步骤S201至S209与前文所述的S101至S109相似，该方法包括：
步骤S201，提供第一晶圆和第二晶圆；
步骤S203，分别在所述第一晶圆和所述第二晶圆上形成顶层金属层；
步骤S205，分别在所述第一晶圆和所述第二晶圆的部分所述顶层金属层上形成凸块；
步骤S207，去除所述第一晶圆中位于所述凸块下方之外的顶层金属层，完全保留所述第二晶圆中的顶层金属层；
步骤S209，分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒；
步骤S211，将所述第二颗粒设置于基板上，所述凸块与所述基板连接，所述基板相对于所述第二颗粒的另一侧设置有用于测试的导电结构。在一实施例中，所述基板为印刷电路板(PCB)、柔性电路板(FPC)或有机基板，所述基板上设置有用于电气连接的焊盘(PAD)，所述凸块与所述基板的焊盘连接。在一实施例中，采用封装胶连接所述测试结构与所述基板，用于补强颗粒与基板之间的连接。在一实施例中，所述导电结构为锡球。
步骤S213，采用探针与所述导电结构310接触，测试所述第二颗粒200’的电学性能，所述第二颗粒200’的电学性能作为所述第一颗粒电学性能的参考。在一实施例中，所述电学性能包括电阻性能和电感性能。
图8示出了一实施例中电学性能测试过程的示意图。第二颗粒200’倒置与基板300上，凸块222’与基板300上的焊盘(图中未示出)电气连接，凸块222’与基板300之间设置有封装胶(图中未示出)，基板300相对于所述第二颗粒200’的另一侧设置有锡球310。测试电学性能时，采用两个探针(图中箭头所示)分别与锡球310接触，其中一个探针的一端接地端(G)，另一个探针的一端接信号端(S)，采用矢量网络分析仪分别测试颗粒的电阻值和电感值，矢量网络分析仪采用本领域技术人员公知的方法测试电阻值和电感值，在此不做赘述。下表1中给出了本申请与现有的测试方法测量的电阻值(R)与电感值(H)的结果，下表1中仅以信号DAC1为例进行列举，分别 测试了不同的6个样品，当然本领域技术人员可以测试QACA13等其他的信号。从下表1中可以看出，本申请的测试方法对于电阻值测试的改善非常明显，电阻值的标准差由38.5667降低到0.0568，同时对于电感值的测试也有一定程度的改善。
表1电学性能的测试结果
Figure PCTCN2020090699-appb-000001
需要说明的是，在本专利的申请文件中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。本专利的申请文件中，如果提到根据某要素执行某行为，则是指至少根据该要素执行该行为的意思，其中包括了两种情况：仅根据该要素执 行该行为、和根据该要素和其它要素执行该行为。多个、多次、多种等表达包括2个、2次、2种以及2个以上、2次以上、2种以上。
在本说明书提及的所有文献都被认为是整体性地包括在本申请的公开内容中，以便在必要时可以作为修改的依据。此外应理解，以上所述仅为本说明书的较佳实施例而已，并非用于限定本说明书的保护范围。凡在本说明书一个或多个实施例的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本说明书一个或多个实施例的保护范围之内。
在一些情况下，在权利要求书中记载的动作或步骤可以按照不同于实施例中的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序才能实现期望的结果。在某些实施方式中，多任务处理和并行处理也是可以的或者可能是有利的。

Claims (10)

  1. 一种封装芯片电学性能测试结构的制作方法，其特征在于，包括：
    提供第一晶圆和第二晶圆；
    分别在所述第一晶圆和所述第二晶圆上形成顶层金属层；
    分别在所述第一晶圆和所述第二晶圆的部分所述顶层金属层上形成凸块；
    去除所述第一晶圆中位于所述凸块下方之外的顶层金属层，完全保留所述第二晶圆中的顶层金属层；
    分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒，所述第二颗粒作为测试结构，所述第二颗粒的电学性能作为所述第一颗粒电学性能的参考。
  2. 如权利要求1所述的测试结构的制作方法，其特征在于，在部分所述顶层金属层上形成凸块的步骤，进一步包括：
    在所述顶层金属层上沉积图案化的光阻，所述图案化的光阻暴露出部分的顶层金属层；
    采用电镀沉积工艺在所述暴露的部分顶层金属层上生长所述凸块；
    去除所述图案化的光阻。
  3. 如权利要求2所述的测试结构的制作方法，其特征在于，所述凸块包括铜、镍、锡、银中的一种或其任意组合。
  4. 如权利要求1所述的测试结构的制作方法，其特征在于，采用溅射工艺生长所述顶层金属层，所述顶层金属层包括铜、钛、金、银、镍、锡中的一种或其任意组合。
  5. 如权利要求1所述的测试结构的制作方法，其特征在于，所述第一晶圆内包括有晶体管、互连结构和控制电路。
  6. 如权利要求1所述的测试结构的制作方法，其特征在于，分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒的步骤，进一步包括：采用相同的封装工艺封装所述第一晶圆和所述第二晶圆。
  7. 一种封装芯片电学性能的测试方法，其特征在于，采用如权利要求1-6中任意一项所述的制作方法制作的测试结构，包括：
    将所述测试结构设置于基板上，所述测试结构的凸块与所述基板连接，所述基板相对于所述测试结构的另一侧设置有用于测试的导电结构；
    采用探针与所述导电结构接触，测试所述测试结构的电学性能。
  8. 如权利要求7所述的封装芯片电学性能的测试方法，其特征在于，所述电学性能包括电阻性能和电感性能。
  9. 如权利要求7所述的封装芯片电学性能的测试方法，其特征在于，所述基板为印刷电路板、柔性电路板、陶瓷基板或有机基板。
  10. 如权利要求7所述的封装芯片电学性能的测试方法，其特征在于，所述导电结构包括锡球。
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