WO2021203894A9 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2021203894A9
WO2021203894A9 PCT/CN2021/079786 CN2021079786W WO2021203894A9 WO 2021203894 A9 WO2021203894 A9 WO 2021203894A9 CN 2021079786 W CN2021079786 W CN 2021079786W WO 2021203894 A9 WO2021203894 A9 WO 2021203894A9
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Prior art keywords
storage capacitor
capacitor
layer
pixel electrode
sub
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PCT/CN2021/079786
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English (en)
French (fr)
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WO2021203894A1 (zh
Inventor
张正东
杨小飞
苏磊
王立苗
王红军
孟佳
胡晓旭
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US17/772,531 priority Critical patent/US11988927B2/en
Publication of WO2021203894A1 publication Critical patent/WO2021203894A1/zh
Publication of WO2021203894A9 publication Critical patent/WO2021203894A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a manufacturing method thereof, and a display device.
  • the storage capacitor is responsible for charging the liquid crystal capacitor during the screen holding phase to ensure that the voltage of the liquid crystal capacitor continues until the next screen update.
  • the embodiments of the present disclosure provide an array substrate, a manufacturing method thereof, and a display device, which can increase the storage capacitor capacity and improve display uniformity.
  • the technical solution is as follows:
  • an array substrate has a plurality of sub-pixels, a storage capacitor and an extended storage capacitor are arranged in the sub-pixels, and the extended storage capacitor and the storage capacitor are connected in parallel;
  • the array substrate includes: a gate layer, a source and drain layer, and a pixel electrode;
  • the first capacitor plate of the storage capacitor is located in the layer where the pixel electrode is located, and the second capacitor plate of the storage capacitor is located in at least one of the gate layer and the source/drain layer;
  • the first capacitor plate of the extended storage capacitor is located in the layer where the pixel electrode is located, and the second capacitor plate of the storage capacitor is located in at least one of the gate layer and the source drain layer.
  • the first capacitor plate of the storage capacitor is the pixel electrode, and the second capacitor plate of the storage capacitor is the first electrode in the source-drain layer;
  • the first capacitor plate of the extended storage capacitor is the pixel electrode, and the second capacitor plate of the extended storage capacitor is located in the source-drain layer and connected to the first electrode of the source-drain layer.
  • the plurality of sub-pixels are arranged in an array, and the source drain layer has a plurality of data lines extending in a column direction;
  • Two sub-pixels in the same row of sub-pixels are arranged between two adjacent data lines, the two sub-pixels each have an opening area, and the second capacitor plate of the extended storage capacitor of the two sub-pixels is Between the two opening regions of the two sub-pixels.
  • the second capacitor plate of the extended storage capacitor is in a strip shape, and the two adjacent data lines are located in the same row of sub-pixels between the two strip-shaped second capacitor plates.
  • the length direction extends along the column direction, the first ends of the strip-shaped second capacitor plates are all connected to the corresponding first poles, and the orthographic projections of the two strip-shaped second capacitor plates in the row direction are not Overlapping, the row direction is perpendicular to the column direction.
  • the first capacitor plate of the storage capacitor is the pixel electrode, and the second capacitor plate of the storage capacitor is a light blocking pattern in the gate layer;
  • the first capacitor plate of the extended storage capacitor is in the same layer as the pixel electrode and is connected to the pixel electrode, and the second capacitor plate of the extended storage capacitor is a light blocking pattern in the gate layer.
  • the plurality of sub-pixels are arranged in an array
  • the source and drain layer has a plurality of data lines extending in a column direction; a column of sub-pixels are respectively arranged on both sides of the data line;
  • the gate layers of the two sub-pixels located in the same row have a first light-blocking pattern and a second light-blocking pattern respectively, and the two sub-pixels located in the same row
  • the sub-pixels respectively have a first pixel electrode and a second pixel electrode, the first light-blocking pattern and the first pixel electrode are located in the same sub-pixel, and the second light-blocking pattern and the second pixel electrode are located in the same sub-pixel.
  • the first light-blocking pattern and the first pixel electrode close to the data line are projected on the base substrate in an orthographic projection that overlaps, and the second light-blocking pattern and the second pixel electrode are close to the The orthographic projection of one side of the data line on the base substrate coincides.
  • the gate layer includes a gate metal sublayer and a conductive thin film sublayer, and the gate layer has a U-shaped light blocking pattern;
  • the first capacitor plate of the storage capacitor is the pixel electrode, and the second capacitor plate of the storage capacitor is the light blocking pattern;
  • the first capacitor plate of the extended storage capacitor is the pixel electrode, the second capacitor plate of the extended storage capacitor is located in the conductive film sublayer, and the second capacitor plate of the extended storage capacitor is connected to the The orthographic projections of the U-shaped opening of the light blocking pattern on the base substrate at least partially overlap, and the second capacitor plate of the extended storage capacitor is electrically connected to the light blocking pattern.
  • the light blocking pattern is composed of the gate metal sublayer and the conductive thin film sublayer.
  • the storage capacitor has a size of 0.12 pF to 0.15 pF, and the capacitance of the extended storage capacitor and the storage capacitor in parallel is 0.18 pF to 0.22 pF.
  • a display device in one aspect, includes the array substrate as described above.
  • a manufacturing method of an array substrate is provided, the array substrate has a plurality of sub-pixels, and the manufacturing method includes:
  • the first capacitor plate of the storage capacitor is located in the layer where the pixel electrode is located, and the second capacitor plate of the storage capacitor is located in at least one of the gate layer and the source-drain layer;
  • the first capacitor plate of the extended storage capacitor is located in the layer where the pixel electrode is located, and the second capacitor plate of the extended storage capacitor is located in at least one of the gate layer and the source drain layer.
  • fabricating the gate layer, the source drain layer and the pixel electrode in sequence includes:
  • a conductive thin film sublayer, a gate metal sublayer, a gate insulating layer, an active layer, a source and drain layer, a planarization layer, and a pixel electrode are sequentially fabricated on the base substrate.
  • the gate layer includes a gate metal sublayer And a conductive thin film sub-layer, the gate layer has a U-shaped light blocking pattern;
  • the first capacitor plate of the storage capacitor is the pixel electrode, and the second capacitor plate of the storage capacitor is the light blocking pattern;
  • the first capacitor plate of the extended storage capacitor is the pixel electrode, the second capacitor plate of the extended storage capacitor is located in the conductive film sublayer, and the second capacitor plate of the extended storage capacitor is connected to the The orthographic projections of the U-shaped opening of the light blocking pattern on the base substrate at least partially overlap, and the second capacitor plate of the extended storage capacitor is electrically connected to the light blocking pattern.
  • sequentially fabricating a conductive thin film sublayer and a gate metal sublayer on the base substrate includes:
  • the photoresist is exposed using a halftone mask process, wherein the area corresponding to the light blocking pattern is an unexposed area, and the U-shaped opening of the light blocking pattern is a half exposed area;
  • the photoresist in the unexposed area is removed to obtain the conductive thin film sublayer and the gate metal sublayer.
  • This solution increases the capacity of the storage capacitor by adding an extended storage capacitor in parallel with the storage capacitor, and prevents the coupling capacitor between the signal lines in the display substrate from affecting the display of the display panel when the capacity of the storage capacitor is not large enough, thereby improving the display Uniformity; solves the problem of vertical stripes of liquid crystal displays and improves the image quality of liquid crystal displays.
  • FIG. 1 is a schematic circuit diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a hierarchical structure diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of the structure of a source and drain layer provided by an embodiment of the present disclosure
  • Figure 5 shows a cross-sectional view of Figure 3 at the data line A-A';
  • FIG. 6 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • Fig. 7 shows a cross-sectional view of Fig. 6 at the data line A-A';
  • FIG. 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • 15 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • 16 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • FIG. 1 is a schematic circuit diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate is a double-grid line array substrate.
  • the array substrate has a plurality of sub-pixels 10.
  • these sub-pixels 10 are divided into multiple pairs, and each pair of sub-pixels 10 includes two adjacent sub-pixels 10 (usually in the row direction). Two adjacent sub-pixels 10).
  • the two sub-pixels 10 of each pair of sub-pixels 10 are connected to the same data line 12 and are respectively located on both sides of the data line 12; each pair of sub-pixels 10 corresponds to two gate lines 11, and each sub-pixel 10 is connected to one of the gate lines.
  • String A storage capacitor C1 and an extended storage capacitor C2 are arranged in the sub-pixel 10, and the extended storage capacitor C2 and the storage capacitor C1 are connected in parallel.
  • a thin film transistor T and a liquid crystal capacitor C are formed in the sub-pixel 10.
  • the storage capacitor C1 and the extended storage capacitor C2 can both charge the liquid crystal capacitor C to ensure that the voltage of the liquid crystal capacitor C continues to The next time the screen is updated.
  • the size of the storage capacitor C1 may be 0.12 pF to 0.15 pF, and the capacitance of the extended storage capacitor C2 and the storage capacitor C1 after being connected in parallel may be 0.18 pF to 0.22 pF.
  • the size of the storage capacitor C1 may be 0.14 pF, and the capacitance of the extended storage capacitor C2 and the storage capacitor C1 in parallel may be 0.18 pF.
  • the array substrate provided by the embodiments of the present disclosure may be a display substrate of a twisted nematic (TN) liquid crystal display; the array substrate may also be an Advanced Super Dimension Switch (ADS), in-plane conversion Type (In Plane Switching, IPS) and other LCD display substrates.
  • ADS Advanced Super Dimension Switch
  • IPS in-plane conversion Type
  • other LCD display substrates other LCD display substrates.
  • the number of extended storage capacitors C2 in the sub-pixel 10 may be 1 to 3.
  • one or more extended storage capacitors C2 can be used in parallel with the storage capacitor C1 in one sub-pixel 10, so as to increase the capacity of the storage capacitor.
  • FIG. 2 is a hierarchical structure diagram of an array substrate provided by an embodiment of the present disclosure.
  • the array substrate includes: a base substrate 20, a gate layer 21, a gate insulating layer 22, an active layer 23, a source and drain layer 24, and a planarization layer 25 stacked on the base substrate 20 in sequence. (Or the protective layer PVX) and the pixel electrode 26.
  • the source-drain layer 24 includes a data line, a source electrode, and a drain electrode. The drain electrode is connected to the data line, and the source electrode is connected to the pixel electrode 26 through a via hole.
  • the connection here can be an electrical connection.
  • the base substrate 20 may be a glass substrate.
  • the gate layer 21 and the source/drain layer 24 may be a metal layer or an indium tin oxide layer.
  • the gate insulating layer 22 may be an insulating layer formed of one of silicon oxide, silicon nitride, and silicon oxynitride, or a stacked layer formed of at least two of them.
  • the active layer 23 may be a polysilicon layer or an amorphous silicon layer.
  • the planarization layer 25 may be a resin layer, and the planarization layer may also be a planarization layer formed of one of silicon oxide, silicon nitride, and silicon oxynitride, or a stacked layer formed of at least two of them.
  • the pixel electrode 26 may be an indium tin oxide electrode.
  • Figure 2 shows only one implementation of the structure of the array substrate at the thin film transistor.
  • the array substrate can also have other structures, as long as it can realize the function of the array substrate, for example, as shown in Figure 2 It is a bottom gate structure.
  • the array substrate may also be a top gate structure or the like.
  • the first capacitor plate of the storage capacitor C1 is located on the layer where the aforementioned pixel electrode 26 is located, and the second capacitor plate of the storage capacitor C1 may be located on at least one of the gate layer 21 and the source/drain layer 24.
  • the first capacitor plate of the extended storage capacitor C2 is located in the layer where the pixel electrode 26 is located, and the second capacitor plate of the storage capacitor C1 may be located in at least one of the gate layer 21 and the source/drain layer 24.
  • the pixel electrode 26 and the light blocking pattern in the gate layer 21 may form the aforementioned storage capacitor C1.
  • the pixel electrode 26 and one electrode of the source and drain layer 24 may form the aforementioned storage capacitor C1.
  • the pixel electrode 26 may simultaneously form the aforementioned storage capacitor C1 with the light blocking pattern in the gate layer 21 and one electrode of the source and drain layer 24 respectively.
  • FIG. 3 is a schematic diagram of a part of the structure of an array substrate provided by an embodiment of the present disclosure.
  • the source-drain layer 24 includes a data line 12, a first electrode 241 and a second electrode 242.
  • the first electrode 241 is one of the source and the drain
  • the second electrode 242 is the other of the source and the drain.
  • the first electrode 241 is a source electrode
  • the second electrode 242 is a drain electrode.
  • FIG. 4 further shows the structure of the source and drain layers.
  • the second capacitor plate of the storage capacitor C1 is the first electrode 241 in the source and drain layer 24, which is specifically marked M in FIG. 4 Corresponding to the part in the dashed box.
  • the first capacitor plate of the extended storage capacitor C2 is the pixel electrode 26, and the second capacitor plate C20 of the extended storage capacitor C2 is located on the source-drain layer 24 and connected to the source of the source-drain layer 24, which is shown in FIG. 4
  • the long strip part in the dashed box corresponding to the number N.
  • the second capacitor plate C20 of the extended storage capacitor is located in the source-drain layer 24, it can be electrically connected to the source.
  • the second capacitor plate C20 of the extended storage capacitor C2 connected to the source of the source-drain layer 24 is added to form an extended storage capacitor C2 with the pixel electrode 26, which is equivalent to increasing the source of the source-drain layer.
  • the electrode area is enlarged to overlap with the pixel electrode, thereby increasing the storage capacitance.
  • FIG. 3 only shows four sub-pixels 10 in a row.
  • the source-drain layer 24 has a plurality of data lines 12 extending in the column direction b.
  • two sub-pixels 10 in the same row of sub-pixels 10 are arranged between two adjacent data lines 12, the two sub-pixels 10 each have an opening area 13, and the extended storage capacitors C2 of the two sub-pixels 10
  • the second capacitor plate C20 is between the two opening regions 13 of the two sub-pixels 10.
  • the opening area 13 in FIG. 3 is surrounded by the light blocking pattern (Shield Bar, SB) 210 in the gate layer 21. As shown in FIG. For the opening area 13.
  • the light-blocking patterns 210 of the two sub-pixels 10 between the two data lines 12 are completely connected together as an integrated structure; while the light-blocking patterns 210 of the two sub-pixels 10 located on both sides of a data line 12
  • the pattern 210 is connected together by two connecting parts, which reduces the overlapping area of the data line 12 and the light blocking pattern 210.
  • the connecting part is the part in the elliptical dashed frame corresponding to the reference number P in FIG. 3.
  • the light blocking pattern 210 can also be another pattern that can define the opening area 13, such as a U-shape.
  • the light blocking pattern 210 can be multiplexed as a plate of a storage capacitor, that is, a common (COM) electrode; on the other hand, it can block light together with the black matrix on the color filter substrate.
  • COM common
  • the second capacitor plate C20 of the extended storage capacitor C2 is arranged between the opening regions 13 of the two sub-pixels 10.
  • the extended storage capacitor C2 can be arranged in this way. It is ensured that it overlaps with the pixel electrode 26.
  • setting the extended storage capacitor C2 in this way does not occupy the opening area 13, and does not affect the opening ratio of the display panel.
  • the second capacitor plate C20 of the extended storage capacitor C2 may be in a strip shape, and two adjacent data lines 12 are located in the same row of sub-pixels 10 in two strip shapes.
  • the length of the capacitor plate C20 extends along the column direction b.
  • the first ends of the strip-shaped second capacitor plates C20 are connected to the corresponding first poles 241, and the two strip-shaped second capacitor plates C20 are on the row side.
  • the upward orthographic projections do not overlap, and the row direction is perpendicular to the column direction b, that is, the direction a in the figure.
  • the minimum distance between the two strip-shaped second capacitor plates C20 is that of the two strip-shaped second capacitor plates C20.
  • the distance between the second ends of the two strip-shaped second capacitor plates C20 is greater than the threshold.
  • the threshold may be the distance between the two strip-shaped second capacitor plates C20 in the row direction b. Of course, this is only It is an example.
  • the threshold can be set according to actual conditions, and it is necessary to ensure that the interference between the two strip-shaped second capacitor plates C20 is sufficiently small.
  • strip-shaped second capacitor plates C20 and the arrangement of the second capacitor plates C20 in the above manner can ensure that there is a sufficient distance between the second capacitor plates C20 in the two sub-pixels 10 and avoid the two expansion storage capacitors C2. The distance of the second capacitor plate C20 is too close to affect the performance of the capacitor.
  • the orthographic projection of the second capacitor plate C20 of the extended storage capacitor C2 on the base substrate is located within the orthographic projection of the pixel electrode 26 on the base substrate. Since there is a certain distance between the pixel electrodes 26 of adjacent sub-pixels, the design of the second capacitor plate C20 in this way can also prevent the width of the second capacitor plate C20 in the row direction from being too large, and ensure that the second capacitor plate of the adjacent sub-pixels The spacing of C20 in the row direction to avoid mutual interference.
  • the orthographic projection of the second capacitor plate C20 of the extended storage capacitor C2 on the base substrate and the orthographic projection of the opening area 13 on the base substrate do not overlap.
  • the orthographic projections of the two sides of the second capacitor plate C20 of the extended storage capacitor C2 on the base substrate coincide with the orthographic projections of the edge of the opening area 13 and the edge of the pixel electrode 26 on the base substrate, respectively. This ensures that the area of the second capacitor plate C20 is as large as possible.
  • Fig. 5 is a cross-sectional view of Fig. 3 at the data line A-A'. 5, on both sides of the data line 12, the side of the pixel electrode 26 close to the data line 12 and the side of the light blocking pattern 210 close to the data line 12 are not aligned, that is, the pixel electrode 26 is close to one side of the data line 12.
  • the orthographic projections of the side and the side of the light blocking pattern 210 close to the data line 12 on the base substrate 20 do not overlap, and the side of the light blocking pattern 210 close to the data line 12 is closer to the data line 12 than the pixel electrode 26.
  • the second capacitor plate of the storage capacitor C1 is the light blocking pattern 210 in the gate layer 21;
  • the first capacitor plate of the extended storage capacitor C2 is in the same layer as the pixel electrode 26 and is connected to the pixel electrode 26.
  • the second capacitor plate C20 of the extended storage capacitor C2 is the light blocking pattern 210 in the gate layer 21.
  • the same layer may mean that it is formed in one patterning process, or it may mean that it is located on the same side of the same layer, or it may mean that the surfaces close to the base substrate are all in contact with the same layer, or the like.
  • the second capacitor plate C20 of the extended storage capacitor C2 connected to the pixel electrode 26 is added to form an extended storage capacitor C2 with the light blocking pattern 210 in the gate layer 21, which is equivalent to increasing the area of the pixel electrode 26 To enlarge the overlapping area with the light blocking pattern 210, thereby increasing the storage capacitance.
  • the array substrate provided by the embodiment of the present disclosure is an array substrate with a double-gate structure, that is, a column of sub-pixels 10 are respectively arranged on both sides of the data line 12.
  • FIG. 6 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure. Compared with FIG. 3, the difference in FIG. 6 is that the second capacitor plate C20 in FIG. 3 is not provided in the source and drain layers; on both sides of the data line 12, the pixel electrode 26 is close to one side of the data line 12 and blocks light.
  • the side of the pattern 210 close to the data line 12 is aligned, that is, the side of the pixel electrode 26 close to the data line 12 and the side of the light blocking pattern 210 close to the data line 12 are aligned with the orthographic projection on the base substrate 20.
  • Fig. 7 is a cross-sectional view of Fig. 6 at the data line A-A'.
  • the gate layers of the two sub-pixels located in the same row respectively have a first light blocking pattern 210A and a second light blocking pattern 210B, which are located in two columns of the same row.
  • Each sub-pixel has a first pixel electrode 261 and a second pixel electrode 262, the first light blocking pattern 210A and the first pixel electrode 261 are located in the same sub-pixel 10, and the second light blocking pattern 210B and the second pixel electrode 262 are located in the same sub-pixel 10.
  • the orthographic projections of the first light blocking pattern 210A and the first pixel electrode 261 close to the data line 12 are overlapped on the base substrate, and the second light blocking pattern 210B and the second pixel electrode 262 close to the data line 12 side.
  • the orthographic projections on the base substrate coincide.
  • the extra parts of the first pixel electrode 261 and the second pixel electrode 262 in FIG. 7 compared to those in FIG. 5 are the first capacitor plates of the aforementioned expanded storage capacitor C2.
  • FIG. 8 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure. Compared with FIG. 3, the difference in FIG. 8 is that the second capacitor plate C20 in FIG. 3 is not provided on the source and drain layers; the gate layer 21 includes a gate metal sublayer 211 and a conductive thin film sublayer 212. Exemplarily, the conductive thin film sublayer 212 is located between the base substrate and the gate metal sublayer 211.
  • the gate layer 21 has a U-shaped light blocking pattern 210.
  • the second capacitor plate of the storage capacitor C1 is the light-blocking pattern 210; the first capacitor plate of the extended storage capacitor C2 is the pixel electrode 26, and the second capacitor plate C20 of the extended storage capacitor C2 is located on the conductive film sublayer 212 to extend the storage
  • the orthographic projection of the second capacitor plate C20 of the capacitor C2 and the U-shaped opening of the light blocking pattern 210 on the base substrate at least partially overlap, and the second capacitor plate C20 of the extended storage capacitor C2 is electrically connected to the light blocking pattern 210 .
  • an extended storage capacitor is formed by overlapping the newly added conductive thin film sublayer 212 and the pixel electrode, thereby increasing the storage capacitor.
  • the advantage of using the conductive thin film sublayer 212 and the pixel electrode to form the capacitor is that the distance between the conductive thin film sublayer 212 and the gate line 11 in the gate layer is greater than the distance between the light blocking pattern 210 and the gate line 11, and the conductive thin film sublayer 212 and the gate
  • the parasitic capacitance of the line 11 is smaller than the parasitic capacitance of the light blocking pattern 210 and the gate line 11, so the capacitance formed by the conductive thin film sublayer 212 and the pixel electrode 26 is more stable.
  • the conductive thin film sub-layer 212 may be an indium tin oxide layer.
  • the extended storage capacitor can be implemented using any one of the foregoing embodiments, or a combination of two or more embodiments, that is, two or more extended storage capacitors are designed at the same time, and the storage capacitor in parallel.
  • the extended storage capacitor includes a first extended storage capacitor and a second extended storage capacitor.
  • the first capacitor plate of the first extended storage capacitor is the pixel electrode 26, and the second capacitor plate C20 of the first extended storage capacitor is located on the source-drain layer 24 and is connected to the first electrode 241 of the source-drain layer 24 (ie The scheme shown in FIG. 3); the first capacitor plate of the second extended storage capacitor is in the same layer as the pixel electrode 26 and is connected to the pixel electrode 26, and the second capacitor plate of the second extended storage capacitor is in the gate layer 21
  • the light blocking pattern 210 that is, the solution shown in FIG. 6).
  • the extended storage capacitor includes a first extended storage capacitor and a third extended storage capacitor.
  • the first capacitor plate of the first extended storage capacitor is the pixel electrode 26, and the second capacitor plate of the first extended storage capacitor is located on the source-drain layer 24 and is connected to the first electrode 241 of the source-drain layer 24 (i.e.
  • the first capacitor plate of the third extended storage capacitor is the pixel electrode 26
  • the second capacitor plate of the third extended storage capacitor is located on the conductive film sublayer 212
  • the second capacitor of the third extended storage capacitor The orthographic projection of the U-shaped opening of the electrode plate and the light blocking pattern 210 on the base substrate 20 at least partially overlap, and the second capacitor plate of the third extended storage capacitor is electrically connected to the light blocking pattern 210 (that is, as shown in FIG. 8 Plan).
  • the extended storage capacitor includes a second extended storage capacitor and a third extended storage capacitor.
  • the first capacitor plate of the second extended storage capacitor is in the same layer as the pixel electrode 26 and is connected to the pixel electrode 26.
  • the second capacitor plate of the second extended storage capacitor is the light-blocking pattern 210 in the gate layer 21 (i.e.
  • the first capacitor plate of the third extended storage capacitor is the pixel electrode 26
  • the second capacitor plate of the third extended storage capacitor is located on the conductive film sublayer 212
  • the second capacitor of the third extended storage capacitor The orthographic projection of the U-shaped opening of the electrode plate and the light blocking pattern 210 on the base substrate 20 at least partially overlap, and the second capacitor plate of the third extended storage capacitor is electrically connected to the light blocking pattern 210 (that is, as shown in FIG. 8 Plan).
  • the extended storage capacitor includes a first extended storage capacitor, a second extended storage capacitor, and a third extended storage capacitor.
  • the first capacitor plate of the first extended storage capacitor is the pixel electrode 26, and the second capacitor plate C20 of the first extended storage capacitor is located on the source-drain layer 24 and is connected to the first electrode 241 of the source-drain layer 24 (ie The scheme shown in FIG. 3); the first capacitor plate of the second extended storage capacitor is in the same layer as the pixel electrode 26 and is connected to the pixel electrode 26, and the second capacitor plate of the second extended storage capacitor is in the gate layer 21
  • the light blocking pattern 210 that is, the solution shown in FIG.
  • the first capacitor plate of the third extended storage capacitor is the pixel electrode 26, and the second capacitor plate of the third extended storage capacitor is located on the conductive film sublayer 212,
  • the orthographic projections on the base substrate 20 of the second capacitor plate of the third extended storage capacitor and the U-shaped opening of the light blocking pattern 210 at least partially overlap, and the second capacitor plate of the third extended storage capacitor and the light blocking pattern 210 are at least partially overlapped Electrical connection (ie the scheme shown in Figure 8).
  • the present disclosure provides a display device, which includes the array substrate as described in any of the previous embodiments.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • This solution increases the capacity of the storage capacitor by adding an extended storage capacitor in parallel with the storage capacitor, and prevents the coupling capacitor between the signal lines in the display substrate from affecting the display of the display panel when the capacity of the storage capacitor is not large enough, thereby improving the display Uniformity.
  • the embodiments of the present disclosure also provide a manufacturing method of an array substrate for manufacturing the array substrate described in any one of the foregoing embodiments.
  • the manufacturing method includes: manufacturing storage capacitors and expanding storage capacitors in sub-pixels, expanding storage capacitors and The storage capacitors are connected in parallel.
  • This solution increases the capacity of the storage capacitor by adding an extended storage capacitor in parallel with the storage capacitor, and prevents the coupling capacitor between the signal lines in the display substrate from affecting the display of the display panel when the capacity of the storage capacitor is not large enough, thereby improving the display Uniformity.
  • FIG. 9 is a flowchart of a manufacturing method of an array substrate provided by an embodiment of the present disclosure. Referring to Figure 9, the method includes:
  • Step 801 Provide a base substrate.
  • the base substrate may be a glass substrate.
  • Step 802 sequentially fabricate a gate layer, a gate insulating layer, an active layer, a source-drain layer, a planarization layer, and a pixel electrode on a base substrate.
  • the first capacitor plate of the storage capacitor is located in the layer where the pixel electrode is located, and the second capacitor plate of the storage capacitor is located in at least one of the gate layer and the source-drain layer.
  • the first capacitor plate of the extended storage capacitor is located in the layer where the pixel electrode is located, and the second capacitor plate of the extended storage capacitor is located in at least one of the gate layer and the source-drain layer.
  • the gate layer and the source/drain layer may be a metal layer or an indium tin oxide layer.
  • the gate insulating layer may be an insulating layer formed of one of silicon oxide, silicon nitride, and silicon oxynitride, or a stacked layer formed of at least two of them.
  • the active layer may be a polysilicon layer or an amorphous silicon layer.
  • the planarization layer may be a resin layer, and the planarization layer may also be a planarization layer formed of one of silicon oxide, silicon nitride, and silicon oxynitride, or a stacked layer formed of at least two of them.
  • the pixel electrode may be an indium tin oxide electrode.
  • the first capacitor plate of the storage capacitor is a pixel electrode, and the second capacitor plate of the storage capacitor is the first electrode in the source and drain layer;
  • the first capacitor plate of the extended storage capacitor is a pixel electrode
  • the second capacitor plate of the extended storage capacitor is located in the source-drain layer and is connected to the first electrode of the source-drain layer.
  • step 802 may include: forming a gate layer on the base substrate; forming a gate insulating layer and an active layer on the gate layer; forming a source-drain layer on the active layer, the source-drain layer including Source electrode, drain electrode, data line and second capacitor plate for expanding storage capacitor; forming a planarization layer on the source and drain layer and via holes for connecting the source and pixel electrodes; forming pixel electrode on the planarization layer .
  • the array substrate can be manufactured using a 5Mask (mask) process.
  • the first capacitor plate of the storage capacitor is a pixel electrode, and the second capacitor plate of the storage capacitor is a light blocking pattern in the gate layer;
  • the first capacitor plate of the extended storage capacitor is in the same layer as the pixel electrode and is connected to the pixel electrode, and the second capacitor plate is a light-blocking pattern in the gate layer.
  • step 802 may include: forming a gate layer on the base substrate; forming a gate insulating layer and an active layer on the gate layer; forming a source-drain layer on the active layer; A planarization layer and a via hole for connecting the source electrode and the pixel electrode are formed thereon; the pixel electrode and a first capacitor plate for extending the storage capacitor are formed on the planarization layer.
  • the array substrate can be manufactured using a 5Mask (mask) process.
  • the gate layer includes a gate metal sublayer and a conductive thin film sublayer, and the gate layer has a U-shaped light blocking pattern;
  • the first capacitor plate of the storage capacitor is a pixel electrode, and the second capacitor plate of the storage capacitor is a light blocking pattern;
  • the first capacitor plate of the extended storage capacitor is the pixel electrode
  • the second capacitor plate of the extended storage capacitor is located in the conductive film sublayer
  • the second capacitor plate of the extended storage capacitor and the U-shaped opening of the light blocking pattern are on the base substrate
  • the orthographic projections on the upper part are at least partially overlapped, and the second capacitor plate of the extended storage capacitor is electrically connected to the light blocking pattern.
  • Sequentially fabricating the conductive thin film sublayer and the gate metal sublayer on the base substrate may include:
  • Step S1 Depositing a conductive film and gate metal on the base substrate in sequence.
  • FIG. 10 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure. Referring to FIG. 10, a conductive film 2120 and a gate metal 2110 are sequentially deposited on the base substrate 20.
  • Step S2 coating a layer of photoresist on the gate metal.
  • FIG. 11 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • a layer of photoresist 2130 is coated on the gate metal 2110.
  • the photoresist may be a positive photoresist or a negative photoresist.
  • Step S3 Expose the photoresist by using a halftone mask process, where the area corresponding to the light-blocking pattern is an unexposed area, the U-shaped opening of the light-blocking pattern is a half-exposed area, the opening area and the grid lines and light blocking The area between the patterns is the fully exposed area.
  • FIG. 12 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • a halftone mask (HTM) process is used to expose the photoresist 2130.
  • the exposed display substrate is divided into 3 areas, the non-exposed area M1, the half-exposed area M2, and the full-exposed area M3 .
  • Step S4 sequentially removing the photoresist, the gate metal and the conductive film in the fully exposed area.
  • FIG. 13 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • the photoresist 2130 in the fully exposed area M3 is first removed by a photoresist removal process. At this time, the thickness of the photoresist in the half exposed area M2 is removed.
  • FIG. 14 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • the gate metal 2110 and the conductive film 2120 in the fully exposed area M3 are sequentially removed by an etching process. Since the gate metal 2110 and the conductive film 2120 have different materials, it needs to be carried out in two steps. Exemplarily, the aforementioned etching process may be a wet etching process. A gate metal etching solution is used when removing the gate metal 2110, and a conductive film etching solution is used when removing the conductive film 2120.
  • Step S5 sequentially removing the photoresist and the gate metal in the half-exposed area.
  • FIG. 15 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure. Referring to FIG. 15, first, the photoresist 2130 in the half-exposed area M2 is removed by a photoresist removal process.
  • FIG. 16 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure.
  • an etching process is used to remove the gate metal 2110 in the half-exposed area M2.
  • the aforementioned etching process may be a wet etching process, and a gate metal etching solution is used when removing the gate metal 2110.
  • Step S6 removing the photoresist in the unexposed area to obtain a conductive thin film sublayer and a gate metal sublayer.
  • FIG. 17 is a schematic diagram showing the manufacturing process of the array substrate according to an embodiment of the present disclosure. Referring to FIG. 17, a photoresist removal process is used to remove the photoresist 2130 in the unexposed area M1.
  • the array substrate can still be made by the 5Mask (mask) process.
  • the effect of improving the vertical stripes of the liquid crystal display can be achieved without adding a new mask, reducing the production cost of improving the vertical stripes problem, and reducing the process time, so that the design of the scheme can quickly realize productization and mass production.

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Abstract

一种阵列基板及其制作方法、显示装置，其中阵列基板为双栅线阵列基板，具有多个子像素（10），子像素（10）内布置有存储电容（C1）和扩展存储电容（C2），扩展存储电容（C2）和存储电容（C1）并联，通过增加一个与存储电容（C1）并联的扩展存储电容（C2），从而增加了存储电容容量，避免信号线之间的耦合电容在存储电容的容量不够大时，影响显示面板的显示，改善了显示均一性。

Description

阵列基板及其制作方法、显示装置
本公开要求于2020年4月10日提交的申请号为202010281302.6、发明名称为“阵列基板及其制作方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板及其制作方法、显示装置。
背景技术
在液晶显示器(Liquid Crystal Display，LCD)的显示面板，也即液晶显示面板中，存储电容负责在画面保持阶段给液晶电容充电，保证液晶电容的电压持续到下一次画面更新时。
液晶显示面板中相互靠近的信号线之间存在耦合电容，这些耦合电容会在存储电容的容量不够大时，影响显示面板的显示。特别是对于双栅线结构(Dual Gate)(即一行子像素与两根栅线连接)的液晶显示面板，由于同一根数据线连接的两列子像素的结构并非完全对称，例如信号线间距离不等，造成两列子像素中信号线间的寄生电容不等，所以与同一根数据线连接的两列子像素会出现亮暗不均的情况，例如LCD出现一列亮一列暗规律变化的竖向条纹。
发明内容
本公开实施例提供了一种阵列基板及其制作方法、显示装置，能够增加存储电容容量，改善显示均一性。所述技术方案如下：
一方面，提供了一种阵列基板，所述阵列基板具有多个子像素，所述子像素内布置有存储电容和扩展存储电容，所述扩展存储电容和所述存储电容并联；
所述阵列基板包括：栅极层、源漏极层和像素电极；
所述存储电容的第一电容极板位于所述像素电极所在的层，所述存储电容的第二电容极板位于所述栅极层和所述源漏极层中的至少一层中；
所述扩展存储电容的第一电容极板位于所述像素电极所在的层，所述存储 电容的第二电容极板位于所述栅极层和所述源漏极层中的至少一层中。
可选地，所述存储电容的第一电容极板为所述像素电极，所述存储电容的第二电容极板为所述源漏极层中的第一极；
所述扩展存储电容的第一电容极板为所述像素电极，所述扩展存储电容的第二电容极板位于所述源漏极层，且与所述源漏极层的第一极相连。
可选地，所述多个子像素按阵列排布，所述源漏极层具有多根沿列方向延伸的数据线；
两根相邻的所述数据线之间布置有同一行子像素中的两个子像素，所述两个子像素分别具有一个开口区域，所述两个子像素的扩展存储电容的第二电容极板在所述两个子像素的两个开口区域之间。
可选地，所述扩展存储电容的第二电容极板呈条状，两根相邻的所述数据线之间位于同一行子像素中的两个条状的所述第二电容极板的长度方向均沿列方向延伸，条状的所述第二电容极板的第一端均与对应的第一极相连，两个条状的所述第二电容极板在行方向上的正投影不重叠，所述行方向垂直于所述列方向。
可选地，所述存储电容的第一电容极板为所述像素电极，所述存储电容的第二电容极板为栅极层中的挡光图案；
所述扩展存储电容的第一电容极板与所述像素电极同层，且与所述像素电极相连，所述扩展存储电容的第二电容极板为所述栅极层中的挡光图案。
可选地，所述多个子像素按阵列排布，所述源漏极层具有多根沿列方向延伸的数据线；所述数据线的两侧分别布置有一列子像素；
在同一根所述数据线两侧的两列子像素中，位于同一行的两个所述子像素的栅极层分别具有第一挡光图案和第二挡光图案，位于同一行的两个所述子像素分别具有第一像素电极和第二像素电极，所述第一挡光图案和所述第一像素电极位于同一子像素中，所述第二挡光图案和所述第二像素电极位于同一子像素中；
所述第一挡光图案和所述第一像素电极靠近所述数据线的一侧边在衬底基板上的正投影重合，所述第二挡光图案和所述第二像素电极靠近所述数据线的一侧边在衬底基板上的正投影重合。
可选地，所述栅极层包括栅极金属子层和导电薄膜子层，所述栅极层具有U型的挡光图案；
所述存储电容的第一电容极板为所述像素电极，所述存储电容的第二电容极板为所述挡光图案；
所述扩展存储电容的第一电容极板为所述像素电极，所述扩展存储电容的第二电容极板位于所述导电薄膜子层，所述扩展存储电容的第二电容极板与所述挡光图案的U型开口处在衬底基板上的正投影至少部分重合，且所述扩展存储电容的第二电容极板与所述挡光图案电连接。
可选地，所述挡光图案由所述栅极金属子层和导电薄膜子层组成。
可选地，所述存储电容大小为0.12pF～0.15pF，所述扩展存储电容和所述存储电容并联后的电容大小为0.18pF～0.22pF。
一方面，提供了一种显示装置，所述显示装置包括如前所述的阵列基板。
一方面，提供了一种阵列基板的制作方法，所述阵列基板具有多个子像素，所述制作方法包括：
依次制作栅极层、源漏极层和像素电极，在所述子像素中形成存储电容和扩展存储电容，所述扩展存储电容和所述存储电容并联；
所述存储电容的第一电容极板位于所述像素电极所在的层，所述存储电容的第二电容极板位于所述栅极层和所述源漏极层中的至少一层中；所述扩展存储电容的第一电容极板位于所述像素电极所在的层，所述扩展存储电容的第二电容极板位于所述栅极层和所述源漏极层中的至少一层中。
可选地，依次制作栅极层、源漏极层和像素电极，包括：
在衬底基板上依次制作导电薄膜子层、栅极金属子层、栅极绝缘层、有源层、源漏极层、平坦化层和像素电极，所述栅极层包括栅极金属子层和导电薄膜子层，所述栅极层具有U型的挡光图案；
所述存储电容的第一电容极板为所述像素电极，所述存储电容的第二电容极板为所述挡光图案；
所述扩展存储电容的第一电容极板为所述像素电极，所述扩展存储电容的第二电容极板位于所述导电薄膜子层，所述扩展存储电容的第二电容极板与所述挡光图案的U型开口处在所述衬底基板上的正投影至少部分重合，且所述扩展存储电容的第二电容极板与所述挡光图案电连接。
可选地，在衬底基板上依次制作导电薄膜子层和栅极金属子层，包括：
在所述衬底基板上依次沉积导电薄膜和栅极金属；
在所述栅极金属上涂布一层光刻胶；
采用半色调掩膜板工艺对所述光刻胶进行曝光，其中，所述挡光图案对应区域为不曝光区域，所述挡光图案的U型开口处为半曝光区域；
依次除去全曝光区域的所述光刻胶、所述栅极金属和所述导电薄膜；
依次除去半曝光区域的所述光刻胶和所述栅极金属；
除去不曝光区域的所述光刻胶，得到所述导电薄膜子层和栅极金属子层。
本公开实施例提供的技术方案带来的有益效果是：
本方案通过增加一个与存储电容并联的扩展存储电容，从而增加了存储电容容量，避免显示基板中信号线之间的耦合电容在存储电容的容量不够大时，影响显示面板的显示，改善了显示均一性；解决了液晶显示器的竖向条纹问题，改善了液晶显示器的产品画面品质。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种阵列基板的电路示意图；
图2是本公开实施例提供的一种阵列基板的层级结构图；
图3是本公开实施例提供的一种阵列基板的结构示意图；
图4是本公开实施例提供的源漏极层的结构示意图；
图5所示为图3在数据线处A-A’的截面图；
图6是本公开实施例提供的一种阵列基板的结构示意图；
图7所示为图6在数据线处A-A’的截面图；
图8是本公开实施例提供的一种阵列基板的结构示意图；
图9是本公开实施例提供的一种阵列基板的制作方法流程图；
图10是本公开实施例示出阵列基板的制作过程示意图；
图11是本公开实施例示出阵列基板的制作过程示意图；
图12是本公开实施例示出阵列基板的制作过程示意图；
图13是本公开实施例示出阵列基板的制作过程示意图；
图14是本公开实施例示出阵列基板的制作过程示意图；
图15是本公开实施例示出阵列基板的制作过程示意图；
图16是本公开实施例示出阵列基板的制作过程示意图；
图17是本公开实施例示出阵列基板的制作过程示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
图1是本公开实施例提供的一种阵列基板的电路示意图。该阵列基板为双栅线阵列基板。如图1所示，阵列基板具有多个子像素10，在双栅线阵列基板中，这些子像素10分为多对，每对子像素10包括相邻的两个子像素10(通常为行方向上相邻的两个子像素10)。每对子像素10的两个子像素10连接同一根数据线12，且分别位于数据线12的两侧；每对子像素10对应两根栅线11，且每个子像素10分别连接其中一根栅线。在子像素10内布置有存储电容C1和扩展存储电容C2，扩展存储电容C2和存储电容C1并联。
如图1所示，在子像素10中形成有薄膜晶体管T和液晶电容C，在画面保持阶段，存储电容C1和扩展存储电容C2均可以给液晶电容C充电，保证液晶电容C的电压持续到下一次画面更新时。
相关技术中，由于存储电容设计不足，加上显示面板中相互靠近的信号线之间存在耦合电容的作用，导致同一根数据线左右侧子像素呈现亮暗的差异，宏观上表现为一列亮一列暗规律变化的竖向条纹。本方案通过增加一个与存储电容并联的扩展存储电容，从而增加了整体的存储电容容量，改善了显示基板中信号线之间的耦合电容在存储电容的容量不够大时，出现的竖向条纹，提高了显示均一性。
在本公开实施例中，存储电容C1的大小可以为0.12pF～0.15pF，扩展存储电容C2和存储电容C1并联后的电容大小可以为0.18pF～0.22pF。通过并联扩展存储电容C2和存储电容C1增大电容容量，从而保证显示均一性。
示例性地，存储电容C1的大小可以为0.14pF，扩展存储电容C2和存储电容C1并联后的电容大小可以为0.18pF。
本公开实施例提供的阵列基板可以为扭曲向列型(Twisted Nematic，TN)液晶显示器的显示基板；该阵列基板也可以为高级超维场转换型(Advanced  Super Dimension Switch，ADS)、面内转换型(In Plane Switching，IPS)等液晶显示器的显示基板。
在本公开实施例中，子像素10中扩展存储电容C2的数量可以为1至3个。
也就是说，在一个子像素10中可以采用一个或多个扩展存储电容C2与存储电容C1并联，从而实现存储电容容量的增大。
下面结合附图对扩展存储电容C2的结构进行详细说明，在此之前先介绍下阵列基板的膜层结构，以便更好地说明扩展存储电容的结构。
图2是本公开实施例提供的一种阵列基板的层级结构图。参见图2，该阵列基板包括：衬底基板20、依次层叠设置在衬底基板20上的栅极层21、栅极绝缘层22、有源层23、源漏极层24、平坦化层25(或保护层PVX)和像素电极26。其中，源漏极层24包括数据线、源极和漏极，其中，漏极和数据线连接，源极通过过孔和像素电极26连接。这里的连接可以是电连接。
其中，衬底基板20可以为玻璃基板。栅极层21和源漏极层24可以为金属层或氧化铟锡层。栅极绝缘层22可以为氧化硅、氮化硅、氮氧化硅中的一种形成的绝缘层，或者其中至少两种形成的叠层。有源层23可以为多晶硅层或非晶硅层。平坦化层25可以为树脂层，平坦化层也可以为氧化硅、氮化硅、氮氧化硅中的一种形成的平坦化层，或者其中至少两种形成的叠层。像素电极26可以为氧化铟锡电极。
图2所示仅为阵列基板在薄膜晶体管处结构的一种实现方式中，在其他实现方式中，阵列基板也可以为其他结构，只要能够实现阵列基板的功能即可，例如，图2所示为底栅结构，在其他实现方式中，阵列基板也可以为顶栅结构等。
在本公开实施例中，存储电容C1的第一电容极板位于前述像素电极26所在的层，存储电容C1的第二电容极板可以位于栅极层21和源漏极层24中的至少一层中。扩展存储电容C2的第一电容极板位于像素电极26所在的层，存储电容C1的第二电容极板可以位于栅极层21和源漏极层24中的至少一层中。
示例性地，像素电极26可以和栅极层21中的挡光图案形成前述存储电容C1。或者，像素电极26可以和源漏极层24的一个电极形成前述存储电容C1。或者，像素电极26可以同时和栅极层21中的挡光图案以及源漏极层24的一个电极分别形成前述存储电容C1。
图3是本公开实施例提供的一种阵列基板的部分结构示意图。图3中仅示 出了栅极层21、有源层23、源漏极层24和像素电极26，未示出衬底基板20、栅极绝缘层22和平坦化层25。源漏极层24包括数据线12、第一极241和第二极242。其中，第一极241为源极和漏极中的一个，第二极242为源极和漏极中的另一个。示例性地，第一极241为源极，第二极242为漏极。
图4进一步示出了源漏极层的结构，如图3和4所示，存储电容C1的第二电容极板为源漏极层24中的第一极241，具体是图4中标号M对应的虚线框中的部分。扩展存储电容C2的第一电容极板为像素电极26，扩展存储电容C2的第二电容极板C20位于源漏极层24，且与源漏极层24的源极相连，也即图4中标号N对应的虚线框中的长条形部分。
这里，由于扩展存储电容的第二电容极板C20位于源漏极层24，因此可以和源极电连接。
在该实现方式中，增加与源漏极层24的源极相连的扩展存储电容C2的第二电容极板C20，与像素电极26形成扩展存储电容C2，相当于增大源漏极层中源极面积来扩大和像素电极的交叠，从而增大了存储电容。
在本公开实施例中，多个子像素10按阵列排布，图3仅示出了一行中的四个子像素10。源漏极层24具有多根沿列方向b延伸的数据线12。
如图3所示，两根相邻的数据线12之间布置有同一行子像素10中的两个子像素10，两个子像素10分别具有一个开口区域13，两个子像素10的扩展存储电容C2的第二电容极板C20在两个子像素10的两个开口区域13之间。
图3中开口区域13由栅极层21中的挡光图案(Shield Bar，SB)210围成，如图3所示该挡光图案210为一口字型，口字型中部镂空区域对应的即为开口区域13。
从图3可以看出，两根数据线12之间的两个子像素10的挡光图案210是完全连在一起的一体结构；而位于一根数据线12两侧的两个子像素10的挡光图案210，是通过两个连接部连接在一起，减小了数据线12与挡光图案210的交叠面积，该连接部即为图3中标号P对应的椭圆虚线框中的部分。
在其他实施例中，挡光图案210还可以为其他可以限定出开口区域13的图案，例如U字型等。在本公开实施例中，挡光图案210一方面可以复用为存储电容的极板，也即公共(COM)电极；另一方面，与彩膜基板上的黑矩阵一起起到挡光作用。
将扩展存储电容C2的第二电容极板C20设置在两个子像素10的开口区域 13之间，一方面，由于像素电极26可以覆盖两个开口区域13之间，因此这样设置扩展存储电容C2可以保证与像素电极26的交叠，另一方面，这样设置扩展存储电容C2不会占用开口区域13，不影响显示面板的开口率。
如图3和图4所示，扩展存储电容C2的第二电容极板C20可以呈条状，两根相邻的数据线12之间位于同一行子像素10中的两个条状的第二电容极板C20的长度方向均沿列方向b延伸，条状的第二电容极板C20的第一端均与对应的第一极241相连，两个条状的第二电容极板C20在行方向上的正投影不重叠，行方向垂直于列方向b，也即图中的方向a。
由于两个条状的第二电容极板C20在行方向上的正投影不重叠，因此两个条状的第二电容极板C20间的最小距离为两个条状的第二电容极板C20的第二端之间的距离。两个条状的第二电容极板C20的第二端之间的距离大于阈值，例如该阈值可以为两个条状的第二电容极板C20在行方向b上的间距，当然这也仅是一种示例，该阈值可以根据实际情况设置，要保证两个条状的第二电容极板C20间干扰足够小。
采用条状的第二电容极板C20，以及按照上述方式设置第二电容极板C20，可以保证两个子像素10中的第二电容极板C20间有足够距离，避免两个扩展存储电容C2的第二电容极板C20距离过近影响电容性能。
示例性地，扩展存储电容C2的第二电容极板C20在衬底基板上的正投影位于像素电极26在衬底基板上的正投影内。由于相邻子像素的像素电极26间存在一定距离，这样设计第二电容极板C20也可以避免第二电容极板C20在行方向上的宽度过大，保证相邻子像素的第二电容极板C20在行方向上的间距，避免相互干扰。另外，扩展存储电容C2的第二电容极板C20在衬底基板上的正投影与开口区域13在衬底基板上的正投影不重叠。
例如，扩展存储电容C2的第二电容极板C20的两个侧边在衬底基板上的正投影，分别与开口区域13的边缘以及像素电极26的边缘在衬底基板上的正投影重合，从而保证第二电容极板C20的面积尽量大。
图5所示为图3在数据线处A-A’的截面图。参见图5，在数据线12两侧，像素电极26靠近数据线12的一侧边和挡光图案210靠近数据线12的一侧边并不对齐，也即像素电极26靠近数据线12的一侧边和挡光图案210靠近数据线12的一侧在衬底基板20上的正投影并不重合，挡光图案210靠近数据线12的一侧离数据线12比像素电极26更近。
在本公开实施例的一种实现方式中，存储电容C1的第二电容极板为栅极层21中的挡光图案210；
扩展存储电容C2的第一电容极板与像素电极26同层，且与像素电极26连接，扩展存储电容C2的第二电容极板C20为栅极层21中的挡光图案210。同层可以是指在一次构图工艺中形成，或者可以是指位于同一层的同一侧，或者可以是指靠近衬底基板的表面均与同一层接触等。
在该实现方式中，增加与像素电极26相连的扩展存储电容C2的第二电容极板C20，与栅极层21中的挡光图案210形成扩展存储电容C2，相当于增大像素电极26面积来扩大和挡光图案210的交叠面积，从而增大了存储电容。
如前所述，本公开实施例提供的阵列基板为双栅结构的阵列基板，也即数据线12的两侧分别布置有一列子像素10。
图6是本公开实施例提供的一种阵列基板的结构示意图。图6相比于图3，区别在于，没有在源漏极层设置图3中的第二电容极板C20；在数据线12两侧，像素电极26靠近数据线12的一侧边和挡光图案210靠近数据线12的一侧边对齐，也即像素电极26靠近数据线12的一侧边和挡光图案210靠近数据线12的一侧在衬底基板20上的正投影重合。
图7所示为图6在数据线处A-A’的截面图。参见图7，在同一根数据线12两侧的两列子像素中，位于同一行的两个子像素的栅极层分别具有第一挡光图案210A和第二挡光图案210B，位于同一行的两个子像素分别具有第一像素电极261和第二像素电极262，第一挡光图案210A和第一像素电极261位于同一子像素10中，第二挡光图案210B和第二像素电极262位于同一子像素10中；
第一挡光图案210A和第一像素电极261靠近数据线12的一侧边在衬底基板上的正投影重合，第二挡光图案210B和第二像素电极262靠近数据线12的一侧边在衬底基板上的正投影重合。
图7中的第一像素电极261和第二像素电极262相比于图5中多出的部分，即为前述扩展存储电容C2的第一电容极板。
图8是本公开实施例提供的一种阵列基板的结构示意图。图8相比于图3，区别在于，没有在源漏极层设置图3中的第二电容极板C20；栅极层21包括栅极金属子层211和导电薄膜子层212。示例性地，该导电薄膜子层212位于衬底基板和栅极金属子层211之间。栅极层21具有U型的挡光图案210。
存储电容C1的第二电容极板为挡光图案210；扩展存储电容C2的第一电 容极板为像素电极26，扩展存储电容C2的第二电容极板C20位于导电薄膜子层212，扩展存储电容C2的第二电容极板C20与挡光图案210的U型开口处在衬底基板上的正投影至少部分重合，且扩展存储电容C2的第二电容极板C20与挡光图案210电连接。
在该实现方式中，通过新增导电薄膜子层212和像素电极的交叠形成扩展存储电容，从而增大存储电容。这里，采用导电薄膜子层212和像素电极形成电容的优点是，导电薄膜子层212和栅极层中栅线11距离比挡光图案210和栅线11距离大，导电薄膜子层212和栅线11的寄生电容比挡光图案210和栅线11的寄生电容小，因此导电薄膜子层212和像素电极26形成的电容更稳定。
其中，导电薄膜子层212可以为氧化铟锡层。
在本公开实施例中，扩展存储电容可以采用前述任一实施例实现，也可以采用两种或多种实施例的组合实现，也即同时设计两个或多个扩展存储电容，同时与存储电容并联。
例如，扩展存储电容包括第一扩展存储电容和第二扩展存储电容。第一扩展存储电容的第一电容极板为像素电极26，第一扩展存储电容的第二电容极板C20位于源漏极层24，且与源漏极层24的第一极241相连(即图3所示的方案)；第二扩展存储电容的第一电容极板与像素电极26同层，且与像素电极26相连，第二扩展存储电容的第二电容极板为栅极层21中的挡光图案210(即图6所示的方案)。
例如，扩展存储电容包括第一扩展存储电容和第三扩展存储电容。第一扩展存储电容的第一电容极板为像素电极26，第一扩展存储电容的第二电容极板位于源漏极层24，且与源漏极层24的第一极241相连(即图3所示的方案)；第三扩展存储电容的第一电容极板为像素电极26，第三扩展存储电容的第二电容极板位于导电薄膜子层212，第三扩展存储电容的第二电容极板与挡光图案210的U型开口处在衬底基板20上的正投影至少部分重合，且第三扩展存储电容的第二电容极板与挡光图案210电连接(即图8所示的方案)。
例如，扩展存储电容包括第二扩展存储电容和第三扩展存储电容。第二扩展存储电容的第一电容极板与像素电极26同层，且与像素电极26相连，第二扩展存储电容的第二电容极板为栅极层21中的挡光图案210(即图6所示的方案)；第三扩展存储电容的第一电容极板为像素电极26，第三扩展存储电容的第二电容极板位于导电薄膜子层212，第三扩展存储电容的第二电容极板与挡光图 案210的U型开口处在衬底基板20上的正投影至少部分重合，且第三扩展存储电容的第二电容极板与挡光图案210电连接(即图8所示的方案)。
例如，扩展存储电容包括第一扩展存储电容、第二扩展存储电容和第三扩展存储电容。第一扩展存储电容的第一电容极板为像素电极26，第一扩展存储电容的第二电容极板C20位于源漏极层24，且与源漏极层24的第一极241相连(即图3所示的方案)；第二扩展存储电容的第一电容极板与像素电极26同层，且与像素电极26相连，第二扩展存储电容的第二电容极板为栅极层21中的挡光图案210(即图6所示的方案)；第三扩展存储电容的第一电容极板为像素电极26，第三扩展存储电容的第二电容极板位于导电薄膜子层212，第三扩展存储电容的第二电容极板与挡光图案210的U型开口处在衬底基板20上的正投影至少部分重合，且第三扩展存储电容的第二电容极板与挡光图案210电连接(即图8所示的方案)。
本公开提供了一种显示装置，显示装置包括如前任一实施例所述的阵列基板。
在具体实施时，本公开实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本方案通过增加一个与存储电容并联的扩展存储电容，从而增加了存储电容容量，避免显示基板中信号线之间的耦合电容在存储电容的容量不够大时，影响显示面板的显示，改善了显示均一性。
本公开实施例还提供了一种阵列基板的制作方法，用于制作前述任一实施例所述的阵列基板，该制作方法包括：在子像素中制作存储电容和扩展存储电容，扩展存储电容和存储电容并联。
本方案通过增加一个与存储电容并联的扩展存储电容，从而增加了存储电容容量，避免显示基板中信号线之间的耦合电容在存储电容的容量不够大时，影响显示面板的显示，改善了显示均一性。
图9是本公开实施例提供的一种阵列基板的制作方法流程图。参见图9，该方法包括：
步骤801：提供一衬底基板。
其中，衬底基板可以为玻璃基板。
步骤802：在衬底基板上依次制作栅极层、栅极绝缘层、有源层、源漏极层、平坦化层和像素电极。
存储电容的第一电容极板位于像素电极所在的层，存储电容的第二电容极板位于栅极层和源漏极层中的至少一层中。扩展存储电容的第一电容极板位于像素电极所在的层，扩展存储电容的第二电容极板位于栅极层和源漏极层中的至少一层中。
其中，栅极层和源漏极层可以为金属层或氧化铟锡层。栅极绝缘层可以为氧化硅、氮化硅、氮氧化硅中的一种形成的绝缘层，或者其中至少两种形成的叠层。有源层可以为多晶硅层或非晶硅层。平坦化层可以为树脂层，平坦化层也可以为氧化硅、氮化硅、氮氧化硅中的一种形成的平坦化层，或者其中至少两种形成的叠层。像素电极可以为氧化铟锡电极。
在本公开实施例的一种实现方式中，存储电容的第一电容极板为像素电极，存储电容的第二电容极板为源漏极层中的第一极；
扩展存储电容的第一电容极板为像素电极，扩展存储电容的第二电容极板位于源漏极层，且与源漏极层的第一极相连。
示例性地，步骤802可以包括：在衬底基板上形成栅极层；在栅极层上形成栅极绝缘层和有源层；在有源层上形成源漏极层，源漏极层包括源极、漏极、数据线以及扩展存储电容的第二电容极板；在源漏极层上形成平坦化层和用于连接源极和像素电极的过孔；在平坦化层上形成像素电极。
在该实现方式中，阵列基板可以采用5Mask(掩膜板)工艺制成。
在本公开实施例的另一种实现方式中，存储电容的第一电容极板为像素电极，存储电容的第二电容极板为栅极层中的挡光图案；
扩展存储电容的第一电容极板与像素电极同层，且与像素电极连接，第二电容极板为栅极层中的挡光图案。
示例性地，步骤802可以包括：在衬底基板上形成栅极层；在栅极层上形成栅极绝缘层和有源层；在有源层上形成源漏极层；在源漏极层上形成平坦化层和用于连接源极和像素电极的过孔；在平坦化层上形成像素电极和扩展存储电容的第一电容极板。
在该实现方式中，阵列基板可以采用5Mask(掩膜板)工艺制成。
在本公开实施例的又一种实现方式中，栅极层包括栅极金属子层和导电薄膜子层，栅极层具有U型的挡光图案；
存储电容的第一电容极板为像素电极，存储电容的第二电容极板为挡光图案；
扩展存储电容的第一电容极板为像素电极，扩展存储电容的第二电容极板位于导电薄膜子层，扩展存储电容的第二电容极板与挡光图案的U型开口处在衬底基板上的正投影至少部分重合，且扩展存储电容的第二电容极板与挡光图案电连接。
下面结合附图对该实现方式进行详细说明。在衬底基板上依次制作导电薄膜子层和栅极金属子层，可以包括：
步骤S1、在衬底基板上依次沉积导电薄膜和栅极金属。
图10是本公开实施例示出阵列基板的制作过程示意图。参见图10，在衬底基板20上依次沉积导电薄膜2120和栅极金属2110。
步骤S2、在栅极金属上涂布一层光刻胶。
图11是本公开实施例示出阵列基板的制作过程示意图。参见图11，在栅极金属2110涂布一层光刻胶2130，该光刻胶可以为正性光刻胶，也可以为负性光刻胶。
步骤S3、采用半色调掩膜板工艺对光刻胶进行曝光，其中，挡光图案对应区域为不曝光区域，挡光图案的U型开口处为半曝光区域，开口区域以及栅线和挡光图案之间的区域为全曝光区域。
图12是本公开实施例示出阵列基板的制作过程示意图。参见图12，采用半色调掩膜板(Halftone Mask，HTM)工艺对光刻胶2130进行曝光，曝光后的显示基板分为3个区域，不曝光区域M1、半曝光区域M2和全曝光区域M3。
步骤S4、依次除去全曝光区域的光刻胶、栅极金属和导电薄膜。
图13是本公开实施例示出阵列基板的制作过程示意图。参见图13，先采用光刻胶去除工艺去掉全曝光区域M3的光刻胶2130，此时半曝光区域M2中光刻胶部分厚度被除去。
图14是本公开实施例示出阵列基板的制作过程示意图。参见图14，采用刻蚀工艺依次去掉全曝光区域M3的栅极金属2110和导电薄膜2120。由于栅极金属2110和导电薄膜2120材料不同，因此需要分2步进行。示例性地，前述刻蚀工艺可以为湿刻工艺，去掉栅极金属2110时使用栅极金属刻蚀液，去掉导电 薄膜2120时使用导电薄膜刻蚀液。
步骤S5、依次除去半曝光区域的光刻胶和栅极金属。
图15是本公开实施例示出阵列基板的制作过程示意图。参见图15，先采用光刻胶去除工艺去掉半曝光区域M2的光刻胶2130。
图16是本公开实施例示出阵列基板的制作过程示意图。参见图16，采用刻蚀工艺去掉半曝光区域M2的栅极金属2110。示例性地，前述刻蚀工艺可以为湿刻工艺，去掉栅极金属2110时使用栅极金属刻蚀液。
步骤S6、除去不曝光区域的光刻胶，得到导电薄膜子层和栅极金属子层。
图17是本公开实施例示出阵列基板的制作过程示意图。参见图17，采用光刻胶去除工艺去掉不曝光区域M1的光刻胶2130。
可以看出，虽然增加了导电薄膜子层，但导电薄膜子层和栅极金属子层采用同一个掩膜板制作完成，因此，该阵列基板仍然可以采用5Mask(掩膜板)工艺制成，无需新增掩膜板即可达到改善液晶显示器竖向条纹的效果，降低了改善竖向条纹问题的生产成本，减少了工艺时间，使得该方案设计能很快实现产品化并批量生产。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (13)

  1. 一种阵列基板，其特征在于，所述阵列基板具有多个子像素(10)，所述子像素(10)内布置有存储电容(C1)和扩展存储电容(C2)，所述扩展存储电容(C2)和所述存储电容(C1)并联；
    所述阵列基板包括：栅极层(21)、源漏极层(24)和像素电极(26)；
    所述存储电容(C1)的第一电容极板位于所述像素电极(26)所在的层，所述存储电容(C1)的第二电容极板位于所述栅极层(21)和所述源漏极层(24)中的至少一层中；
    所述扩展存储电容(C2)的第一电容极板位于所述像素电极(26)所在的层，所述存储电容(C1)的第二电容极板位于所述栅极层(21)和所述源漏极层(24)中的至少一层中。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述存储电容(C1)的第一电容极板为所述像素电极(26)，所述存储电容(C1)的第二电容极板为所述源漏极层(24)中的第一极(241)；
    所述扩展存储电容(C2)的第一电容极板为所述像素电极(26)，所述扩展存储电容(C2)的第二电容极板(C20)位于所述源漏极层(24)，且与所述源漏极层(24)的第一极(241)相连。
  3. 根据权利要求2所述的阵列基板，其特征在于，所述多个子像素(10)按阵列排布，所述源漏极层(24)具有多根沿列方向延伸的数据线(12)；
    两根相邻的所述数据线(12)之间布置有同一行子像素(10)中的两个子像素(10)，所述两个子像素(10)分别具有一个开口区域(13)，所述两个子像素(10)的扩展存储电容(C2)的第二电容极板(C20)在所述两个子像素(10)的两个开口区域(13)之间。
  4. 根据权利要求3所述的阵列基板，其特征在于，所述扩展存储电容(C2)的第二电容极板(C20)呈条状，两根相邻的所述数据线(12)之间位于同一行子像素(10)中的两个条状的所述第二电容极板(C20)的长度方向均沿列方向延伸，条状的所述第二电容极板(C20)的第一端分别与对应的第一极(241)相连，两个条状的所述第二电容极板(C20)在行方向上的正投影不重叠，所述行方向垂直于所述列方向。
  5. 根据权利要求1所述的阵列基板，其特征在于，所述存储电容(C1)的第 一电容极板为所述像素电极(26)，所述存储电容(C1)的第二电容极板为栅极层(21)中的挡光图案(210)；
    所述扩展存储电容(C2)的第一电容极板与所述像素电极(26)同层，且与所述像素电极(26)相连，所述扩展存储电容(C2)的第二电容极板(C20)为所述栅极层(21)中的挡光图案(210)。
  6. 根据权利要求5所述的阵列基板，其特征在于，所述多个子像素(10)按阵列排布，所述源漏极层(24)具有多根沿列方向延伸的数据线(12)；所述数据线(12)的两侧分别布置有一列子像素(10)；
    在同一根所述数据线(12)两侧的两列子像素(10)中，位于同一行的两个所述子像素(10)的栅极层(21)分别具有第一挡光图案(210A)和第二挡光图案(210B)，位于同一行的两个所述子像素(10)分别具有第一像素电极(261)和第二像素电极(262)，所述第一挡光图案(210A)和所述第一像素电极(261)位于同一子像素(10)中，所述第二挡光图案(210B)和所述第二像素电极(262)位于同一子像素(10)中；
    所述第一挡光图案(210A)和所述第一像素电极(261)靠近所述数据线(12)的一侧边在衬底基板(20)上的正投影重合，所述第二挡光图案(210B)和所述第二像素电极(262)靠近所述数据线(12)的一侧边在衬底基板(20)上的正投影重合。
  7. 根据权利要求1所述的阵列基板，其特征在于，所述栅极层(21)包括栅极金属子层(211)和导电薄膜子层(212)，所述栅极层(21)具有U型的挡光图案(210)；
    所述存储电容(C1)的第一电容极板为所述像素电极(26)，所述存储电容(C1)的第二电容极板为所述挡光图案(210)；
    所述扩展存储电容(C2)的第一电容极板为所述像素电极(26)，所述扩展存储电容(C2)的第二电容极板(C20)位于所述导电薄膜子层(212)，所述扩展存储电容(C2)的第二电容极板(C20)与所述挡光图案(210)的U型开口处在衬底基板(20)上的正投影至少部分重合，且所述扩展存储电容(C2)的第二电容极板(C20)与所述挡光图案(210)电连接。
  8. 根据权利要求7所述的阵列基板，其特征在于，所述挡光图案(210)由所述栅极金属子层(211)和导电薄膜子层(212)组成。
  9. 根据权利要求1至8任一项所述的阵列基板，其特征在于，所述存储电容(C1)大小为0.12pF～0.15pF，所述扩展存储电容(C2)和所述存储电容(C1)并联后的电容大小为0.18pF～0.22pF。
  10. 一种显示装置，其特征在于，所述显示装置包括如权利要求1至9任一项所述的阵列基板。
  11. 一种阵列基板的制作方法，其特征在于，所述阵列基板具有多个子像素，所述制作方法包括：
    依次制作栅极层、源漏极层和像素电极，在所述子像素中形成存储电容和扩展存储电容，所述扩展存储电容和所述存储电容并联；
    所述存储电容的第一电容极板位于所述像素电极所在的层，所述存储电容的第二电容极板位于所述栅极层和所述源漏极层中的至少一层中；所述扩展存储电容的第一电容极板位于所述像素电极所在的层，所述扩展存储电容的第二电容极板位于所述栅极层和所述源漏极层中的至少一层中。
  12. 根据权利要求11所述的制作方法，其特征在于，依次制作栅极层、源漏极层和像素电极，包括：
    在衬底基板上依次制作导电薄膜子层、栅极金属子层、栅极绝缘层、有源层、源漏极层、平坦化层和像素电极，所述栅极层包括栅极金属子层和导电薄膜子层，所述栅极层具有U型的挡光图案；
    所述存储电容的第一电容极板为所述像素电极，所述存储电容的第二电容极板为所述挡光图案；
    所述扩展存储电容的第一电容极板为所述像素电极，所述扩展存储电容的第二电容极板位于所述导电薄膜子层，所述扩展存储电容的第二电容极板与所述挡光图案的U型开口处在所述衬底基板上的正投影至少部分重合，且所述扩展存储电容的第二电容极板与所述挡光图案电连接。
  13. 根据权利要求12所述的制作方法，其特征在于，在衬底基板上依次制作导电薄膜子层和栅极金属子层，包括：
    在所述衬底基板上依次沉积导电薄膜和栅极金属；
    在所述栅极金属上涂布一层光刻胶；
    采用半色调掩膜板工艺对所述光刻胶进行曝光，其中，所述挡光图案对应区域为不曝光区域，所述挡光图案的U型开口处为半曝光区域；
    依次除去全曝光区域的所述光刻胶、所述栅极金属和所述导电薄膜；
    依次除去半曝光区域的所述光刻胶和所述栅极金属；
    除去不曝光区域的所述光刻胶，得到所述导电薄膜子层和栅极金属子层。
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CN111338142B (zh) 2020-04-10 2022-09-06 成都京东方光电科技有限公司 阵列基板及其制作方法、显示装置
WO2022011582A1 (zh) * 2020-07-15 2022-01-20 京东方科技集团股份有限公司 显示基板、显示面板和显示装置
CN112599010B (zh) * 2020-12-15 2022-08-09 昆山国显光电有限公司 显示面板和显示装置
CN114236924A (zh) * 2021-12-14 2022-03-25 Tcl华星光电技术有限公司 显示面板及移动终端
CN114660864B (zh) * 2022-03-22 2023-10-13 Tcl华星光电技术有限公司 像素结构及显示面板

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100675626B1 (ko) * 2002-08-22 2007-02-01 엘지.필립스 엘시디 주식회사 액정표시소자
TW583464B (en) * 2002-11-12 2004-04-11 Hannstar Display Corp Liquid crystal display
KR101086477B1 (ko) * 2004-05-27 2011-11-25 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 제조 방법
KR20060059481A (ko) 2004-11-29 2006-06-02 삼성전자주식회사 개구율이 향상된 어레이 기판, 이의 제조방법 및 이를포함한 액정 표시 장치
KR101096718B1 (ko) * 2004-12-24 2011-12-22 엘지디스플레이 주식회사 수평 전계 박막 트랜지스터 기판의 제조 방법
TWI393977B (zh) * 2009-06-24 2013-04-21 Chunghwa Picture Tubes Ltd 畫素組
US8665192B2 (en) 2009-07-08 2014-03-04 Hitachi Displays, Ltd. Liquid crystal display device
KR20120012741A (ko) * 2010-08-03 2012-02-10 엘지디스플레이 주식회사 액정표시장치
KR101820032B1 (ko) * 2010-09-30 2018-01-19 삼성디스플레이 주식회사 박막 트랜지스터 기판, 액정 표시 장치 및 이들의 리페어 방법
CN202332850U (zh) * 2011-11-04 2012-07-11 京东方科技集团股份有限公司 一种tft阵列基板及显示器件
CN104503164B (zh) 2014-12-23 2017-12-22 上海天马微电子有限公司 一种阵列基板及其制作方法、显示装置
CN105093740B (zh) * 2015-08-04 2018-07-17 深圳市华星光电技术有限公司 阵列基板、液晶显示面板及其液晶显示装置
CN106125436B (zh) * 2016-08-31 2019-09-20 京东方科技集团股份有限公司 一种阵列基板、显示面板及制作方法
CN111338142B (zh) 2020-04-10 2022-09-06 成都京东方光电科技有限公司 阵列基板及其制作方法、显示装置

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