WO2021196574A1 - 用于优化芯片静电泄放能力的管脚环的自动布局方法 - Google Patents

用于优化芯片静电泄放能力的管脚环的自动布局方法 Download PDF

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WO2021196574A1
WO2021196574A1 PCT/CN2020/123587 CN2020123587W WO2021196574A1 WO 2021196574 A1 WO2021196574 A1 WO 2021196574A1 CN 2020123587 W CN2020123587 W CN 2020123587W WO 2021196574 A1 WO2021196574 A1 WO 2021196574A1
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lead module
module
power lead
pad
boundary
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PCT/CN2020/123587
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English (en)
French (fr)
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赵少峰
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安徽省东科半导体有限公司
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Priority to JP2021569339A priority Critical patent/JP7229593B2/ja
Priority to US17/595,632 priority patent/US20230205962A1/en
Publication of WO2021196574A1 publication Critical patent/WO2021196574A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Definitions

  • the invention relates to the field of microelectronics technology, and in particular to an automatic layout method of a pin ring for optimizing the electrostatic discharge capability of a chip.
  • layout is a design step that determines the location of core units, macro modules and other circuit components on the layout plane. By assigning physical locations to units, macro modules, etc. on the layout, the units, macro modules, and other components do not overlap each other. The allocation needs to optimize the cost function according to the specific constraints given by the user. After layout, the exact locations of the cells and pins have been determined, and the required interconnections have also been determined. The layouts usually discussed are focused on the layout of the chip core. For chip design, another critical layout step is to lay out the PAD ring.
  • Electrostatic Discharge should be the main culprit that causes excessive electrical stress (EOS) damage to all electronic components or integrated circuit systems. Because static electricity usually has a very high instantaneous voltage (>several thousand volts), this kind of damage is devastating and permanent, and will cause the circuit to burn directly. Therefore, preventing electrostatic damage is the number one problem in all chip design and manufacturing.
  • the discharge of ESD is also an important task of the pin ring (PAD ring).
  • the modules of the electrostatic discharge path are all next to the signal lead module Signal PAD, and cannot be inside the chip, because the external static electricity needs to be discharged in the first time.
  • the automatic layout method of the pin ring (PAD ring) commonly used in the industry is a completely random layout under the constraint conditions, such as the layout in the order of module names. This leads to the fact that automatic layout cannot meet the needs of chip designers at all. Needless to say, how to automatically select a PAD ring layout solution with a stronger ESD discharge capability. More experienced chip designers often abandon automatic layout and adopt manual layout to make the layout of the pin ring (PAD ring) meet the design requirements, and on this basis, optimize the design by manually adjusting the layout.
  • the purpose of the present invention is to provide an automatic layout method of pin ring for optimizing the electrostatic discharge capacity of the chip in view of the defects of the prior art.
  • an embodiment of the present invention provides an automatic layout method for pin rings for optimizing the electrostatic discharge capability of a chip, including:
  • the location information of the core includes the boundary location coordinates of the core
  • the position information of the pin ring of the chip is determined; the pin ring has four boundaries; the position information of the pin ring includes: Position coordinates and width information of each boundary;
  • the power lead module type includes the first power lead The module group and the second power lead module group;
  • the first power lead module group includes a first level lead module Vss PAD and a second level lead module Vdd Pad;
  • the second power lead module group includes a first level Input and output lead module Vss IO PAD and second level input and output lead module Vdd IO Pad;
  • the power lead module group consists of four groups of lead modules to be laid out; the four groups of lead modules to be laid out have a one-to-one correspondence with the four boundaries;
  • the first automatic layout includes: selecting the boundary vertex according to the boundary position coordinates of the pin ring, and determining that the position coordinates of the selected boundary vertex are the position coordinates of the boundary Layout start point coordinates; call the first subroutine, use the start point coordinates as the starting point, call and insert a border module corner cell by the process library, and record the end position coordinates of the border module; according to the end position of the border module
  • the coordinates and the lead module to be laid out corresponding to the boundary are sequentially polled and called the second subroutine and the third subroutine, so that the required Signal PAD, the first power lead module group and/or the required signal PAD, the first power lead module group and/or The second power lead module group, and record the end position coordinates after each insertion; wherein the second subroutine is used to insert the Signal PAD, and the third subroutine is used to insert the first power lead module group and/or the first power lead module group.
  • the boundary vertices of an adjacent boundary and the module size of the boundary module calculate the size of the remaining gap for each boundary after the first automatic layout is executed, and according to the size of the remaining gap Performing a second automatic layout to optimize the electrostatic discharge capability of the chip;
  • the second automatic layout specifically includes:
  • the third subroutine is called in the Insert a first level lead module Vss PAD in the remaining gap.
  • the method further includes:
  • the boundary vertices of an adjacent boundary, and the module size of the boundary module calculate the size of the secondary remaining gap for each boundary after the second automatic layout is executed, and A fourth subroutine is called according to the size of the secondary residual gap, and one or more filler cells are called by the process library through the fourth subroutine to fill the secondary residual gap.
  • the type and quantity of the signal lead module Signal PAD of the chip are specifically determined as follows:
  • the package constraint information extract the required signal lead module Signal PAD type from the selected process library, and determine the number of Signal PAD corresponding to each signal lead module; different types of signal lead modules Signal PAD have their own horizontal size.
  • the combination of the designed total power consumption data and the type and quantity of the signal lead module Signal PAD to determine the type of power lead module and the basic required quantity corresponding to each group of power lead module types are specifically:
  • the type of the power lead module Preferably, based on the type and quantity of the Signal PAD, the type of the power lead module, the number of basic requirements corresponding to each group of power lead module types, and the package constraint information, the Signal PAD, the first power source
  • the lead module group and the second power lead module group are four groups of lead modules to be laid out specifically including:
  • the placement rule parameter includes the maximum distance between the Signal PAD and the first-level lead module Vss PAD with the largest electrostatic discharge capability
  • each of the Signal PAD, the first power lead module group and the second power lead module group are allocated to a group of leads to be laid out according to the principle of even distribution Module, and determine the sort position information in the group.
  • the method further includes: outputting a layout error warning prompt message.
  • the present invention provides an automatic layout method of pin ring for optimizing the electrostatic discharge capability of a chip to design total power consumption data, area constraint information, packaging constraint information, core position information and chip design selection process library Based on the information, locate the position of the filling ring, determine the signal PAD type and the required quantity of the signal lead module arranged in the filling ring, and the type of power lead module and the basic required quantity corresponding to each group of power lead module type, and the filling ring Perform the first automatic layout for each boundary of, to automatically insert the boundary modules Corner Cell, Signal PAD, and power lead module, and then prioritize the remaining gaps according to the first level lead module Vss PAD with the strongest electrostatic discharge capability The principle of inserting is performed, and finally, random automatic layout is performed on the remaining gaps that are not enough to insert Vss PAD, and the filling module is inserted in the remaining gaps.
  • FIG. 1 is a flowchart of an automatic layout method for filling loops in chip design according to an embodiment of the present invention
  • FIG. 3 is the second schematic diagram of the filling loop layout process of the automatic layout method provided by the embodiment of the present invention.
  • Fig. 4 is the third schematic diagram of the filling loop layout process of the automatic layout method provided by the embodiment of the present invention.
  • FIG. 5 is a fourth schematic diagram of the filling loop layout process of the automatic layout method provided by the embodiment of the present invention.
  • the embodiment of the present invention provides an automatic layout method of pin ring for optimizing the electrostatic discharge capability of a chip to design total power consumption data, area constraint information, package constraint information, core position information, and chip design selection process Based on the information of the library, position the filling ring, determine the type and required quantity of signal lead modules in the filling ring, and the type of power lead module and the basic required quantity corresponding to each group of power lead module types. Automatic layout is performed on each boundary of the, and the remaining gaps are inserted in accordance with the principle of priority layout of the first level lead module Vss PAD with the strongest electrostatic discharge capability.
  • Step 110 Obtain chip design total power consumption data, area constraint information, package constraint information, core location information, and chip design selected process library information;
  • the position information of the core includes the boundary position coordinates of the core.
  • the unit of the chip core can be generated by the netlist generated by synthesis, and the core is mainly used to realize the logic function of the chip.
  • Step 120 Determine the position information of the padding loop of the chip according to the area constraint information and the boundary position coordinates of the kernel;
  • the synthesized netlist usually only generates the cells of the chip core, and does not include the Pad module of the power supply and the ground, and the corner cell of the boundary module.
  • the width of the pad ring PAD ring can be determined according to the chip boundary and the boundary of the inner core corresponding to the chip area constraint information, and its position information can also be determined at the same time.
  • the boundary length of the chip is a and the boundary length of the core is b. Then the width of the padding ring PAD ring is (a-b)/2, and the length is the same as the boundary length a of the chip.
  • the filling ring has four boundaries; the position information of the filling ring includes: the position coordinates and width information of each boundary of the filling ring.
  • the upper left vertex coordinates of the core Core are (x, y), then the upper left vertex coordinates of the pad ring PAD ring are (x-(a-b)/2, y-(a-b)/2).
  • the filling ring of the chip includes the Pad module including the power supply and the ground, the border module Corner Cell, etc. Specifically, the signal lead module Signal PAD, the power lead module, the border module Corner Cell and the filler cell of the chip are included in this embodiment. .
  • Step 130 Determine the type and quantity of the signal lead module Signal PAD of the chip according to the information of the selected process library and the package constraint information;
  • the process library is selected before chip design, and is determined according to the process used in the specific tapeout and the design tool.
  • Each process library has corresponding regulations for the size and function of each module in the filling ring of the chip.
  • the various modules in the pad ring vary according to the functions performed by the IO port. Some modules implement level conversion and drive, and some modules have electrostatic discharge (ESD) protection functions. Because under the ESD stress, there will be a large current flowing, which is easy to cause the latch-up effect, so the impact of the latch-up effect must be considered in the specific design.
  • ESD electrostatic discharge
  • the influence of the wiring of each module on the circuit is mainly the influence of the parasitic parameters of the wiring on the circuit performance.
  • Package constraint information refers to how many signal lead modules Signal PAD are required according to the logic function requirements of the chip during packaging. Therefore, according to the package constraint information, the required signal lead module Signal PAD type can be extracted from the selected process library, and the number of Signal PAD corresponding to each signal lead module can be determined; different types of signal lead modules Signal PAD have their own lateral dimensions.
  • Step 140 Combining the design total power consumption data and the type and quantity of the signal lead module Signal PAD to determine the type of power lead module and the basic required quantity corresponding to each group of power lead module types;
  • the types of power lead modules include a first power lead module group and a second power lead module group; the first power lead module group includes a first level lead module Vss PAD and a second level lead module Vdd Pad; the second power source The lead module group includes a first level input and output lead module Vss IO PAD and a second level input and output lead module Vdd IO Pad;
  • the first power lead module group is used to supply power to the internal modules of the core, that is, core ground
  • the second power lead module group is used to drive power supply for the signal lead module Signal PAD, that is, pad ground, and voltage discharge protection.
  • Step 150 Based on the type and quantity of Signal PAD, the type of power lead module, and the basic required quantity and packaging constraint information corresponding to each group of power lead module types, combine the Signal PAD, the first power lead module group and the second power lead module group Divided into four groups of lead modules to be laid out;
  • the package constraint information also specifies which side of the chip some specific signal pins need to be led from. Therefore, the signal PAD is arranged according to the package constraint information. For those without specific requirements, the principle of evenly distributed as far as possible is carried out. Signal PAD is arranged on the four borders.
  • the placement rule parameters of the Signal PAD can be determined according to the package constraint information, and the placement rule parameters include the maximum distance between the Signal PAD and the first-level lead module Vss PAD with the maximum voltage discharge capability.
  • each Signal PAD, the first power lead module group and the second power lead module group are allocated to a group of lead modules to be laid out according to the principle of equal distribution, and determined in Sort position information in the group. This can be used to realize the automatic arrangement of the Signal PAD, the first power lead module group and the second power lead module group.
  • the four groups of lead modules to be laid out have a one-to-one correspondence with the four boundaries.
  • Step 160 Perform a first automatic layout on each boundary
  • the first automatic layout includes:
  • Step 161 Select the boundary vertex according to the boundary position coordinates of the filling ring, and determine the position coordinates of the selected boundary vertex as the layout starting point coordinates of the boundary;
  • Step 162 Call the first subroutine, take the starting point coordinates as the starting point, call and insert a border module Corner Cell from the process library, and record the end position coordinates of the border module.
  • Corner Cell is a module used to fill the gaps between cells at the junction of horizontal and vertical boundaries.
  • Step 163 According to the end position coordinates of the boundary module and the lead module to be laid out corresponding to the boundary, the second subroutine and the third subroutine are polled and called in sequence, so that the required Signal PAD, first The power lead module group and/or the second power lead module group, and record the coordinates of the termination position after each insertion;
  • the second subroutine is used to insert Signal PAD
  • the third subroutine is used to insert the first power lead module group and/or the second power lead module group.
  • one or more Signal PADs can be called at a time, and one or more sets of the first power lead module group and/or the second power lead module group can be called at a time under the condition that each constraint is satisfied. , As long as the Signal PAD meets the constraints, there is a first power lead module group and a second power lead module group.
  • the module layout is shown in Figure 3.
  • the execution of each boundary can be carried out in accordance with the above process, and can be carried out synchronously or distributed.
  • the modules in the filling ring can meet the drive capability of the chip itself and the requirements for electrostatic discharge capability.
  • the size of the remaining gap will be less than 0. In this case, a layout error will be output.
  • the warning message is used to remind the chip designer to return to the netlist design and no longer perform the automatic layout of the filling ring.
  • Step 170 Calculate the size of the remaining gap for each boundary after the first automatic layout is executed according to the end position coordinates after the last insertion, the boundary vertices of the adjacent boundary, and the module size of the boundary module, and execute it according to the size of the remaining gap
  • the second automatic layout is used to optimize the electrostatic discharge capability of the chip.
  • the first power lead module group containing the Vss PAD with the strongest electrostatic discharge capability is inserted into the remaining gap in the module group first.
  • the implementation process can be specifically as follows:
  • the third subroutine is called in the remaining gap Insert a first level lead module Vss PAD inside.
  • Step 180 Calculate the size of the secondary remaining gap for each boundary after the second automatic layout is executed according to the coordinates of the end position after the last insertion of the second automatic layout, the boundary vertices of an adjacent boundary, and the module size of the boundary module.
  • the fourth subroutine is called according to the size of the secondary remaining gap, and one or more filler cells are called by the process library through the fourth subroutine to fill the secondary remaining gap.
  • the secondary residual gap is shown at the position marked d2 in the figure.
  • Filling module filler cell refers to the fillers that are not related to logic in the cell library of the selected process library. It can be divided into input and output filling module IO filler and ordinary standard cell filling module standard cell filler.
  • the IO filler also called pad filler, is used to fill the ring filling, which is usually used to fill the gap of the PAD ring.
  • the present invention provides an automatic layout method of pin ring for optimizing the electrostatic discharge capability of a chip to design total power consumption data, area constraint information, package constraint information, core position information and chip design selection process library Based on the information, locate the position of the filling ring, determine the signal PAD type and the required quantity of the signal lead module arranged in the filling ring, and the type of power lead module and the basic required quantity corresponding to each group of power lead module type, and the filling ring
  • the first automatic layout is executed for each boundary of, which is used to automatically insert the boundary modules Corner Cell, Signal PAD and power lead module, and then the remaining gap will be given priority to the first level lead module Vss PAD with the strongest electrostatic discharge capability.
  • the principle of the layout is to insert, and finally perform random automatic layout for the remaining gaps that are not enough to insert the Vss PAD, and insert the filling module in the remaining gaps.

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Abstract

一种用于优化芯片静电泄放能力的管脚环的自动布局方法，包括：根据选定工艺库的信息和封装约束信息，确定芯片的信号引线模块的种类和数量，并结合设计总功耗数据确定电源引线模块的种类和对应每组电源引线模块种类的基本需求数量；基于信号引线模块和电源引线模块的种类、数量和封装约束信息，得到四条边界各自的待布局引线模块的分组；对每条边界执行第一自动布局，插入一个边界模块后，依次轮询调用第二子程序和第三子程序，分别用于插入信号引线模块，第一电源引线模块组和/或第二电源引线模块组；根据该边界执行第一自动布局后的剩余间隙的尺寸执行第二自动布局，用以优化芯片的静电泄放能力。

Description

用于优化芯片静电泄放能力的管脚环的自动布局方法
本申请要求于2020年03月30日提交中国专利局、申请号为202010236818.9，发明名称为“用于优化芯片静电泄放能力的管脚环的自动布局方法”的中国专利申请的优先权。
技术领域
本发明涉及微电子技术领域，尤其涉及一种用于优化芯片静电泄放能力的管脚环的自动布局方法。
背景技术
芯片设计中，布局是决定内核单元、宏模块等电路部件位于版图平面的位置的设计步骤。通过在版图上给单元、宏模块等分配物理位置，使得单元、宏模块等部件互不重叠。该分配需要根据用户给出的特定约束来对代价函数进行优化。布局之后,单元和引脚的确切位置己经确定,所需的互联也已经确定。通常讨论的布局，都集中在芯片内核的布局。对于芯片设计来说，还有一个很关键的布局步骤是对管脚环(PAD ring)进行布局。
静电放电(Electrostatic Discharge，ESD)，应该是造成所有电子元器件或集成电路系统造成过度电应力(EOS)破坏的主要元凶。因为静电通常瞬间电压非常高(>几千伏)，所以这种损伤是毁灭性和永久性的，会造成电路直接烧毁。所以预防静电损伤是所有芯片设计和制造的头号难题。
ESD的泄放也是管脚环(PAD ring)的一个重要任务，静电泄放通路的模块都是在信号引线模块Signal PAD旁边，不能在芯片里面，因为外界的静电需要第一时间泄放掉。
而目前业内常用的管脚环(PAD ring)的自动布局方法是在满足约束条 件下的完全随机布局，例如按照模块名称顺序排列的布局。这导致了自动布局根本无法满足芯片设计者的使用需求，跟不用说如何自动的优选ESD泄放能力更强的管脚环(PAD ring)布局方案。较为有经验的芯片设计者往往抛弃自动布局而采用手工布局的方式，以使管脚环(PAD ring)的布局满足设计要求，并在此基础上通过手动调整布局的方式对设计进行优化。
发明内容
本发明的目的是针对现有技术的缺陷，提供一种用于优化芯片静电泄放能力的管脚环的自动布局方法。
有鉴于此，本发明实施例提供了一种用于优化芯片静电泄放能力的管脚环的自动布局方法，包括：
获取芯片的设计总功耗数据、面积约束信息、封装约束信息、内核的位置信息和芯片设计选定工艺库的信息；所述内核的位置信息包括内核的边界位置坐标；
根据所述面积约束信息和内核的边界位置坐标，确定所述芯片的管脚环的位置信息；所述管脚环具有四条边界；所述管脚环的位置信息包括：所述管脚环的每条边界的位置坐标和宽度信息；
根据所述选定工艺库的信息和封装约束信息，确定所述芯片的信号引线模块Signal PAD的种类和数量；
结合所述设计总功耗数据与所述信号引线模块Signal PAD的种类和数量确定电源引线模块的种类和对应每组电源引线模块种类的基本需求数量；所述电源引线模块种类包括第一电源引线模块组和第二电源引线模块组；所述第一电源引线模块组包括第一电平引线模块Vss PAD和第二电平引线模块Vdd Pad；所述第二电源引线模块组包括第一电平输入输出引线模块Vss IO PAD和第二电平输入输出引线模块Vdd IO Pad；
基于所述Signal PAD的种类和数量、所述电源引线模块的种类和对应 每组电源引线模块种类的基本需求数量和所述封装约束信息，将所述Signal PAD、第一电源引线模块组和第二电源引线模块组分为四组待布局引线模块；所述四组待布局引线模块与所述四条边界具有一一对应关系；
对每条边界执行第一自动布局；所述第一自动布局包括：根据所述管脚环的边界位置坐标选定该边界顶点，并确定选定的所述边界顶点的位置坐标为该边界的布局起始点坐标；调用第一子程序，以所述起始点坐标作为起点，由所述工艺库调用并插入一个边界模块corner cell，记录所述边界模块的终止位置坐标；根据边界模块的终止位置坐标以及该边界对应的待布局引线模块，依次轮询调用第二子程序和第三子程序，从而依次由所述工艺库调用并插入所需的Signal PAD、第一电源引线模块组和/或第二电源引线模块组，并记录每次插入后的终止位置坐标；其中所述第二子程序用于插入Signal PAD，所述第三子程序用于插入第一电源引线模块组和/或第二电源引线模块组；
根据最后一次插入后的终止位置坐标、相邻一条边界的边界顶点和边界模块的模块尺寸，计算每条边界执行所述第一自动布局后的剩余间隙的尺寸，并根据所述剩余间隙的尺寸执行第二自动布局，用以优化所述芯片的静电泄放能力；
所述第二自动布局具体包括：
当所述剩余间隙的尺寸大于等于第一电源引线模块组的横向尺寸时，调用第三子程序在所述剩余间隙内插入一组或多组第一电源引线模块组；
当所述剩余间隙的尺寸于小于第一电源引线模块组的横向尺寸且大于等于第二电源引线模块组的横向尺寸时，调用第三子程序在所述剩余间隙内插入一组第二电源引线模块组；
当所述剩余间隙的尺寸分别小于第一电源引线模块组及第二电源引线模块组的横向尺寸，但大于等于第一电平引线模块Vss PAD的横向尺寸时时，调用第三子程序在所述剩余间隙内插入一个第一电平引线模块Vss  PAD。
优选的，所述方法还包括：
根据第二自动布局执行最后一次插入后的终止位置坐标、相邻一条边界的边界顶点和边界模块的模块尺寸，计算每条边界执行所述第二自动布局后的二次剩余间隙的尺寸，并根据所述二次剩余间隙的尺寸调用第四子程序，通过所述第四子程序由所述工艺库调用并插入一个或多个填充模块filler cell，用以填满所述二次剩余间隙。
优选的，根据所述选定工艺库的信息和封装约束信息，确定所述芯片的信号引线模块Signal PAD的种类和数量具体为：
根据所述封装约束信息从所述选定工艺库中提取所需的信号引线模块Signal PAD的种类，并确定对应每种信号引线模块Signal PAD的数量；不同种类信号引线模块Signal PAD具有各自的横向尺寸。
优选的，所述结合所述设计总功耗数据与所述信号引线模块Signal PAD的种类和数量确定电源引线模块的种类和对应每组电源引线模块种类的基本需求数量具体为：
计算所述信号引线模块Signal PAD输出的信号同时翻转时的最大能耗，并根据所述最大能耗确定所需第一电平输入输出引线模块Vss IO PAD和第二电平输入输出引线模块Vdd IO Pad的最小布局数量；
根据设计总功耗数据中芯片的核内典型功耗消耗值计算第一电平引线模块Vss PAD和第二电平引线模块Vdd Pad的最小布局数量。
优选的，所述基于所述Signal PAD的种类和数量、所述电源引线模块的种类和对应每组电源引线模块种类的基本需求数量和所述封装约束信息，将所述Signal PAD、第一电源引线模块组和第二电源引线模块组分为四组待布局引线模块具体包括：
根据封装约束信息确定Signal PAD的放置规则参数，所述放置规则参数包括Signal PAD到具有最大静电泄放能力的第一电平引线模块Vss PAD 之间的最大间距；
根据所述最大间距、所述Signal PAD的放置规则参数，对每个所述Signal PAD、所述第一电源引线模块组和第二电源引线模块组按照平均分布原则，分配到一组待布局引线模块中，并确定在组中的排序位置信息。
优选的，当所述剩余间隙的尺寸小于0时，所述方法还包括：输出布局错误告警提示信息。
本发明提供了一种用于优化芯片静电泄放能力的管脚环的自动布局方法，以设计总功耗数据、面积约束信息、封装约束信息、内核的位置信息和芯片设计选定工艺库的信息为基础，对填补环进行位置定位，确定填补环内排布信号引线模块Signal PAD种类和需求数量，以及电源引线模块的种类和对应每组电源引线模块种类的基本需求数量，并对填补环的每条边界执行第一自动布局，用以自动插入边界模块Corner Cell、Signal PAD和电源引线模块，并在随后对剩余间隙按照静电泄放能力最强的第一电平引线模块Vss PAD优先布局的原则进行插入，最后再对剩余的不够插入Vss PAD的间隙执行随机自动布局，在剩余间隙内插入填充模块。
附图说明
下面通过附图和实施例，对本发明实施例的技术方案做进一步详细描述。
下面通过附图和实施例，对本发明实施例的技术方案做进一步详细描述。
图1为本发明实施例提供的芯片设计中填补环的自动布局方法流程图；
图2为本发明实施例提供的自动布局方法进行填补环布局的过程示意图之一；
图3为本发明实施例提供的自动布局方法进行填补环布局的过程示意图之二；
图4为本发明实施例提供的自动布局方法进行填补环布局的过程示意图 之三。
图5为本发明实施例提供的自动布局方法进行填补环布局的过程示意图之四。
具体实施方式
本发明实施例提供了一种用于优化芯片静电泄放能力的管脚环的自动布局方法，以设计总功耗数据、面积约束信息、封装约束信息、内核的位置信息和芯片设计选定工艺库的信息为基础，对填补环进行位置定位，确定填补环内排布信号引线模块种类和需求数量，以及电源引线模块的种类和对应每组电源引线模块种类的基本需求数量，并对填补环的每条边界执行自动布局，并对剩余间隙按照静电泄放能力最强的第一电平引线模块Vss PAD优先布局的原则进行插入。
本发明实施例提供的自动布局方法，其主要执行步骤如图1所示的方法流程图所示。
步骤110，获取芯片的设计总功耗数据、面积约束信息、封装约束信息、内核的位置信息和芯片设计选定工艺库的信息；
具体的，芯片设计时，基于设计要求会有对芯片设计的总功耗、芯片面积约束、封装约束、所采用的工艺库等的信息，在获得芯片面积约束后，内核位置也是在芯片设计开始时就确定了的。内核的位置信息包括内核Core的边界位置坐标。芯片内核的单元可以通过综合产生的网表生成，内核主要用于实现芯片的逻辑功能。
步骤120，根据面积约束信息和内核的边界位置坐标，确定芯片的填补环的位置信息；
具体的，综合产生的网表通常只产生芯片内核的单元，不包含电源、地的Pad模块、边界模块Corner Cell等。在确定了芯片面积约束信息和内 核的边界位置坐标后就可以根据芯片面积约束信息对应的芯片的边界与内核的边界确定填补环PAD ring的宽度，也同时确定其位置信息。
如图2所示，根据芯片面积约束信息确定芯片的边界长度为a，内核的边界长度为b，那么填补环PAD ring的宽度为(a-b)/2，长度与芯片的边界长度a相同。
填补环具有四条边界；填补环的位置信息包括：填补环的每条边界的位置坐标和宽度信息。
例如图2中，内核Core的左上角顶点坐标为(x,y),那么填补环PAD ring的左上角顶点坐标就是(x-(a-b)/2，y-(a-b)/2)。
芯片的填补环中包含了包含电源、地的Pad模块、边界模块Corner Cell等，具体的在本实施例中包括芯片的信号引线模块Signal PAD、电源引线模块、边界模块Corner Cell和填充模块filler cell。
步骤130，根据选定工艺库的信息和封装约束信息，确定芯片的信号引线模块Signal PAD的种类和数量；
具体的，芯片设计前工艺库就是选定的，根据具体流片所采用的工艺结合设计工具而定，每个工艺库中对于芯片的填补环中各个模块的尺寸、功能都有相应的规定。
填补环PAD ring中的各个模块根据IO端口完成的功能不同而不同，有些模块实现电平转换和驱动，有些模块为静电泄放(ESD)保护功能。因为在ESD应力下，会有大电流流过，容易引起栓锁效应，因此在具体的设计时必须考虑栓锁效应的影响。各模块的连线对电路的影响主要是连线的寄生参数对电路性能的影响。
封装约束信息是指封装时根据芯片的逻辑功能需要，要求有多少个何种功能的信号引线模块Signal PAD。因此根据封装约束信息可以从选定工艺库中提取所需的信号引线模块Signal PAD的种类，并确定对应每种信号引线模块Signal PAD的数量；不同种类信号引线模块Signal PAD具有各自 的横向尺寸。
步骤140，结合设计总功耗数据与信号引线模块Signal PAD的种类和数量确定电源引线模块的种类和对应每组电源引线模块种类的基本需求数量；
具体的，电源引线模块种类包括第一电源引线模块组和第二电源引线模块组；第一电源引线模块组包括第一电平引线模块Vss PAD和第二电平引线模块Vdd Pad；第二电源引线模块组包括第一电平输入输出引线模块Vss IO PAD和第二电平输入输出引线模块Vdd IO Pad；
第一电源引线模块组用于对内核内部模块的供电，也就是core ground，第二电源引线模块组用于信号引线模块Signal PAD的驱动供电，也就是pad ground，以及电压泄放保护等。
通过计算信号引线模块Signal PAD输出的信号同时翻转时的最大能耗，并根据最大能耗确定所需第一电平输入输出引线模块Vss IO PAD和第二电平输入输出引线模块Vdd IO Pad的最小布局数量；
根据设计总功耗数据中芯片的核内典型功耗消耗值计算第一电平引线模块Vss PAD和第二电平引线模块Vdd Pad的最小布局数量。
步骤150，基于Signal PAD的种类和数量、电源引线模块的种类和对应每组电源引线模块种类的基本需求数量和封装约束信息，将Signal PAD、第一电源引线模块组和第二电源引线模块组分为四组待布局引线模块；
具体的，封装约束信息还规定了某些特定的信号管脚需要从芯片的哪个边引出，因此根据这个封装约束信息进行Signal PAD的排布，对于没有特定要求的，按照尽量平均分布的原则进行Signal PAD在四条边界的排布。
填补环中信号引线模块Signal PAD的排布按照封装约束信息还有一个规则，就是规定了Signal PAD到用于ESD泄放的电源引线模块之间的最大间距。也就是可以根据封装约束信息确定Signal PAD的放置规则参数，放置规则参数包括Signal PAD到具有最大电压泄放能力的第一电平引线模块 Vss PAD之间的最大间距。
根据所述最大间距、Signal PAD的放置规则参数，对每个Signal PAD、第一电源引线模块组和第二电源引线模块组按照平均分布原则，分配到一组待布局引线模块中，并确定在组中的排序位置信息。由此可以用来实现Signal PAD、第一电源引线模块组和第二电源引线模块组的自动排布。
四组待布局引线模块与四条边界具有一一对应关系。
步骤160，对每条边界执行第一自动布局；
第一自动布局包括：
步骤161，根据填补环的边界位置坐标选定该边界顶点，并确定选定的边界顶点的位置坐标为该边界的布局起始点坐标；
步骤162，调用第一子程序，以起始点坐标作为起点，由工艺库调用并插入一个边界模块Corner Cell，记录边界模块的终止位置坐标。
边界模块Corner Cell是用于填补水平和垂直边界交接处单元之间的空白的模块。
步骤163，根据边界模块的终止位置坐标以及该边界对应的待布局引线模块，依次轮询调用第二子程序和第三子程序，从而依次由工艺库调用并插入所需的Signal PAD、第一电源引线模块组和/或第二电源引线模块组，并记录每次插入后的终止位置坐标；
其中，第二子程序用于插入Signal PAD，第三子程序用于插入第一电源引线模块组和/或第二电源引线模块组。
根据前面所说的约束信息，可以在满足各约束的条件下，一次调用一个或多个Signal PAD，再一次性调用一组或多组第一电源引线模块组和/或第二电源引线模块组，只要满足Signal PAD在符合约束条件范围内有第一电源引线模块组和第二电源引线模块组。
按照上述方法完成一条边界的布局后，在一个具体例子中，其模块布局如图3所示。各边界的执行均可按照上述流程进行，可以同步或分布进行。 图3布局后，填补环中的模块就可以满足芯片本身的驱动能力和对静电泄放能力的要求。
在个别情况下，可能会发生设计约束条件与芯片尺寸规定及芯片实际逻辑和驱动能力需求不匹配的情况，此时会发生剩余间隙的尺寸小于0的情况，在此情况下，会输出布局错误告警提示信息，用以提示芯片设计人员需要重新返回到网表设计，不再执行填补环的自动布局。
步骤170，根据最后一次插入后的终止位置坐标、相邻一条边界的边界顶点和边界模块的模块尺寸，计算每条边界执行第一自动布局后的剩余间隙的尺寸，并根据剩余间隙的尺寸执行第二自动布局，用以优化芯片的静电泄放能力。
为提升芯片的静电泄放能力，在剩余间隙内优先的以模块组方式插入插入静电泄放能力最强的包含Vss PAD的第一电源引线模块组。
在本发明的具体实施里中，实施过程可以具体如下：
当剩余间隙的尺寸大于等于第一电源引线模块组的横向尺寸时，调用第三子程序在所述剩余间隙内插入一组或多组第一电源引线模块组；
当剩余间隙的尺寸于小于第一电源引线模块组的横向尺寸且大于等于第二电源引线模块组的横向尺寸时，调用第三子程序在所述剩余间隙内插入一组第二电源引线模块组；
当剩余间隙的尺寸分别小于第一电源引线模块组及第二电源引线模块组的横向尺寸，但大于等于第一电平引线模块Vss PAD的横向尺寸时时，调用第三子程序在所述剩余间隙内插入一个第一电平引线模块Vss PAD。
在图3所示的示意图中，剩余间隙如图中标注d1的区域所示。在此区域执行第二自动布局，用以将该区域填充满。
在本例中，首先填入一组第一电源引线模块组，剩余的间隙不足以插入第二电源引线模块组，但可以插入一个第一电平引线模块Vss PAD，因此再填入一个第一电平引线模块Vss PAD。完成本步骤的第二自动布局后， 一条边界的模块布局如图4所示。
步骤180，根据第二自动布局执行最后一次插入后的终止位置坐标、相邻一条边界的边界顶点和边界模块的模块尺寸，计算每条边界执行第二自动布局后的二次剩余间隙的尺寸，并根据二次剩余间隙的尺寸调用第四子程序，通过第四子程序由工艺库调用并插入一个或多个填充模块filler cell，用以填满所述二次剩余间隙。
根据图4所示，二次剩余间隙如图中标注d2位置所示。
填充模块filler cell是指选定工艺库的单元库中与逻辑无关的填充物，可以分为输入输出填充模块IO filler以及普通的标准单元填充模块standard cell filler。
在填补环的填充所用的是IO filler，也叫pad filler，通常用来填充PAD ring的空隙。
在本例中，一条边界在自动布局完成后的其模块布局如图5所示。
本发明提供的一种用于优化芯片静电泄放能力的管脚环的自动布局方法，以设计总功耗数据、面积约束信息、封装约束信息、内核的位置信息和芯片设计选定工艺库的信息为基础，对填补环进行位置定位，确定填补环内排布信号引线模块Signal PAD种类和需求数量，以及电源引线模块的种类和对应每组电源引线模块种类的基本需求数量，并对填补环的每条边界执行第一自动布局，用以自动插入边界模块Corner Cell、Signal PAD和电源引线模块，并在随后对述剩余间隙按照静电泄放能力最强的第一电平引线模块Vss PAD优先布局的原则进行插入，最后再对剩余的不够插入Vss PAD的间隙执行随机自动布局，在剩余间隙内插入填充模块。
以上所述的具体实施方式，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施方式而已，并不用于限定本发明的保护范围，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (6)

  1. 一种用于优化芯片静电泄放能力的管脚环的自动布局方法，其特征在于，所述方法包括：
    获取芯片的设计总功耗数据、面积约束信息、封装约束信息、内核的位置信息和芯片设计选定工艺库的信息；所述内核的位置信息包括内核的边界位置坐标；
    根据所述面积约束信息和内核的边界位置坐标，确定所述芯片的管脚环的位置信息；所述管脚环具有四条边界；所述管脚环的位置信息包括：所述管脚环的每条边界的位置坐标和宽度信息；
    根据所述选定工艺库的信息和封装约束信息，确定所述芯片的信号引线模块Signal PAD的种类和数量；
    结合所述设计总功耗数据与所述信号引线模块Signal PAD的种类和数量确定电源引线模块的种类和对应每组电源引线模块种类的基本需求数量；所述电源引线模块种类包括第一电源引线模块组和第二电源引线模块组；所述第一电源引线模块组包括第一电平引线模块Vss PAD和第二电平引线模块Vdd Pad；所述第二电源引线模块组包括第一电平输入输出引线模块Vss IO PAD和第二电平输入输出引线模块Vdd IO Pad；
    基于所述Signal PAD的种类和数量、所述电源引线模块的种类和对应每组电源引线模块种类的基本需求数量和所述封装约束信息，将所述Signal PAD、第一电源引线模块组和第二电源引线模块组分为四组待布局引线模块；所述四组待布局引线模块与所述四条边界具有一一对应关系；
    对每条边界执行第一自动布局；所述第一自动布局包括：根据所述管脚环的边界位置坐标选定该边界顶点，并确定选定的所述边界顶点的位置坐标为该边界的布局起始点坐标；调用第一子程序，以所述起始点坐标作为起点，由所述工艺库调用并插入一个边界模块corner cell，记录所述边界模块的终止位置坐标；根据边界模块的终止位置坐标以及该边界对应的 待布局引线模块，依次轮询调用第二子程序和第三子程序，从而依次由所述工艺库调用并插入所需的Signal PAD、第一电源引线模块组和/或第二电源引线模块组，并记录每次插入后的终止位置坐标；其中所述第二子程序用于插入Signal PAD，所述第三子程序用于插入第一电源引线模块组和/或第二电源引线模块组；
    根据最后一次插入后的终止位置坐标、相邻一条边界的边界顶点和边界模块的模块尺寸，计算每条边界执行所述第一自动布局后的剩余间隙的尺寸，并根据所述剩余间隙的尺寸执行第二自动布局，用以优化所述芯片的静电泄放能力；
    所述第二自动布局具体包括：
    当所述剩余间隙的尺寸大于等于第一电源引线模块组的横向尺寸时，调用第三子程序在所述剩余间隙内插入一组或多组第一电源引线模块组；
    当所述剩余间隙的尺寸于小于第一电源引线模块组的横向尺寸且大于等于第二电源引线模块组的横向尺寸时，调用第三子程序在所述剩余间隙内插入一组第二电源引线模块组；
    当所述剩余间隙的尺寸分别小于第一电源引线模块组及第二电源引线模块组的横向尺寸，但大于等于第一电平引线模块Vss PAD的横向尺寸时时，调用第三子程序在所述剩余间隙内插入一个第一电平引线模块Vss PAD。
  2. 根据权利要求1所述的管脚环的自动布局方法，其特征在于，所述方法还包括：
    根据第二自动布局执行最后一次插入后的终止位置坐标、相邻一条边界的边界顶点和边界模块的模块尺寸，计算每条边界执行所述第二自动布局后的二次剩余间隙的尺寸，并根据所述二次剩余间隙的尺寸调用第四子程序，通过所述第四子程序由所述工艺库调用并插入一个或多个填充模块filler cell，用以填满所述二次剩余间隙。
  3. 根据权利要求1所述的管脚环的自动布局方法，其特征在于，根据所述选定工艺库的信息和封装约束信息，确定所述芯片的信号引线模块Signal PAD的种类和数量具体为：
    根据所述封装约束信息从所述选定工艺库中提取所需的信号引线模块Signal PAD的种类，并确定对应每种信号引线模块Signal PAD的数量；不同种类信号引线模块Signal PAD具有各自的横向尺寸。
  4. 根据权利要求1所述的管脚环的自动布局方法，其特征在于，所述结合所述设计总功耗数据与所述信号引线模块Signal PAD的种类和数量确定电源引线模块的种类和对应每组电源引线模块种类的基本需求数量具体为：
    计算所述信号引线模块Signal PAD输出的信号同时翻转时的最大能耗，并根据所述最大能耗确定所需第一电平输入输出引线模块Vss IO PAD和第二电平输入输出引线模块Vdd IO Pad的最小布局数量；
    根据设计总功耗数据中芯片的核内典型功耗消耗值计算第一电平引线模块Vss PAD和第二电平引线模块Vdd Pad的最小布局数量。
  5. 根据权利要求1所述的管脚环的自动布局方法，其特征在于，所述基于所述Signal PAD的种类和数量、所述电源引线模块的种类和对应每组电源引线模块种类的基本需求数量和所述封装约束信息，将所述Signal PAD、第一电源引线模块组和第二电源引线模块组分为四组待布局引线模块具体包括：
    根据封装约束信息确定Signal PAD的放置规则参数，所述放置规则参数包括Signal PAD到具有最大静电泄放能力的第一电平引线模块Vss PAD之间的最大间距；
    根据所述最大间距、所述Signal PAD的放置规则参数，对每个所述Signal PAD、所述第一电源引线模块组和第二电源引线模块组按照平均分布原则，分配到一组待布局引线模块中，并确定在组中的排序位置信息。
  6. 根据权利要求1所述的管脚环的自动布局方法，其特征在于，当所述剩余间隙的尺寸小于0时，所述方法还包括：输出布局错误告警提示信息。
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