WO2021195933A9 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2021195933A9
WO2021195933A9 PCT/CN2020/082334 CN2020082334W WO2021195933A9 WO 2021195933 A9 WO2021195933 A9 WO 2021195933A9 CN 2020082334 W CN2020082334 W CN 2020082334W WO 2021195933 A9 WO2021195933 A9 WO 2021195933A9
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WIPO (PCT)
Prior art keywords
sub
electrically connected
pixels
gate
array substrate
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PCT/CN2020/082334
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English (en)
French (fr)
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WO2021195933A1 (zh
Inventor
杨路路
尚庭华
屈忆
姜晓峰
李慧君
王梦奇
张鑫
张猛
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000435.XA priority Critical patent/CN113939863B/zh
Priority to EP20897616.7A priority patent/EP4131235A4/en
Priority to PCT/CN2020/082334 priority patent/WO2021195933A1/zh
Priority to US17/262,306 priority patent/US20220115482A1/en
Priority to JP2021564583A priority patent/JP7493535B2/ja
Publication of WO2021195933A1 publication Critical patent/WO2021195933A1/zh
Publication of WO2021195933A9 publication Critical patent/WO2021195933A9/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0413—Details of dummy pixels or dummy lines in flat panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • Active matrix light emitting diodes active matrix organic light emitting diode, AMOLE D
  • AMOLE D active matrix organic light emitting diode
  • the present application provides an array substrate, a display panel, and a display device.
  • the technical solutions are as follows:
  • an array substrate including:
  • a base substrate having a display area and a peripheral area surrounding the display area
  • a plurality of rows of first sub-pixels located in the display area the plurality of rows of first sub-pixels are light-emitting pixels, and a boundary of the plurality of rows of first sub-pixels is a boundary of the display area;
  • a plurality of gate lines are located in the display area and the peripheral area, and the plurality of rows of first sub-pixels are electrically connected to the plurality of gate lines;
  • a plurality of reset signal lines are located in the display area and the peripheral area, and the plurality of rows of first sub-pixels are electrically connected to the plurality of reset signal lines;
  • the gate line electrically connected to the first sub-pixel in one row and the reset signal line electrically connected to the first sub-pixel in another row are electrically connected to the same first gate driving circuit;
  • the first target trace connected to the first sub-pixel in the first row is electrically connected to the second gate drive circuit; the second target trace connected to the first sub-pixel in the bottom row is electrically connected to the third gate drive circuit connect;
  • one of the first target trace and the second target trace is one of the multiple gate lines, and the other target trace is one of the multiple reset signal lines .
  • the rows of first sub-pixels are electrically connected to the plurality of gate lines in a one-to-one correspondence, and the rows of first sub-pixels are electrically connected to the plurality of reset signal lines in a one-to-one correspondence.
  • the gate lines electrically connected to the first sub-pixels in odd rows and the reset signal lines electrically connected to the first sub-pixels in even rows are the same as the first gate drive Electrical circuit connection;
  • the first target trace is one of the multiple reset signal lines
  • the second target trace is one of the multiple gate lines.
  • the reset signal lines electrically connected to the first sub-pixels in odd-numbered rows and the gate lines electrically connected to the first sub-pixels in even-numbered rows are the same as the first gate driver. Electrical circuit connection;
  • the first target trace is one of the multiple gate lines
  • the second target trace is one of the multiple reset signal lines.
  • the gate lines electrically connected to the first sub-pixels in one row are connected to the reset signal lines electrically connected to the first sub-pixels in another row, and are connected to the same first gate.
  • the drive circuit is electrically connected.
  • a gate line electrically connected to the first sub-pixel in one row is connected to a reset signal line electrically connected to the first sub-pixel in another row, and is connected to the same line through the gate line.
  • the first gate drive circuit is electrically connected.
  • the array substrate includes:
  • a plurality of the first gate driving circuits are located in the peripheral area;
  • the second gate drive circuit is located in the peripheral area and on one side of the plurality of first gate drive circuits;
  • the third gate drive circuit is located in the peripheral area and on a side of the plurality of first gate drive circuits away from the second gate drive circuit.
  • the gate line electrically connected to the first sub-pixel in one row and the reset signal line electrically connected to the first sub-pixel in another row are the same as the first gate line.
  • the drive circuit is electrically connected.
  • the gate lines electrically connected to the first sub-pixels in one row and the reset signal lines electrically connected to the first sub-pixels in another row are connected to the two first gate lines.
  • the pole drive circuit is electrically connected.
  • the two first gate driving circuits electrically connected to the first sub-pixels in every two adjacent rows are oppositely arranged at two ends of the first sub-pixels in two adjacent rows.
  • the first target trace electrically connected to the first sub-pixel located in the first row is electrically connected to the two second gate driving circuits
  • the second target trace electrically connected to the first sub-pixel located in the bottom row is electrically connected
  • the wiring is electrically connected with the two third gate driving circuits.
  • the array substrate further includes:
  • a plurality of light emission control signal lines are located in the display area and the peripheral area, and the plurality of rows of first sub-pixels are electrically connected to the plurality of light emission control signal lines in a one-to-one correspondence.
  • the light-emitting control signal line electrically connected to the first sub-pixels in each row is electrically connected to one light-emitting drive circuit, and the light-emitting control signal lines electrically connected to the first sub-pixels in each row are electrically connected to different light-emitting drive circuits.
  • the light-emitting control signal lines electrically connected to the first sub-pixels in multiple rows are electrically connected to the same light-emitting driving circuit, and the first sub-pixels electrically connected to the same light-emitting driving circuit are located in different rows.
  • the array substrate includes: the light-emitting drive circuit located in the peripheral area.
  • each of the first sub-pixels includes: a pixel circuit and a light-emitting unit electrically connected to the pixel circuit;
  • the pixel circuit is electrically connected to the gate line, the reset signal line, and the light-emitting unit, and the pixel circuit is configured to respond to the gate drive signal provided by the gate line and the reset signal line.
  • the reset signal drives the light-emitting unit to emit light.
  • the pixel circuit is also electrically connected to the light emission control signal line;
  • the pixel circuit is configured to drive the light-emitting unit to emit light in response to the gate drive signal, the reset signal, and the light-emission control signal provided by the light-emission control signal line.
  • the array substrate further includes:
  • a plurality of rows of second sub-pixels are located in the peripheral area and on a side of the second gate driving circuit away from the first gate driving circuit, and the plurality of rows of second sub-pixels are non-luminous pixels.
  • a display panel in another aspect, includes: a packaging cover plate, and the array substrate as described in the above-mentioned aspect.
  • a display device in yet another aspect, includes: a drive circuit, and the display panel as described in the above aspect, the drive circuit is electrically connected to the display panel, and the drive circuit is used to drive the display panel. The operation of the display panel is described.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of still another array substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of still another array substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of still another array substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a first sub-pixel provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another first sub-pixel provided by an embodiment of the present application.
  • FIG. 9 is a partial schematic diagram of the layout of an array substrate provided by an embodiment of the present application.
  • FIG. 10 is a partial schematic diagram of the layout of another array substrate provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the difference in loading on the reset line electrically connected to the display sub-pixels of each row is small, that is, The reset signal lines included in the array substrate are all in the same working environment.
  • a row of non-luminous dummy sub-pixels adjacent to the first sub-pixel of the first row is arranged at the top of the display area, that is, at the boundary of the display area.
  • a dummy pixel is provided, and a gate line is electrically connected to the row of dummy sub-pixels.
  • the reset signal lines electrically connected to the odd-numbered rows of display sub-pixels and the gate lines electrically connected to the even-numbered rows of display sub-pixels are electrically connected to the same gate drive circuit.
  • the reset signal line electrically connected to the display sub-pixels in the first row can also be electrically connected to the gate line electrically connected to the adjacent dummy sub-pixels with the same gate driving circuit.
  • the reset signal lines electrically connected to each row of display sub-pixels are all in the same working environment.
  • other signal lines e.g., emission control signal lines
  • the DC signal terminal that provides the DC signal will be electrically connected to other signal lines.
  • the arrangement of the dummy sub-pixels and the introduction of signal lines electrically connected to the dummy sub-pixels make the design of the array substrate more complicated.
  • the structure of the pixel circuit included in the pixel has become more and more complex, and the space utilization requirements for the array substrate are getting higher and higher.
  • some simple Effective layout becomes very important.
  • the embodiments of the present application provide an array substrate, which not only can ensure that the normal display is not affected, but also has less wiring on the array substrate, simpler design, and lower manufacturing cost.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present application. As shown in FIG. 1, the array substrate may include:
  • the base substrate 01 has a display area A1 and a peripheral area A2 surrounding the display area A1.
  • first sub-pixels Multiple rows of first sub-pixels (n rows of first sub-pixels P1 to Pn as shown in FIG. 1) are located in the display area A1.
  • the multiple rows of first sub-pixels are light-emitting pixels and the boundary of the multiple rows of first sub-pixels is the display
  • the boundary of the area A1, that is, the display area A1 is the outer edge contour of the first sub-pixels in multiple rows.
  • n is an integer greater than zero. Since the first sub-pixel is a light-emitting pixel, the first sub-pixel may also be referred to as a display sub-pixel.
  • a plurality of gate lines (n gate lines GATE1 to GATEn as shown in FIG. 1) are located in the display area A1 and the peripheral area A2, and the plurality of rows of first sub-pixels may be electrically connected to the plurality of gate lines.
  • a plurality of reset signal lines (n reset signal lines RST1 to RSTn as shown in FIG. 1) are located in the display area A1 and the peripheral area A2, and the rows of first sub-pixels may be electrically connected to the plurality of reset signal lines.
  • the gate line electrically connected to the first sub-pixel in one row and the reset signal line electrically connected to the first sub-pixel in another row may be electrically connected to the same first gate driving circuit 10 .
  • the first target trace connected to the first sub-pixel in the first row may be electrically connected to the second gate drive circuit 20; the second target trace connected to the first sub-pixel in the bottom row may be connected to the third gate.
  • the driving circuit 30 is electrically connected.
  • one of the first target wiring and the second target wiring may be one of multiple gate lines, and the other target wiring may be one of multiple reset signal lines.
  • the first target trace is the first reset signal line RST1 among the reset lines.
  • the second target trace L2 is the last gate line GATEn among the plurality of gate lines.
  • the first sub-pixel P1 in the first row is electrically connected to the first gate line GATE1 and the first reset signal line RST1;
  • the first sub-pixel P2 in the second row is electrically connected to the second gate line GATE2 and the second reset signal
  • the line RST2 is correspondingly electrically connected;
  • the first sub-pixel P3 in the third row is correspondingly electrically connected with the third gate line GATE3 and the third reset signal line RST3; and so on.
  • the gate line GATE1 electrically connected to the first sub-pixel P1 in the first row and the reset signal line RST2 electrically connected to the first sub-pixel P2 in the second row are electrically connected to the same first gate driving circuit 10; the second row The gate line GATE2 electrically connected to the first sub-pixel P2 and the reset signal line RST3 electrically connected to the first sub-pixel P3 in the third row are electrically connected to the same other first gate driving circuit 10; and so on, until The gate line GATE(n-1) electrically connected to the first sub-pixel P(n-1) in the n-1th row and the reset signal line RSTn electrically connected to the first sub-pixel Pn in the nth row are the same as the last one.
  • the first gate driving circuit 10 is electrically connected.
  • the reset signal line RST1 (ie, the first target trace) electrically connected to the first sub-pixel P1 in the first row is electrically connected to the second gate driving circuit 20.
  • the gate line GATEn (ie, the second target line) electrically connected to the first sub-pixel Pn in the nth row is electrically connected to the third gate driving circuit 30.
  • the reset signal lines electrically connected to the first sub-pixels located in different rows may be different; the first sub-pixels located in different rows are electrically connected
  • the connected gate lines, that is, the gate driving circuits electrically connected to different gate lines may be different.
  • the reset signal line RST1 electrically connected to the first sub-pixel P1 in the first row is connected to the second gate driving circuit 20, and the reset signal line RST2 electrically connected to the first sub-pixel P2 in the second row is connected to One first gate driving circuit 10 is connected, and the reset signal line RST3 electrically connected to the first sub-pixel P3 in the third row is connected to another first gate driving circuit 10, and so on.
  • the gate line GATE1 electrically connected to the first sub-pixel P1 in the first row is connected to a first gate driving circuit 10
  • the gate line GATE2 electrically connected to the first sub-pixel P1 in the second row is connected to another first gate driving circuit 10 connections, and so on.
  • each gate driving circuit may provide a signal to the first sub-pixel electrically connected to the signal line through the signal line electrically connected to the gate driving circuit, so as to drive the first sub-pixel to emit light.
  • the second gate driving circuit 20 can be controlled to output a reset signal to the first sub-pixel P1 in the first row through the reset signal line RST1 electrically connected to it. Reset the first sub-pixel P1 in the first row; then, control the first first gate driving circuit 10 to output a gate driving signal to the first sub-pixel P1 in the first row through the gate line GATE1 electrically connected to it.
  • the first sub-pixel P1 in the first row is driven to emit light.
  • the first first gate driving circuit 10 can also output a reset signal to the first sub-pixel P2 in the second row through the reset signal line RST2 electrically connected to it, so as to realize the control of the first sub-pixel P2 in the second row.
  • the reset the second first gate driving circuit 10 is controlled to output a gate driving signal to the first sub-pixel P2 in the second row through the gate line GATE2 to which it is electrically connected, so as to drive the first sub-pixel P2 in the second row to emit light.
  • the second first gate driving circuit 10 can also output a reset signal to the first sub-pixel P3 in the third row through the reset signal line RST3 electrically connected to it, so as to realize the control of the first sub-pixel P3 in the third row.
  • the reset, and so on, the drivers of other rows will not be repeated.
  • the embodiment of the present application provides an array substrate. Combining the electrical connection relationship of the first sub-pixel, each signal line and the gate drive circuit of the array substrate, it can be seen that during normal operation, each gate drive circuit can be flexibly controlled to provide signals to the signal lines that are electrically connected to it.
  • the first sub-pixel is reliably driven row by row.
  • the array substrate can not only display normally, but also has a simpler design.
  • each gate driving circuit ie, the second gate driving circuit 20, each of the first gate driving circuit 10 and the third gate driving circuit 30
  • each gate driving circuit can be arranged outside the array substrate independently of the array substrate.
  • each gate driving circuit may also be provided on the array substrate. That is, as shown in FIG. 2, the array substrate may further include:
  • the plurality of first gate driving circuits 10 are located in the peripheral area A2 of the base substrate 01.
  • the second gate driving circuit 20 is located in the peripheral area A2 of the base substrate 01 and on one side of the plurality of first gate driving circuits 10.
  • the third gate driving circuit 30 is located in the peripheral area A2 of the base substrate 01 and on the side of the plurality of first gate driving circuits 10 away from the second gate driving circuit 20.
  • each gate driving circuit can also be referred to as a gate on array (GOA) unit fabricated on an array substrate.
  • GAA gate on array
  • each gate driving circuit is provided on the array substrate as an example for description, and FIG. 2 and the drawings involved in the following embodiments all use GOA1 to represent the first gate driving circuit 10, and GOA2 to represent the first gate drive circuit 10.
  • the second gate driving circuit 20 is called, and the third gate driving circuit 30 is represented by GOA3.
  • the second gate driving circuit 20, each of the first gate driving circuits 10, and the third gate driving circuit 30 provided by the embodiments of the present application may be arranged in order along the extending direction perpendicular to the gate lines. On the array substrate. Moreover, every two adjacent gate driving circuits can be cascaded (not shown in the figure), and activated in sequence in the cascade sequence.
  • the circuit composed of the second gate driving circuit 20, each of the first gate driving circuits 10, and the third gate driving circuit 30 may be referred to as a gate driving device.
  • the second gate driving circuit 20 may start to work in sequence, that is, the gate driving device may drive row by row from the first sub-pixel in the first row.
  • the array substrate includes multiple rows of first sub-pixels, and this scanning method may also be referred to as forward scanning.
  • the gate driving device may also work sequentially from the third gate driving circuit 30, that is, the gate driving device may drive the first sub-pixels of the array substrate row by row starting from the first sub-pixel in the last row. The method can also be called reverse scan.
  • the reset signal line electrically connected to the pixels in the row provides a reset signal to the first sub-pixel in the last row.
  • the second gate driving circuit 20 needs to be electrically connected to the reset signal electrically connected to the first sub-pixel in the first row Line;
  • the third gate driving circuit 30 needs to be electrically connected to the reset signal line electrically connected to the first sub-pixel in the last row.
  • the gate lines electrically connected to the first sub-pixels in odd rows and the resets electrically connected to the first sub-pixels in even rows may be electrically connected to the same first gate driving circuit 10.
  • the first target trace can be one of the multiple reset lines (RST1 shown in Figure 1)
  • the second target trace can be one of the multiple gate lines.
  • the reset signal line electrically connected to the first sub-pixels in odd rows and the reset signal lines electrically connected to the first sub-pixels in even rows
  • the gate line may be electrically connected to the same first gate driving circuit 10.
  • the first target trace can be one of the multiple gate lines (GATE1 shown in Figure 2)
  • the second target trace can be one of the multiple reset signal lines.
  • Reset signal line RSTn shown in Figure 2).
  • FIG. 2 continues to illustrate an array substrate including n rows of first sub-pixels P1 to Pn, n gate lines GATE1 to GATEn, and n reset signal lines RST1 to RSTn as an example.
  • the reset signal line RST1 electrically connected to the first sub-pixel P1 in the first row and the gate line GATE2 electrically connected to the first sub-pixel P2 in the second row are identical to the same first gate electrode.
  • the driving circuit 10 (that is, the first GOA1 shown in FIG. 2) is electrically connected.
  • the reset signal line RST2 electrically connected to the first sub-pixel P2 in the second row and the gate line GATE3 electrically connected to the first sub-pixel P3 in the third row are identical to another first gate driving circuit 10 (ie, shown in FIG. 2).
  • the second GOA1) is electrically connected; and so on, until the reset signal line RST(n-1) electrically connected to the first sub-pixel P(n-1) in the n-1th row is electrically connected to the first sub-pixel in the nth row
  • the gate line GATEn electrically connected to the pixel Pn is electrically connected to the same last first gate driving circuit 10 (that is, the last GOA1 shown in FIG. 2).
  • gate line GATE1 electrically connected to the first sub-pixel P1 in the first row is electrically connected to the second gate driving circuit 20 (i.e., GOA2 shown in FIG. 2).
  • the reset signal line RSTn electrically connected to the first sub-pixel Pn in the nth row is electrically connected to the third gate driving circuit 30 (that is, GOA3 shown in FIG. 2 ).
  • FIG. 1 and FIG. 2 show that in every two adjacent rows of first sub-pixels, the reset signal line electrically connected to the first sub-pixel in one row and the gate line electrically connected to the first sub-pixel in another row are both Each is electrically connected to the same first gate driving circuit 10 as an example for description.
  • the gate lines electrically connected to the first sub-pixels in odd rows and the reset signal lines electrically connected to the first sub-pixels in even rows Is electrically connected to the same first gate driving circuit 10, the first target trace is a reset signal line, and the second target trace is a gate line as an example.
  • FIG. 3 shows another array substrate. Referring to FIG. 3, the gate line electrically connected to the first sub-pixels in one row and the reset signal line electrically connected to the first sub-pixels in the other row included in the array substrate 100 may be connected and electrically connected to the same first gate driving circuit 10 .
  • the gate line electrically connected to the first sub-pixel of one row is connected to the reset signal line electrically connected to the first sub-pixel of another row, the gate line or the reset signal line can be driven with the same first gate.
  • the circuit 10 is electrically connected.
  • a gate drive circuit 10 that is, with reference to FIG. 3, the gate line GATE1 electrically connected to the first sub-pixel P1 in the first row and the reset signal line RST2 electrically connected to the first sub-pixel P2 in the second row may be connected, and electrically connected to the first sub-pixel P1 through the gate line GATE1.
  • a first gate driving circuit 10 ie the first GOA1 shown in FIG.
  • the gate line GATE2 electrically connected to the first sub-pixel P2 in the second row is electrically connected to the first sub-pixel P3 in the third row
  • the reset signal line RST3 can be connected, and is electrically connected to the second first gate driving circuit 10 (that is, the second GOA1 shown in FIG. 3) through the gate line GATE2; and so on.
  • the gate lines electrically connected to the first sub-pixels of one row are electrically connected to the first sub-pixels of another row.
  • the reset signal line may be electrically connected to the same first gate driving circuit 10 only.
  • the gate line electrically connected to the first sub-pixels of one row and the reset signal line electrically connected to the first sub-pixels of another row may both be electrically connected to the two first gate driving circuits 10.
  • the two first gate driving circuits 10 electrically connected to the first sub-pixels in every two adjacent rows may be oppositely disposed at both ends of the first sub-pixels in two adjacent rows.
  • the first target trace electrically connected to the first sub-pixel located in the first row can also be electrically connected to the two second gate drive circuits 20, and the second target trace electrically connected to the first sub-pixel located in the bottom row
  • the wire may also be electrically connected to the two third gate driving circuits 30.
  • FIG. 4 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present application.
  • the gate line GATE1 electrically connected to the first sub-pixel P1 in the first row and the reset signal line RST2 electrically connected to the first sub-pixel P2 in the second row are both connected to those provided on the left and right sides of the array substrate 100.
  • the two first gate driving circuits 10 that is, the two GOA1 shown in FIG.
  • the reset signal lines RST3 are electrically connected to the two first gate driving circuits 10 (that is, the other two GOA1 shown in FIG. 4) provided on the left and right sides of the array substrate; and so on.
  • the reset signal line RST1 electrically connected to the first sub-pixel P1 in the first row is opposite to the two second gate driving circuits 20 (that is, the two GOA2 shown in FIG. 4) disposed on the left and right sides of the array substrate 100. Electric connection.
  • the gate line GATEn electrically connected to the first sub-pixel Pn in the last row is electrically connected to two third gate driving circuits 30 (that is, the two GOA3 shown in FIG. 4) disposed on the left and right sides of the array substrate 100 opposite to each other.
  • the signal line provides a signal to the first sub-pixel in the row to drive the first sub-pixel in the row to emit light.
  • both one end and the other end of the first sub-pixel in the row can emit light at the same time, which improves the driving efficiency of driving the first sub-pixel in each row.
  • the driving efficiency is improved significantly.
  • FIG. 5 is a schematic structural diagram of still another array substrate provided by an embodiment of the present application.
  • the array substrate 100 may further include:
  • a plurality of light emission control signal lines (n light emission control signal lines EM1 to EMn as shown in FIG. 5) are located in the display area and the peripheral area (not shown in FIG. 5). Wherein, multiple rows of first sub-pixels (n rows of first sub-pixels P1 to Pn as shown in FIG. 5) may be electrically connected to multiple light emitting control signal lines (such as EM1 to EMn) in a one-to-one correspondence.
  • the first sub-pixel P1 in the first row is electrically connected to the first light-emitting control signal line EM1; the first sub-pixel P2 in the second row is electrically connected to the second light-emitting control signal line EM2; the first sub-pixel P3 in the third row It is electrically connected to the light-emitting control signal line EM3; and so on.
  • the light-emitting control signal line electrically connected to the first sub-pixel in each row may be electrically connected to a light-emitting drive circuit 40, and the light-emitting control signal line electrically connected to the first sub-pixel in each row is The light-emitting drive circuit 40 electrically connected to the signal line is different.
  • Each light-emitting driving circuit 40 can provide a light-emitting control signal to its electrically connected light-emitting control signal line, and the first sub-pixel can then emit light in response to the light-emitting control signal.
  • the light-emitting drive circuit can also be provided on the outside of the array substrate independently of the array substrate, or the light-emitting drive circuit 40 can be provided on the array substrate. That is, in conjunction with FIG. 5, the array substrate 100 may include:
  • the light-emitting drive circuit 40 is located in the peripheral area A2.
  • the light-emitting drive circuit 40 can also be referred to as a light-emitting (emmision on array, EOA) control unit fabricated on the array substrate.
  • EOA light-emitting
  • FIG. 5 the drawings involved in the embodiments of the present application all use EOA 40 to represent the light-emitting drive circuit 40.
  • the light-emitting control signal lines electrically connected to the first sub-pixels in multiple rows may be electrically connected to the same light-emitting driving circuit, and electrically connected to the first sub-pixels of the same light-emitting driving circuit. Located in different rows.
  • FIG. 6 is a schematic structural diagram of still another array substrate provided by an embodiment of the present application.
  • the first sub-pixels in every three adjacent rows may be electrically connected to the same light-emitting drive circuit (ie, one EOA 40 shown in FIG. 6).
  • FIG. 6 also only takes the first sub-pixel P1 in the first row, the first sub-pixel P2 in the second row, and the first sub-pixel P3 in the third row as examples.
  • each light-emitting drive circuit 40 namely, EOA 40 may also be arranged on the array substrate along the extending direction perpendicular to the gate line, and adjacent EOA 40 may be cascaded.
  • each light-emitting drive circuit can sequentially provide signals to the light-emitting control signal line EM electrically connected to it in the order of arrangement.
  • each row of first sub-pixels may include multiple first sub-pixels (in FIGS. 1 to 6 each first sub-pixel is shown by a long square), and
  • the plurality of first sub-pixels may include a red sub-pixel capable of emitting red color light, a green sub-pixel capable of emitting green color light, and a blue sub-pixel capable of emitting blue color light, and the structure of each first sub-pixel may be the same.
  • FIG. 7 shows a schematic structural diagram of a first sub-pixel provided in an embodiment of the present application.
  • FIG. 8 shows a schematic structural diagram of another first sub-pixel provided by an embodiment of the present application.
  • the first sub-pixel may include: a pixel circuit 01 and a light-emitting unit 02 electrically connected to the pixel circuit 01.
  • the pixel circuit 01 may be electrically connected to the gate line GATE1, the reset signal line RST1, and the light-emitting unit 02, respectively.
  • the pixel circuit 01 can drive the light-emitting unit 02 to emit light in response to the gate driving signal provided by the gate line GATE1 and the reset signal provided by the reset signal line RST1.
  • the reset signal line RST1 electrically connected to the pixel circuit 01 can first provide a reset signal to reset the pixel circuit 01; then the gate line GATE1 electrically connected to the pixel circuit 01 can provide a gate driving signal again. And when the gate line GATE1 provides a gate drive signal, the reset signal line RST1 no longer provides a reset signal, and the light-emitting unit 02 emits light in response to the gate drive signal.
  • the pixel circuit 01 can also be electrically connected to a data signal line that provides a data signal.
  • the gate line GATE1 provides a gate driving signal
  • the data signal can be output to the light-emitting unit 02 to drive the light-emitting unit 02 to emit light.
  • the pixel circuit may also be electrically connected to the light emission control signal line EM1.
  • the pixel circuit 01 can also drive the light-emitting unit to emit light in response to the gate drive signal, the reset signal, and the light-emission control signal provided by the light-emission control signal line EM1.
  • the light-emission control signal line may provide the light-emission control signal to the pixel circuit after the gate line to which it is electrically connected provides a gate drive signal to it. By further setting the light-emitting control signal line, the reliable driving of the light-emitting unit 02 can be ensured.
  • the pixel circuit provided by the embodiments of the present application can have a structure of 7T1C (that is, including 7 transistors and 1 capacitor), or other structures, such as 9T2C (that is, including 9 transistors and 2 capacitors). Capacitor), the embodiment of the present application does not limit the specific structure of the pixel circuit.
  • FIG. 9 is a schematic diagram of a partial layout (left partial) of an array substrate provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a partial layout (partial right) of an array substrate provided by an embodiment of the present application.
  • the reset signal line RST1 electrically connected to the first sub-pixel in the first row of the display area is electrically connected to the first gate driving circuit; the first sub-pixel in the first row is electrically connected
  • the gate drive circuit is electrically connected.
  • the other lines are the same, so I won't repeat them here.
  • the left and right sides of the array substrate shown in FIG. 9 and FIG. 10 are arc-shaped, and the array substrate may also include:
  • the pixel P0 is located in the peripheral area (the peripheral area is not shown in FIGS. 9 and 10) and is located on the side of the second gate driving circuit 20 away from the first gate driving circuit 10.
  • the multiple rows of second sub-pixels P0 may not be Luminous pixels. Since the second sub-pixel P0 does not emit light, the second sub-pixel P0 may also be referred to as a dummy sub-pixel.
  • the embodiment of the present application provides an array substrate. Combining the electrical connection relationship of the first sub-pixel, each signal line and the gate drive circuit of the array substrate, it can be seen that during normal operation, each gate drive circuit can be flexibly controlled to provide signals to the signal lines that are electrically connected to it.
  • the first sub-pixel is reliably driven row by row.
  • the array substrate can not only display normally, but also has a simpler design.
  • FIG. 11 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • the display panel may include: a packaging cover 200 and an array substrate 100 as shown in FIGS. 1 to 6, 9 and 10.
  • FIG. 12 is a schematic structural diagram of a display panel provided by an embodiment of the present application. As shown in FIG. 12, the display panel may include: a driving circuit 001, and a display panel 002 as shown in FIG. 11.
  • the driving circuit 001 can be electrically connected to the display panel 002, and the driving circuit 001 can be used to drive the display panel to work.
  • the driving circuit may be a source driving circuit.
  • the display device can be an AMOLED display device, a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

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Abstract

本申请提供了一种阵列基板、显示面板及显示装置，属于显示技术领域。该阵列基板显示区域内仅包括能够发光的第一子像素，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，与相同的第一栅极驱动电路电连接；首行第一子像素所电连接的目标走线(即除电连接至第一栅极驱动电路的走线外的另一走线)与第二栅极驱动电路电连接，末行第一子像素所电连接的目标走线(即除电连接至第一栅极驱动电路的走线外的另一走线)与第三栅极驱动电路电连接。该阵列基板不仅设计简单，且能够实现正常显示。

Description

阵列基板、显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板、显示面板及显示装置。
背景技术
有源矩阵发光二极管(active matrix organic light emitting diode，AMOLE D)因其自发光、对比度高和色域广等优点被广泛应用于目前的显示领域中。
发明内容
本申请提供了一种阵列基板、显示面板及显示装置，所述技术方案如下：
一方面，提供了一种阵列基板，包括：
衬底基板，具有显示区域和围绕所述显示区域的周边区域；
多行第一子像素，位于所述显示区域，所述多行第一子像素为发光像素且所述多行第一子像素的边界为所述显示区域的边界；
多条栅线，位于所述显示区域和所述周边区域，所述多行第一子像素与所述多条栅线电连接；
多条复位信号线，位于所述显示区域和所述周边区域，所述多行第一子像素与所述多条复位信号线电连接；
每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，与相同的第一栅极驱动电路电连接；
位于首行的第一子像素所连接的第一目标走线与第二栅极驱动电路电连接；位于末行的第一子像素所连接的第二目标走线与第三栅极驱动电路电连接；
其中，所述第一目标走线和所述第二目标走线中的一个目标走线为所述多条栅线中的一条，另一个目标走线为所述多条复位信号线中的一条。
可选的，所述多行第一子像素与所述多条栅线一一对应电连接，且所述多行第一子像素与所述多条复位信号线一一对应电连接。
可选的，每相邻两行第一子像素中，奇数行第一子像素所电连接的栅线和偶数行第一子像素所电连接的复位信号线，与相同的第一栅极驱动电路电连接；
所述第一目标走线为所述多条复位信号线中的一条，所述第二目标走线为所述多条栅线中的一条。
可选的，每相邻两行第一子像素中，奇数行第一子像素所电连接的复位信号线和偶数行第一子像素所电连接的栅线，与相同的第一栅极驱动电路电连接；
所述第一目标走线为所述多条栅线中的一条，所述第二目标走线为所述多条复位信号线中的一条。
可选的，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线相连，并与相同的第一栅极驱动电路电连接。
可选的，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线相连，并通过所述栅线与相同的第一栅极驱动电路电连接。
可选的，所述阵列基板包括：
多个所述第一栅极驱动电路，位于所述周边区域；
所述第二栅极驱动电路，位于所述周边区域，且位于多个所述第一栅极驱动电路的一侧；
所述第三栅极驱动电路，位于所述周边区域，且位于所述多个第一栅极驱动电路远离所述第二栅极驱动电路的一侧。
可选的，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，与同一个所述第一栅极驱动电路电连接。
可选的，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，均与两个所述第一栅极驱动电路电连接。
可选的，每相邻两行第一子像素所电连接的两个所述第一栅极驱动电路，相对设置于所述相邻两行第一子像素的两端。
可选的，位于首行的第一子像素所电连接的第一目标走线与两个所述第二栅极驱动电路电连接，位于末行的第一子像素所电连接的第二目标走线与两个所述第三栅极驱动电路电连接。
可选的，所述阵列基板还包括：
多条发光控制信号线，位于所述显示区域与所述周边区域，所述多行第一 子像素与所述多条发光控制信号线一一对应电连接。
可选的，每行第一子像素所电连接的发光控制信号线与一个发光驱动电路电连接，且各行第一子像素所电连接的发光控制信号线电连接的发光驱动电路不同。
可选的，多行第一子像素所电连接的发光控制信号线与同一个发光驱动电路电连接，且电连接至同一个发光驱动电路的第一子像素位于不同行。
可选的，所述阵列基板包括：所述发光驱动电路，位于所述周边区域。
可选的，每个所述第一子像素包括：像素电路以及与所述像素电路电连接的发光单元；
所述像素电路分别与所述栅线、所述复位信号线和所述发光单元电连接，所述像素电路用于响应于所述栅线提供的栅极驱动信号以及所述复位信号线提供的复位信号，驱动所述发光单元发光。
可选的，所述像素电路还与所述发光控制信号线电连接；
所述像素电路用于响应于所述栅极驱动信号、所述复位信号以及所述发光控制信号线提供的发光控制信号，驱动所述发光单元发光。
可选的，所述阵列基板还包括：
多行第二子像素，位于所述周边区域且位于所述第二栅极驱动电路远离所述第一栅极驱动电路的一侧，所述多行第二子像素为不发光像素。
另一方面，提供了一种显示面板，所述显示面板包括：封装盖板，以及如上述方面所述的阵列基板。
又一方面，提供了一种显示装置，所述显示装置包括：驱动电路，以及如上述方面所述的显示面板，所述驱动电路与所述显示面板电连接，所述驱动电路用于驱动所述显示面板工作。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种阵列基板的结构示意图；
图2是本申请实施例提供的另一种阵列基板的结构示意图；
图3是本申请实施例提供的又一种阵列基板的结构示意图；
图4是本申请实施例提供的再一种阵列基板的结构示意图；
图5是本申请实施例提供的再一种阵列基板的结构示意图；
图6是本申请实施例提供的再一种阵列基板的结构示意图；
图7是本申请实施例提供的一种第一子像素的结构示意图；
图8是本申请实施例提供的另一种第一子像素的结构示意图；
图9是本申请实施例提供的一种阵列基板的版图局部示意图；
图10是本申请实施例提供的另一种阵列基板的版图局部示意图；
图11是本申请实施例提供的一种显示面板的结构示意图；
图12是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
目前，为了保证阵列基板显示区域包括的多行能够发光的显示子像素(pixel)中，各行显示子像素所电连接的复位信号线(reset line)上的负载(loading)差异较小，即使得阵列基板包括的各条复位信号线均处于相同的工作环境下，一般会在显示区域的顶部，即显示区域的边界处，设置一行与首行第一子像素相邻的不能够发光的虚设子像素(dummy pixel)，并设置一条栅线(gate line)与该行虚设子像素电连接。
通过该设置结构，可以使得当每相邻两行显示子像素中，奇数行显示子像素所电连接的复位信号线和偶数行显示子像素所电连接的栅线与相同的栅极驱动电路电连接时，首行显示子像素所电连接的复位信号线也能够与其相邻的虚设子像素所电连接的栅线，与相同的栅极驱动电路电连接。进而即保证了各行显示子像素所电连接的复位信号线均处于相同的工作环境下。另外，一般还会设置除栅线外的其他信号线(如，发光控制信号线emmision line)与虚设子像素电连接，相应的，为了保证虚设子像素所电连接的其他信号线的工作稳定性，还会设置提供直流信号的直流信号端电连接至其他信号线。
但是，因虚设子像素的设置以及电连接至虚设子像素的信号线的引入，使得阵列基板的设计较为复杂。然而，随着显示技术的发展，像素包括的像素电路的结构也变得越来越复杂，对于阵列基板的空间利用要求越来越高，为了在 有限的空间内实现更好的设计，一些简单有效的布局变得十分重要。本申请实施例提供了一种阵列基板，该阵列基板不仅能够保证对正常显示不造成影响，而且该阵列基板上的布线较少，设计较为简单，制造成本较低。
图1是本申请实施例提供的一种阵列基板的结构示意图。如图1所示，该阵列基板可以包括：
衬底基板01，具有显示区域A1和围绕显示区域A1的周边区域A2。
多行第一子像素(如图1示出的n行第一子像素P1至Pn)，位于显示区域A1，该多行第一子像素为发光像素且多行第一子像素的边界为显示区域A1的边界，即显示区域A1为多行第一子像素的外边缘轮廓。n为大于0的整数。由于第一子像素为发光像素，因此该第一子像素也可以称为显示子像素。
多条栅线(如图1示出的n条栅线GATE1至GATEn)，位于显示区域A1和周边区域A2，多行第一子像素可以与多条栅线电连接。
多条复位信号线(如图1示出的n条复位信号线RST1至RSTn)，位于显示区域A1和周边区域A2，多行第一子像素可以与多条复位信号线电连接。
每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，可以与相同的第一栅极驱动电路10电连接。
位于首行的第一子像素所连接的第一目标走线可以与第二栅极驱动电路20电连接；位于末行的第一子像素所连接的第二目标走线可以与第三栅极驱动电路30电连接。其中，第一目标走线和第二目标走线中的一个目标走线可以为多条栅线中的一条，另一个目标走线可以为多条复位信号线中的一条。
例如，继续参考图1，其示出的阵列基板中，第一目标走线为多条复位线中的第一条复位信号线RST1。第二目标走线L2为多条栅线中的最后一条栅线GATEn。且，第一行第一子像素P1与第一条栅线GATE1和第一条复位信号线RST1对应电连接；第二行第一子像素P2与第二条栅线GATE2和第二条复位信号线RST2对应电连接；第三行第一子像素P3与第三条栅线GATE3和第三条复位信号线RST3对应电连接；以此类推。
第一行第一子像素P1所电连接的栅线GATE1和第二行第一子像素P2所电连接的复位信号线RST2，与相同的一个第一栅极驱动电路10电连接；第二行第一子像素P2所电连接的栅线GATE2和第三行第一子像素P3所电连接的复位信号线RST3，与相同的另一个第一栅极驱动电路10电连接；以此类推，直至 第n-1行第一子像素P(n-1)所电连接的栅线GATE(n-1)与第n行第一子像素Pn所电连接的复位信号线RSTn，与相同的最后一个第一栅极驱动电路10电连接。
第一行第一子像素P1所电连接的复位信号线RST1(即第一目标走线)与第二栅极驱动电路20电连接。第n行第一子像素Pn所电连接的栅线GATEn(即第二目标走线)与第三栅极驱动电路30电连接。
且，为了保证正常驱动，位于不同行的第一子像素所电连接的复位信号线，即不同的复位信号线所电连接的栅极驱动电路可以不同；位于不同行的第一子像素所电连接的栅线，即不同的栅线所电连接的栅极驱动电路可以不同。如，继续参考图1，第一行第一子像素P1所电连接的复位信号线RST1与第二栅极驱动电路20连接，第二行第一子像素P2所电连接的复位信号线RST2与一个第一栅极驱动电路10连接，第三行第一子像素P3所电连接的复位信号线RST3与另一个第一栅极驱动电路10连接，以此类推。第一行第一子像素P1所电连接的栅线GATE1与一个第一栅极驱动电路10连接，第二行第一子像素P1所电连接的栅线GATE2与另一个第一栅极驱动电路10连接，以此类推。
在本申请实施例中，各栅极驱动电路可以通过其所电连接的信号线，为信号线所电连接的第一子像素提供信号，以驱动第一子像素发光。例如，结合图1所示的阵列基板，为保证正常显示，可以先控制第二栅极驱动电路20通过其所电连接的复位信号线RST1，向首行第一子像素P1输出复位信号，实现对首行第一子像素P1的复位；然后，再控制第一个第一栅极驱动电路10通过其所电连接的栅线GATE1，向首行第一子像素P1输出栅极驱动信号，以驱动首行第一子像素P1发光。与此同时，第一个第一栅极驱动电路10还可以通过其所电连接的复位信号线RST2，向第二行第一子像素P2输出复位信号，实现对第二行第一子像素P2的复位。再然后，控制第二个第一栅极驱动电路10通过其所电连接的栅线GATE2，向第二行第一子像素P2输出栅极驱动信号，以驱动第二行第一子像素P2发光。与此同时，第二个第一栅极驱动电路10还可以通过其所电连接的复位信号线RST3，向第三行第一子像素P3输出复位信号，实现对第三行第一子像素P3的复位，以此类推，其他行的驱动不再赘述。通过该驱动方式，可以可靠实现对各行第一子像素的逐行驱动。
综上所述，本申请实施例提供了一种阵列基板。结合该阵列基板的第一子像素、各信号线和栅极驱动电路的电连接关系可知，在正常工作时，可以通过 控制各栅极驱动电路灵活向其电连接的信号线提供信号，实现对第一子像素的逐行可靠驱动。且由于该阵列基板显示区域内未设置不发光的虚设子像素，因此相对于相关技术的阵列基板，该阵列基板不仅能正常显示，且设计较为简单。
可选的，在本申请实施例中，结合图1，多行第一子像素可以多条栅线一一对应电连接，且多行第一子像素可以多条复位信号线一一对应电连接，且各栅极驱动电路(即第二栅极驱动电路20、各第一栅极驱动电路10和第三栅极驱动电路30)可以独立于阵列基板设置在阵列基板外侧。或者，各栅极驱动电路也可以设置于阵列基板上。即，如图2所示，该阵列基板还可以包括：
多个第一栅极驱动电路10，位于衬底基板01的周边区域A2。第二栅极驱动电路20，位于衬底基板01的周边区域A2，且位于多个第一栅极驱动电路10的一侧。第三栅极驱动电路30，位于衬底基板01的周边区域A2，且位于多个第一栅极驱动电路10远离所述第二栅极驱动电路20的一侧。相应的，每个栅极驱动电路也可以称为制作在阵列基板上的电路(gate on array，GOA)单元。
通过将栅极驱动电路设置于阵列基板上，有利于窄边框设计。下述实施例均以各栅极驱动电路设置于阵列基板上为例进行说明，且图2和下述实施例涉及到的附图均以GOA1表示第一栅极驱动电路10，以GOA2表示第二栅极驱动电路20称为，以GOA3表示第三栅极驱动电路30。
可选的，结合图2，本申请实施例提供的第二栅极驱动电路20、各个第一栅极驱动电路10以及第三栅极驱动电路30可以沿垂直于栅线的延伸方向依次排列于阵列基板上。且，每相邻两个栅极驱动电路可以级联(图中未示出)，并按级联顺序依次启动。由第二栅极驱动电路20、各个第一栅极驱动电路10和第三栅极驱动电路30组成的电路可以称为栅极驱动装置。
需要说明的是，对于栅极驱动装置包括的各栅极驱动电路而言，可以从第二栅极驱动电路20开始依次工作，即栅极驱动装置可以从首行第一子像素开始逐行驱动阵列基板包括的多行第一子像素，该扫描方式也可以称为正向扫描。此外，栅极驱动装置还可以从第三栅极驱动电路30开始依次工作，即栅极驱动装置可以从末行第一子像素开始逐行驱动阵列基板包括的多行第一子像素，该扫描方式也可以称为反向扫描。
若要实现正常驱动，对于正向扫描而言，需要先通过首行第一子像素电连接的复位信号线向首行第一子像素提供复位信号；对于反向扫描而言，需要先 通过末行像素电连接的复位信号线向末行第一子像素提供复位信号。结合各栅极驱动电路的排布级联方式，为了保证逐行可靠驱动，在正向扫描场景下，第二栅极驱动电路20需要电连接至首行第一子像素所电连接的复位信号线；在反向扫描场景下，第三栅极驱动电路30需要电连接至末行第一子像素所电连接的复位信号线。
因此，作为一种可选的实现方式，结合图1，每相邻两行第一子像素中，奇数行第一子像素所电连接的栅线和偶数行第一子像素所电连接的复位信号线，可以与相同的第一栅极驱动电路10电连接。相应的，参考图1，第一目标走线即可以为多条复位线中的一条复位信号线(如图1示出的RST1)，第二目标走线即可以为多条栅线中的一条栅线(如图1示出的GATEn)。
结合上述各栅极驱动电路的级联关系、排布方式和驱动原理可知，对于图1示出的阵列基板结构，栅极驱动装置可以通过正向扫描的方式实现对各行第一子像素的逐行驱动。且相对于相关技术，由于该阵列基板的显示区域边界处未设置虚设子像素，因此在保证正常显示前提下，有效节省了顶部空间。另外，因未设置虚设子像素，则阵列基板内也无需设置电连接至虚设子像素的信号线，即简化了布线。
作为另一种可选的实现方式，继续参考图2，每相邻两行第一子像素中，奇数行第一子像素所电连接的复位信号线和偶数行第一子像素所电连接的栅线，可以与相同的第一栅极驱动电路10电连接。相应的，参考图2，第一目标走线即可以为多条栅线中的一条栅线(如图2示出的GATE1)，第二目标走线即可以为多条复位信号线中的一条复位信号线(如图2示出的RSTn)。
例如，图2继续以包括n行第一子像素P1至Pn，n条栅线GATE1至GATEn，n条复位信号线RST1至RSTn为例示出一种阵列基板。参考图2，该阵列基板中，第一行第一子像素P1所电连接的复位信号线RST1和第二行第一子像素P2所电连接的栅线GATE2，与相同的一个第一栅极驱动电路10(即图2示出的第一个GOA1)电连接。第二行第一子像素P2所电连接的复位信号线RST2和第三行第一子像素P3所电连接的栅线GATE3，与相同的另一个第一栅极驱动电路10(即图2示出的第二个GOA1)电连接；以此类推，直至第n-1行第一子像素P(n-1)所电连接的复位信号线RST(n-1)与第n行第一子像素Pn所电连接的栅线GATEn，与相同的最后一个第一栅极驱动电路10(即图2示出的最后一个GOA1)电连接。且首行第一子像素P1所电连接的栅线GATE1与第二栅极驱动 电路20(即图2示出的GOA2)电连接。第n行第一子像素Pn所电连接的复位信号线RSTn与第三栅极驱动电路30(即图2示出的GOA3)电连接。
结合上述各栅极驱动电路的级联关系、排布方式和驱动原理可知，对于图2示出的阵列基板结构，栅极驱动装置可以通过反向扫描的方式实现对各行第一子像素的逐行驱动。
可选的，图1和图2均是以每相邻两行第一子像素中，一行第一子像素所电连接的复位信号线和另一行第一子像素所电连接的栅线，均各自分别电连接至相同的第一栅极驱动电路10为例进行说明。
然而为进一步简化走线设计，节省设计成本，以每相邻两行第一子像素中，奇数行第一子像素所电连接的栅线和偶数行第一子像素所电连接的复位信号线，与相同的第一栅极驱动电路10电连接，第一目标走线为复位信号线，第二目标走线为栅线为例，图3示出了又一种阵列基板。参考图3，阵列基板100包括的一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线可以相连，并与相同的第一栅极驱动电路10电连接。
且，可选的，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线相连后，可以通过栅线或复位信号线与相同的第一栅极驱动电路10电连接。
例如，图3示出的阵列基板100中，奇数行第一子像素所电连接的栅线和偶数行第一子像素所电连接的复位信号线相连后，可以均通过栅线电连接至第一栅极驱动电路10。即，结合图3，第一行第一子像素P1所电连接的栅线GATE1和第二行第一子像素P2所电连接的复位信号线RST2可以相连，并通过栅线GATE1电连接至第一个第一栅极驱动电路10(即图3示出的第一个GOA1)；第二行第一子像素P2所电连接的栅线GATE2和第三行第一子像素P3所电连接的复位信号线RST3可以相连，并通过栅线GATE2电连接至第二个第一栅极驱动电路10(即图3示出的第二个GOA1)；以此类推。
可选的，在本申请实施例中，结合图1至图3，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，可以仅与同一个第一栅极驱动电路10电连接。
或者，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，可以均与两个第一栅极驱动电路10电连接。且，可选的，每相邻两行第一子像素所电连接的两个第一栅极驱动电路10，可以相对设置于相邻两行 第一子像素的两端。另外，位于首行的第一子像素所电连接的第一目标走线也可以与两个第二栅极驱动电路20电连接，位于末行的第一子像素所电连接的第二目标走线也可以与两个第三栅极驱动电路30电连接。
例如，图4是本申请实施例提供的再一种阵列基板的结构示意图。如图4所示，第一行第一子像素P1所电连接的栅线GATE1和第二行第一子像素P2所电连接的复位信号线RST2，均与设置在阵列基板100左右两侧的两个第一栅极驱动电路10(即图4示出的两个GOA1)电连接；第二行第一子像素P2所电连接的栅线GATE2和第三行第一子像素P3所电连接的复位信号线RST3，均与设置在阵列基板左右两侧的两个第一栅极驱动电路10(即图4示出的另两个GOA1)电连接；以此类推。且，第一行第一子像素P1所电连接的复位信号线RST1，与相对设置于阵列基板100左右两侧的两个第二栅极驱动电路20(即图4示出的两个GOA2)电连接。最后一行第一子像素Pn所电连接的栅线GATEn，与相对设置于阵列基板100左右两侧的两个第三栅极驱动电路30(即图4示出的两个GOA3)电连接。
对于每行第一子像素而言，通过设置该行第一子像素所电连接的信号线均与两个栅极驱动电路电连接，可以控制两个栅极驱动电路同时通过其所电连接的信号线，向该行第一子像素提供信号以驱动该行第一子像素发光。相应的，即可以保证沿栅线延伸方向，该行第一子像素的一端和另一端均可以同时发光，提高了对每行第一子像素进行驱动的驱动效率。针对分辨率较高的阵列基板(即每行包括的第一子像素数量较多的阵列基板)，驱动效率提高较为明显。
可选的，图5是本申请实施例提供的再一种阵列基板的结构示意图。如图5所示，该阵列基板100还可以包括：
多条发光控制信号线(如图5示出的n条发光控制信号线EM1至EMn)，位于显示区域与周边区域(图5未示出)。其中，多行第一子像素(如图5示出的n行第一子像素P1至Pn)可以与多条发光控制信号线(如EM1至EMn)一一对应电连接。
例如，第一行第一子像素P1与第一条发光控制信号线EM1电连接；第二行第一子像素P2与第二条发光控制信号线EM2电连接；第三行第一子像素P3与发光控制信号线EM3电连接；以此类推。
作为一种可选的实现方式，继续参考图5，每行第一子像素所电连接的发光控制信号线可以与一个发光驱动电路40电连接，且各行第一子像素所电连接的 发光控制信号线电连接的发光驱动电路40不同。每个发光驱动电路40可以为其所电连接的发光控制信号线提供发光控制信号，第一子像素可以再响应于该发光控制信号发光。
需要说明的是，与栅极驱动电路同理，该发光驱动电路也可以独立于阵列基板设置在阵列基板外侧，或者，该发光驱动电路40可以设置于阵列基板上。即，结合图5，该阵列基板100可以包括：
发光驱动电路40，位于周边区域A2。相应的，发光驱动电路40也可以称为制作在阵列基板上的发光(emmision on array，EOA)控制单元。结合图5，本申请实施例涉及到的附图均以EOA 40表示发光驱动电路40。通过将发光驱动电路40设置于阵列基板的周边区域A2上，也有利于窄边框设计。
或者，作为另一种可选的实现方式，多行第一子像素所电连接的发光控制信号线可以与同一个发光驱动电路电连接，且电连接至同一个发光驱动电路的第一子像素位于不同行。
例如，图6是本申请实施例提供的再一种阵列基板的结构示意图。如图6所示，其示出的阵列基板100中，每相邻三行第一子像素可以与同一个发光驱动电路(即图6示出的一个EOA 40)电连接。且，图6也仅以第一行第一子像素P1、第二行第一子像素P2和第三行第一子像素P3为例示出。通过设置多行第一子像素与同一个发光驱动电路电连接，进一步简化了设计。
需要说明的是，结合图5，各发光驱动电路40，即EOA 40也可以沿垂直于栅线的延伸方向排布于阵列基板上，且相邻的EOA 40可以级联。相应的，各发光驱动电路可以按排布顺序依次向其所电连接的发光控制信号线EM提供信号。
可选的，结合上述图1至图6可以看出，每行第一子像素可以包括多个第一子像素(图1至图6均以长方块示出每个第一子像素)，且该多个第一子像素可以包括能够发出红颜色光的红色子像素、能够发出绿颜色光的绿色子像素以及能够发出蓝颜色光的蓝色子像素，各第一子像素的结构可以相同。
以位于第一行中第一列的第一子像素为例，图7示出了本申请实施例提供的一种第一子像素的结构示意图。图8示出了本申请实施例提供的另一种第一子像素的结构示意图。参考图7和图8可以看出，该第一子像素可以包括：像素电路01以及与像素电路01电连接的发光单元02。
作为一种可选的实现方式，参考图7，该像素电路01可分别与栅线GATE1、复位信号线RST1和发光单元02电连接。该像素电路01可以响应于栅线GATE1 提供的栅极驱动信号以及复位信号线RST1提供的复位信号，驱动发光单元02发光。例如在正常驱动时，该像素电路01电连接的复位信号线RST1可以先提供复位信号，从而实现对像素电路01的复位；然后像素电路01电连接的栅线GATE1可以再提供栅极驱动信号，且在栅线GATE1提供栅极驱动信号时，复位信号线RST1不再提供复位信号，发光单元02响应于栅极驱动信号发光。
可选的，像素电路01还可以与提供数据信号的数据信号线电连接，在栅线GATE1提供栅极驱动信号时，数据信号可以输出至发光单元02，从而驱动发光单元02发光。
作为另一种可选的实现方式，参考图8，该像素电路还可以与发光控制信号线EM1电连接。相应的，该像素电路01还可以响应于栅极驱动信号、复位信号以及发光控制信号线EM1提供的发光控制信号，驱动发光单元发光。
需要说明的是，对于每个像素电路而言，发光控制信号线可以在其所电连接的栅线向其提供栅极驱动信号后，再提供发光控制信号至像素电路。通过再设置发光控制信号线，可以保证对发光单元02的可靠驱动。
还需要说明的是，本申请实施例提供的像素电路可以为7T1C(即包括7个晶体管和1个电容器)的结构，或者，也可以为其他结构，如9T2C(即包括9个晶体管和2个电容器)，本申请实施例对像素电路的具体结构不作限定。
图9是本申请实施例提供的一种阵列基板的局部版图(左局部)示意图。图10是本申请实施例提供的一种阵列基板的局部版图(右局部)示意图。
结合图9和图10可以看出，位于显示区域的第一行第一子像素所电连接的复位信号线RST1与第一个栅极驱动电路电连接；第一行第一子像素所电连接的发光控制信号线EM1与第一个发光驱动电路电连接；第一行第一子像素所电连接的栅线GATE1与第二行第一子像素所电连接的复位信号线RST2，与同一个栅极驱动电路电连接。其他行同理，在此不再赘述。
除此之外，还可以看出，图9和图10示出的阵列基板左右两侧均为圆弧形，且该阵列基板还可以包括：不与任何信号线电连接的多行第二子像素P0，位于周边区域(图9和图10未示出周边区域)且位于第二栅极驱动电路20远离第一栅极驱动电路10的一侧，该多行第二子像素P0可以为不发光像素。由于该第二子像素P0不发光，因此该第二子像素P0也可以称为虚设子像素。
综上所述，本申请实施例提供了一种阵列基板。结合该阵列基板的第一子像素、各信号线和栅极驱动电路的电连接关系可知，在正常工作时，可以通过 控制各栅极驱动电路灵活向其电连接的信号线提供信号，实现对第一子像素的逐行可靠驱动。且由于该阵列基板显示区域内未设置不发光的虚设子像素，因此相对于相关技术的阵列基板，该阵列基板不仅能正常显示，且设计较为简单。
图11是本申请实施例提供的一种显示面板的结构示意图。如图11所示，该显示面板可以包括：封装盖板200，以及如图1至图6、图9和图10所示的阵列基板100。
图12是本申请实施例提供了一种显示面板的结构示意图。如图12所示，该显示面板可以包括：驱动电路001，以及如图11所示的显示面板002。
其中，驱动电路001可以与显示面板002电连接，驱动电路001可以用于驱动显示面板工作。例如，该驱动电路可以为源极驱动电路。
可选的，该显示装置可以为AMOLED显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
应当理解的是，在本文中提及的“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种阵列基板，包括：
    衬底基板，具有显示区域和围绕所述显示区域的周边区域；
    多行第一子像素，位于所述显示区域，所述多行第一子像素为发光像素且所述多行第一子像素的边界为所述显示区域的边界；
    多条栅线，位于所述显示区域和所述周边区域，所述多行第一子像素与所述多条栅线电连接；
    多条复位信号线，位于所述显示区域和所述周边区域，所述多行第一子像素与所述多条复位信号线电连接；
    每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，与相同的第一栅极驱动电路电连接；
    位于首行的第一子像素所连接的第一目标走线与第二栅极驱动电路电连接；位于末行的第一子像素所连接的第二目标走线与第三栅极驱动电路电连接；
    其中，所述第一目标走线和所述第二目标走线中的一个目标走线为所述多条栅线中的一条，另一个目标走线为所述多条复位信号线中的一条。
  2. 根据权利要求1所述的阵列基板，其特征在于，所述多行第一子像素与所述多条栅线一一对应电连接，且所述多行第一子像素与所述多条复位信号线一一对应电连接。
  3. 根据权利要求1所述的阵列基板，其特征在于，每相邻两行第一子像素中，奇数行第一子像素所电连接的栅线和偶数行第一子像素所电连接的复位信号线，与相同的第一栅极驱动电路电连接；
    所述第一目标走线为所述多条复位信号线中的一条，所述第二目标走线为所述多条栅线中的一条。
  4. 根据权利要求1所述的阵列基板，其特征在于，每相邻两行第一子像素中，奇数行第一子像素所电连接的复位信号线和偶数行第一子像素所电连接的栅线，与相同的第一栅极驱动电路电连接；
    所述第一目标走线为所述多条栅线中的一条，所述第二目标走线为所述多 条复位信号线中的一条。
  5. 根据权利要求1至4任一所述的阵列基板，其特征在于，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线相连，并与相同的第一栅极驱动电路电连接。
  6. 根据权利要求5所述的阵列基板，其特征在于，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线相连，并通过所述栅线与相同的第一栅极驱动电路电连接。
  7. 根据权利要求1至6任一所述的阵列基板，其特征在于，所述阵列基板包括：
    多个所述第一栅极驱动电路，位于所述周边区域；
    所述第二栅极驱动电路，位于所述周边区域，且位于多个所述第一栅极驱动电路的一侧；
    所述第三栅极驱动电路，位于所述周边区域，且位于所述多个第一栅极驱动电路远离所述第二栅极驱动电路的一侧。
  8. 根据权利要求1至7任一所述的阵列基板，其特征在于，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，与同一个所述第一栅极驱动电路电连接。
  9. 根据权利要求1至8任一所述的阵列基板，其特征在于，每相邻两行第一子像素中，一行第一子像素所电连接的栅线和另一行第一子像素所电连接的复位信号线，均与两个所述第一栅极驱动电路电连接。
  10. 根据权利要求9所述的阵列基板，其特征在于，每相邻两行第一子像素所电连接的两个所述第一栅极驱动电路，相对设置于所述相邻两行第一子像素的两端。
  11. 根据权利要求1至10任一所述的阵列基板，其特征在于，位于首行的第一子像素所电连接的第一目标走线与两个所述第二栅极驱动电路电连接，位于末行的第一子像素所电连接的第二目标走线与两个所述第三栅极驱动电路电连接。
  12. 根据权利要求1至11任一所述的阵列基板，其特征在于，所述阵列基板还包括：
    多条发光控制信号线，位于所述显示区域与所述周边区域，所述多行第一子像素与所述多条发光控制信号线一一对应电连接。
  13. 根据权利要求12所述的阵列基板，其特征在于，每行第一子像素所电连接的发光控制信号线与一个发光驱动电路电连接，且各行第一子像素所电连接的发光控制信号线电连接的发光驱动电路不同。
  14. 根据权利要求12所述的阵列基板，其特征在于，多行第一子像素所电连接的发光控制信号线与同一个发光驱动电路电连接，且电连接至同一个发光驱动电路的第一子像素位于不同行。
  15. 根据权利要求13或14所述的阵列基板，其特征在于，所述阵列基板包括：所述发光驱动电路，位于所述周边区域。
  16. 根据权利要求1至15任一所述的阵列基板，其特征在于，每个所述第一子像素包括：像素电路以及与所述像素电路电连接的发光单元；
    所述像素电路分别与所述栅线、所述复位信号线和所述发光单元电连接，所述像素电路用于响应于所述栅线提供的栅极驱动信号以及所述复位信号线提供的复位信号，驱动所述发光单元发光。
  17. 根据权利要求16所述的阵列基板，其特征在于，所述像素电路还与所述发光控制信号线电连接；
    所述像素电路用于响应于所述栅极驱动信号、所述复位信号以及所述发光 控制信号线提供的发光控制信号，驱动所述发光单元发光。
  18. 根据权利要求1至17任一所述的阵列基板，其特征在于，所述阵列基板还包括：
    多行第二子像素，位于所述周边区域且位于所述第二栅极驱动电路远离所述第一栅极驱动电路的一侧，所述多行第二子像素为不发光像素。
  19. 一种显示面板，其特征在于，所述显示面板包括：封装盖板，以及如权利要求1至18任一所述的阵列基板。
  20. 一种显示装置，其特征在于，所述显示装置包括：驱动电路，以及如权利要求19所述的显示面板，所述驱动电路与所述显示面板电连接，所述驱动电路用于驱动所述显示面板工作。
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CN109387962B (zh) * 2018-12-19 2021-08-13 上海天马微电子有限公司 液晶显示面板与液晶显示装置

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