WO2021190182A1 - 像素驱动电路、显示面板的驱动电路以及显示装置 - Google Patents

像素驱动电路、显示面板的驱动电路以及显示装置 Download PDF

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Publication number
WO2021190182A1
WO2021190182A1 PCT/CN2021/075712 CN2021075712W WO2021190182A1 WO 2021190182 A1 WO2021190182 A1 WO 2021190182A1 CN 2021075712 W CN2021075712 W CN 2021075712W WO 2021190182 A1 WO2021190182 A1 WO 2021190182A1
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Prior art keywords
sub
pixel
unit
pixel unit
units
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PCT/CN2021/075712
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English (en)
French (fr)
Inventor
王秀荣
时凌云
谷其兵
胡国锋
杨涛
王蒙蒙
刘文浩
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US17/431,182 priority Critical patent/US11727861B2/en
Publication of WO2021190182A1 publication Critical patent/WO2021190182A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B44/00—Circuit arrangements for operating electroluminescent light sources
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0205—Simultaneous scanning of several lines in flat panels
    • G09G2310/0208—Simultaneous scanning of several lines in flat panels using active addressing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology (for example, the field of computer technology), and in particular, to a pixel drive circuit, a drive circuit of a display panel, and a display device.
  • the field of display technology for example, the field of computer technology
  • Mini LED refers to an LED with a package size of 0.1-0.2mm, also known as a sub-millimeter light-emitting diode.
  • Mini LED displays are composed of a large number of small-sized LED arrays, with small spacing between LEDs, with high brightness, high contrast, ultra-high resolution and color saturation, and have gradually become a development direction of display technology.
  • embodiments of the present disclosure provide a pixel drive circuit, including a switch unit and a drive unit, the switch unit is connected to the drive unit, and the drive unit is configured to be connected to a plurality of sub-pixel units;
  • the switch unit is configured to receive the scan signal and the data signal, turn on under the action of the scan signal, and send the data signal to the drive unit;
  • the driving unit is configured to send data signals to the connected sub-pixel units in a time-sharing manner.
  • the switch unit includes a transistor, a gate of the transistor is configured to receive a scan signal, a first pole is configured to receive a data signal, and a second pole is configured to be connected to the driving unit.
  • the driving unit includes a control sub-unit, a multiple selection sub-unit and a plurality of holding sub-units, wherein:
  • the control sub-unit is set to connect to the switch unit, receive data signals, and output corresponding control signals under the action of the data signals;
  • the multiple selection subunit is set to be connected to the control subunit and the plurality of holding subunits, and under the action of the control signal, the corresponding channel is selected and the corresponding data signal is sent to the corresponding holding subunit;
  • the channels of the multiple selection sub-units are connected to the multiple holding sub-units in a one-to-one correspondence, and the multiple holding sub-units are connected to the multiple sub-pixel units in a one-to-one correspondence.
  • the number of sub-pixel units is set to three, and the three sub-pixel units include a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit of different colors;
  • the sub-pixel unit and the driving unit are arranged in two rows and two columns, the first sub-pixel unit and the second sub-pixel unit are located side by side in the first row, and the third sub-pixel unit and the driving unit are located side by side in the second row of the pixel unit.
  • three data signals are transmitted in one scan signal period.
  • the number of sub-pixel units is set to six, and the six sub-pixel units include a first sub-pixel unit, a second sub-pixel unit, a third sub-pixel unit, a fourth sub-pixel unit, and a fifth sub-pixel unit. And the sixth sub-pixel unit;
  • the sub-pixel unit and the driving unit are arranged in two rows and four columns.
  • the first sub-pixel unit, the second sub-pixel unit and the sixth sub-pixel unit are located side by side in the first row.
  • the third sub-pixel unit, the driving unit, and the fourth sub-pixel unit are arranged side by side.
  • the pixel unit and the fifth sub-pixel unit are located side by side in the second row.
  • six data signals are transmitted in a period of one scan signal.
  • embodiments of the present disclosure provide a drive circuit for a display panel, including pixel units arranged in an array, multiple scan lines, and multiple data lines, and each pixel unit includes the pixel drive provided by any embodiment of the present disclosure.
  • the scan line is located between adjacent row pixel units, and the data line is located between adjacent column pixel units.
  • the sub-pixel unit and the driving unit when the sub-pixel unit and the driving unit are arranged in two rows and two columns; two adjacent columns of pixel units located in the same row, the sub-pixel unit and the driving unit in the pixel unit of the nth column
  • the arrangement is a mirror image of the arrangement of sub-pixel units and drive units in the pixel unit of the (n+1)th column.
  • the mirror axis is located between the pixel unit of the (n+1)th column and the pixel unit of the nth column.
  • a straight line between and parallel to the row direction perpendicular to the column direction, where n ⁇ 1.
  • each row of pixel units is configured to be connected to two rows of scan lines, wherein one row of scan lines is configured to provide scan signals to pixel units in even columns, and the other row of scan lines is configured to provide pixel units in odd columns.
  • Scan signal one row of scan lines passes through the inside of the pixel unit.
  • the sub-pixel unit and the driving unit when the sub-pixel unit and the driving unit are arranged in two rows and four columns; two adjacent columns of pixel units located in the same row, the sub-pixel unit in the pixel unit of the nth column
  • the arrangement of the driving unit and the arrangement of the sub-pixel unit and the driving unit in the pixel unit of the (n+1)th column are mirror images of each other, and the mirror axis is located in the (n+1)th column of the pixel unit and the nth A straight line between column pixel units and parallel to the row direction perpendicular to the column direction, where n ⁇ 1.
  • an embodiment of the present disclosure provides a display device, including the driving circuit of the display panel provided in the foregoing embodiment of the present disclosure.
  • Fig. 1 shows an exemplary structural block diagram of a driving method of a Mini LED display panel
  • Fig. 2 shows an exemplary structural block diagram of a pixel driving circuit according to an embodiment of the present disclosure
  • Fig. 3 shows an exemplary structural block diagram of a driving unit according to an embodiment of the present disclosure
  • FIG. 4 shows an exemplary timing diagram of scanning lines and data lines in the pixel driving circuit of FIG. 2;
  • Fig. 5 is a block diagram showing an exemplary structure of a driving circuit of a display panel to which the pixel driving circuit of Fig. 2 is applied;
  • Fig. 6 shows an exemplary structural block diagram of another pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 7 shows an exemplary structural block diagram of another driving unit according to an embodiment of the present disclosure.
  • FIG. 8 shows an exemplary structural block diagram of a driving circuit of a display panel to which the pixel driving circuit of FIG. 6 is applied.
  • the sub-pixel unit includes m rows and n columns, m row driving lines from row driving line H1 to row driving line Hm, and n column tubes from column driving line L1 to column driving line Ln, wherein the row driving The line is connected to the anode of each LED in the corresponding row, and the column driving line is connected to the cathode of each LED in the corresponding column.
  • One pixel unit 1 includes three sub-pixel units of RGB.
  • m row driving lines and n column driving lines need to be connected to an external circuit (such as a PCB) to provide electrical signals for each sub-pixel unit.
  • an external circuit such as a PCB
  • the above-mentioned arrangement of the driving lines requires a higher lead process on the side of the panel, which will increase the process cost and increase the thickness of the module.
  • the present disclosure proposes a hybrid driving architecture that combines sub-pixel units and driving units.
  • a pixel driving circuit including a switch unit and a driving unit 10, the switch unit is connected to the driving unit 10, and the driving unit 10 is connected to a plurality of sub-pixel units ;
  • the switch unit is set to receive the scan signal Gate and the data signal SD, is turned on under the action of the scan signal Gate, and sends the data signal SD to the drive unit 10, which is set to send the data signal to all connected devices in a time-sharing manner.
  • the multiple sub-pixel units are set to receive the scan signal Gate and the data signal SD, is turned on under the action of the scan signal Gate, and sends the data signal SD to the drive unit 10, which is set to send the data signal to all connected devices in a time-sharing manner.
  • the switch unit and the driving unit By providing the switch unit and the driving unit to provide corresponding data signals to multiple sub-pixel units, that is, multiple sub-pixel units share one pixel drive circuit, the effect of reducing the number of signal lines (including scan lines and data lines) is obtained.
  • the plurality of sub-pixel units mentioned here may be any number, and the embodiment of the present disclosure does not limit the number of sub-pixel units connected to the driving unit 10.
  • the sub-pixel unit may be an electroluminescent device.
  • the switch unit may include a transistor T1, the gate of the transistor T1 receives the scan signal Gate, the first electrode receives the data signal SD, and the second electrode is connected to the driving unit 10.
  • the transistor T1 in the circuit can be either an N-type transistor or a P-type transistor.
  • the driving unit 10 may include a control sub-unit 101, a multiple selection sub-unit 102 and multiple holding sub-units 103, wherein:
  • the control sub-unit 101 may be configured to be connected to the switch unit to receive the data signal SD, and under the action of the data signal SD, the control sub-unit 101 can output a corresponding control signal;
  • the multiplexing subunit 102 can be set to be connected to the control subunit 101 and multiple holding subunits 103. Under the action of the control signal, the multiplexing subunit 102 selects the corresponding channel and sends the corresponding data signal to the corresponding holding Subunit
  • the channels of the multiplexing subunit 102 and the holding subunit 103 can be connected in a one-to-one correspondence, and the multiple holding subunits 103 and the multiple sub-pixel units can be connected in a one-to-one correspondence.
  • the driving unit 10 can provide data signals to three sub-pixel units of different colors, that is, the first sub-pixel unit 21, the second sub-pixel unit 22, and the third sub-pixel unit 23.
  • Each sub-pixel unit includes a positive electrode and a negative electrode.
  • the first sub-pixel unit 21, the second sub-pixel unit 22, and the third sub-pixel unit 23 are added with the suffix -1 or -2 Ways to distinguish the positive and negative poles of each sub-pixel unit, where the suffix -1 indicates the positive pole, and the suffix -2 indicates the negative pole.
  • the sub-pixel unit and the driving unit 10 can be arranged in two rows and two columns, the first sub-pixel unit 21 and the second sub-pixel unit 22 can be located side by side in the first row, and the third sub-pixel unit 23 and the drive unit 10 can be located side by side. second line.
  • This arrangement of pixel units makes full use of space, has a compact structure, and is suitable for high-resolution applications.
  • the upper left corner of the pixel unit may be the first sub-pixel unit 21, the upper right corner may be the second sub-pixel unit 22, the lower left corner may be the third sub-pixel unit 23, and the lower right corner may be the driving unit 10.
  • the diagonal positions of the aforementioned sub-pixel unit and the driving unit 10 can be interchanged, which is not limited here.
  • the upper left corner of the pixel unit may be the second sub-pixel unit 22, the upper right corner may be the first sub-pixel unit 21, the lower left corner may be the driving unit 10, and the lower right corner may be the third sub-pixel unit 23.
  • the first sub-pixel unit 21 may be red
  • the second sub-pixel unit 22 may be green
  • the third sub-pixel unit 23 may be blue. The corresponding relationship between the color and the sub-pixel unit can be matched as needed, which is not limited here.
  • the following relationship may exist between the scan signal and the data signal: three data signals may be sent in sequence within one scan signal time period.
  • the scan signal time period refers to the time period during which the scan signal is valid.
  • the scan signal may be low-level effective or high-level effective, and may be determined according to the type of transistor used.
  • the scanning signal Gate shown in Figure 4 is a pulse signal, which is valid at high level; the corresponding data signal SD is also a pulse signal, which is valid at high level.
  • the data signal can also be a low-level effective signal, which is not limited here.
  • the driving unit 10 needs to write the three data signals to the corresponding sub-pixel units during the period when the scan signal is valid.
  • the switch unit is turned on during the time period when the scan signal is valid, and the control subunit 101 receives the data signal, and outputs the corresponding multiplexer subunit 102's path that is turned on according to the data signal during the time period during which each data signal is valid.
  • the control signal causes the corresponding data signal to be transmitted to the corresponding holding subunit.
  • the control subunit 101 can control the multiplexer unit 102 to be turned on.
  • the first path allows the data signal 201 to be written to the holding sub-unit 103-1.
  • the control sub-unit 101 can control the multiplexer sub-unit 102 to turn on the second channel, so that the data signal 202 is written to the holding sub-unit 103- 2.
  • the control sub-unit 101 can control the multiplexer sub-unit 102 to turn on the third channel, so that the data signal 203 is written to the holding sub-unit 103-3. Since the holding sub-unit 103-3 is connected to the sub-pixel unit 23, The sub-pixel unit 23 is lit. In this way, the driving of multiple sub-pixel units is realized.
  • Fig. 2 only shows an exemplary embodiment of a driving unit, in which the number of paths of the multiple selection subunit and the number of holding subunits can be determined according to needs, and are not limited to three.
  • the multiplexer subunit has six paths, corresponding to six holding subunits.
  • the data signal may include six effective level pulses in one scan signal period.
  • the pixel driving circuit of FIG. 6 is described below.
  • the pixel unit of FIG. 6 includes six sub-pixel units, and the six sub-pixel units include a first sub-pixel unit 21, a second sub-pixel unit 22, a third sub-pixel unit 23, and a fourth sub-pixel unit.
  • the positive and negative electrodes are distinguished by adding the suffix -1 or -2. -1 means positive pole, suffix -2 means negative pole.
  • the sub-pixel unit and the driving unit 10 can be arranged in two rows and four columns, the first sub-pixel unit 21, the second sub-pixel unit 22, and the sixth sub-pixel unit 26 can be located side by side in the first row, and the third sub-pixel unit 23
  • the driving unit 10, the fourth sub-pixel unit 24, and the fifth sub-pixel unit 25 may be located side by side in the second row.
  • the first row and first column of the pixel unit may be the first sub-pixel unit 21, the first row and second column may be the second sub-pixel unit 22, and the first row and third column may be the sixth sub-pixel unit.
  • Pixel unit 26 the second row and first column may be the third sub-pixel unit 23, the second row and second column may be the driving unit 10, the second row and third column may be the fourth sub-pixel unit 24, and the second row and third column may be the fourth sub-pixel unit 24.
  • the four columns may be the fifth sub-pixel unit 25.
  • the above-mentioned first row and second row can be interchanged, and the position of the driving unit 10 can also be interchanged with the sub-pixel unit, which is not limited here.
  • the first sub-pixel unit 21 and the fourth sub-pixel unit 24 may be set to red
  • the second sub-pixel unit 22 and the fifth sub-pixel unit 25 may be set to green
  • the third sub-pixel unit 26 and the fourth sub-pixel unit 23 may be set Set to blue.
  • this method can drive two groups of sub-pixel units of three primary colors.
  • the driving circuit of FIG. 6 can reduce the number of scan lines and data lines, and is beneficial to improve the display resolution.
  • the corresponding relationship between the color and the sub-pixel unit can be matched as needed, which is not limited here.
  • the position setting of the sub-pixel units is not limited to the positional relationship given in Figure 6, and can also be arranged in 4 rows and 2 columns as required, as long as the uniformity of the color arrangement of multiple pixel units including the three primary colors is ensured, and the same color is avoided.
  • the pixel units are arranged together.
  • the driving unit 10 of the driving circuit of FIG. 8 needs to write six data signals to the corresponding sub-pixel units during the period when the scan signal is valid.
  • the driving unit 10 needs to sequentially write the valid level pulses of the data signal to the corresponding sub-pixel unit during the period when the scan signal is valid. Therefore, the driving unit 10 includes a control subunit 101, a multiplexer subunit 102, and six holding subunits 103.
  • the embodiment of the present disclosure also provides a driving circuit for a display panel.
  • the driving circuit of the display panel includes an array of pixel units 1, a plurality of scan lines Gate and a plurality of data lines SD, and each pixel unit 1 includes any one of the above-mentioned embodiments of the present disclosure.
  • Pixel drive circuit
  • the scan line Gate is located between adjacent row pixel units, and the data line SD is located between adjacent column pixel units.
  • each pixel unit 1 may include three sub-pixel units, one switch unit, and one drive unit arranged in an array.
  • the three sub-pixel units and one drive unit may be arranged in an array into two rows and two columns, and the switch The unit may be arranged on the side of the driving unit away from the three sub-pixel units.
  • the entire display panel includes pixel units 1 arranged in an array of m/2 rows and n columns, m rows of scan lines from scan line Gate 1 to scan line Gate m, and n columns of data lines from data line SD1 to data line SD n.
  • each row of pixel units can be connected to two rows of scan lines.
  • One row of scan lines can be set to provide scan signals to pixel units in even columns, and the other row of scan lines can be set to pixel units in odd columns.
  • the pixel units in each column can share a data line SD, and the data signal of the data line SD can be provided by the peripheral drive data chip DDIC (Display Driver IC), and can be transmitted to the corresponding drive unit through the switch unit .
  • Each pixel unit includes a plurality of sub-pixel units, and the arrangement of the sub-pixel units and the driving units in each pixel unit may be different. As shown in FIG.
  • the arrangement of the sub-pixel units and driving units in the pixel unit of the nth column in two adjacent columns of pixel units located in the same row can be that of the pixel unit of the (n+1)th column.
  • the arrangement of the sub-pixel units and the driving units is along the line between the (n+1)th column of pixel units and the nth column of pixel units and parallel to the row direction perpendicular to the column direction as the axis, which is obtained after mirroring ,
  • n ⁇ 1 that is, the arrangement of the sub-pixel units and drive units in the pixel unit of the nth column and the arrangement of the sub-pixel units and drive units in the pixel unit of the (n+1)th column are mutually exclusive
  • the mirror axis is a straight line between the pixel unit of the (n+1)th column and the pixel unit of the nth column and parallel to the row direction perpendicular to the column direction.
  • the sub-pixel unit and the driving unit of the first pixel unit in the first row and first column are vertically flipped along the axis parallel to Gate2 to obtain the sub-pixels in the second pixel unit in the first row and second column.
  • the upper left corner of the pixel unit in the first column may be the first sub-pixel unit 21, the upper right corner may be the second sub-pixel unit 22, the lower left corner may be the third sub-pixel unit 23, and the lower right corner may be the driving unit 10.
  • the upper left corner of the pixel structure in the second column may be the third sub-pixel unit 23, the upper right corner may be the driving unit 10, the lower left corner may be the first sub-pixel unit 21, and the lower right corner may be the second sub-pixel unit 22.
  • a driving manner in which pixel units in each row share one scan line can be adopted.
  • scan lines of m rows from scan line Gate 1 to scan line Gate m can be provided by GOA circuits or integrated circuits (ICs).
  • ICs integrated circuits
  • a display panel shown in FIG. 8 includes pixel units 1 of m/2 rows and n/2 columns, m/2 scan lines of scan lines Gate1 to scan lines Gate m/2, and data lines SD1 to data lines SD n/2 columns of data lines.
  • Each row of pixel units can share a row scan line Gate, and each column of pixel units can share a data line SD.
  • the data signal of the data line SD can be provided by the driving data chip DDIC provided on the periphery, and can be transmitted to the corresponding through the switch unit The drive unit.
  • the arrangement of the sub-pixels in the pixel units 1 in each row and each column may be completely the same, the scan line Gate may be located between adjacent row pixel units, and the data line SD may be located between adjacent column pixel units.
  • this embodiment can further save the number of leads (ie, signal lines).
  • the display panel of FIG. 5 may adopt an arrangement similar to that of the sub-pixel units in each row and each column of pixel units 1 in FIG. 8, and the display panel of FIG. 8 may adopt an arrangement similar to the sub-pixel units in FIG. 5, namely:
  • the arrangement of the sub-pixel units and driving units in the pixel unit of the nth column in two adjacent columns of pixel units in the same row is the arrangement of the sub-pixel units and driving units in the pixel unit of the (n+1)th column
  • the arrangement is obtained by mirroring along the line between the pixel unit in the (n+1)th column and the pixel unit in the nth column and parallel to the row direction perpendicular to the column direction, where n ⁇ 1, that is
  • the arrangement of the sub-pixel units and drive units in the pixel unit of the nth column and the arrangement of the sub-pixel units and drive units in the pixel unit of the (n+1)th column are mirror images of each other, and the mirror axis is located in the A straight line between the pixel unit
  • the sub-pixel unit and driving unit in the first pixel unit in the first row and first column are vertically flipped along the axis parallel to Gate1 to obtain the sub-pixel unit and driving unit in the second pixel unit in the first row and second column.
  • the first pixel unit and the second pixel unit are mirror images of each other, and the mirror axis is the axis that is vertically flipped.
  • An embodiment of the present disclosure further provides a display device, which includes the drive circuit of the display panel provided in any of the foregoing embodiments of the present disclosure.

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Abstract

一种像素驱动电路、显示面板的驱动电路以及显示装置。像素驱动电路包括开关单元和驱动单元（10），开关单元与驱动单元（10）连接，驱动单元（10）设置为与多个子像素单元连接；开关单元设置为接收扫描信号（Gate）和数据信号（SD），在扫描信号（Gate）的作用下导通，将数据信号（SD）发送至驱动单元（10），驱动单元（10）设置为将数据信号（SD）分时发送至连接的多个子像素单元。像素驱动电路能够减少扫描线和数据线的数量，提高了显示分辨率。

Description

像素驱动电路、显示面板的驱动电路以及显示装置
本申请要求于2020年03月23日提交中国专利局、申请号为202010208335.8、发明名称为“像素驱动电路、显示面板的驱动电路以及显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于显示技术领域(例如，计算机技术领域)，尤其涉及像素驱动电路、显示面板的驱动电路以及显示装置。
背景技术
Mini LED是指封装大小在0.1-0.2mm的LED，又称为次毫米发光二极管。Mini LED显示器是由数量众多的小尺寸LED阵列组成，LED之间的间距较小，具有高亮度、高对比度、超高解析度和色彩饱和度，逐渐成为显示技术的一个发展方向。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开实施例提供一种像素驱动电路，包括开关单元和驱动单元，所述开关单元与驱动单元连接，所述驱动单元设置为与多个子像素单元连接；
开关单元设置为接收扫描信号和数据信号，在扫描信号的作用下导通，将数据信号发送至驱动单元；
所述驱动单元设置为将数据信号分时发送至所连接的所述多个子像素单元。
在一些示例性实施例中，所述开关单元包括晶体管，晶体管的栅极设置为接收扫描信号，第一极设置为接收数据信号，第二极设置为连接驱动单元。
在一些示例性实施例中，驱动单元包括控制子单元、多路选择子单元和多个保持子单元，其中：
控制子单元设置为连接开关单元，接收数据信号，在数据信号的作用下输出对应的控制信号；
多路选择子单元设置为与控制子单元、所述多个保持子单元连接，在控制信号的作用下，选择对应的通道将对应的数据信号发送至对应的保持子单元；
多路选择子单元的通道与所述多个保持子单元一一对应连接，所述多个保持子单元与多个子像素单元一一对应连接。
在一些示例性实施例中，子像素单元设置为三个，三个子像素单元包括不同颜色的第一子像素单元、第二子像素单元和第三子像素单元；
子像素单元和驱动单元采用两行两列的排列方式，第一子像素单元和第二子像素单元并排位于第一行，第三子像素单元和驱动单元位于像素单元并排位于第二行。
在一些示例性实施例中，在一个扫描信号时间段内发送三个数据信号。
在一些示例性实施例中，子像素单元设置为六个，六个子像素单元包括第一子像素单元、第二子像素单元、第三子像素单元、第四子像素单元、第五子像素单元和第六子像素单元；
子像素单元和驱动单元采用两行四列的排列方式，第一子像素单元、第二子像素单元和第六子像素单元并排位于第一行，第三子像素单元、驱动单元、第四子像素单元和第五子像素单元并排位于第二行。
在一些示例性实施例中，在一个扫描信号的时间段内发送六个数据信号。
第二方面，本公开实施例提供一种显示面板的驱动电路，包括阵列排列的像素单元、多个扫描线和多个数据线，每个像素单元包括本公开任一实施例所提供的像素驱动电路；
扫描线位于相邻的行像素单元之间，数据线位于相邻的列像素单元之间。
在一些示例性实施例中，子像素单元和驱动单元采用两行两列的排列方式时；位于同一行的相邻两列像素单元，第n列的像素单元中的子像素单元和驱动单元的排布方式与第(n+1)列的像素单元中的子像素单元和驱动单元的排布方式互为镜像，镜像轴为位于第(n+1)列像素单元和第n列像素单元之间的且平行于与列方向垂直的行方向的直线，其中n≥1。
在一些示例性实施例中，每行像素单元设置为与两行扫描线连接，其中一行扫描线设置为向偶数列的像素单元提供扫描信号，另一行扫描线设置为向奇数列的像素单元提供扫描信号，其中一行扫描线经过像素单元的内部。
在一些示例性实施例中，所述子像素单元和所述驱动单元采用两行四列的排列方式时；位于同一行的相邻两列像素单元，第n列的像素单元中的子像素单元和驱动单元的排布方式与第(n+1)列的像素单元中的子像素单元和驱动单元的排布方式互为镜像，镜像轴为位于第(n+1)列像素单元和第n列像素单元之间的且平行于与列方向垂直的行方向的直线，其中n≥1。
第三方面，本公开实施例提供一种显示装置，包括本公开上述实施例所提供的显示面板的驱动电路。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1示出了一种Mini LED显示面板的驱动方式的示例性结构框图；
图2示出了根据本公开实施例的像素驱动电路的示例性结构框图；
图3示出了本公开实施例一种驱动单元的示例性结构框图；
图4示出了应用图2的像素驱动电路中扫描线和数据线的示例性时序图；
图5示出了应用图2的像素驱动电路的显示面板的驱动电路示例性结构 框图；
图6示出了根据本公开实施例的另一种像素驱动电路的示例性结构框图；
图7示出了本公开实施例另一种驱动单元的示例性结构框图；
图8示出了应用图6的像素驱动电路的显示面板的驱动电路的示例性结构框图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。此处所描述的实施例仅仅用于解释本公开，而非对本公开的限定。为了便于描述，附图中仅示出了与公开实施例相关的部分。
在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。本领域的普通技术人员应当理解，可以对本公开实施例的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求范围当中。下面将参考附图并结合实施例来说明本公开。
随着Mini LED的发展，在Mini LED显示产品中，除了采用4合一封装的LED外，可以采用单色RGB的LED进行子像素排布，这种子像素排布方式比较简单。如图1所示，包括m行n列的子像素单元、行驱动线H1至行驱动线Hm的m根行驱动线和列驱动线L1至列驱动线Ln的n根列管，其中行驱动线与对应行的每个LED的正极连接，列驱动线与对应列的每个LED的负极连接，一个像素单元1包括RGB三个子像素单元。对于显示面板，需要将m根行驱动线和n根列驱动线连接至外部电路(如PCB)，从而为每个子像素单元提供电信号。上述驱动线的设置方式，对面板侧边的引线工艺要求较高，会增加工艺成本，且增加模组厚度。本公开提出一种将子像素单元与驱动单元相结合的混合驱动的架构。
在一示例性实施例中，请参考图2和图6所示，一种像素驱动电路，包括开关单元和驱动单元10，开关单元与驱动单元10连接，该驱动单元10与多个子像素单元连接；
开关单元设置为接收扫描信号Gate和数据信号SD，在扫描信号Gate的 作用下导通，将数据信号SD发送至驱动单元10，该驱动单元10设置为将数据信号分时发送至所连接的所述多个子像素单元。
通过设置由开关单元和驱动单元向多个子像素单元提供对应的数据信号，即多个子像素单元共用一个像素驱动电路，获得了减少信号线(包括扫描线和数据线)的数量的效果。此处所说的多个子像素单元可以是任意多个，本公开实施例对与驱动单元10相连接的子像素单元的个数不做限定。在Mini LED显示领域，该子像素单元可以是一个电致发光器件。
如图2或图6所示，开关单元可以包括晶体管T1，晶体管T1的栅极接收扫描信号Gate，第一极接收数据信号SD，第二极连接驱动单元10。在实际应用中，根据不同的应用场景，电路中的晶体管T1可以选择N型晶体管或者P型晶体管中的任一种。
在一示例性实施例中，请参考图3中给出的驱动单元10的结构示意图，驱动单元10可以包括控制子单元101、多路选择子单元102和多个保持子单元103，其中：
控制子单元101可以设置为连接开关单元接收数据信号SD，在数据信号SD的作用下，控制子单元101能够输出对应的控制信号；
多路选择子单元102可以设置为与控制子单元101、多个保持子单元103连接，在控制信号的作用下，多路选择子单元102选择对应的通道将对应的数据信号发送至对应的保持子单元；
多路选择子单元102的通道与保持子单元103可以一一对应连接，多个保持子单元103与多个子像素单元可以一一对应连接。
如图2和图3所示，驱动单元10可以向三个不同颜色的子像素单元即第一子像素单元21、第二子像素单元22、第三子像素单元23提供数据信号。其中每个子像素单元包括正极和负极，为了区分正负极，图2中，对第一子像素单元21、第二子像素单元22、第三子像素单元23采用增加后缀-1或-2的方式来区分每个子像素单元的正负极，其中后缀-1表示正极，后缀-2表示负极。子像素单元和驱动单元10可以采用两行两列的排列方式，第一子像素单元21和第二子像素单元22可以并排位于第一行，第三子像素单元23和驱 动单元10可以并排位于第二行。这种像素单元的排布方式充分利用了空间，结构紧凑，适合用在高分辨率的应用场合。如图2所示，像素单元的左上角可以为第一子像素单元21，右上角可以为第二子像素单元22、左下角可以为第三子像素单元23，右下角可以为驱动单元10。其中，上述子像素单元和驱动单元10的对角位置可以互换，这里不做限定。例如，像素单元的左上角可以为第二子像素单元22，右上角可以为第一子像素单元21、左下角可以为驱动单元10，右下角可以为第三子像素单元23。另外，第一子像素单元21可以为红色，第二子像素单元22可以为绿色，第三子像素单元23可以为蓝色。颜色与子像素单元的对应关系可根据需要匹配，这里不做限定。
如图4所示，扫描信号与数据信号之间可以存在如下关系：在一个扫描信号时间段内可以依次发送三个数据信号。扫描信号时间段是指扫描信号有效的时间段，该扫描信号可以是低电平有效或者是高电平有效，可以根据所采用的晶体管的类型来确定。图4给出的扫描信号Gate为脉冲信号，高电平有效；对应的数据信号SD也是脉冲信号，高电平有效。数据信号也可以采用低电平有效的信号，这里不做限定。驱动单元10需要在扫描信号有效的时间段将三个数据信号写入到对应的子像素单元。其中，扫描信号有效的时间段，开关单元导通，控制子单元101接收到数据信号，根据数据信号在每个数据信号有效的时间段，输出对应的多路选择子单元102的通路导通的控制信号，使得对应的数据信号传输到对应的保持子单元。如图4所示，在扫描信号有效的时间段中，对应数据信号SD出现的第一个有效电平数据信号201的子时间段，控制子单元101可以通过控制多路选择子单元102导通第一个通路，使得数据信号201写入到保持子单元103-1，由于保持子单元103-1与子像素单元21连接，子像素单元21点亮；在扫描信号有效时间段中，对应数据信号SD出现的第二个有效电平数据信号202的子时间段，控制子单元101可以通过控制多路选择子单元102导通第二个通路，使得数据信号202写入到保持子单元103-2，由于保持子单元103-2与子像素单元22连接，子像素单元22被点亮；在扫描信号有效时间段中，对应数据信号SD出现的第三个有效电平数据信号203的子时间段，控制子单元101可以通过控制多路选择子单元102导通第三个通路，使得数据信号203写入到保持子单元103-3， 由于保持子单元103-3与子像素单元23连接，子像素单元23被点亮。通过这种方式，实现了对多个子像素单元的驱动。
图2仅给出一种驱动单元的示例性实施例，其中多路选择子单元的通路数量、保持子单元的数量可以根据需要确定，并不限制在三个。例如，图6所示的像素单元中，多路选择子单元具备六个通路，对应六个保持子单元。这种情况下，扫描信号与数据信号之间可以存在如下关系：一个扫描信号时间段内数据信号可以包括六个有效电平的脉冲。
下面说明图6的像素驱动电路，图6的像素单元包括六个子像素单元，六个子像素单元包括第一子像素单元21、第二子像素单元22、第三子像素单元23、第四子像素单元24、第五子像素单元25和第六子像素单元26；其中每个子像素单元包括正极和负极，对上述六个子像素单元，以增加后缀-1或-2的方式区分正负极，后缀-1表示正极，后缀-2表示负极。子像素单元和驱动单元10可以采用两行四列的排列方式，第一子像素单元21、第二子像素单元22和第六子像素单元26可以并排位于第一行，第三子像素单元23、驱动单元10、第四子像素单元24和第五子像素单元25可以并排位于第二行。
如图6所示，像素单元的第一行第一列可以为第一子像素单元21，第一行第二列可以为第二子像素单元22、第一行第三列可以为第六子像素单元26，第二行第一列可以为第三子像素单元23，第二行第二列可以为驱动单元10，第二行第三列可以为第四子像素单元24，第二行第四列可以为第五子像素单元25。其中，上述第一行和第二行可以互换，驱动单元10的位置也可以与子像素单元互换，这里不做限定。第一子像素单元21和第四子像素单元24可以设置为红色，第二子像素单元22和第五子像素单元25可以设置为绿色，第三子像素单元26和第四子像素单元23可以设置为蓝色。在以红绿蓝三种颜色为基色的显示面板中，该方式可以驱动两组三基色的子像素单元。相对图2的驱动电路而言，图6的驱动电路能够减少扫描线和数据线的数量，并有利于提高显示分辨率。
颜色与子像素单元的对应关系可根据需要匹配，这里不做限定。子像素单元的位置设置不限定于图6给出的位置关系，也可以根据需要排列成4行2列，只要确保包括三基色的多个像素单元的颜色排布的均匀性，避免相同 颜色的像素单元排列在一起。
图8的驱动电路的驱动单元10需要在扫描信号有效的时间段将六个数据信号写入到对应的子像素单元。驱动单元10需要在扫描信号有效的时间段将数据信号的有效电平脉冲依次写入到对应的子像素单元。因此，驱动单元10包括控制子单元101、多路选择子单元102，以及六个保持子单元103。
本公开实施例还提供一种显示面板的驱动电路。
请参考图5和图8，该显示面板的驱动电路包括阵列排列的像素单元1、多个扫描线Gate和多个数据线SD，每个像素单元1包括本公开上述任一实施例所提供的像素驱动电路；
扫描线Gate位于相邻的行像素单元之间，数据线SD位于相邻的列像素单元之间。
如图5所示，每个像素单元1可以包括阵列排布的三个子像素单元、一个开关单元以及一个驱动单元，三个子像素单元和一个驱动单元可以阵列排布为两行两列，而开关单元可以设置在驱动单元的远离三个子像素单元的一侧。整个显示面板包括m/2行n列阵列排布的像素单元1，扫描线Gate 1至扫描线Gate m的m行扫描线，以及数据线SD1至数据线SD n的n列数据线。为了降低走线的复杂度，每行像素单元可以与两行扫描线连接，其中一行扫描线可以设置为向偶数列的像素单元提供扫描信号，另一行扫描线可以设置为向奇数列的像素单元提供扫描信号。每列的像素单元可以共用一条数据线SD，数据线SD的数据信号可以由设置于外围的驱动数据芯片DDIC(Display Driver IC，显示驱动芯片)提供，并可以通过开关单元传输至对应的驱动单元。每个像素单元包括多个子像素单元，每个像素单元中子像素单元与驱动单元的排布方式可以不同。如图5所示，位于同一行的相邻两列像素单元，第n列的像素单元中的子像素单元和驱动单元的排布方式，可以是第(n+1)列的像素单元中的子像素单元和驱动单元的排布方式沿位于第(n+1)列像素单元和第n列像素单元之间的且平行于与列方向垂直的行方向的直线为轴，进行镜像后得到的，其中n≥1，即第n列的像素单元中的子像素单元和驱动单元的排布方式与第(n+1)列的像素单元中的子像素单元和驱动单元的排布方式互为镜像，镜像轴为位于第(n+1)列像素单元和第n列像素单元之 间的且平行于与列方向垂直的行方向的直线。如图5所示，第一行第一列的第一像素单元的子像素单元和驱动单元沿与Gate2平行的轴垂直翻转后可以得到第一行第二列的第二像素单元中的子像素单元和驱动单元的排布，由此，第一像素单元和第二像素单元互为镜像，镜像轴即为垂直翻转的轴。采用这种排列方式，有利于每种颜色的均匀分布。第一列中像素单元的左上角可以设置为第一子像素单元21，右上角可以为第二子像素单元22、左下角可以为第三子像素单元23，右下角可以为驱动单元10。而第二列中像素结构的左上角可以为第三子像素单元23，右上角可以为驱动单元10、左下角可以为第一子像素单元21，右下角可以为第二子像素单元22。本实施例可以采用每行的像素单元共用一条扫描线的驱动方式。
如图5所示，扫描线Gate 1至扫描线Gate m的m行扫描线可以由GOA电路或者集成电路(IC)提供，相对于图1的驱动方式而言，图5中示出的驱动方式，在沿列方向上的每一根数据线能够给大于1个子像素单元提供信号，因此在驱动相同数量的子像素单元时，本实施例能够节省信号线的数量。
图8所示的一种显示面板，包括m/2行n/2列的像素单元1，扫描线Gate1至扫描线Gate m/2的m/2行扫描线，以及数据线SD1至数据线SD n/2的n/2列数据线。每行像素单元可以共用一个行扫描线Gate，每列的像素单元可以共用一条数据线SD，数据线SD的数据信号可以由设置于外围的驱动数据芯片DDIC提供，并可以通过开关单元传输至对应的驱动单元。每行每列的像素单元1中的子像素的排布方式可以完全相同，扫描线Gate可以位于相邻的行像素单元之间，数据线SD可以位于相邻的列像素单元之间。相对于图5的驱动方式而言，在驱动相同数量的子像素单元时，本实施例能够更加节省引线(即信号线)的数量。
图5的显示面板可以采用类似图8的每行每列像素单元1中的子像素单元的排布方式，图8的显示面板可以采用类似图5中的子像素单元的排布方式，即：位于同一行的相邻两列像素单元，第n列的像素单元中的子像素单元和驱动单元的排布方式，是第(n+1)列的像素单元中的子像素单元和驱动单元的排布方式沿位于第(n+1)列像素单元和第n列像素单元之间的且平行于与列方向垂直的行方向的直线为轴，进行镜像后得到的，其中n≥1， 即第n列的像素单元中的子像素单元和驱动单元的排布方式与第(n+1)列的像素单元中的子像素单元和驱动单元的排布方式互为镜像，镜像轴为位于第(n+1)列像素单元和第n列像素单元之间的且平行于与列方向垂直的行方向的直线。第一行第一列的第一像素单元中的子像素单元和驱动单元沿与Gate1平行的轴垂直翻转后可以得到第一行第二列的第二像素单元中的子像素单元和驱动单元的排布，由此，第一像素单元和第二像素单元互为镜像，镜像轴即为垂直翻转的轴。
本公开实施例还提供一种显示装置，该显示装置包括本公开上述任一实施例所提供的显示面板的驱动电路。
以上描述仅为本公开的示例性实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，也应涵盖在不脱离所述发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开实施例中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (12)

  1. 一种像素驱动电路，包括开关单元和驱动单元，所述开关单元与所述驱动单元连接，所述驱动单元设置为与多个子像素单元连接；
    所述开关单元设置为接收扫描信号和数据信号，在扫描信号的作用下导通，将所述数据信号发送至所述驱动单元；
    所述驱动单元设置为将所述数据信号分时发送至所连接的所述多个子像素单元。
  2. 根据权利要求1所述的像素驱动电路，其中，所述开关单元包括晶体管，所述晶体管的栅极设置为接收扫描信号，第一极设置为接收数据信号，第二极设置为连接所述驱动单元。
  3. 根据权利要求1所述的像素驱动电路，其中，所述驱动单元包括控制子单元、多路选择子单元和多个保持子单元，其中：
    所述控制子单元设置为连接所述开关单元，接收所述数据信号，在所述数据信号的作用下输出对应的控制信号；
    所述多路选择子单元设置为与所述控制子单元、所述多个保持子单元连接，在所述控制信号的作用下，选择对应的通道将对应的数据信号发送至对应的保持子单元；
    所述多路选择子单元的通道与所述多个保持子单元一一对应连接，所述多个保持子单元与所述多个子像素单元一一对应连接。
  4. 根据权利要求1所述的像素驱动电路，其中，所述子像素单元设置为三个，所述三个子像素单元包括不同颜色的第一子像素单元、第二子像素单元和第三子像素单元；
    所述子像素单元和所述驱动单元采用两行两列的排列方式，所述第一子像素单元和所述第二子像素单元并排位于第一行，所述第三子像素单元和所述驱动单元位于像素单元并排位于第二行。
  5. 根据权利要求4所述的像素驱动电路，其中，在一个所述扫描信号时间段内发送三个所述数据信号。
  6. 根据权利要求1所述的像素驱动电路，其中，所述子像素单元设置为六个，所述六个子像素单元包括第一子像素单元、第二子像素单元、第三子像素单元、第四子像素单元、第五子像素单元和第六子像素单元；
    所述子像素单元和所述驱动单元采用两行四列的排列方式，所述第一子像素单元、所述第二子像素单元和所述第六子像素单元并排位于第一行，所述第三子像素单元、所述驱动单元、所述第四子像素单元和第五子像素单元并排位于第二行。
  7. 根据权利要求6所述的像素驱动电路，其中，在一个所述扫描信号的时间段内发送六个所述数据信号。
  8. 一种显示面板的驱动电路，包括阵列排列的像素单元、多个扫描线和多个数据线，每个所述像素单元包括权利要求1至7中任一项所述的像素驱动电路；
    扫描线位于相邻的行像素单元之间，数据线位于相邻的列像素单元之间。
  9. 根据权利要求8所述的显示面板的驱动电路，其中，
    所述子像素单元和所述驱动单元采用两行两列的排列方式时；
    位于同一行的相邻两列像素单元，第n列的像素单元中的子像素单元和驱动单元的排布方式与第(n+1)列的像素单元中的子像素单元和驱动单元的排布方式互为镜像，镜像轴为位于第(n+1)列像素单元和第n列像素单元之间的且平行于与列方向垂直的行方向的直线，其中n≥1。
  10. 根据权利要求9所述的显示面板的驱动电路，其中，
    每行像素单元设置为与两行扫描线连接，其中一行扫描线设置为向偶数列的像素单元提供扫描信号，另一行扫描线设置为向奇数列的像素单元提供扫描信号，其中一行扫描线经过所述像素单元的内部。
  11. 根据权利要求8所述的显示面板的驱动电路，其中，
    所述子像素单元和所述驱动单元采用两行四列的排列方式时；
    位于同一行的相邻两列像素单元，第n列的像素单元中的子像素单元和驱动单元的排布方式与第(n+1)列的像素单元中的子像素单元和驱动单元 的排布方式互为镜像，镜像轴为位于第(n+1)列像素单元和第n列像素单元之间的且平行于与列方向垂直的行方向的直线，其中n≥1。
  12. 一种显示装置，包括权利要求8至11中任一项所述的显示面板的驱动电路。
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