WO2022057902A1 - 显示面板与半导体显示装置 - Google Patents

显示面板与半导体显示装置 Download PDF

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Publication number
WO2022057902A1
WO2022057902A1 PCT/CN2021/119100 CN2021119100W WO2022057902A1 WO 2022057902 A1 WO2022057902 A1 WO 2022057902A1 CN 2021119100 W CN2021119100 W CN 2021119100W WO 2022057902 A1 WO2022057902 A1 WO 2022057902A1
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WO
WIPO (PCT)
Prior art keywords
pixel
driving circuit
data
display
pixel driving
Prior art date
Application number
PCT/CN2021/119100
Other languages
English (en)
French (fr)
Inventor
郑志伟
周宴
曾玉超
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21868724.2A priority Critical patent/EP4207157A4/en
Publication of WO2022057902A1 publication Critical patent/WO2022057902A1/zh
Priority to US18/186,295 priority patent/US20230237961A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
    • G09G3/2088—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a semiconductor display device using miniature light-emitting diodes as light-emitting elements.
  • Micro LED Micro-Size Light Emitting Diode, Micro LED or ⁇ -LED
  • Micro LED is called a micro light-emitting diode.
  • the millimeter The length of the LED of the level is further reduced to the micron level to achieve ultra-high pixels and ultra-high resolution.
  • Micro LED has the characteristics of no backlight and self-illumination. Micro LED color is easier and more accurate to debug, and has a longer luminous life and higher brightness, and has low packaging requirements, making it easier to achieve flexible and seamless splicing display, It is one of the display types with great development prospects in the future.
  • the display panel is provided with matrix-connected pixel units in the display area, each pixel unit includes a plurality of ⁇ -LEDs and at least one integrated pixel driving circuit, and the pixel driving circuit is used for receiving image data and controlling a plurality of ⁇ -LEDs according to the image data.
  • the luminous brightness of the LED is provided with matrix-connected pixel units in the display area, each pixel unit includes a plurality of ⁇ -LEDs and at least one integrated pixel driving circuit, and the pixel driving circuit is used for receiving image data and controlling a plurality of ⁇ -LEDs according to the image data. - The luminous brightness of the LED.
  • each pixel driving circuit needs to be directly connected to the display driving circuit to receive image data and clock signals, obviously it is necessary to provide more input/output ports (I/O) for the display driving circuit, As a result, there are many connection lines between the pixel driving circuit and the display driving circuit, resulting in a crowded wiring space of the display panel, and the wiring path between the pixel driving circuit and the display driving circuit is long, resulting in image data and clock signals. power consumption is high.
  • embodiments of the present application provide a display panel with lower signal transmission power and larger wiring space, and a semiconductor display device including the aforementioned display panel.
  • a display panel which includes pixel regions connected in a matrix with N rows*M columns, and each pixel region includes pixels with Q rows*P columns connected in a matrix.
  • a driving module, each pixel driving circuit is connected to at least one pixel unit, and the pixel driving circuit drives the pixel unit to emit light according to the image data to be displayed to display a picture, and the N, M, Q, and P are greater than 1 Natural number.
  • all pixel regions in any one column of pixel regions are connected to the same group of data interfaces, and pixel regions of different columns are connected to different groups of data interfaces.
  • a plurality of pixel driving circuits in any column of pixel driving circuits are cascaded in sequence to form a Q-level cascaded pixel driving circuit, and the pixel driving circuit in the first level is connected to a data interface to receive the image. data, the image data is transmitted to the Q-th pixel driving circuit in a cascaded sequence.
  • the pixel drive circuits in the display area are divided into multiple pixel areas, and then the pixel drive circuits in each pixel area are connected in cascade to transmit image data, and each pixel area receives image data separately, so as to effectively The transmission power consumption of image data during transmission is reduced.
  • the pixel driving circuits in each pixel area are cascaded in sequence, which effectively reduces the number of traces and interfaces used for image data transmission and the transmission power consumption of image data. Accuracy of image data transfer.
  • the display area only needs to perform image display in a part of the area, only the image data needs to be loaded in the part of the pixel area where the image display is performed, and the area that does not need to perform image display can be in a black screen state without loading data, that is, in the display area.
  • the image display is performed in the local area of the area, so that the power consumption of data transmission can be further reduced.
  • the display drive modules of at least two different pixel regions are connected to different clock interfaces, and the clock interfaces include a data clock interface for providing a data clock signal, and the data clock signal is used to control any column.
  • the pixel driving circuit in the first stage is connected to a data clock interface to receive the data clock signal, and the data clock signal is transmitted to the pixel driving circuit of the Qth stage in a cascade sequence.
  • the pixel drive circuit in the display area is divided into multiple pixel areas, and then the pixel drive circuits in each pixel area are connected in cascade to transmit image data, and each pixel area receives the clock signal independently, so as to effectively The transmission power consumption of the clock signal in the transmission process is reduced.
  • the data clock signal includes Q continuous pulse signals, wherein corresponding to each pulse signal, one bit byte of image data is loaded into the first-level pixel driving circuit, and according to the Q continuous pulse signals The image data are respectively loaded into the Q-level pixel driving circuits.
  • Each pulse signal in the data clock corresponds to a first-level pixel driving circuit, so that image data is accurately loaded into the corresponding pixel driving circuit and the pixel unit according to the data clock.
  • the clock interface further includes a global data clock interface, and the global data clock signal is used to control the light-emitting duration of each pixel unit in the duration of one frame of image, and the pixel driving circuit in the first stage.
  • a global clock interface is connected to receive a global clock signal, which is transmitted to the Q-th stage pixel driving circuit in cascade order. The global clock signal cooperates with the data clock signal to accurately control the pixel driving circuit to drive the pixel unit to emit light, so that the pixel unit accurately emits light according to the image data to display the image.
  • each pixel unit includes three light-emitting elements, each light-emitting element emits light of a different color, the light-emitting element is a micro light-emitting diode, the anode of the micro-light-emitting diode is connected to a driving power supply, and the micro-light emitting The cathode of the diode is connected to the pixel driving circuit, and the driving power supply is used for driving to provide a driving current for the light-emitting element;
  • the pixel driving circuit controls the length of time during which the driving current is supplied to each of the light-emitting elements according to the image data, wherein the light-emitting luminance of each of the light-emitting elements is positively correlated with the length of time.
  • each pixel driving circuit is connected to four of the pixel units, the pixel driving circuit includes one input interface and four sets of output interfaces, the input interfaces are connected to one of the data interfaces, and one set of the output interfaces The interface connects the cathodes of the three light-emitting elements in one pixel.
  • the pixel driving circuit makes the driving capability of the pixel driving circuit match the pixel unit serving as the load, thereby ensuring the accurate display of image data.
  • the pixel driving circuit is a micro integrated circuit.
  • the display panel includes a display area and a non-display area, and the pixel areas with N rows*M columns connected in a matrix are arranged in the display area.
  • the display panel further includes a display drive circuit disposed in the non-display area, the display drive circuit is connected to the pixel drive circuits in the plurality of pixel areas, and is used for outputting the image data, the data clock signal and the global clock signal to the the pixel drive circuit.
  • the image data outputted by the display driver circuit and the clock signal cooperate with each other and are accurately recorded into the pixels through the pixel driver circuit for image display.
  • the display driver circuit is connected to the partitioned pixel driver circuit, the number of signal input/output interfaces and wiring is effectively reduced , thereby simplifying the design and wiring space of the display drive circuit, and also reducing the power consumption for transmitting image data and clock signals.
  • the display driving circuit includes P*M data interfaces, M*N data clock interfaces, and M* N global clock interfaces.
  • a semiconductor display device in an embodiment of the present application, includes the aforementioned display panel.
  • Fig. 1 is the side structure schematic diagram of a kind of display terminal of the present application
  • FIG. 2 is a schematic plan view of the bearing panel shown in FIG. 1;
  • FIG. 3 is a schematic three-dimensional structural diagram of a middle pixel unit of the display panel shown in FIG. 2;
  • FIG. 4 is a schematic structural diagram of a driving circuit of a pixel unit in the display panel shown in FIG. 3;
  • FIG. 5 is a schematic diagram of a specific connection structure of the pixel driving circuit and the pixel unit shown in FIG. 4;
  • FIG. 6 is a schematic diagram of the partition of the pixel driving circuit shown in FIG. 4;
  • FIG. 7 is a schematic diagram of a circuit structure of a pixel driving circuit in a plurality of display areas shown in FIG. 6;
  • FIG. 8 is a schematic diagram of a circuit structure of a pixel driving circuit in each display area shown in FIG. 7;
  • FIG. 9 is a timing chart of receiving image data by the pixel drive circuit in the display area shown in FIG. 8;
  • FIG. 10 is an equivalent circuit diagram of the image data transmission of the pixel drive circuit in a pixel area shown in FIG. 7;
  • FIG. 11 is a graph showing the transmission rate between the clock signal of the pixel driving circuit and the image data in one pixel area shown in FIG. 7 .
  • FIG. 1 is a schematic side structure diagram of a display terminal of the present application.
  • the electronic terminal 10 includes a protective layer 13 and a carrier panel 11 which are arranged in layers.
  • the carrying panel 11 includes an array substrate 111 and a plurality of light-emitting elements 11 a connected in a matrix and arranged on the surface of the array substrate 111 for emitting light to display images.
  • the light-emitting elements 11 a are sandwiched between the protective layer 13 and the array substrate 111 .
  • the protective layer 13 is used to protect the light-emitting element 11a and prevent the light-emitting element 11a from being damaged.
  • the light-emitting element 11a is a Micro-Size Light Emitting Diode (Micro-Size Light Emitting Diode, Micro LED or ⁇ -LED), wherein the size of the light-emitting element 11a ranges from 1 to 100 ⁇ m. Since the micro light-emitting diodes are light-emitting elements made of semiconductor materials, the electronic terminal 10 including the micro light-emitting diodes can also be referred to as a semiconductor display device at this time.
  • the carrier panel 11 is a display panel
  • the light-emitting element 11a provided on the array substrate 111 is a pixel element for image display, which is used for image display.
  • the electronic terminal 10 may also be a light source
  • the array substrate 111 may be a supporting structure such as a circuit board.
  • the electronic terminal 10 may be a terminal device such as a wearable device such as a watch, a mobile phone, or a display.
  • the carrier panel 11 is taken as an example of a display panel to specifically describe the panel layer structure and the specific manufacturing process.
  • FIG. 2 is a schematic plan view of the carrying panel 11 shown in FIG. 1 .
  • the display area AA (Active Area) of the display panel 11 includes a plurality of pixel units P in an array and uniformly arranged, and each pixel unit P includes a plurality of light-emitting elements 11a arranged at a predetermined distance.
  • the pixel unit P includes a plurality of light-emitting elements 11a that emit light of different colors.
  • the non-display area NA Not active Area
  • the non-display area NA does not perform image display
  • other functional modules that drive the pixel unit to perform image display may be functional circuits such as a display driving circuit and a power supply circuit.
  • FIG. 3 is a schematic three-dimensional structural diagram of the pixel unit of the display panel 11 shown in FIG. 2 .
  • the pixel unit P includes light-emitting elements 11a-R for emitting red light, light-emitting elements 11a-G for green light, and light-emitting elements 11a-B for blue light.
  • the gray-scale brightness enables the pixel units P to emit light of different colors, thereby enabling the display panel 11 to display color images.
  • red is defined as the first color
  • green is defined as the second color
  • blue is defined as the third color.
  • the pixel unit P may further include light-emitting elements that emit four colors of red light, green light, blue light, and white light.
  • the first color can be one of the four colors of red, green, blue and white
  • the second color can be one of the four colors of red, green, blue and white
  • the third color can be The tri-color can be one of the four colors red, green, blue and white.
  • the first color, the second color and the third color may be different from each other.
  • the first color is green, the second color is blue, and the third color is red; or, the first color is blue, the second color is red, and the third color is green; or, the first color is white, the second color is blue, and the third color is red; or, the first color is green, the second color is white, and the third color is red; or, the first color is green, the second color is blue, The third color is white.
  • FIG. 4 is a schematic structural diagram of a driving circuit of a pixel unit in the display panel shown in FIG. 3 .
  • the display area AA includes a plurality of pixel units P arranged in an array and a plurality of pixel driving circuits PD arranged in an array.
  • one pixel driving circuit PD is connected to at least one pixel unit P, that is, one pixel driving circuit PD is connected to K pixel units, and K is a natural number greater than or equal to 1.
  • the display area AA includes pixel driving circuits PD arranged in a matrix of n*m, where n and m are natural numbers greater than 1.
  • a plurality of pixel driving circuits PD arranged in the display area AA may be as shown in FIG. 4: the pixel driving circuits PD in the first row: PD11, PD12, . . . PD1m; the pixel driving circuits PD in the second row: PD21, PD22,...PD2m; pixel driving circuit PD in the nth row: PDn1, PDn2,...PDnm.
  • the pixel drive circuit PD is also connected to the display drive circuit DD.
  • the display driving circuit DD is used for receiving the image data Data to be displayed and the clock signal CK from the timing control circuit.
  • the image data received by the display driving circuit DD is a digital signal.
  • the clock signal CK is a pulse signal with a preset pulse width (duty cycle).
  • the clock signal CK includes the data clock signal CLK and the global clock signal GCLK(GK), wherein the clock signal includes the data clock signal SCLK(SK) for controlling the timing of data loading of the pixel driving circuit PD.
  • the global clock signal GCLK is used to control the length of time during which the pixel driving circuit PD loads image data into the pixel units, that is, used to control the length of time during which each pixel unit emits light to display image data in one frame of image display period.
  • the global clock signal GCLK is the time control clock for the light-emitting element to emit light, and its clock frequency is related to the number of bits and the frame rate of the pixel unit.
  • the global clock signal GCLK can be expressed as: 2 12 *60Hz.
  • the pixel driving circuit PD receives the image data according to the clock signal, and when the image data is a digital signal, converts the image data into a driving data current of an analog signal, and then transmits and loads it into each light-emitting element in the pixel unit P, thereby controlling The light-emitting element emits light with corresponding brightness according to the image data and performs corresponding image display.
  • the pixel driving circuit PD controls the time length of the driving current supplied to each of the light-emitting elements according to the image data, wherein the light-emitting brightness of each of the light-emitting elements is positively correlated with the time length, that is, the image data is represented by binary
  • the gray-scale brightness is greater, the longer the time period for which the pixel driving circuit PD controls the driving current to supply each of the light-emitting elements, the correspondingly makes the brightness of the pixel unit greater; when the gray-scale brightness is smaller, the The shorter the time length that the pixel driving circuit PD controls the driving current to be supplied to each of the light-emitting elements, the smaller the brightness of the pixel unit is correspondingly.
  • the pixel driving circuit PD adopts a pulse width modulation (Pulse Width Modulation, PWM) method to control the length of time that the driving current is supplied to each of the light-emitting elements, that is, when the gray-scale brightness is greater, the pixel driving circuit PD outputs a
  • PWM Pulse Width Modulation
  • the display driver circuit DD may be a Display Driver Integrated Circuit (DDIC) in the form of an integrated circuit, that is, the display driver circuit DD can simultaneously output image data, data clock signal, global clock signal, and frame synchronization signal , line sync signal, etc.
  • DDIC Display Driver Integrated Circuit
  • FIG. 5 is a schematic diagram of a specific connection structure of the pixel driving circuit PD and the pixel unit P shown in FIG. 4 .
  • one pixel driving circuit PD is connected to 4 pixel units, that is, K is 4.
  • the 4 pixel units are respectively represented as P1 ⁇ P4
  • Each pixel unit P includes three light-emitting elements, and the three light-emitting elements are the light-emitting elements 11a-R(R) that emit red light, the light-emitting elements 11a-G(G) that emit green light, and the light-emitting elements 11a-G(G) that emit blue light.
  • the three light-emitting elements 11a-R, 11a-G, and 11a-B are all micro light-emitting diodes ⁇ -LED, wherein the anode of each light-emitting element serving as the micro light-emitting diode ⁇ -LED is connected to the driving power supply Vd, and the cathode is connected to the pixel drive circuit PD.
  • the anodes of the light-emitting elements 11a-R are connected to the driving power supply Vd-r
  • the anodes of the light-emitting elements 11a-G are connected to the driving power supply Vd-g
  • the anodes of the light-emitting elements 11a-B are connected to the driving power supply Vd-b.
  • the pixel driving circuit PD includes a set of input interfaces I1 and four sets of output interfaces O corresponding to four pixel units.
  • the four sets of output interfaces O are marked as O1 to O4 respectively as shown in FIG. 5 .
  • the input interface I1 is connected to the display driving circuit DD for receiving image data and clock signals to be displayed from the display driving circuit DD, and each group of output interfaces O1 is connected to a pixel unit P, wherein each group of output interfaces O1 includes A plurality of interface ends, each interface end is connected to a light-emitting element.
  • the output interface O1 is connected to the pixel unit P1
  • the output interface O2 is connected to the pixel unit P2
  • the output interface O3 is connected to the pixel unit P3
  • the output interface O4 is connected to the pixel unit P4.
  • each group of output interfaces O1 includes three interface terminals, and each interface terminal is correspondingly connected to the cathode of the light-emitting element.
  • the pixel driving circuit PD receives the image data according to the clock signal, and when the image data is a digital signal, converts the image data into a driving data current of an analog signal, and then transmits and loads it into each light-emitting element in the pixel unit P, thereby controlling The light-emitting element emits light with corresponding brightness according to the image data and performs corresponding image display.
  • FIG. 6 is a schematic diagram of a partition of the pixel driving circuit shown in FIG. 4 .
  • the display area AA includes a pixel area DB (display pixel block) connected in a matrix with N rows*M columns, wherein M and N are both natural numbers greater than 1.
  • each pixel area DB includes a plurality of pixel driving circuits PD.
  • the pixel regions DB in any column of display regions are all connected to the same set of data interfaces in the display driving circuit DD, and at the same time, the pixel regions DB of different columns are connected to different sets of data interfaces. Meanwhile, each pixel area DB receives a different clock signal, respectively.
  • the display driving circuit DD includes M groups of data interfaces DI (data interfaces), and the pixel driving circuits PD in the pixel regions DB of the same column are connected to a group of data interfaces DI through a group of data lines DL (Data Line).
  • the M groups of data interfaces DI are respectively marked as DI1 to DIM
  • the M groups of data lines DL are respectively marked as DL1 to DLM.
  • the display area of the M column of the first row the pixel area DB11, the pixel area DB12, ..., the pixel area DB1M;
  • the display area of column M in the second row pixel area DB21, pixel area DB22, pixel area DB2M;
  • the display area of the Nth row and the M column the pixel area DBN1, the pixel area DBN2, and the pixel area DBNM.
  • the display area pixel area DB11, pixel area DB21, ... located in the first column, the pixel area DBN1 is connected to the first group of data interfaces DI1 through the first group of data lines DL1;
  • the display area pixel area DB12, pixel area DB22, ... located in the second column, the pixel area DBN2 is connected to the second group of data interfaces DI1 through the second group of data lines DL2;
  • the pixel driving circuits PD in the pixel regions DB of the same row simultaneously receive and load image data, and the pixel regions DB of different rows receive image data in different time periods.
  • the pixel driving circuit PD in the pixel area DB of the same row drives the corresponding light-emitting element to perform image display according to the image data.
  • each pixel area DB receives a separate set of clock signals, that is, different pixel units DB respectively receive a different set of clock signals CK, wherein the clock signals include the data clock signal SCLK ( FIG. 7 ) with the global clock signal GLCK ( Figure 7).
  • the display driving circuit DD outputs N*M groups of clock signals CK through N*M groups of clock interfaces CI respectively, and the N*M groups of clock interfaces CI are respectively marked as CI11, CI12, ..., CI1M; CI21, CI22 ,...CI2M;...,CIN1,CIN2,...CINM, the N*M groups of clock signals CK are marked as CK11, CK12,...,CK1M; CK21, CK22,...CK2M;...,CKN1,CKN2 , ... CKNM.
  • N*M groups of clock signals CK are respectively provided to the pixel areas DB11, DB12, ... ..., DB1M; DB21, DB22, ... DB2M; ..., DBN1, DBN2, ... DBNM.
  • FIG. 7 is a schematic diagram of a circuit structure of a pixel driving circuit in a plurality of display areas as shown in FIG. 6
  • FIG. 8 is a schematic diagram of a circuit structure of a pixel driving circuit in each display area shown in FIG. 7 . .
  • each display area in the pixel area DB with N rows*M columns connected in a matrix each pixel area DB includes a pixel driving circuit PD connected in a matrix with Q rows*P columns, wherein, Q and P are natural numbers greater than 1, respectively.
  • the pixel driving circuits of the P column in the first row pixel driving circuit PD11 , pixel driving circuit PD12 , . . . , pixel driving circuit PD1P;
  • the pixel driving circuit of the P column in the second row pixel driving circuit PD21, pixel driving circuit PD22, pixel driving circuit PD2P;
  • the pixel drive circuit of the Qth row and the P column pixel drive circuit PDN1, pixel drive circuit PDN2, pixel drive circuit PDQP.
  • the pixel driving circuits PD in the same column are cascaded in sequence to form the first-level pixel driving circuit to the Q-th level pixel driving circuit, wherein the input interface I1 of the first-level pixel driving circuit PD is connected to the display driving circuit DD A set of data interfaces and clock interfaces are used to receive image data and clock signals to be displayed; the input interface I1 of the second-level pixel driving circuit PD is connected to the output interface O1 of the first-level pixel driving circuit PD; the third-level pixel driving circuit The input interface I1 of the PD is connected to the output interface O1 of the second-level pixel driving circuit PD; and so on, the input interface I1 of the Q-level pixel driving circuit PD is connected to the output interface O1 of the Q-1-level pixel driving circuit PD.
  • the pixel driving circuit PD11 -pixel For example, as shown in FIG. 8 , taking the pixel region DBij of the i-th row and the j-th column as an example, in the pixel region DBij, for the pixel driving circuit PD of the first column, the pixel driving circuit PD11 -pixel
  • the driving circuits PDQ1 are cascaded in sequence to form a Q-level cascaded pixel driving circuit.
  • the pixel drive circuit PD11 is used as the first-stage pixel drive circuit
  • the pixel drive circuit PD21 is used as the second-stage pixel drive circuit
  • the pixel drive circuit PD31 is used as the third-stage pixel drive circuit
  • the pixel drive circuit PDQ1 is used as the Q-th stage. pixel driver circuit.
  • the input interface I1 of the pixel driving circuit PD11 which is the first-stage pixel driving circuit, is connected to a group of data interfaces DIi1 and clock interfaces CIi1 of the display driving circuit DD, and is used to receive the image data DA1 to be displayed and the clock signal SK/CK1;
  • the input interface I1 of the pixel driving circuit PD21 as the second-stage pixel driving circuit is connected to the output interface O1 of the pixel driving circuit PD11, and receives the image data DA21 and the clock signal SK/CK21 from the pixel driving circuit PD11;
  • the input interface I1 of the pixel driving circuit PD31 (not shown in the figure), which is the third-stage pixel driving circuit, is connected to the output interface O1 of the pixel driving circuit PD21, and receives image data (not shown in the figure) and a clock signal (not shown in the figure) from the pixel driving circuit PD21. not shown);
  • the input interface I1 of the pixel drive circuit PDQ1 as the Q-th level pixel drive circuit is connected to the output interface O1 of the pixel drive circuit PDQ-11, and receives the image data DA Q1 and the clock signal SK/ from the pixel drive circuit PDQ-11. CKQ1.
  • the cascading method is the same as that of the pixel driving circuit PD in the first column, which is the same as that of the received image data and clock signals, which is not repeated in this embodiment.
  • the pixel driving circuits PD in different columns start to receive image data and clock signals at the same time, and the pixel driving circuits PD in the same column receive sequentially according to the cascaded order. image data and clock signals.
  • each column of pixel driving circuits requires a data interface 1
  • the display driving circuits DD include at least P*M data interfaces.
  • each pixel area DB includes an independent data clock signal SCLK and an independent global clock signal GCLK, then for the N*M display area, the display driving circuit DD includes 2*N* M clock interfaces.
  • the display driver circuit DD includes P*M+2*N*M data interfaces and clock interfaces. If both the data interface and the clock interface are defined as input/output interface I/O, then the display driver Circuit DD requires P*M+2*N*M input/output interface I/Os.
  • the display driving circuit DD needs 3m data interfaces and clock interfaces, while in the technical solution of this case, the display driving circuit DD includes m+2*N*M data interfaces and clock interfaces, while M, N are all data less than m, thus, the input/output interface I/O required by the display driving circuit DD can be effectively reduced, and then a plurality of matrix-connected pixel driving circuits PD and display driving circuits in the display area AA can be effectively reduced.
  • the complexity of the wiring between DDs increases the wiring space.
  • FIG. 9 is a timing diagram of receiving image data by the pixel driving circuit in the display area shown in FIG. 8 .
  • FIGS. 8-9 the process of receiving image data by the pixel driving circuit in a display area is described in detail.
  • Data is the image data that needs to be received by the same column of pixel driving circuits in a display area
  • CLK is the pixel driving circuit that controls the same column of pixel driving circuits in a display area, and the pixel driving circuits of different levels receive images in time-sharing Data clock signal for data.
  • Data contains Q bits of image data, one bit of image data is corresponding to the image data loaded into a pixel drive circuit, correspondingly, CLK contains a clock pulse of Q cycles , corresponding to a clock pulse of one cycle, load one bit of image data into the corresponding pixel drive circuit PD.
  • the image data of the first bit in the image data Data is loaded into the pixel drive circuit PD1j of the first stage;
  • the image data of the second bit in the image data Data is loaded into the pixel driving circuit PD2j of the second stage;
  • the image data of the third bit in the image data Data is loaded into the pixel driving circuit PD3j of the third stage;
  • the image data of the Qth bit in the image data Data is loaded into the pixel driving circuit PDQj of the Qth stage.
  • the display driving circuit DD loads the image data into the display area of the Nth row according to the timing synchronization system Vk1, that is, for the pixel area DBN1 to the pixel area DBNM of the Nth row, the image data Data are simultaneously received, and each display area of the Nth row receives the image data Data at the same time.
  • image data is sequentially loaded from the pixel driving circuit PD1j of the first stage to the pixel driving circuit PDQj of the Qth stage according to the data clock signal CLK.
  • the light-emitting elements are further controlled to emit light according to the image data under the control of the global clock signal to perform image display.
  • the display driving circuit DD further loads the image data into the display area of the N-1th row according to the timing synchronization system Vk1, that is, for the pixel area DB(N-1)1 to the pixel area DB(N-1 of the N-1th row 1)
  • M receives image data Data at the same time, and in each display area of the Nth row, the image data is sequentially loaded from the pixel driving circuit PD1j of the first stage to the pixel driving circuit PDQj of the Qth stage according to the data clock signal CLK.
  • the pixel area DB(N-1)1 to the pixel area DB(N-1)M in the N-1th row of the pixel area DB(N-1)1 to the pixel area DB(N-1)M at all levels of the pixel drive circuit PD loads the image data, and further controls the light emission according to the image data under the control of the global clock signal
  • the element emits light to perform image display.
  • the display driver circuit DD finally loads the image data into the display area of the first row according to the timing synchronization system Vk1, that is, the pixel area DB11 to the pixel area DB1M of the first row receive the image data Data at the same time.
  • image data is sequentially loaded from the pixel driving circuit PD1j of the first stage to the pixel driving circuit PDQj of the Qth stage according to the data clock signal CLK.
  • the light-emitting elements are further controlled to emit light according to the image data under the control of the global clock signal to perform image display.
  • the pixel driving circuits PD in the display area AA are divided into a plurality of pixel areas DB, and then the pixel driving circuits PD in each pixel area DB are connected in a cascade manner to transmit image data.
  • Each pixel area DB receives the clock signal independently, thereby effectively reducing the transmission power consumption of the clock signal during the transmission process.
  • the display area AA when the display area AA only needs to perform image display in a part of the area, it only needs to load the image data in the part of the pixel area DB where the image display is performed, and the area that does not need to perform image display can be in a black screen state without loading data, that is, Image display is performed in a partial area of the display area AA, thereby further reducing the power consumption of data transmission.
  • the image when the electronic terminal 10 is in a standby state or a low power consumption state, the image does not need to be displayed in full screen, but only needs to be displayed in the preset partial display area AA. At this time, only the image data needs to be loaded into the preset local display area AA
  • the pixel area DB in the preset partial display area AA is sufficient, and the pixel area DB other than the preset partial display area AA does not need to be loaded with image data. It can be seen that, because other pixel areas DB other than the preset local display area AA do not need to load image data, the power consumption of transmitting image data to this partial area can be effectively saved.
  • FIG. 10 is the equivalent circuit diagram of the image data transmission of the pixel driving circuit in one pixel area as shown in FIG. 7, and FIG. 10 is the clock signal and image of the pixel driving circuit in one pixel area as shown in FIG. 7. Data transfer rate graph.
  • the image data Data when the image data Data is transmitted in any pixel area, the image data Data passes through the wiring resistance R_m, the wiring capacitance Cm and the grounding resistance R-gnd-m on the display substrate (backplane circuit board). , and then pass through Q data routing resistors R_sig and Q input/output buffer interface I/O buffers and transfer.
  • the Q input/output buffer interface I/O buffers are the input/output interfaces of the Q-level cascaded pixel drive circuit PD.
  • the input/output buffer interface I/O buffer of each stage of the pixel driving circuit PD is also connected to the ground terminal through the connecting terminal capacitor Cpad and the grounding resistor R-gnd of the pixel driving circuit PD.
  • Table 1 is a list of clock signal and image data power consumption shown in FIG. 7 and FIG. 10 .
  • V3_1 represents the waveform of the data cascade link shown in Figure 7
  • V1_3 is the waveform representing the main data link shown in Figure 7
  • V2_2 represents each pixel
  • FIG. 11 in the embodiment of the present application, the data transmission rate when the data is cascaded and the clock signal transmission when the clock is cascaded are obviously greatly improved.
  • N*Q is 320 and M*P is 320
  • M*P is 320
  • the pixel shown in FIG. 7 is determined according to the aforementioned technical method.
  • the power consumption calculation results of data transmission and clock signal transmission in the driving circuit are shown in Table 2-Table 3.
  • Table 2 is the parameter definition of the pixel driving circuit included in the display area AA
  • Table 3 is the data transmission and the pixel driving circuit. The power consumption of the clock signal transmission.
  • Table 2 The power consumption of data transmission and clock signal transmission in the pixel drive circuit
  • the pixel and the pixel driving circuit are partitioned and cascaded in the block, which can effectively ensure the clock and the data on the data line in the data transmission.
  • the signal integrity of data can be greatly reduced, and the power consumption of data transmission can be greatly reduced, thereby reducing the overall power consumption of display panels and semiconductor display devices.

Abstract

一种信号传输功率较小、布线空间较大的显示面板（11），及一种包括显示面板（11）的半导体显示装置。显示面板（11）包括N行*M列呈矩阵式连接的像素区域（DB），每个像素区域（DB）包括Q行*P列呈矩阵式连接的像素驱动模组，每个像素驱动电路（PD）连接至少一个像素单元（P），且像素驱动电路（PD）依据待显示的图像数据驱动像素单元（P）发光以显示图。任意一列像素区域（DB）中的全部像素区域（DB）均连接于同一组数据接口（DI），不同列的像素区域（DB）连接不同组的数据接口（DI）。任意一个像素区域（DB）内，任意一列像素驱动电路（PD）中的多个像素驱动电路（PD）依次级联形成Q级级联的像素驱动电路（PD），处于第一级的像素驱动电路（PD）连接一个数据接口（DI）以接收图像数据，图像数据按照级联顺序传输至第Q级像素驱动电路（PD）。

Description

显示面板与半导体显示装置
本申请要求于2020年09月21日提交中国专利局、申请号为202011012477.3、申请名称为“显示面板与半导体显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种以微型发光二极管作为发光元件的显示面板与半导体显示装置。
背景技术
Micro LED(Micro-Size Light Emitting Diode,Micro LED或者μ-LED)称为微型发光二极管，为将传统LED阵列化、微缩化后定址巨量转移到电路基板上，形成超小间距LED，将毫米级别的LED长度进一步微缩到微米级，以达到超高像素、超高解析率。Micro LED具备无需背光源、能够自发光的特性，Micro LED色彩较容易准确的调试，且具有较长的发光寿命和更高的亮度，且封装要求低，更容易实现柔性及无缝拼接显示，是未来极具发展前景的显示器类型之一。
显示面板在显示区域内设置矩阵式连接的像素单元，每个像素单元包含有多个μ-LED以及至少一个集成的像素驱动电路，像素驱动电路用于接收图像数据并且依据图像数据控制多个μ-LED的发光亮度。其中，每个像素驱动电路均需要直接连接至显示驱动电路中以接收图像数据与时钟信号，显然需要提供为显示驱动电路提供较多的输入/输出接口(input/output port，I/O)，这就像素驱动电路与显示驱动电路之间的连接走线较多，导致显示面板的布线空间较为拥挤，并且像素驱动电路与显示驱动电路之间的走线路径较长，导致图像数据与时钟信号的功耗较大。
发明内容
为解决前述技术问题，本申请实施例提供一种信号传输功率较小、布线空间较大的显示面板以及包含前述显示面板的半导体显示装置。
第一方面，在本申请的一种实现方式中，提供一种显示面板，包括N行*M列呈矩阵式连接的像素区域，每个像素区域包括Q行*P列呈矩阵式连接的像素驱动模组，每个像素驱动电路连接至少一个像素单元，且所述像素驱动电路依据待显示的图像数据驱动所述像素单元发光以显示图，所述N、M、Q、P为大于1的自然数。其中，任意一列像素区域中的全部像素区域均连接于同一组数据接口，不同列的像素区域连接不同组的数据接口。任意一个所述像素区域内，任意一列像素驱动电路中的多个像素驱动电路依次级联形成Q级级联的像素驱动电路，处于第一级的像素驱动电路连接一个数据接口以接收所述图像数据，所述图像数据按照级联顺序传输至第Q级像素驱动电路。
将显示区域中的像素驱动电路分为多个像素区域，然后每个像素区域内的像素驱动电路通过级联的方式连接并进行图像数据的传输，每个像素区域均单独接收图像数据，从而有效降低了图像数据在传输过程中的传输功耗，同时，每个像素区域中的像素驱动电路依次级联，有效降低了图像数据传输用的走线以及接口数量以及图像数据的传输功耗，保证图像数据传输的准确性。
进一步，当显示区域仅需要针在部分区域进行图像显示时，仅需要在进行图像显示的部分像素区域加载图像数据，而无需执行图像显示的区域则可以无需加载数据而处于黑屏状态，即在显示区域的局部区域进行图像显示，从而可进一步的降低数据传输功耗。
在一实施例中，至少两个不同的所述像素区域的显示驱动模组连接不同的时钟接口，所述时钟接口包括提供数据时钟信号的数据时钟接口，所述数据时钟信号用于控制任意一列像素驱动电路中的多个像素驱动电路加载所述图像数据的时序。处于第一级的像素驱动电路连接一个数据时钟接口以接收所述数据时钟信号，所述数据时钟信号按照级联顺序传输至第Q级像素驱动电路。
将显示区域中的像素驱动电路分为多个像素区域，然后每个像素区域内的像素驱动电路通过级联的方式连接并进行图像数据的传输，每个像素区域均单独接收时钟信号，从而有效降低了时钟信号在传输过程中的传输功耗。
在一实施例中，所述数据时钟信号包括Q个连续的脉冲信号，其中，对应每一个脉冲信号加载一个比特字节的图像数据至一级像素驱动电路，依据所述Q个连续的脉冲信号将图像数据分别加载至所述Q级像素驱动电路。数据时钟中的每个脉冲信号对应一级像素驱动电路，从而依据数据时钟准确将图像数据加载至对应的像素驱动电路以及像素单元中。
在一实施例中，所述时钟接口还包括全局数据时钟接口，所述全局数据时钟信号用于控制每个像素单元在一帧图像时间长度中的发光的时长，处于第一级的像素驱动电路连接一个全局时钟接口以接收全局时钟信号，所述全局时钟信号按照级联顺序传输至第Q级像素驱动电路。全局时钟信号与数据时钟信号配合准确控制像素驱动电路驱动像素单元发光时长，使得像素单元依据图像数据准确出射光线显示图像。
在一实施例中，每个像素单元包括三个发光元件，每个发光元件出射不同颜色的光线，所述发光元件为微型发光二极管，所述微型发光二极管的阳极连接驱动电源，所述微型发光二极管的阴极连接所述像素驱动电路，所述驱动电源用于驱动为所述发光元件提供驱动电流；
所述像素驱动电路依据所述图像数据控制所述驱动电流提供至每个所述发光元件的时间长度，其中，每个所述发光元件的发光亮度与所述时间长度呈正相关。
在一实施例中，每个像素驱动电路连接四个所述像素单元，所述像素驱动电路包括一个输入接口与四组输出接口，所述输入接口连接一个所述数据接口，一组所述输出接口连接一个像素中的所述三个发光元件的阴极。像素驱动电路通过驱动四个像素单元，使得像素驱动电路的驱动能力与作为负载的像素单元较为匹配，从而保证图像数据的准确显示。
在一实施例中，所述像素驱动电路为微型集成电路。
在一实施例中，所述显示面板包括显示区域与非显示区域，所述N行*M列呈矩阵式连接的像素区域设置于所述显示区域内。所述显示面板还包括设置于非显示区域的显示驱动电路，所述显示驱动电路连接所述多个像素区域内的像素驱动电路，用于输出所述图像数据、数据时钟信号以及全局时钟信号至所述像素驱动电路。显示驱动电路输出的图像数据与时钟信号相互配合通过像素驱动电路准确记载至像素中进行图像显示，由于显示驱动电路与分区的像素驱动电路进行连接，有效减少了信号输入/输出接口以及走线数量，从而简化了显示驱动电路的设计以及布线空间，同时也降低了传输图像数据与时钟信号的功耗。
在一实施例中，若不同的每个所述像素区域的显示驱动模组连接不同的时钟接口时，所述显示驱动电路包括P*M个数据接口、M*N个数据时钟接口以及M*N个全局时钟接口。
在第二方面，在本申请一种实施例中，提供一种半导体显示装置，所述半导体显示装置包括前述的显示面板。
附图说明
图1为为本申请一种显示终端的侧面结构示意图；
图2为图1所示承载面板的平面结构示意图；
图3为图2所示显示面板的中像素单元的立体结构示意图；
图4为图3所示显示面板中像素单元的驱动电路结构示意图；
图5为图4所示像素驱动电路与像素单元的具体连接结构示意图；
图6为图4所示像素驱动电路分区示意图；
图7为图6所示多个显示区域中像素驱动电路的电路结构示意图；
图8为图7所示每一个显示区域中像素驱动电路的电路结构示意图；
图9为图8所示显示区域内像素驱动电路接收图像数据的时序图；
图10为图7所示一个像素区域内像素驱动电路图像数据传输的等效电路图；
图11为图7所示一个像素区域内像素驱动电路时钟信号与图像数据的传输速率曲线图。
具体实施方式
下面以具体的实施例对本申请进行说明。
请参阅图1，其为本申请一种显示终端的侧面结构示意图。如图1所示，电子终端10包括层叠设置的保护层13与承载面板11。其中，承载面板11包括阵列基板111以及多个呈矩阵式连接并设置于阵列基板111表面、用于出射光线以显示图像的发光元件11a，发光元件11a夹设于保护层13与阵列基板111之间，保护层13用于保护发光元件11a，防止发光元件11a损坏。
本实施例中，发光元件11a为微型发光二极管(Micro-Size Light Emitting Diode,Micro LED或者μ-LED)，其中，发光元件11a的尺寸范围为1～100μm。由于微型发光二极管为半导体材质的发光元件，此时包含微型发光二极管的电子终端10也可称为半导体显示装置。
本实施例中，电子终端10为显示终端时，承载面板11即为显示面板，阵列基板111上设置的发光元件11a即作为图像显示的像素元件，用于执行图像显示。在本申请其他实施例中，电子终端10还可以为光源，阵列基板111则可以为电路板等支撑结构。
本实施例中，电子终端10可以为可穿戴设备的手表、手机或者显示器等终端设备。
本实施例中，以承载面板11为显示面板为例具体说明其面板层结构以及具体的制程。
请参阅图2与图3，图2为图1所示承载面板11的平面结构示意图。如图2所述，在显示面板11的显示区域AA(Active Area)内包括多个呈阵列且均匀排布的像素单元P，每一个像素单元P包括多个间隔预设距离设置的发光元件11a其中，像素单元P中包括有多个出射不同颜色光线的发光元件11a。在显示面板的非显示区域NA(Not active Area)(请参阅图4)设置有驱动像素单元执行图像显示的其他功能模组。其中，本实施例中，非显示区域NA并不执行图像显示，驱动像素单元执行图像显示的其他功能模组可以为显示驱动电路、电源电路等功能电路。
请参阅图3，其为图2所示显示面板11的中像素单元的立体结构示意图。如图3所示，像素单元P包括出射红色光线的发光元件11a-R、绿色光线的发光元件11a-G，蓝色光线的发光元件11a-B，通过控制发光元件11a出射的不同颜色光线的灰阶亮度，即可使得像素单元P出射不同颜色彩色光线，进而使得显示面板11能够执行彩色图像的显示。本实施例中，红色定义为第一颜色，绿色定义为第二颜色，蓝色定义为第三颜色。
在本申请其他实施例中，像素单元P还可以包括出射红色光线、绿色光线、蓝色光线、白色光线四种颜色发光元件。此时，第一颜色则可为红色、绿色、蓝色与白色四种颜色中的一种颜色，第二颜色则可为红色、绿色、蓝色与白色四种颜色中的一种颜色，第三颜色则可为红色、绿色、蓝色与白色四种颜色中的一种颜色。其中，在同一个像素单元P中，第一颜色、第二颜色与第三颜色互不相同即可。举例而言，第一颜色为绿色，第二颜色为蓝色、第三颜色为红色；或者，第一颜色为蓝色，第二颜色为红色、第三颜色为绿色；或者，第一颜色为白色，第二颜色为蓝色、第三颜色为红色；或者，第一颜色为绿色，第二颜色为白色、第三颜色为红色；或者，第一颜色为绿色，第二颜色为蓝色、第三颜色为白色。
请参阅图4，其为图3所示显示面板中像素单元的驱动电路结构示意图。
如图4所示，在显示区域AA中，包括多个呈阵列方式排布的像素单元P与多个呈阵列方式排布的像素驱动电路PD。其中，一个像素驱动电路PD连接于至少一个像素单元P，即是一个像素驱动电路PD连接K个像素单元，K为大于或者等于1的自然数。本实施例中，显示区域AA包括n*m呈矩阵排布的像素驱动电路PD，其中，n、m为大于1的自然数。
本实施例中，在显示区域AA排列的多个像素驱动电路PD可以如图4所示：第一行的像素驱动电路PD：PD11、PD12、……PD1m；第二行的像素驱动电路PD：PD21、PD22、……PD2m；第n行的像素驱动电路PD：PDn1、PDn2、……PDnm。
像素驱动电路PD还连接显示驱动电路DD。其中显示驱动电路DD用于自时序控制电路接收待显示的图像数据Data以及时钟信号CK。本实施例中，显示驱动电路DD接收的图像数据为数字形式的信号。时钟信号CK预设脉宽(占空比)的脉冲信号。本实施例中，时钟信号CK包括数据时钟信号CLK与全局时钟信号GCLK(GK)，其中，时钟信号包括数据时钟信号SCLK(SK)用于控制数据加载是像素驱动电路PD的时序。
全局时钟信号GCLK用于控制像素驱动电路PD将图像数据加载至像素单元的时间长度，即用于控制每个像素单元在一帧图像显示周期内发光显示图像数据的时间长度。本实施例中，全局时钟信号GCLK为发光元件的发光的时间控制时钟，其时钟频率与像素单元的比特字节(bit)数和帧率相关，当像素单元的灰阶采用12个二进制表示时，那么全局时钟信号GCLK可以表示为：2 12*60Hz。
像素驱动电路PD依据时钟信号接收图像数据，并且当图像数据为数字形式的信号时，将图像数据转换为模拟信号的驱动数据电流然后再传输加载至像素单元P中的各个发光元件中，从而控制发光元件依据图像数据出射相应亮度的光线并执行相应的图像显示。具体地，像素驱动电路PD依据图像数据控制驱动电流提供至每个所述发光元件的时间长度，其中，每个所述发光元件的发光亮度与所述时间长度呈正相关，即图像数据采用二进制表示的灰阶亮度，当灰阶亮度越大，像素驱动电路PD控制驱动电流提供至每个所述发光元件的时间长度越长，对应使得像素单元的亮度就越大；当灰阶亮度越小，像素驱动电路PD控制驱动电流提供至每个所述发光元件的时间长度越小，对应使得像素单元的亮度就越小。
本实施例中，像素驱动电路PD采用脉宽调制方式(Pulse Width Modulation，PWM)控制驱动电流提供至每个所述发光元件的时间长度，即当灰阶亮度越大，像素驱动电路PD输出的PWM信号的占空比(duty)越大，对应控制驱动电流提供至每个所述发光元件的时间长度越长，当灰阶亮度越小，像素驱动电路PD输出的PWM信号的占空比越小，对应控制驱动电流提供至每个所述发光元件的时间长度越小。
本实施例中，显示驱动电路DD可以为集成电路形式的显示驱动集成电路(Display Driver  Integrated Circuit,DDIC)，即显示驱动电路DD能够同时输出图像数据、数据时钟信号、全局时钟信号、帧同步信号、行同步信号等。
更为具体地，请参阅图5，其为图4所示像素驱动电路PD与像素单元P的具体连接结构示意图。
本实施例中，一个像素驱动电路PD连接4个像素单元，即是K为4。其中，4个像素单元分别表征为P1～P4
每一个像素单元P包括三个发光元件，三个发光元件分别为出射红色光线的发光元件11a-R(R)、绿色光线的发光元件11a-G(G)，蓝色光线的发光元件11a-B(B)。三个发光元件11a-R、11a-G、11a-B均为微型发光二极管μ-LED，其中，作为微型发光二极管μ-LED的每一个发光元件的阳极连接驱动电源Vd，阴极连接于像素驱动电路PD。本实施例例中，发光元件11a-R的阳极连接驱动电源Vd-r，发光元件11a-G的阳极连接驱动电源Vd-g，发光元件11a-B的阳极连接驱动电源Vd-b。
本实施例中，像素驱动电路PD包括一组输入接口I1以及对应4个像素单元的4组输出接口O，本实施例中，4组输出接口O如图5所示分别标记为O1～O4。其中，输入接口I1连接于显示驱动电路DD，用于自显示驱动电路DD接收待显示的图像数据以及时钟信号，每一组输出接口O1连接一个像素单元P，其中，每一组输出接口O1包括多个接口端，每个接口端连接于一个发光元件。如图5所示，输出接口O1连接像素单元P1，输出接口O2连接像素单元P2，输出接口O3连接像素单元P3，输出接口O4连接像素单元P4。
其中，每一组输出接口O1中接口端的数量与像素单元P中发光元件的数量相同。本实施例中，每一组输出接口O1包括三个接口端，且每一个接口端相应连接于发光元件的阴极。
像素驱动电路PD依据时钟信号接收图像数据，并且当图像数据为数字形式的信号时，将图像数据转换为模拟信号的驱动数据电流然后再传输加载至像素单元P中的各个发光元件中，从而控制发光元件依据图像数据出射相应亮度的光线并执行相应的图像显示。
请参阅图6，其为图4所示像素驱动电路分区示意图。
如图6所示，在显示区域AA中，包括N行*M列呈矩阵式连接的像素区域DB(display pixel block)，其中，M、N均为大于1的自然数。其中，每个像素区域DB中包括多个像素驱动电路PD。任意一列显示区域中的像素区域DB均连接于显示驱动电路DD中同一组数据接口，同时，不同列的像素区域DB连接不同组数据接口。同时，每个像素区域DB分别接收不同的时钟信号。
具体地，显示驱动电路DD包括M组数据接口DI(data interface)，同一列的像素区域DB中的像素驱动电路PD通过一组数据线DL(Data Line)连接于一组数据接口DI。本实施例中，M组数据接口DI分别标示为DI1～DIM，M组数据线DL分别标示DL1～DLM。
其中，第一行的M列的显示区域：像素区域DB11、像素区域DB12、……，像素区域DB1M；
第二行的M列的显示区域：像素区域DB21、像素区域DB22、像素区域DB2M；
……，
第N行的M列的显示区域：像素区域DBN1、像素区域DBN2、像素区域DBNM。
位于第一列的显示区域像素区域DB11、像素区域DB21、……，像素区域DBN1通过第一组数据线DL1连接于第一组数据接口DI1；
位于第二列的显示区域像素区域DB12、像素区域DB22、……，像素区域DBN2通过第二组数据线DL2连接于第二组数据接口DI1；
……，
位于第M列的显示区域像素区域DB1M、像素区域DB2M、……，像素区域DBNM通过第M组数据线DLM连接于第M组数据接口DI1。
本实施例中，同一行的像素区域DB中的像素驱动电路PD同时接收并加载到图像数据，不同行的像素区域DB在不同时间段接收到图像数据。同一行的像素区域DB中的像素驱动电路PD在接收到图像数据后，依据图像数据驱动相应的发光元件进行图像显示。同时，本实施例中，每一个像素区域DB单独接收一组时钟信号，也即是不同的像素单元DB分别接收不同的一组时钟信号CK，其中，时钟信号包括数据时钟信号SCLK(图7)与全局时钟信号GLCK(图7)。
本实施例中，显示驱动电路DD通过N*M组时钟接口CI分别输出N*M组时钟信号CK，该N*M组时钟接口CI分别标示为CI11、CI12、……，CI1M；CI21、CI22、……CI2M；……，CIN1、CIN2、……CINM，该N*M组时钟信号CK分别标示为CK11、CK12、……，CK1M；CK21、CK22、……CK2M；……，CKN1、CKN2、……CKNM。N*M组时钟信号CK分别依次通过时钟接口CI11、CI12、……，CI1M；CI21、CI22、……CI2M；……，CIN1、CIN2、……CINM，对应提供至像素区域DB11、DB12、……，DB1M；DB21、DB22、……DB2M；……，DBN1、DBN2、……DBNM。
请一并参阅图7与图8，图7为如图6所示多个显示区域中像素驱动电路的电路结构示意图，图8为图7所示每一个显示区域中像素驱动电路的电路结构示意图。
如图7所示，N行*M列呈矩阵式连接的像素区域DB中的每一个显示区域，每个像素区域DB中包括Q行*P列呈矩阵式连接的像素驱动电路PD，其中，Q、P分别为大于1的自然数。
具体地，如图8所示，第一行的P列的像素驱动电路：像素驱动电路PD11、像素驱动电路PD12、……，像素驱动电路PD1P；
第二行的P列的像素驱动电路：像素驱动电路PD21、像素驱动电路PD22、像素驱动电路PD2P；
……；
第Q行的P列的像素驱动电路：像素驱动电路PDN1、像素驱动电路PDN2、像素驱动电路PDQP。
本实施例中，同一列的像素驱动电路PD依次级联，从而构成第一级像素驱动电路～第Q级像素驱动电路，其中，第一级像素驱动电路PD的输入接口I1连接显示驱动电路DD的一组数据接口以及时钟接口，用于接收待显示图像数据与时钟信号；第二级像素驱动电路PD的输入接口I1连接第一级像素驱动电路PD的输出接口O1；第三级像素驱动电路PD的输入接口I1连接第二级像素驱动电路PD的输出接口O1；以此类推，第Q级像素驱动电路PD的输入接口I1连接第Q-1级像素驱动电路PD的输出接口O1。
举例而言，如图8所示，以对于第i行、第j列的像素区域DBij为例，在该像素区域DBij中，对于第1列像素驱动电路PD来说，像素驱动电路PD11～像素驱动电路PDQ1依次级联从而构成Q级级联的像素驱动电路。
如图8所示，像素驱动电路PD11作为第一级像素驱动电路，像素驱动电路PD21作为第 二级像素驱动电路，像素驱动电路PD31作为第三级像素驱动电路，像素驱动电路PDQ1作为第Q级像素驱动电路。
作为第一级像素驱动电路的像素驱动电路PD11的输入接口I1连接显示驱动电路DD的一组数据接口DIi1以及时钟接口CIi1，用于接收待显示图像数据DA1与时钟信号SK/CK1；
作为第二级像素驱动电路的像素驱动电路PD21的输入接口I1连接像素驱动电路PD11的输出接口O1，并从像素驱动电路PD11接收图像数据DA21与时钟信号SK/CK21；
作为第三级像素驱动电路的像素驱动电路PD31(图未示)的输入接口I1连接像素驱动电路PD21的输出接口O1，并从像素驱动电路PD21接收图像数据(图未示)与时钟信(图未示)；
以此类推，作为第Q级像素驱动电路的像素驱动电路PDQ1的输入接口I1连接像素驱动电路PDQ-11的输出接口O1，并从像素驱动电路PDQ-11接收图像数据DA Q1与时钟信号SK/CKQ1。
当然，对于第2-P列的像素驱动电路PD来说，其级联方式与接收的图像数据、时钟信号的与第1列的像素驱动电路PD相同，本实施例不再赘述。
其中需要说明的是，对于任一个像素区域DB中的像素驱动电路而言，不同列的像素驱动电路PD同时开始接收图像数据以及时钟信号，同一列的像素驱动电路PD依据级联的顺序依次接收图像数据以及时钟信号。
本实施例中，对于显示区域AA中的多个矩阵式连接的像素驱动电路PD以及显示驱动电路DD来说以及对于图像数据而言，每一列像素驱动电路需要一个数据接口1，由于每一个像素区域DB包括P列像素驱动电路PD，那么对于M列显示区域而言，显示驱动电路DD至少包括P*M个数据接口。其中，P*M也即是像素驱动电路PD的列数m，即P*M＝m。
对于时钟信号而言，每一个像素区域DB包括1个独立的数据时钟信号SCLK与1个独立的全局时钟信号GCLK，那么对于N*M的显示区域而言，显示驱动电路DD包括2*N*M个时钟接口。
由此，本实施例中，显示驱动电路DD包括P*M+2*N*M个数据接口和时钟接口，若将数据接口与时钟接口均定义为输入/输出接口I/O，那么显示驱动电路DD需要P*M+2*N*M个输入/输出接口I/O。
然而，传统的技术方案中，显示驱动电路DD需要3m个数据接口以及时钟接口，而本案技术方案中，显示驱动电路DD包括m+2*N*M个数据接口和时钟接口，而M、N均为小于m的数据，由此，显示驱动电路DD需要的输入/输出接口I/O有效减少，那么即可有效降低显示区域AA中的多个矩阵式连接的像素驱动电路PD与显示驱动电路DD之间走线的复杂程度，提高了布线空间。
请参阅图9，图9为图8所示显示区域内像素驱动电路接收图像数据的时序图，现结合图8-图9，具体说明一个显示区域内像素驱动电路接收图像数据的过程。
图9中各个符号表示说明如下：Data为一个显示区域内同一列像素驱动电路需要接收的图像数据；CLK为控制一个显示区域内同一列像素驱动电路中，不同级的像素驱动电路分时接收图像数据的数据时钟信号。
Data包含有Q个比特字节(bit)的图像数据，一个比特字节(bit)的图像数据为对应加载至一个像素驱动电路的图像数据，对应地，CLK包含有个Q个周期的时钟脉冲，对应一个 周期的时钟脉冲，加载一个比特字节(bit)的图像数据至对应的像素驱动电路PD中。
具体地，在数据时钟信号CLK的第一个周期的时钟脉冲，图像数据Data中第一个比特字节(bit)的图像数据加载至第一级的像素驱动电路PD1j中；
在数据时钟信号CLK的第二个周期的时钟脉冲，图像数据Data中第二个比特字节(bit)的图像数据加载至第二级的像素驱动电路PD2j中；
在数据时钟信号CLK的第三个周期的时钟脉冲，图像数据Data中第三个比特字节(bit)的图像数据加载至第三级的像素驱动电路PD3j中；
……，以此类推，在数据时钟信号CLK的第Q个周期的时钟脉冲，图像数据Data中第Q个比特字节(bit)的图像数据加载至第Q级的像素驱动电路PDQj中。
现结合图5-图9，具体说明在显示区域AA内各像素区域DB中显示驱动电路的工作时序。
显示驱动电路DD依据时序同步系统Vk1将图像数据加载至第N行的显示区域中，即是对于第N行的像素区域DBN1～像素区域DBNM同时接收到图像数据Data，第N行的每个显示区域中依据数据时钟信号CLK将图像数据自第一级的像素驱动电路PD1j依序加载至第Q级的像素驱动电路PDQj中。
当第N行的像素区域DBN1～像素区域DBNM中各级像素驱动电路PD加载完成图像数据，进一步在全局时钟信号控制下依据图像数据控制发光元件发光以执行图像显示。
显示驱动电路DD进一步依据时序同步系统Vk1将图像数据加载至第N-1行的显示区域中，即是对于第N-1行的像素区域DB(N-1)1～像素区域DB(N-1)M同时接收到图像数据Data，第N行的每个显示区域中依据数据时钟信号CLK将图像数据自第一级的像素驱动电路PD1j依序加载至第Q级的像素驱动电路PDQj中。
当第N-1行的像素区域DB(N-1)1～像素区域DB(N-1)M中各级像素驱动电路PD加载完成图像数据，进一步在全局时钟信号控制下依据图像数据控制发光元件发光以执行图像显示。
以此类推，显示驱动电路DD最后依据时序同步系统Vk1将图像数据加载至第一行的显示区域中，即是对于第一行的像素区域DB11～像素区域DB1M同时接收到图像数据Data，第一行的每个显示区域中依据数据时钟信号CLK将图像数据自第一级的像素驱动电路PD1j依序加载至第Q级的像素驱动电路PDQj中。
当第一行的像素区域DB11～像素区域DB1M中各级像素驱动电路PD加载完成图像数据，进一步在全局时钟信号控制下依据图像数据控制发光元件发光以执行图像显示。
本实施例中，将显示区域AA中的像素驱动电路PD分为多个像素区域DB，然后每个像素区域DB内的像素驱动电路PD通过级联的方式连接并进行图像数据的传输，每个像素区域DB均单独接收时钟信号，从而有效降低了时钟信号在传输过程中的传输功耗。
另外，当显示区域AA仅需要针在部分区域进行图像显示时，仅需要在进行图像显示的部分像素区域DB加载图像数据，而无需执行图像显示的区域则可以无需加载数据而处于黑屏状态，即在显示区域AA的局部区域进行图像显示，从而可进一步的降低数据传输功耗。
举例而言，当电子终端10处于待机状态或者低功耗状态，并不需要全屏显示图像，而仅需要在预设的局部显示区域AA进行图像显示，此时，仅需将图像数据加载至预设的局部显示区域AA中的像素区域DB即可，而除了预设的局部显示区域AA之外的像素区域DB则 无需加载图像数据。可见，由于除了预设的局部显示区域AA之外的其他像素区域DB则无需加载图像数据，就可以有效节省将图像数据传输至该部分区域的功耗。
请参阅图10-图11，图10为如图7所示一个像素区域内像素驱动电路图像数据传输的等效电路图，图10为如图7所示一个像素区域内像素驱动电路时钟信号与图像数据的传输速率曲线图。
如图10所示，图像数据Data在任意一个像素区域内传输时，图像数据Data经过显示基板(背板电路板)上的走线电阻R_m、走线电容Cm以及接地电阻R-gnd-m后，再经过Q个数据走线电阻R_sig以及Q个输入/输出缓冲接口I/O buffer以及传递。其中，Q个输入/输出缓冲接口I/O buffer则为Q级级联的像素驱动电路PD的输入/输出接口。其中，每一级像素驱动电路PD的输入/输出缓冲接口I/O buffer还通过像素驱动电路PD的连接端电容Cpad以及接地电阻R-gnd连接接地端。
进一步，请参阅表1，其为图7以及图10所示时钟信号与图像数据功耗列表。
Figure PCTCN2021119100-appb-000001
Figure PCTCN2021119100-appb-000002
表1图像数据与时钟信号的功耗计算方式
如图11所示，图11中各个符号表示说明如下：V3_1表征如图7所示数据级联链路的波形；V1_3为表征如图7所示数据主链路的波形；V2_2为每个像素驱动电路直接连接显示驱动电路时数据传输的信号波形。如图11所示，本申请实施例中数据级联时数据传输速率以及时钟级联时时钟信号传输明显有了较大提高。
更为具体地，当N*Q为320，M*P为320时，即显示区域AA中包括320*320呈矩阵式连接的像素驱动电路PD时，依据前述技术方式确定如图7所示像素驱动电路中数据传输与时钟信号传输的功耗计算结果如表2-表3所示，其中表2为显示区域AA中包含的像素驱动电路的参数定义，表3为像素驱动电路中数据传输与时钟信号传输的功耗。
参数 数值 单位
链路电容C m 5 pF
Pad电容C pad 0.1 pF
信号幅度V sig 1 V
子像素bit数 12 bit
PD控制像素数 5 pixel
PD X方向数量m 320 个
PD Y方向数量n 320 个
像素区域行数N 16 个
像素区域列数M 8 个
PD行数/Block P 20 个
PD列数/Block Q 40 个
帧率F vsync 60 Hz
GCLK频率 245760 Hz
表2像素驱动电路中数据传输与时钟信号传输的功耗
Figure PCTCN2021119100-appb-000003
Figure PCTCN2021119100-appb-000004
表3像素驱动电路中数据传输与时钟信号传输的功耗
可见，本实施例中，对巨量的μ-LED和像素驱动电路PD的信号传输中，采用像素与像素驱动电路分区和区块内级联，能够有效保证数据传输中数据线上的时钟和数据的信号完整性，同时可以大大降低数据传输功耗，继而降低显示面板、半导体显示装置的整体功耗。
以上所述是本申请的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本申请的保护范围。

Claims (10)

  1. 一种显示面板，其特征在于，包括N行*M列呈矩阵式连接的像素区域，每个像素区域包括Q行*P列呈矩阵式连接的像素驱动模组，每个像素驱动电路连接至少一个像素单元，且所述像素驱动电路依据待显示的图像数据驱动所述像素单元发光以显示图，所述N、M、Q、P为大于1的自然数；
    任意一列像素区域中的全部像素区域均连接于同一组数据接口，不同列的像素区域连接不同组的数据接口；
    任意一个所述像素区域内，任意一列像素驱动电路中的多个像素驱动电路依次级联形成Q级级联的像素驱动电路，处于第一级的像素驱动电路连接一个数据接口以接收所述图像数据，所述图像数据按照级联顺序传输至第Q级像素驱动电路。
  2. 根据权利要求1所述的显示面板，其特征在于，至少两个不同的所述像素区域的显示驱动模组连接不同的时钟接口，所述时钟接口包括提供数据时钟信号的数据时钟接口，所述数据时钟信号用于控制任意一列像素驱动电路中的多个像素驱动电路加载所述图像数据的时序；
    处于第一级的像素驱动电路连接一个数据时钟接口以接收所述数据时钟信号，所述数据时钟信号按照级联顺序传输至第Q级像素驱动电路。
  3. 根据权利要求2所述的显示面板，其特征在于，所述数据时钟信号包括Q个连续的脉冲信号，其中，对应每一个脉冲信号加载一个比特字节的图像数据至一级像素驱动电路，依据所述Q个连续的脉冲信号将图像数据分别加载至所述Q级像素驱动电路。
  4. 根据权利要求2所述的显示面板，其特征在于，所述时钟接口还包括全局数据时钟接口，所述全局数据时钟信号用于控制每个像素单元在一帧图像时间长度中的发光的时长；
    处于第一级的像素驱动电路连接一个全局时钟接口以接收全局时钟信号，所述全局时钟信号按照级联顺序传输至第Q级像素驱动电路。
  5. 根据权利要求1-4中任意一项所述的显示面板，其特征在于，每个所述像素单元包括三个发光元件，每个发光元件出射不同颜色的光线，所述发光元件为微型发光二极管，所述微型发光二极管的阳极连接驱动电源，所述微型发光二极管的阴极连接所述像素驱动电路，所述驱动电源用于驱动为所述发光元件提供驱动电流；
    所述像素驱动电路依据所述图像数据控制所述驱动电流提供至每个所述发光元件的时间长度，其中，每个所述发光元件的发光亮度与所述时间长度呈正相关。
  6. 根据权利要求5所述的显示面板，其特征在于，每个像素驱动电路连接四个所述像素单元，所述像素驱动电路包括一个输入接口与四组输出接口，所述输入接口连接一个所述数据接口，一组所述输出接口连接一个像素单元中的所述三个发光元件的阴极。
  7. 根据权利要求6所述的显示面板，其特征在于，所述像素驱动电路为微型集成电路。
  8. 根据权利要求7所述的显示面板，其特征在于，所述显示面板包括显示区域与非显示区域，所述N行*M列呈矩阵式连接的像素区域设置于所述显示区域内；
    所述显示面板还包括设置于非显示区域的显示驱动电路，所述显示驱动电路连接所述多个像素区域内的像素驱动电路，用于输出所述图像数据、数据时钟信号以及全局时钟信号至所述像素驱动电路。
  9. 根据权利要求2-8中任意一项所述的显示面板，其特征在于，若不同的每个所述像素区域的显示驱动模组连接不同的时钟接口时，所述显示驱动电路包括P*M个数据接口、M*N个数据时钟接口以及M*N个全局时钟接口。
  10. 一种半导体显示装置，其特征在于，所述半导体显示装置包括权利要求1-9中任意一项所述的显示面板。
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