WO2020030993A1

WO2020030993A1 - Microcontroller based control of light emitting diode (led) video wall

Info

Publication number: WO2020030993A1
Application number: PCT/IB2019/054977
Authority: WO
Inventors: Santanu Roy; Vijay Kumar; Naveen DAGAR; Dileep Singh
Original assignee: Santanu Roy
Priority date: 2018-08-09
Filing date: 2019-06-14
Publication date: 2020-02-13

Abstract

The present disclosure relates to a display device, and, more specifically, to a system and method for driving a true color light emitting diode (LED) video wall by integration of a microcontroller. An aspect of the present disclosure relates to video display system having a plurality of light-emitting diodes (LEDs). The video display system can include a controller (1) configured to receive one or more instructions from at least one controlling device to generate an image using a set of said plurality of light-emitting diodes (LEDs). The controller (1) can communicate data to said plurality of light-emitting diodes (LEDs) using Transmission Control Protocol (TCP) protocol and generates a User Datagram Protocol (UDP) pulse to synchronize said plurality of light-emitting diodes (LEDs) to change frame at a same instance.

Description

MICROCONTROLLER BASED CONTROL OF LIGHT EMITTING DIODE (LED)

VIDEO WALL

TECHNICAL FIELD

[0001] The present disclosure relates to a display device, and, more specifically, to a system and method for driving a true color light emitting diode (LED) video wall driven by microcontroller.

BACKGROUND

[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.

[0003] Light emitting diode (LED) matrix is bunch of LEDs arranged in rows and columns so that driving them require lesser number of control lines. Conventionally, LED video walls are being driven by field-programmable gate array (LPGAs) and/or complex programmable logic device (CPLDs) since these matrices requires high refresh rates compared with single color display systems with advancement of microcontroller / microprocessor capabilities now this higher data transfer rates can be achieved with microcontrollers. Driving with LPGA or similar hardware driven device is fast in performance but they have their inherent limitations, the flexibility of LPGAs comes at a price because they consume more power than typical microcontrollers. Making an LPGA function in a certain role would also take a lot longer compared to microcontrollers because you would have to write all the code from scratch and convert it to machine language. Driving with microcontroller have more flexibility in terms of adaptation to new techniques as new drivers can be interfaced by just changing some portion of the code, microcontrollers are less power hungry and are also cost effective.

[0004] These types of video display requires synchronization among various modules so that the images can be reproduced properly in each modules at same point of time, in order to achieve this a separate sync line is used in many applications, however carrying a separate line increase cost, complexity and maintainability, in this embodiment the sync pulse is broken in two 180° out of phase pulse in order to reduce noise and the same communication media is used to generate the sync by using UDP protocol. [0005] In LED video wall a biggest problem is to achieve white balance in all pixel due to component tolerance, drivers are available which can take care of dot corrections but only be updated with consume time thus reducing scanning time and effecting overall image quality, with intelligent brick based modular design topology this can be eliminated with ease.

[0006] Apart from the scanning and other related problem to the conventional LED matrix display also suffer from a ghost image phenomenon whereby a replication of the actual text follows the text in subsequent column or rows with very low intensity, this embodiment also describe technique to reduce the ghost image formed by such driving technique. However, LED matrix display based on FPGAs takes a considerably longer time to set-up. Further, LED matrix display based on FPGA takes more time compared with microcontroller because of their complex design cycles. In general LED video wall are driven by FPGA and CPLDS but are not yet been tried with microcontrollers, with fast development in technology FPGA based design needs longer time for adoption due to their complex design cycle, where by microcontroller-based designs can be easily adopted with new drivers or LEDs just by minor software changes.

[0007] Therefore there is a need to provide a new, efficient, effective and technically advanced a microcontroller based RGB LED video wall in-place of FPGA’ s and/or CPLD’s. Further, there is a need of a microcontroller based LED matrix display that provides flexibility of adding enhanced software functionality (software dot correction, Ghost Image cancellation etc.). Furthermore, there is a need of a microcontroller based LED matrix display that is more modular and provide easy in maintenance. Apart from this microcontroller based design LED matrix display generating noise free SYNC Pulse, and software dot correction which is till date only possible with static drive by hardware.

[0008] All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.

[0009] In some embodiments, the numbers expressing quantities of ingredients, properties such as concentration, reaction conditions, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term“about”. Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[00010] As used in the description herein and throughout the claims that follow, the meaning of“a,”“an,” and“the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of“in” includes“in” and “on” unless the context clearly dictates otherwise.

[00011] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g.“such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.

[00012] Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.

OBJECTS OF THE INVENTION [00013] An object of the present disclosure is to provide a system and method for driving a true color light emitting diode (LED) video wall by integration of a microcontroller.

[00014] Another object of the present disclosure is to provide a microcontroller based RGB LED video wall in-place of FPGA’s and/or CPLD’s thereby avoiding formation of ghost images, software dot correction and more modular.

[00015] Another object of the present disclosure is to provide a microcontroller-based LED matrix display that provides flexibility of adding enhanced software functionality with new technologies and advancement in LED.

[00016] Another object of the present disclosure is to present a methodology to achieve high quality video processing by modular intelligent tiles.

[00017] Yet another object of the present disclosure is to eliminate the requirement of a dedicated hardware named as“Sender Card” by using the available Ethernet port of the controller.

[00018] Still another object of the present disclosure is to eliminate the dedicated computer or controller requirement by enabling direct LAN connection over the TCP/IP for the board in network.

SUMMARY

[00019] The present disclosure relates to a display device, and, more specifically, to a system and method for driving a true color light emitting diode (LED) video wall by integration of a microcontroller.

[00020] Problems to be solved in the present invention are that: Apart from the scanning and other related problem to the conventional LED matrix display also suffer from a ghost image phenomenon whereby a replication of the actual text follows the text in subsequent column or rows with very low intensity, this embodiment also describe technique to reduce the ghost image formed by such driving technique. However, LED matrix display based on FPGAs takes a considerably longer time to set-up. Further, LED matrix display based on FPGA takes more time compared with microcontroller because of their complex design cycles.

[00021] Therefore there is a need to provide a new, efficient, effective and technically advanced microcontroller based RGB LED video wall in-place of FPGA’s and/or CPLD’s thereby avoiding dedicated use of computer, and reach software feature like ghost image formation, pixel dot correction. Further there is a need of a microcontroller-based LED matrix display that provides flexibility of remote monitoring via existing LAN and WAN networks.

[00022] To solve the above problems, the present invention is achieved by the following solution:

[00023] The present invention provides a microcontroller based RGB LED video wall in-place of FPGA’s and/or CPLD’s thereby avoiding dedicated use of computer, and reach software feature like ghost image formation, pixel dot correction. The microcontroller based RGB LED video wall can be used as a microcontroller-based LED matrix display that provides flexibility of remote monitoring via existing LAN and WAN networks.

[00024] Accordingly, embodiments of the present disclosure provide a true color LED video wall display that can be controlled by a 32-bit microcontroller, and hence the use of FPGA or CPLDs can be obviated. In addition, the synchronization among various modules of a video wall can be achieved by incorporation of UDP pulse, wherein synchronization data is transferred by using TCP/IP protocol. Software Dot correction method can be employed to achieve white balance. Also, the prevailing problem of the presence of ghost images during high-speed scanning in a video wall can be removed by including a dead-time between the driving times of two consecutive LED rows.

[00025] In an embodiment, the present invention also discloses an method whereby no dedicated hardware component is required inside the controller and the device can operate on standard available LAN port. This embodiment also helps to bring the LED display board on any Local Area Network or Wide Area Network without the use of a dedicated computer or controller making it easy to drive the display from any corner of the world.

[00026] Thus, a major bottleneck of using a dedicated computer is also eliminated as this video wall can be driven by any computer over the Local Area Network.

[00027] An aspect of the present disclosure relates to video display system having a plurality of light-emitting diodes (LEDs). The video display system can include a controller configured to receive one or more instructions from at least one controlling device in the network to generate an image using a set of said plurality of light-emitting diodes (LEDs). The controller can communicate data to said plurality of light-emitting diodes (LEDs) using Transmission Control Protocol (TCP) protocol and generates a User Datagram Protocol (UDP) pulse to synchronize said plurality of light-emitting diodes (LEDs) to change frame at a same instance.

[00028] In an aspect, the controller can be a microcontroller unit. [00029] In an aspect, the controller can be positioned in a LED module of 16 x 16 LED matrix selected from said plurality of light-emitting diodes (LEDs) to drive 256 pixels.

[00030] In an aspect, at least one controlling device can be a video display controller.

[00031] In an aspect, change in frame can be obtained by breaking the UDP pulse into at least two 180 degree out of phase pulse to operate said plurality of light-emitting diodes (LEDs).

[00032] In an aspect, the video display system does not require Field Programmable Gate Arrays (FPGAs) or a complex programmable logic devices (CPLDs) to generate said image on said plurality of light-emitting diodes (LEDs)

[00033] In an aspect, UDP pulse can synchronize said plurality of light-emitting diodes (LEDs).

[00034] In an aspect, controller can achieve a white balance using a software dot correction.

[00035] In an aspect, the controller can provide a dead time while operating said plurality of light-emitting diodes (LEDs) thereby avoiding formation of ghost images.

[00036] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS

[00037] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The diagrams are for illustration only, which thus is not a limitation of the present disclosure, and wherein:

[00038] FIG. 1 illustrates a block diagram of microcontroller based RGB LED video wall, in accordance with an exemplary embodiment of the present disclosure.

[00039] FIG. 2A illustrates a block diagram of module control with intelligent bricks, in accordance with an exemplary embodiment of the present disclosure.

[00040] FIG. 2B illustrates a block diagram of module control with normal bricks, in accordance with an exemplary embodiment of the present disclosure.

[00041] FIG. 3A illustrates a block diagram of an intelligent tile/brick, in accordance with an exemplary embodiment of the present disclosure. [00042] FIG. 3B illustrates a block diagram of a normal tile/brick, in accordance with an exemplary embodiment of the present disclosure.

[00043] FIG. 4 illustrates a ghost image formation, in accordance with an exemplary embodiment of the present disclosure.

[00044] FIG. 5A illustrates a multiplexing waveform depicting cross over, in accordance with an exemplary embodiment of the present disclosure.

[00045] FIG. 5B illustrates a multiplexing waveform depicting nullified cross over, in accordance with an exemplary embodiment of the present disclosure.

DETAILED DESCRIPTION

[00046] The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure as defined by the appended claims.

[00047] If the specification states a component or feature“may”,“can”,“could”, or “might” be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.

[00048] As used in the description herein and throughout the claims that follow, the meaning of“a,”“an,” and“the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of“in” includes“in” and“on” unless the context clearly dictates otherwise.

[00049] Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These exemplary embodiments are provided only for illustrative purposes and so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. The invention disclosed may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Various modifications will be readily apparent to persons skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the scope of the invention. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure). Also, the terminology and phraseology used is for the purpose of describing exemplary embodiments and should not be considered limiting. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.

[00050] Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the "invention" may in some cases refer to certain specific embodiments only. In other cases it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.

[00051] All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.

[00052] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.

[00053] The present disclosure relates to a display device, and, more specifically, to a system and method for driving a true color light emitting diode (LED) video wall by integration of a microcontroller.

[00054] Accordingly, an aspect of the present disclosure relates to a proposed true color LED video wall display can be controlled by a 32-bit microcontroller, and hence the use of FPGA or CPLDs can be obviated. In addition, the synchronization among various modules of a video wall can be achieved by incorporation of UDP pulse, wherein synchronization data is transferred by using TCP/IP protocol. Software Dot correction method can be employed to achieve white balance. Also, the prevailing problem of the presence of ghost images during high-speed scanning in a video wall can be removed by including a dead-time between the driving times of two consecutive LED rows. The major bottleneck of using a dedicated computer is also eliminated as this video wall can be driven by any computer over the Local Area Network.

[00055] In an aspect, a system and method of driving a true color LED video wall using microcontroller in-place of FPGA’s and/or CPLD’s. Efforts were put in to develop ways to drive LED video wall using microcontroller since microcontrollers are custom built mini computers in an IC while FPGAs are only composed of logic blocks that can be rewired electrically. Microcontrollers consume less power than FPGAs. FPGAs take a considerably longer time to set-up and much costlier while there are ready built microcontrollers being sold for specific uses. Building devices with FPGAs can be costlier than microcontrollers. Adopting new technology with FPGA based designs takes more time compared with microcontroller because of their complex design cycles. Microcontroller based design provides flexibility of adding enhanced software functionality (Software Dot Correction). Microcontroller based design provides benefits of having intelligent modular designs as they are cost effective.

[00056] In an aspect, the microcontroller in used in each brick of 16x16 LED matrix just to drive 256 pixel this each brick are intelligent enough to take care of all its functionality independently like Software dot correction, interlaced scanning, increasing refresh rates etc. bunch of such bricks are then driven by a controller which receive data from PC or any such computer device over Ethernet. While driving such numerous bricks a noise free synchronization mechanism is required, in many designs it has been seen that a separate hardware (wire) is used for carrying the sync pulse to various modules, this technique not only increases the cost but also increase complexity in manufacturing and problems in maintenance. In this embodiment the same Ethernet media has been used to send data to all modules using TCP protocol and a UDP pulse is generated after TCP packets to synchronize all modules to change frame at same time. This frame change takes place 30 - 60 times every second and thus needs a noise free sync pulse for internal brick synchronization, in order to achieve this single pulse originating from the driver card is broken into two 180° out of phase pulse and both are being feed to the bricks so that false sensing can be averted.

[00057] In an aspect, the intelligent bricks can be replaced by normal matrix drivers and driven by a controller in series. [00058] Another major problem in LED video wall is to achieve white balance in all pixel due to component tolerance, drivers are available which can take care of dot corrections but only when driven in static mode, but with current trend of multiplexed driving which helps in reducing the average current thus minimizing the heat loss and also cost effective, designers are willing to go for multiplexed drive, but in multiplexed mode to achieve dot correction in every scan the configuration has to be updated which consume time thus reducing scanning time and effecting overall image quality, with intelligent brick based modular design topology as described in this embodiment software dot correction can be easily implemented and has been described in details.

[00059] While scanning this type of matrix normally a ghost visual effect is seen. Scanning of the next row starts before the previous one is completely turned off; this can be reduced by selectable enhanced PWM which specifically turn off the complete display for very short time before switching rows thus allowing the previous LED to turn off completely as image is formed in progressive scan.

[00060] FIG. 1 illustrates a block diagram of microcontroller based RGB LED video wall, in accordance with an exemplary embodiment of the present disclosure.

[00061] In an embodiment, microcontroller based RGB LED video wall comprises a plurality of LEDs arranged in module/tiles form (4) to form the LED video wall, a PC or similar device driver (13) to control one or more controllers (1-1, 1-2, . 1-9) which in return controls the plurality of LEDs arranged in module/tiles form (4). The one or more controllers (1-1, 1-2, . 1-9) can also be controlled by a switch/ hub (6).

[00062] In an exemplary embodiment, an 8 bit selector switch/ hub (6) can be used to select the address of tile (modules) which is compared by the controller or module control (1) with the incoming data while receiving data in multi -processor communication interface with controller. In an embodiment, the controller (1) can receive data from a PC or similar device driver (13) in form of BGR (Blue-Green-Red) starting from the left bottom comer and progressing sequentially upwards.

[00063] FIG. 2A illustrates a block diagram of module control with intelligent bricks, in accordance with an exemplary embodiment of the present disclosure.

[00064] As shown in FIG. 2A, the controller (1) can be based on and ARM 32-bit Cortex-M3 CPU with Ethernet connectivity. The ARM 32-bit Cortex™-M3 CPU with Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution performance from Flash memory, frequency up to 180 MHz, memory protection unit, with 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588n2 hardware, MII/RMII. [00065] In an embodiment, the ethernet (2) can be the PHY Terminal for Ethernet connectivity, The DP83848C is a robust fully featured 10/100 single port Physical Layer device offering low power consumption, including several intelligent power down states. These low power modes increase overall product reliability due to decreased power dissipation. Supporting multiple intelligent power modes allows the application to use the absolute minimum amount of power needed for operation. The DP83848C includes a 25MHz clock out. The DP83848C easily interfaces to twisted pair media via an external transformer. Both Mil and RMII are supported ensuring ease and flexibility of design. The DP83848C features integrated sub layers to support both 10BASE-T and 100BASE-TX Ethernet protocols, which ensure compatibility and interoperability with all other standards, based Ethernet solutions.

[00066] In an embodiment, the RS-485 lines (3) can be driven by industry standard RS-485 drivers (6). In an exemplary embodiment, there is six such line drivers (3) can send the pixels data to the tile communicating on a multiprocessor communication topology.

[00067] In an embodiment, RS-485 lines (3) can be driven by industry standard RS- 485 drivers (6). In another embodiment, the tile (4) can be independent and intelligent to scan their respective matrix of 256 LED (16x16) with the data received from the controller and also apply local dot correction.

[00068] In an embodiment, the controller (1) can receive data from a PC or similar device driver (13) in form of BGR (Blue-Green-Red) starting from the left bottom comer and progressing sequentially upwards. Once a complete frame is received the controller (1) relay the received data upon the six RS-485 network parallel to cut down the transmission time by 6, thus a complete frame data is being sent to all tile within 25 ms only. After transmitting the data to tile the controller (1) waits for a UDP SYNC pulse which is generated from the master server upon completing transmission to the entire module client network connected to the server, once the UDP SYNC pulse is received the Module controller generates a 180° out of phase pulse to instruct the tiles to change the frame as discussed in section TILE ENGINEERING, thus the complete video screen changes the frame with synchronization generating a smooth video. Since a minimum of 25 FPS is required for smooth video to ensure false free transition the sync signal is being broken in two phase so that false triggering can be averted.

[00069] In an embodiment, 8 bit selector switch or address selector (5) can be used to select the address of tile which is compared by the controller with the incoming data while receiving data in multi-processor communication interface with controller. [00070] FIG. 2B illustrates a block diagram of module control with normal bricks, in accordance with an exemplary embodiment of the present disclosure.

[00071] In an embodiment, the receiver card / controller is based on and ARM 32-bit Cortex-M# CPU with Ethernet connectivity the detail blocks are as shown in FIG.2A.

[00072] In an embodiment, the ethemet (2) can be the physical Ethernet connectivity, The DP83848C is a robust fully featured 10/100 single port Physical Layer device offering low power consumption, including several intelligent power down states.

[00073] In an embodiment, an ethernet receiver (7) and matrix scanner (8) can be are ARM 32-bit Cortex™-M3 CPU with Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution performance from Flash memory, frequency up to 180 MHz, memory protection unit, with 10/100 Ethemet MAC with dedicated DMA: supports IEEE 1588n2 hardware, MIERMII.

[00074] In an embodiment, the ethemet receiver (7) can be used to receive the video data from PC / control unit over the TCP/IP interface and then distribute into 3 blocks as per module configuration and then send the data packet over high speed SPI interface to the matrix scanner controller (8). The Matrix scanner (8) can control the scanning process of the display tiles without intelligence.

[00075] FIG. 3A illustrates a block diagram of an intelligent tile/brick, in accordance with an exemplary embodiment of the present disclosure.

[00076] In an embodiment, row drivers (9) can be P-Chanel MOSFET driven by the micro-controller unit in sync with the column driver to achieve the scanning of matrix. This P-Channel MOSFET is a rugged gate version advanced Power Trench MOSFET. It has been optimized for power management applications requiring a wide range of gave drives voltage ratings (4.5V - 25V).

[00077] In an embodiment, column driver IC (10) can be based on 16-channel PWM LED driver like STP1612PW05 / TC62D723FNG is a l6-channel constant current sink LED driver. The maximum output current value for all the 16 channels is set by a single resistor from 3 mA to 60 mA. The device features 8-bit gain (256 steps) for global LED brightness adjustment with two selectable ranges. This function is accessible via a serial interface. The device has an individual adjustable PWM brightness control for each output channel. The PWM counters are selectable via a serial interface with 4096 or 65536 steps (12 or 16 bit). The STP1612PW05 / TC62D723FNG also provides enhanced pulse-width modulation counting algorithms called e-PWM to reduce flickering effects (ghost visual effects) improving the overall image Quality. The device has a dual size l6-bit or 256-bit shift register. All the control and the shift register read back data are accessible via serial interface. The STP1612PW05 has the capability to detect open and short LED failure and over temperature, reporting the status through SPI line. The device guarantees a 20 V output driving capability, allowing connecting more LEDs in series.

[00078] In an embodiment, the controller (1) can control the brick activities the controller is ARM 32-bit Cortex™-M3 CPU, the controller (1) receives data for the particular brick from the controller, communication between the controller and the brick is through RS485 network implemented using multiprocessor communication technique, where in the controller send data for all bring simultaneously with 16-bit address as header of the string the tile controller detects its relevant data from the string and stores in a secondary frame buffer, when the complete frame is transmitted the controller sends a 180° out of phase sync signal when the brick controller bring the secondary frame buffer in front and starts receiving the next frame data on the primary frame buffer. This process continues to achieve a seamless frame transition which is done in synchronization with the row scanning.

[00079] In an embodiment, the communication interface (12) can be based on RS485 networks achieved using industry standard 485 drivers SN75176, The SN75176A differential bus transceiver is a monolithic integrated circuit designed for bidirectional data communication on multipoint bus-transmission lines. It is designed for balanced transmission lines. The SN75176A combines a 3-state differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active high and active-low enables, respectively, that can be externally connected together to function as a direction control. The driver differential outputs and the receiver differential inputs are connected internally to form differential input/output (EO) bus ports that are designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These ports feature wide positive and negative common-mode voltage ranges making the device suitable for party-line applications. The driver is designed to handle loads up to 60 mA of sink or source current. The driver features positive- and negative-current limiting and thermal shutdown for protection from line fault conditions. Thermal shutdown is designed to occur at a junction temperature of approximately l50°C. The receiver features a minimum input impedance of 12 kW, an input sensitivity of ±200 mV, and a typical input hysteresis of 50V. The SN75176A can be used in transmission-line applications employing the SN75172 and SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers. The SN75176A is characterized for operation from 0°C to 70°C. [00080] In an embodiment, a linear voltage regulator (11) can control the supply voltage for the control unit and other semiconductor devices onboard. The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.

[00081] In an embodiment, the 4 bit selector switch (5) can be used to select the address of tile which is compared by the controller with the incoming data while receiving data in multi-processor communication interface with controller.

[00082] The controller drive the rows of the matrix in alternate fashion in a interlaced mode to generate a visual image in half the time as compared with progressive scan technique, thus the visible refresh rate of the complete image is double than the scanning rate due to persistence of vision of human eye. With this modular and intelligent tile concept now each tile have capability for adjusting the brightness of individual dots to compensate the component tolerance up to ± 5%, this is achieved by adding or subtracting the compensation value of the respective dot with the pre-stored values while updating the display brick. Thus allowing software dot correction, however drivers are available which can take care of dot corrections but only when driven in static mode, but with current trend of multiplexed driving which helps in reducing the average current thus minimizing the heat loss and also cost effective, designers are willing to go for multiplexed drive, but in multiplexed mode to achieve dot correction in every scan the configuration has to be updated which consume time thus reducing scanning time and effecting overall image quality, with intelligent brick based modular design topology as described software dot correction can resolve the problem up to certain extent.

[00083] FIG. 3B illustrates a block diagram of a normal tile/brick, in accordance with an exemplary embodiment of the present disclosure.

[00084] In an embodiment, the normal tiles are without any intelligence build within itself; these tiles receive the RGB color data from a master controller via SPI communication.

[00085] In an embodiment, the row drivers (9) can be P-Chanel MOSFET driven by the micro-controller unit in sync with the column driver to achieve the scanning of matrix, same as described in intelligent tile above.

[00086] In an embodiment, the column driver IC (10) can be based on l6-channel

PWM LED driver The STP1612PW05 / TC62D723FNG or similar is a l6-channel constant current sink LED driver, same as described in intelligent tile above. [00087] In an embodiment, the SPI Communication interface (12) can control the brick scanning as received from the master controller the master controller shall be ARM 32-bit Cortex™-M3 CPU.

[00088] The controller drive the rows of the matrix in alternate fashion in a interlaced mode to generate a visual image in half the time as compared with progressive scan technique, thus the visible refresh rate of the complete image is double than the scanning rate due to persistence of vision of human eye.

[00089] FIG. 4 illustrates a ghost image formation, in accordance with an exemplary embodiment of the present disclosure.

[00090] LED display boards suffers from a phenomenon known as ghost image, faint ghosting images from parasitic currents can occur when the multiplexing changes phases from row 1 and 9 to row 2 and 10 and so on. The effect is most pronounced when the LEDs on the multiplexed circuits are of different colors (light wavelengths) and, hence, has significantly different voltage drops for a given current flow. It happen when the first enabled row drives signal turns off and the micro controller turn on the consequent row signal but the parasitic current in the previously turned on row takes time to diminish off completely, and in between the next row comes up thus a fainted image of the LEDs turned on in the previous channel will super impose on the desired image under scanning in current channel as shown in FIG. 4.

[00091] FIG. 5A illustrates a multiplexing waveform depicting cross over, in accordance with an exemplary embodiment of the present disclosure.

[00092] The timing diagram illustrated in FIG. 5A shows the crossover between two enabled signals at time TlOFF signal from microcontroller turns off and at time T2 ON consecutive channel signal gets turn off from the controller, however the parasitic currents continues to follow from the row driver until time TlOFF + A hence for time duration between T20N and TlOFF +D the LEDs in next channel becomes visible and a fainted image of the previous line is super imposed on the current line, thus forming an undesired image running at the back of main image.

[00093] FIG. 5B illustrates a multiplexing waveform depicting nullified cross over, in accordance with an exemplary embodiment of the present disclosure.

[00094] In an embodiment, the faint ghosting image can reduce same by applying an advanced synchronized PWM (S-PWM) signal with dead-time which when logically AND with the row scanning signal generates a signal as shown in FIG. 5B which eliminates the flow of parasitic current while crossover. This advanced scanning reduces the flow of parasitic / leakage current between consequent rows and turns off the display completely once before crossing over to next row there by also reduce the total power consumption of the display.

[00095] The various illustrative logical blocks, modules and circuits and algorithm steps described herein may be implemented or performed as electronic hardware, software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. It is noted that the configurations may be described as a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re arranged. A process is terminated when its operations are completed. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination corresponds to a return of the function to the calling function or the main function.

[00096] When implemented in hardware, various examples may employ a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core or any other such configuration.

[00097] When implemented in software, various examples may employ firmware, middleware or microcode. The program code or code segments to perform the necessary tasks may be stored in a computer-readable medium or processor-readable medium such as a storage medium or other storage(s). A processor may perform the necessary tasks. A code segment may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and/or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[00098] As used in this application, the terms "component," "module," "system," and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal).

[00099] In one or more examples herein, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium or processor-readable medium. A processor- readable media and/or computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium or processor-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blue-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Software may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs and across multiple storage media. An exemplary storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

[000100] One or more of the components, steps, and/or functions illustrated in the Figures may be rearranged and/or combined into a single component, step, or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from the invention. The novel algorithms described herein may be efficiently implemented in software and/or embedded hardware.

[000101] Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.

[000102] It should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the appended claims. Moreover, in interpreting both the specification and the claims, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms“comprises” and“comprising” should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. [000103] Where the specification claims refers to at least one of something selected from the group consisting of A, B, C ....and N, the text should be interpreted as requiring only one element from the group, not A plus N, or B plus N, etc. The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the appended claims.

[000104] While embodiments of the present disclosure have been illustrated and described, it will be clear that the disclosure is not limited to these embodiments only. Numerous modifications, changes, variations, substitutions, and equivalents will be apparent to those skilled in the art, without departing from the spirit and scope of the disclosure, as described in the claims.

[000105] In the description of the present specification, reference to the term "one embodiment," "an embodiments", "an example", "an instance", or "some examples" and the description is meant in connection with the embodiment or example described The particular feature, structure, material, or characteristic included in the present invention, at least one embodiment or example. In the present specification, the term of the above schematic representation is not necessarily for the same embodiment or example. Furthermore, the particular features structures, materials, or characteristics described in any one or more embodiments or examples in proper manner. Moreover, those skilled in the art can be described in the specification of different embodiments or examples are joined and combinations thereof.

[000106] All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

[000107] Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

[000108] The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

[000109] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

ADVANTAGES OF THE INVENTION

[000110] The present disclosure provides a system and method for driving a true color light emitting diode (LED) video wall by integration of a microcontroller.

[000111] The present disclosure provides a microcontroller based RGB LED video wall in-place of FPGA’s and/or CPLD’s thereby avoiding requirement of dedicated computer or video controller.

[000112] The present disclosure provides a microcontroller-based LED matrix display that provides flexibility of adding enhanced software functionality (software dot correction).

[000113] The present disclosure provides a microcontroller-based LED matrix display that provides flexibility of being driven from within the LAN or WAN without use of a dedicated computer.

[000114] The present disclosure provides a microcontroller-based LED matrix display that provides flexibility of repair and maintenance being modular at tile engineering.

[000115] The present disclosure provides a microcontroller-based LED matrix display that provides flexibility of remote monitoring at module level as each module can be accessed over the network independently.

[000116] The present disclosure provides a microcontroller-based LED matrix display that provides flexibility of higher refresh rates and scanning rates as each brick are intelligent. [000117] The present disclosure provides a microcontroller-based LED matrix display that provides flexibility of being cascaded to larger walls without any limitation.

Claims

I Claim:

1. A video display system having a plurality of light-emitting diodes (LEDs), said video display system comprising:

a controller (1) configured to receive one or more instructions from at least one controlling device to generate an image using a set of said plurality of light-emitting diodes (LEDs), wherein said controller communicates data to said plurality of light-emitting diodes (LEDs) using Transmission Control Protocol (TCP) protocol, and generates a User Datagram Protocol (UDP) pulse to synchronize said plurality of light-emitting diodes (LEDs) to change frame at a same instance.

2. The video display system as claimed in claim 1, wherein said controller (1) is a microcontroller unit.

3. The video display system as claimed in claim 1, wherein said controller (1) is positioned in a LED module of 16 x 16 LED matrix selected from said plurality of light- emitting diodes (LEDs) to drive 256 pixels.

4. The video display system as claimed in claim 1, wherein said at least one controlling device is a microcontroller.

5. The video display system as claimed in claim 1, wherein said change in frame is obtained by breaking the UDP pulse into at least two 180 degree out of phase pulse to operate said plurality of light-emitting diodes (LEDs).

6. The video display system as claimed in claim 1, wherein said video display system does not require Field Programmable Gate Arrays (FPGAs) or a complex programmable logic devices (CPLDs) to generate said image on said plurality of light-emitting diodes (LEDs).

7. The video display system as claimed in claim 1, wherein said UDP pulse synchronizes said plurality of light-emitting diodes (LEDs).

8. The video display system as claimed in claim 1, wherein said controller (1) achieves a white balance using a software dot correction.

9. The video display system as claimed in claim 1, wherein said controller (1) provides a dead time while operating said plurality of light-emitting diodes (LEDs) thereby avoiding formation of ghost images.

10. The video display system as claimed in claim 1, wherein said controller (1) provides a connection over the LAN / WAN networks and can be accessed from remote locations in the network.

11. The video display system as claimed in claim 1, wherein said controller (1) provides a remote monitoring by a single instruction, preferably said single instruction is a“PING” command over the ethernet.

12. The video display system as claimed in claim 1, wherein said controller (1) provides a connection over the LAN / WAN networks and is accessed from remote locations in the network.