WO2021190508A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021190508A1
WO2021190508A1 PCT/CN2021/082427 CN2021082427W WO2021190508A1 WO 2021190508 A1 WO2021190508 A1 WO 2021190508A1 CN 2021082427 W CN2021082427 W CN 2021082427W WO 2021190508 A1 WO2021190508 A1 WO 2021190508A1
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WO
WIPO (PCT)
Prior art keywords
light
base substrate
anode
orthographic projection
emitting element
Prior art date
Application number
PCT/CN2021/082427
Other languages
English (en)
French (fr)
Inventor
王思雨
王梦奇
张顺
代洁
尚庭华
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202180000563.9A priority Critical patent/CN113728440A/zh
Priority to EP21755882.4A priority patent/EP4131404A4/en
Priority to JP2021539892A priority patent/JP2023518619A/ja
Priority to KR1020217028574A priority patent/KR20220158596A/ko
Priority to CN202211034963.4A priority patent/CN115360313A/zh
Priority to US17/427,443 priority patent/US11825696B2/en
Publication of WO2021190508A1 publication Critical patent/WO2021190508A1/zh
Priority to US17/699,948 priority patent/US11785806B2/en
Priority to US17/940,566 priority patent/US11825697B2/en
Priority to US18/462,962 priority patent/US20230422556A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H10K50/81—Anodes
    • H10K50/813—Anodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/842—Containers
    • H10K50/8428—Vertical spacers, e.g. arranged between the sealing arrangement and the OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/352—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels the areas of the RGB subpixels being different
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the embodiments of the present disclosure relate to a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • the embodiment of the present disclosure provides a display substrate and a display device.
  • the closed annular portion can ensure a high degree of flatness of the first anode, thereby ensuring that the luminous intensity of the first anode in different directions is consistent, thereby effectively improving the color shift; on the other hand, since the closed annular portion has The hollow design can improve the light transmittance of the display substrate and is beneficial to the fingerprint recognition device under the screen to receive signals.
  • At least one embodiment of the present disclosure further provides a display substrate, which includes: a base substrate; a plurality of pixel drive circuits, including a semiconductor layer; a first conductive layer located on a side of the semiconductor layer away from the base substrate; The first flat layer is located on the side of the first conductive layer away from the base substrate; the second conductive layer is located on the side of the first flat layer away from the first conductive layer; the second flat layer, Located on the side of the second conductive layer away from the base substrate; and a plurality of light-emitting element groups located on the side of the second flat layer away from the second conductive layer, the second conductive layer including the edge A plurality of conductive parts arranged in a first direction, each of the conductive parts has a larger size in the second direction than in the first direction, the second direction intersects the first direction, and the plurality of conductive parts includes a first A conductive portion, the first conductive portion includes a closed ring portion, the closed ring portion and at least one adjacent conductive portion in
  • the size of the closed annular portion in the first direction is at least larger than the size of a part of the first conductive portion in the first direction
  • the plurality of The pixel driving circuit includes a first pixel driving circuit
  • the first pixel driving circuit has a semiconductor pattern on the semiconductor layer
  • the semiconductor pattern overlaps in the orthographic projection of the base substrate
  • the first pixel driving circuit includes a driving transistor
  • the first conductive layer includes a first conductive pattern
  • the first conductive pattern is connected to the gate of the driving transistor.
  • the electrodes have the same potential
  • the first conductive pattern and the gate of the drive transistor together form the gate potential metal
  • the hollow area inside the closed ring part is orthographically projected on the base substrate and the gate
  • the extreme potential metals overlap.
  • the inner side of the closed annular portion has a hollow area
  • the first conductive portion has a plurality of the hollow areas arranged along the second direction, adjacent to each other.
  • the shape and size of the two hollow areas are approximately the same.
  • the first light-emitting element includes an effective light-emitting area, and a straight line that passes through the center of the effective light-emitting area of the first light-emitting element and extends along the second direction is in the
  • the orthographic projection of the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the second conductive portion on the base substrate.
  • the two edges of the closed ring portion in the first direction are connected to the anodes of the multiple light-emitting elements in the light-emitting element group on the base substrate.
  • the orthographic projection of the base plate overlaps, and the hollow area of the closed ring portion and the effective light-emitting area of the plurality of light-emitting elements are separately arranged on the orthographic projection of the base substrate.
  • the first conductive layer further includes conductive metal configured to provide power to the pixel driving circuit
  • the first flat layer includes conductive metal vias, so The conductive portion is electrically connected to the conductive metal through the conductive metal via hole
  • the first pixel driving circuit further includes a first light-emitting control transistor and a storage capacitor
  • the storage capacitor includes a first electrode block and a second electrode
  • the second electrode block is located on the side of the first electrode block away from the base substrate, and the conductive metal is electrically connected to the source of the first light-emitting control transistor and the second electrode block. Connected.
  • the orthographic projection of the closed ring portion on the base substrate overlaps with the orthographic projection of the first electrode block on the base substrate.
  • the second electrode block includes an opening, the orthographic projection of the opening on the base substrate overlaps the orthographic projection of the first electrode block on the base substrate, and the closed ring portion is located at the The orthographic projection on the base substrate and the orthographic projection of the opening on the base substrate also overlap.
  • the first pixel driving circuit further includes a data writing transistor, a compensation transistor, a reset transistor, an anode initialization transistor, and a second light emission control transistor
  • the display substrate further includes : A reset signal line connected to the gate of the reset transistor; a gate line connected to the gate of the compensation transistor; a light emission control line connected to the gate of the first light emission control transistor; and an initialization signal line, Connected to the source of the reset transistor, the orthographic projection of the closed ring portion on the base substrate is respectively connected to the reset signal line, the gate line and the initialization signal line on the base substrate The orthographic projections overlap.
  • one end of the first conductive pattern is electrically connected to the gate of the driving transistor through the opening, and the other end of the first conductive pattern is connected to the gate of the driving transistor.
  • the source or drain of the compensation transistor is electrically connected.
  • the closed annular portion includes a first part and a second part arranged in the first direction, and a third part and a fourth part arranged in the second direction.
  • the first part, the third part, the second part and the fourth part are connected end to end to form the closed ring part, and the first part and the second part are on the base substrate
  • the orthographic projection of the upper surface overlaps the orthographic projection of the second electrode block on the base substrate.
  • the orthographic projection of the first portion on the base substrate overlaps the orthographic projection of the first conductive pattern on the base substrate, and
  • the shapes of the first conductive pattern and the first portion are both elongated, and the extending direction of the long side of the first conductive pattern is the same as the extending direction of the long side of the first portion.
  • the first conductive layer further includes a second conductive pattern and a third conductive pattern, and the second conductive pattern is connected to the initialization signal line and the reset transistor respectively.
  • the second conductive layer further includes an anode connection part, the third conductive pattern is connected to the drain of the second light-emitting control transistor and the anode connection part, and the third part is in the
  • the orthographic projection on the base substrate overlaps the orthographic projection of the initialization signal line on the base substrate, and the orthographic projection of the third part on the base substrate is in the same position as the second conductive pattern.
  • the orthographic projection on the base substrate overlaps, and the orthographic projection of the fourth portion on the base substrate overlaps the orthographic projection of the first conductive pattern on the base substrate.
  • the orthographic projection of the hollow area on the base substrate overlaps the orthographic projection of the initialization signal line on the base substrate, and the hollow
  • the orthographic projection of the region on the base substrate overlaps the orthographic projection of the second conductive pattern on the base substrate, and the orthographic projection of the hollow region on the base substrate overlaps with the orthographic projection of the second conductive pattern on the base substrate.
  • the orthographic projections of the electrode blocks on the base substrate overlap.
  • the plurality of light-emitting element groups are arranged along the first direction to form a plurality of light-emitting element columns, and they are arranged along the second direction to form a plurality of light-emitting element rows.
  • Each of the light-emitting element groups includes a first light-emitting element, a second light-emitting element, a third light-emitting element, and a fourth light-emitting element
  • the first anode includes a main body
  • the first light-emitting element The orthographic projection of the effective light-emitting area on the base substrate is located inside the main body of the first anode in the orthographic projection of the base substrate, and the main body of the first anode and the first anode have at least Part of the same boundary
  • the plurality of conductive portions include a second conductive portion, the first conductive portion and the second conductive portion are respectively located in the first direction of the effective light-emitting area of the first light-emitting element
  • the distance between the orthographic projection of the closed annular portion on the base substrate and the orthographic projection of the center of the effective light-emitting area of the first light-emitting element on the base substrate is at the same distance as the second conductive portion.
  • the orthographic projection of the first anode on the base substrate and the light emission control line of the first pixel drive circuit are on the base substrate
  • the orthographic projection of the fourth light-emitting element overlaps with the center of the hollowed-out area in the second direction, and the orthographic projection of the anode of the fourth light-emitting element on the base substrate is the same as the The orthographic projections of the gate line, the reset signal line, and the initialization signal line on the base substrate all overlap.
  • the orthographic projection of the gate line on the base substrate overlaps with the orthographic projection of the first conductive pattern on the base substrate.
  • the orthographic projection of the first electrode block and the second electrode block on the base substrate is located on the orthographic projection of the gate line on the base substrate and the light emission control The line is between the orthographic projection on the base substrate, and the orthographic projection of the reset signal line on the base substrate is located between the orthographic projection of the gate line on the base substrate and the initialization signal line.
  • the light-emitting control line, the first electrode block, the gate line, the reset signal line, and the initialization signal line are arranged along the second direction.
  • the plurality of pixel driving circuits further include a second gate electrode layer located on a side of the first conductive layer close to the base substrate, and the second electrode The block is located on the second gate electrode layer, and at least two of the second electrode blocks are connected at the second gate electrode layer.
  • the orthographic projection of the effective light-emitting area of the first light-emitting element and the effective light-emitting area of the second light-emitting element on the base substrate and the conductive part are in the same position.
  • the orthographic projection on the base substrate does not overlap, the second light-emitting element is configured to emit green light, and the center of the effective light-emitting area of the fourth light-emitting element is orthographically projected on the base substrate with the conductive
  • the orthographic projection of the portion on the base substrate overlaps, the portion where the conductive portion and the center of the effective light-emitting area of the fourth light-emitting element overlap in the orthographic projection of the base substrate is a solid part, and the The fourth light emitting element is configured to emit blue light.
  • the second light-emitting element includes a second anode, and the effective light-emitting area of the second light-emitting element is located at the second anode in the orthographic projection of the base substrate.
  • the main body of the base substrate is inside the orthographic projection of the base substrate, and the main body of the second anode and the second anode have at least partly the same boundary, and the main body of the second anode and the second anode.
  • the overlapping areas of the two adjacent conductive portions of the anode in the first direction are approximately the same.
  • the orthographic projection of the hollow area on the base substrate is located in the effective light-emitting area of the first light-emitting element and the effective light-emitting area of the second light-emitting element In between, the first light-emitting element and the second light-emitting element are the first light-emitting element and the second light-emitting element that are closest in the first direction.
  • the size of the middle portion of the anode of the light emitting element configured to emit red light in the second direction in the first direction is larger than the size of the anode in the first direction.
  • the size of the edge portion in the second direction in the first direction is larger than the size in the first direction of the middle portion of the anode of the light emitting element configured to emit blue light in the second direction.
  • the orthographic projection of the anodes of at least two light-emitting elements on the base substrate is consistent with the opening of the second electrode block.
  • the orthographic projection of the hole on the base substrate overlaps, and the orthographic projection of the effective light-emitting area of at least one light-emitting element on the base substrate is the same as that of the first electrode block or the second electrode block on the liner.
  • the orthographic projections on the base substrate do not overlap.
  • the first flat layer has an anode hole, the anode of the light-emitting element is connected to the pixel drive circuit corresponding to the light-emitting element through the anode hole, and the anode hole of the anode of the light-emitting element is configured to emit red light.
  • the orthographic projection on the base substrate and the orthographic projection of the main body of the anode on the base substrate do not overlap in the second direction, and the anode hole of the anode of the light emitting element configured to emit red light is in the The orthographic projection on the base substrate and the effective light-emitting area of the light-emitting element configured to emit red light do not overlap in the second direction on the base substrate and are configured as a light-emitting element configured to emit blue light
  • the orthographic projection of the anode hole of the anode on the base substrate and the effective light-emitting area of the light-emitting element configured to emit blue light on the base substrate do not overlap in the second direction.
  • a data line is provided between two adjacent conductive parts, and the adjacent conductive parts and the data line are on the base substrate.
  • the distance between the orthographic projections is smaller than the distance between the orthographic projections of two adjacent conductive parts on the base substrate.
  • At least one embodiment of the present disclosure further provides a display device, which includes the display substrate described in any one of the above.
  • Figure 1 is a schematic partial cross-sectional view of a display substrate
  • Fig. 2 shows a schematic diagram of the display substrate shown in Fig. 1 emitting light
  • FIG. 3 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 4A is a schematic cross-sectional view of a display substrate along the AA direction in FIG. 3 according to an embodiment of the present disclosure
  • FIG. 4B is a schematic cross-sectional view of another display substrate along the AA direction in FIG. 3 according to an embodiment of the present disclosure
  • 5A is a schematic cross-sectional view of a display substrate along the BB direction in FIG. 3 according to an embodiment of the present disclosure
  • 5B is a schematic cross-sectional view of a display substrate along the GG direction in FIG. 3 according to an embodiment of the present disclosure
  • FIG. 6 is a schematic plan view of a light-emitting element in a display substrate provided by an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a planar relationship between a second conductive layer and an anode layer in a display substrate provided by an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • Fig. 9 is a schematic partial cross-sectional view of another display substrate.
  • FIG. 10 is a schematic partial cross-sectional view of another display substrate
  • FIG. 11 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 12A is a schematic cross-sectional view of a display substrate along the HH direction in FIG. 11 according to an embodiment of the present disclosure
  • FIG. 12B is a schematic cross-sectional view of a display substrate along the JJ direction in FIG. 11 according to an embodiment of the present disclosure
  • FIG. 13 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 15 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 16 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • Figure 17 is a schematic diagram of an evaporation process using a fine metal mask
  • FIG. 18 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 19 is a schematic cross-sectional view of a display substrate along the CC direction in FIG. 18 according to an embodiment of the present disclosure
  • 20 is a schematic plan view of another display substrate according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic cross-sectional view of a display substrate along the DD direction in FIG. 20 according to an embodiment of the present disclosure
  • FIG. 22 is a schematic cross-sectional view of a display substrate along the EE direction in FIG. 20 according to an embodiment of the present disclosure
  • FIG. 23 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 24 is a manufacturing method of a display substrate according to an embodiment of the present disclosure.
  • 25-27 are schematic plan views of a mask set according to an embodiment of the present disclosure.
  • 28A is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • 28B is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 29 is a schematic cross-sectional view of a display substrate along the FF direction in FIG. 28A according to an embodiment of the present disclosure
  • 30A-30D are schematic plan views of multiple film layers in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 31 is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 32 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 33 is a partial schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 34 is a schematic cross-sectional view of a display substrate along the KK direction in FIG. 33 according to an embodiment of the disclosure.
  • 35A is a schematic cross-sectional view of a display substrate along the MM direction in FIG. 33 according to an embodiment of the present disclosure
  • 35B is a schematic cross-sectional view of a display substrate along the NN direction in FIG. 33 according to an embodiment of the present disclosure
  • 35C is a schematic cross-sectional view of a display substrate along the QQ direction in FIG. 33 according to an embodiment of the present disclosure
  • 36 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 37A is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 37B is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 38 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 39 is a schematic diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 40 is a schematic cross-sectional view of a display substrate along line TT in FIG. 39 according to an embodiment of the disclosure
  • FIG. 41 is a schematic diagram of a second conductive layer and an anode layer in a display substrate provided by an embodiment of the present disclosure.
  • FIG. 42 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • Display devices have many performance specifications such as power consumption, brightness, and color coordinates, and color shift is an important parameter among them. Generally, there are many factors that affect the color shift of an organic light emitting diode (OLED) display device. From the design point of view of the display substrate (the array substrate or backplane of the organic light emitting diode), the flatness of the anode has a great influence on the color shift. .
  • OLED organic light emitting diode
  • Fig. 1 is a schematic partial cross-sectional view of a display substrate
  • Fig. 2 shows a schematic diagram of the display substrate shown in Fig. 1 emitting light.
  • the sub-pixels of the display substrate include a base substrate 110, a semiconductor layer 120, a first gate layer 130, a second gate layer 140, a first conductive layer 150, and a first flat layer 241 arranged in sequence.
  • the semiconductor layer 120, the first gate layer 130, the second gate layer 140, and the first conductive layer 150 may form a pixel driving circuit including a thin film transistor and a storage capacitor.
  • the second conductive layer 160 includes a connection electrode 161 through which the connection electrode 161 passes.
  • the via hole (not shown) in the first flat layer 241 is connected to the pixel driving circuit, and the anode 170 is connected to the connection electrode 161 through the via hole 271 in the second flat layer 242.
  • the pixel defining layer 190 includes an opening 191 to expose a portion of the anode 170.
  • the anode 175 can contact the organic light-emitting layer 180 and drive the organic light-emitting layer to emit light; the area defined by the opening 191 is The effective light-emitting area of the sub-pixel.
  • the via 271 in the second flat layer 242 will affect the flatness of the anode 175. If the distance between the via 271 and the opening 191 (that is, the effective light-emitting area) is close, the anode 175 at the position of the opening 191 will be generated. "Tilt" phenomenon, which causes the light-emitting direction of the sub-pixel to shift. If the "tilt" directions of the anodes in the sub-pixels of different colors are different, the intensities of the light emitted by the sub-pixels of different colors (for example, red, green, and blue) in different directions will not match, resulting in a color shift phenomenon. For example, the display screen turns red when viewed from one side of the display device including the display substrate, and the display screen turns blue when viewed from the other side of the display device.
  • inventions of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer and a plurality of light-emitting element groups; the first conductive layer is located on the base substrate; the first flat layer is located on the A conductive layer is located on the side away from the base substrate; the second conductive layer is located on the side of the first flat layer away from the first conductive layer; the second flat layer is located on the side of the second conductive layer away from the first flat layer; multiple light emitting The element group is located on the side of the second flat layer away from the base substrate.
  • a plurality of light-emitting element groups are arranged along a first direction to form a plurality of light-emitting element columns, and a plurality of light-emitting element groups are arranged along a second direction to form a plurality of light-emitting element rows.
  • Each light-emitting element group includes a first light-emitting element, a second light-emitting element, and a first light-emitting element.
  • the light emitting element includes a first anode
  • the second light emitting element includes a second anode
  • the third light emitting element includes a third anode
  • the fourth light emitting element includes a fourth anode
  • the second conductive layer includes a first connecting electrode, a second connecting electrode, and a second anode.
  • the second flat layer includes a first via hole, a second via hole, a third via hole and a fourth via hole.
  • the first anode is connected to the first connection electrode through the first via hole.
  • the two anodes are connected to the second connecting electrode through the second via hole, the third anode is connected to the third connecting electrode through the third via hole, and the fourth anode is connected to the fourth connecting electrode through the fourth via hole.
  • a row of light-emitting elements corresponds to
  • the plurality of third vias are substantially located on a first straight line extending along the first direction, and the orthographic projection of the fourth via with the closest distance to the first straight line on the base substrate is located on the first straight line close to the fourth via Corresponding to the side of the fourth anode.
  • the display substrate increases the distance between the fourth via hole and the effective light-emitting area of the adjacent first light-emitting element by moving the position of the fourth via to the direction close to the fourth anode, thereby ensuring that it is located at the first
  • the flatness of the first anode in the effective light-emitting area of the light-emitting element thereby avoiding color shift
  • the resistance between the fourth anode and the fourth connecting electrode of the zone and also increased the distance between the first anode and the fourth anode, so as to avoid the first anode and the fourth anode caused by the residue left by the manufacturing process. catch.
  • FIG. 3 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • FIGS. 4A and 4B are schematic cross-sectional views of a display substrate provided by an embodiment of the present disclosure along the AA direction in FIG. 3
  • FIG. 5A is the present disclosure
  • FIG. 5B is a cross-sectional schematic diagram of a display substrate along the GG direction in FIG. 3 provided by an embodiment of the disclosure
  • FIG. 6 is an implementation of the disclosure
  • the example provides a schematic plan view of a light-emitting element in a display substrate.
  • the display substrate 100 includes a base substrate 110, a first conductive layer 150, a first flat layer 241, a second conductive layer 160, and a second conductive layer.
  • the first flat layer 241 is on the side away from the first conductive layer 150; the second flat layer 242 is on the side of the second conductive layer 160 away from the first flat layer 241; the multiple light-emitting element groups 310 are on the second flat layer 242 away from the liner One side of the base substrate 110.
  • the multiple light-emitting element groups 310 are arranged along the first direction to form multiple light-emitting element columns 320, and are arranged along the second direction to form multiple light-emitting element rows 330.
  • Each light-emitting element group 310 includes a first light-emitting element 311 and a second light-emitting element 311.
  • the light-emitting element 312, a third light-emitting element 313 and a fourth light-emitting element 314, the second light-emitting element 312 and the third light-emitting element 313 are arranged in the second direction to form a light-emitting element pair 315, a first light-emitting element 311, a light-emitting element pair 315 And the fourth light-emitting element 314 are arranged along the first direction, the first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 Including the fourth anode 1754, the second conductive layer 160 includes the first connecting electrode 1611, the second connecting electrode 1612, the third connecting electrode 1613 and the fourth connecting electrode 1614, the second flat layer 242 includes the first via 2421, the second Via 2422, third via 24
  • a light emitting element row 330 corresponds to a plurality of third electrodes.
  • the hole 2423 is approximately located on the first straight line 301 extending along the first direction, and the orthographic projection of the fourth via 2424 closest to the first straight line 301 on the base substrate 110 is located on the first straight line 301 close to the fourth pass.
  • the hole 2424 corresponds to the side of the fourth anode 1754. It should be noted that the above-mentioned first conductive layer and second conductive layer are sequentially stacked along the direction away from the base substrate.
  • the second light-emitting element and the third light-emitting element are arranged along the second direction to form a light-emitting element pair, and the first light-emitting element, the light-emitting element pair, and the third light-emitting element are arranged along the first direction. That is, the second anode and the third anode are arranged in the second direction to form an anode pair, and the first anode, the anode pair and the third anode are arranged in the first direction.
  • the orthographic projection of the fourth via hole closest to the first straight line on the base substrate is located on the side of the first straight line close to the fourth anode, that is, the display substrate changes the position of the fourth via to the side close to the fourth anode. Move in direction.
  • the display substrate has the following beneficial effects: (1) The distance between the fourth via hole and the effective light-emitting area of the adjacent first light-emitting element is increased, thereby ensuring that the first light-emitting area is located in the effective light-emitting area of the first light-emitting element.
  • the flatness of the anode thereby avoiding the phenomenon of color shift; (2) Reduce the distance between the fourth via hole and the effective light-emitting area of the fourth light-emitting element, thereby reducing the fourth anode and the effective light-emitting area of the fourth light-emitting element The resistance between the fourth connecting electrodes; (3) The distance between the first anode and the fourth anode is increased, so that the first anode and the fourth anode can be prevented from being short-circuited due to the residue left by the manufacturing process.
  • the display substrate moves the position of the fourth via hole 2424 to a direction close to the fourth anode 1754, so the fourth via hole 2424 is connected to the adjacent first light-emitting element.
  • the distance of the effective light-emitting area ie, the area defined by the opening 1951
  • moving the position of the fourth via 2424 to a direction closer to the fourth anode 1754 will not match the effective light-emitting area of the fourth light-emitting element (ie The area defined by the opening 1954) overlaps.
  • the fourth via 2424 has a proper distance from the effective light-emitting area of the adjacent first light-emitting element and the effective light-emitting area of the fourth light-emitting element, so that the distance between the effective light-emitting area of the first light-emitting element and the effective light-emitting area can be ensured at the same time.
  • the flatness of the first anode and the fourth anode located in the effective light-emitting area of the fourth light-emitting element thereby avoiding color shift.
  • the display substrate moves the position of the fourth via hole 2424 to a direction closer to the fourth anode 1754, thereby reducing the difference between the fourth via hole 2424 and the fourth light-emitting element.
  • the distance of the effective light-emitting area reduces the resistance between the fourth anode and the fourth connecting electrode in the effective light-emitting area of the fourth light-emitting element.
  • the display substrate also increases the distance between the first anode 1751 and the fourth anode 1754 by moving the position of the fourth via 2424 closer to the fourth anode 1754, thereby avoiding the first anode 1751.
  • the fourth anode 1754 and the fourth anode 1754 are short-circuited due to the residue left by the manufacturing process.
  • the shortest distance between the orthographic projection of the first anode on the base substrate and the orthographic projection of the adjacent fourth anode on the base substrate is greater than 0.8 times the width of the effective light-emitting area of the first light-emitting element in the first direction Therefore, the first anode and the fourth anode can be effectively prevented from being short-circuited due to the residue left by the manufacturing process.
  • the fourth anode 1754 includes a main body portion 1754A and a connecting portion 1754B.
  • the effective light-emitting area of the fourth light-emitting element 314 falls within the orthographic projection of the main body portion 1754A on the base substrate 110, and the connecting portion 1754B passes
  • the fourth via 2424 is connected to the corresponding fourth connecting electrode 1614, and the connecting portion 1754B is located on the side of the first straight line 301 close to the main body portion 1754A, thereby effectively reducing the area of the connecting portion, thereby reducing the location of the fourth light-emitting element.
  • the resistance between the fourth anode and the fourth connecting electrode of the effective light-emitting area For example, as shown in FIG.
  • the fourth anode 1754 further includes a first supplementary portion 1754C.
  • the first supplementary portion 1754C can cover the two channel regions of the compensation thin film transistor in the corresponding pixel driving circuit, thereby improving the compensation thin film transistor.
  • the stability and lifetime of the display substrate can thereby improve the long-term luminescence stability and lifetime of the display substrate.
  • the first supplementary portion 1754C protrudes from the fourth body portion 1754A to the third anode 1753, and the first supplementary portion 1754C is located on the side of the fourth connecting portion 1754B close to the fourth body portion 1754A .
  • the first supplementary portion 1754C is connected to both the fourth main body portion 1754A and the fourth connecting portion 1754B. Therefore, the display substrate can make full use of the area on the display substrate, and the first anode, the second anode, the third anode, and the fourth anode are closely arranged, so that the resolution of the display substrate can be ensured.
  • the display substrate includes a base substrate 110, a semiconductor layer 120, a first insulating layer 361, a first gate layer 130, a second insulating layer 362, a second gate layer 140, The interlayer insulating layer 363, the first conductive layer 150, the first flat layer 241, the second conductive layer 160, and the second flat layer 242.
  • the first gate layer 130 may include gate lines 131 and a first electrode block CE1
  • the second gate layer may include a second gate block CE2.
  • the orthographic projection of the block CE2 on the base substrate 110 at least partially overlaps, so that a storage capacitor can be formed.
  • the first conductive layer 150 may further include a power line and a data line
  • the second conductive layer 160 may include a conductive part overlapping the power line, and the conductive part may be electrically connected to the power line, thereby The resistance of the power cord can be reduced.
  • the display substrate may further include a passivation layer 364 located between the first conductive layer 150 and the first flat layer 241.
  • a passivation layer 364 located between the first conductive layer 150 and the first flat layer 241.
  • the embodiments of the present disclosure include but are not limited thereto, and the display substrate may not be provided with a passivation layer.
  • the plurality of second via holes 2422 corresponding to the light emitting element row 330 adjacent to the light emitting element row 330 corresponding to the first straight line 301 are also substantially located on the first straight line 301.
  • the fourth via 2424 in one light-emitting element group 310 is located along the first anode 1751 in the light-emitting element group 310 adjacent to the light-emitting element group 310 in the second direction.
  • One side of the bisecting line in the two directions, for example, the bisecting line of the first anode 1751 along the second direction is close to the second anode 1752 of the light-emitting element group 310 where the first anode 1751 is located. That is, the fourth via hole in one light-emitting element group is located on the side of the bisector of the first anode in the light-emitting element group adjacent to the light-emitting element group in the second direction along the second direction.
  • the first via 2421 is located on one side of the bisecting line of the first anode 1751 along the second direction, for example, the first anode 1751 is along the second direction.
  • the bisector line is close to the side of the third anode 1753;
  • the second via 2422 is located on the side of the bisector of the second anode 1752 along the second direction close to the first anode 1751;
  • the third via 2423 is located on the side of the third anode 1753 along the second
  • the bisector of the direction is close to one side of the first anode 1751.
  • a plurality of fourth via holes 2424 corresponding to a row of light-emitting elements 330 are substantially located on a straight line extending along the first direction, and the straight line passes through a plurality of fourth via holes corresponding to the row of light-emitting elements 330.
  • a plurality of fourth via holes 2424 corresponding to one light-emitting element row 320 are substantially located on a second straight line extending in the second direction, and the second straight line passes through the corresponding light-emitting element row 320.
  • the distance between the fourth anode 1754 and the closest first anode 1751 is smaller than the distance between the first anode 1751 located in the same row and the fourth anode 1754 closest to it. .
  • the light-emitting element group 310 includes a first light-emitting element group and a second light-emitting element group that are adjacent in the second direction, and the first light-emitting element group and the second light-emitting element group are respectively arranged in phases.
  • the connecting portion of the fourth anode 1754 in the first light-emitting element group and the connecting portion of the first anode 1751 in the second light-emitting element group are both located along the second direction of the fourth anode 1754 On the same side of the bisector. That is, the main body portion of the fourth anode is provided with the connection portion of the fourth anode and the connection portion of the first anode adjacent to the fourth anode in the second direction on the same side of the bisector in the second direction.
  • the shape of the body portion of the first anode 1751 includes a hexagon, and the first anode 1751 is closest to the fourth anode 1754 adjacent to the first anode 1751 in the second direction.
  • the points are the vertices of the hexagon.
  • two adjacent light-emitting element rows 330 are arranged staggered by 1/2 pitch, and the above-mentioned pitch is equal to the two second light-emitting element groups 310 in the first direction.
  • the first straight line 301 is located between two adjacent light-emitting element rows 330.
  • the orthographic projection of the first via 2421 closest to the first straight line 301 on the base substrate 110 is located on the first straight line 301 close to the first line 301.
  • the via 2421 corresponds to one side of the first anode 1751. That is, the display substrate moves the position of the first via to a direction close to the first anode. Therefore, the display substrate has the following beneficial effects: (1) The distance between the first via hole and the effective light-emitting area of the fourth light-emitting element that is closest in the second direction is increased, thereby ensuring that the fourth light-emitting element is located adjacent to it.
  • the flatness of the fourth anode in the effective light-emitting area of the element thereby avoiding color shift; (2) The distance between the first via hole and the effective light-emitting area of the first light-emitting element is reduced, thereby reducing the distance between the first light-emitting element and the The resistance between the first anode and the first connecting electrode in the effective light-emitting area; (3) The distance between the first anode and the fourth anode is increased, so that the first anode and the fourth anode can be avoided due to the manufacturing process. The residue causes a short circuit.
  • the embodiments of the present disclosure are not limited thereto, and the orthographic projection of the first via on the base substrate may also be located on the first straight line.
  • the distance between the orthographic projection of the fourth via 2424 on the base substrate 110 and the orthographic projection of the first straight line 301 on the base substrate 110 is greater than that of the first via 2421 on the base substrate 110.
  • the fourth via has a larger offset.
  • the embodiments of the present disclosure include but are not limited thereto. Relative to the first straight line, the offset amount of the fourth via hole may also be equal to the offset amount of the first via hole.
  • the orthographic projection of the effective light-emitting area of the second light-emitting element 312 on the base substrate 110 and the orthographic projection of the second via 2422 on the base substrate 110 have the first shortest distance L1.
  • the orthographic projection of the effective light-emitting area of the third light-emitting element 313 on the base substrate 110 and the orthographic projection of the third via 2423 on the base substrate 110 have the second shortest distance L2, the first shortest distance L1, and the second shortest distance L1.
  • the two shortest distances L2 are roughly equal.
  • first shortest distance and second shortest distance are approximately equal, including the case where the first shortest distance and the second shortest distance are completely equal, and also include the case where the difference between the first shortest distance and the second shortest distance is less than 1 micron. Condition.
  • the display substrate can make the second anode located in the effective light-emitting area of the second light-emitting element and the third anode located in the effective light-emitting area of the third light-emitting element have the same degree of inclination and opposite inclination directions, thereby effectively avoiding color The occurrence of partial phenomenon. It should be noted that when the second anode located in the effective light-emitting area of the second light-emitting element and the third anode located in the effective light-emitting area of the third light-emitting element are not inclined, it can be considered that the second light-emitting element is the second light-emitting area of the effective light-emitting area.
  • the inclination degree of the second anode and the third anode located in the effective light-emitting area of the third light-emitting element is zero; in addition, the above-mentioned orthographic projection of the effective light-emitting area of the second light-emitting element on the base substrate and the second via hole in the substrate
  • the first shortest distance of the orthographic projection on the substrate may be the shortest distance between the edge of the orthographic projection of the effective light-emitting area of the second light-emitting element on the base substrate and the edge of the orthographic projection of the second via on the base substrate ;
  • the second shortest distance between the orthographic projection of the effective light-emitting area of the third light-emitting element on the base substrate and the orthographic projection of the third via on the base substrate may be the effective of the third light-emitting element
  • the orthographic projection of the fourth via 2424 on the base substrate 110 and the effective light-emitting area of the first light-emitting element 311 adjacent in the second direction are on the base substrate 110.
  • the distance C between the projections is greater than 1.2 times the width A in the first direction of the effective light-emitting areas of the first light-emitting elements 311 adjacent in the second direction. Therefore, the display substrate can ensure that the first anode located in the effective light-emitting area of the first light-emitting element has good flatness.
  • the shortest distance B between the fourth via 2424 in one light-emitting element group 310 and the first anode 1751 in the adjacent light-emitting element group 310 is smaller than the fourth through hole in the light-emitting element group 310.
  • the shortest distance between the fourth anode 1754 in one light-emitting element group 310 and the first anode 1751 in the light-emitting element group 310 that is closest to the four anode 1754 in the second direction is The distance between the vertex of the first anode 1751 in the adjacent light-emitting element group 310 and the fourth anode 1754 in the light-emitting element group 310.
  • the vertex of the first anode 1751 in the adjacent light-emitting element group 310 is the point closest to the fourth anode 1754 in the light-emitting element group 310.
  • the shape of the orthographic projection of the first anode 1751 on the base substrate 110 is a hexagon, and the aforementioned vertex is the vertex on the long axis of the hexagon.
  • the display substrate 100 further includes a pixel defining layer 190; the pixel defining layer 190 is located on the first anode 1751 and the second anode. 1752, a side of the third anode 1753 and the fourth anode 1754 away from the base substrate 110; the pixel defining layer 190 includes a first opening 1951, a second opening 1952, a third opening 1953, and a fourth opening 1954.
  • the first light-emitting element 311 includes a first light-emitting portion 1851
  • the second light-emitting element 312 includes a second light-emitting portion 1852
  • the third light-emitting element 313 includes a third light-emitting portion 1853
  • the fourth light-emitting element 314 includes a fourth light-emitting portion 1854.
  • the first opening 1951 falls within the orthographic projection of the first anode 1751 on the base substrate 110, at least a part of the first light-emitting portion 1851 is located in the first opening 1951 and covers the exposed portion of the first anode 1751, and the second opening 1952 Within the orthographic projection of the second anode 1752 on the base substrate 110, at least a part of the second light-emitting portion 1852 is located in the second opening 1952 and covers the exposed part of the second anode 1752, and the third opening 1953 falls into the third
  • the anode 1753 is within the orthographic projection on the base substrate 110, at least a part of the third light-emitting portion 1853 is located in the third opening 1953 and covers the exposed part of the third anode 1753, and the fourth opening 1954 falls into the fourth anode 1754 in the lining
  • at least a part of the fourth light-emitting portion 1854 is located in the fourth opening 1954 and covers the exposed portion of the fourth anode 1754.
  • the area defined by the first opening 1951 is the effective light-emitting area of the first light-emitting element 313, the area defined by the second opening 1952 is the effective light-emitting area of the second light-emitting element 312, and the area defined by the third opening 1953 is the effective light-emitting area of the third light-emitting element 313.
  • the effective light-emitting area is the effective light-emitting area of the fourth light-emitting element 314 defined by the fourth opening 1954.
  • the distance between the orthographic projection of the fourth via 2424 on the base substrate 110 and the orthographic projection of the first opening 1951 adjacent in the second direction on the base substrate 110 C is greater than 1.2 times the width A of the first opening 1951 in the first direction. Therefore, the display substrate can ensure that the first anode located at the first opening (that is, the portion of the first anode exposed by the first opening) has good flatness.
  • the display substrate 100 includes a first flat layer 241 and a first conductive layer 150;
  • the second conductive layer 160 is close to the side of the base substrate 110;
  • the first conductive layer 150 is located on the side of the first flat layer 241 close to the base substrate 110.
  • the first conductive layer 150 includes a first drain 1511, a second drain 1512, a third drain 1513, and a fourth drain 1514;
  • the first flat layer 241 includes a fifth via 2415, a sixth via 2416, and a seventh drain.
  • the first connection electrode 1611 is connected to the first drain 1511 through the fifth via 2415
  • the second connection electrode 1612 is connected to the second drain 1512 through the sixth via 2416
  • the third connection electrode 1613 is connected to the third drain 1513 through the seventh via hole 2417
  • the fourth connection electrode 1614 is connected to the fourth drain 1514 through the eighth via 2418.
  • the display substrate 100 further includes a first pixel driving circuit 2651, a second pixel driving circuit 2652, a third pixel driving circuit 2653, and a fourth pixel driving circuit 2654;
  • the drain 1511 is a part of the first pixel driving circuit 2651
  • the second drain 1512 is a part of the second pixel driving circuit 2652
  • the third drain 1513 is a part of the third pixel driving circuit 2653
  • the fourth drain 1514 is a part of the third pixel driving circuit 2653. Part of the four-pixel driving circuit 2654.
  • the first pixel driving circuit 2651 is connected to the first anode 1751 through the first connecting electrode 1611, thereby applying a driving signal to the first anode 1751;
  • the second pixel driving circuit 2652 is connected to the second anode 1752 through the second connecting electrode 1612, thereby The second anode 1752 applies a driving signal;
  • the third pixel driving circuit 2653 is connected to the third anode 1753 through the third connecting electrode 1613, thereby applying a driving signal to the third anode 1753;
  • the fourth pixel driving circuit 2654 is connected to the third anode 1753 through the fourth connecting electrode 1614
  • the fourth anode 1754 is connected to apply a driving signal to the fourth anode 1754.
  • FIG. 7 is a schematic diagram of a planar relationship between a second conductive layer and an anode layer in a display substrate provided by an embodiment of the present disclosure.
  • the second anode 1752 and the third anode 1753 are arranged along the second direction to form an anode pair 1755, the first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged along the first direction;
  • the layer 160 also includes a first conductive portion 1621, a second conductive portion 1622, a third conductive portion 1623, and a fourth conductive portion 1624 extending in the second direction.
  • the first conductive portion 1621 is located at one of the first anode 1751 away from the anode pair 1755.
  • the second conductive portion 1622 is located between the first anode 1751 and the anode pair 1755
  • the third conductive portion 1623 is located between the anode pair 1755 and the fourth anode 1754
  • the fourth conductive portion 1624 overlaps the fourth anode 1754.
  • the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, and the fourth conductive portion 1624 extending in the second direction can be connected to the power line in the first conductive layer 150, thereby reducing The resistance of the power cord.
  • the orthographic projection of the first conductive portion 1621 and the second conductive portion 1622 on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate 110 do not overlap.
  • the orthographic projection of the second conductive portion 1622 and the third conductive portion 1623 on the base substrate 110 and the orthographic projection of the anode pair 1755 on the base substrate 110 do not overlap. Therefore, the first conductive portion 1621 and the second conductive portion 1622 have little effect on the flatness of the first anode 175; The flatness of the anode 1753 is less affected.
  • the embodiments of the present disclosure include but are not limited thereto, and the first conductive portion, the second conductive portion, and the third conductive portion may also overlap the anode.
  • the orthographic projection of the first conductive portion 1621 and the second conductive portion 1622 on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate 110 respectively have a first overlapping portion and a second overlapping portion,
  • the areas of the first overlap portion and the second overlap portion are approximately equal, so that the flatness of the first anode 1751 can also be improved.
  • the orthographic projection of the second conductive portion 1622 and the third conductive portion 1623 on the base substrate 110 and the orthographic projection of the anode pair 1755 on the base substrate 110 respectively have a third overlapping portion and a fourth overlapping portion
  • the areas of the third overlapped portion and the fourth overlapped portion are approximately equal, so that the flatness of the second anode 1752 and the third anode 1753 of the anode pair 1755 can also be improved.
  • substantially equal includes the case where they are completely equal and the case where the difference between the two is less than 10% of the average value of the two.
  • the first overlapping portion and the second overlapping portion are symmetrical with respect to the main body of the first anode 1751, that is, the effective light-emitting area of the first light-emitting element 311 along the bisector of the second direction, so that the first light-emitting element can be further improved.
  • the flatness of the effective light-emitting area of the 311; the third and fourth overlaps are symmetrical about the bisector of the anode pair 1755 in the second direction, so that the second anode 1752 and the third anode of the anode pair 1755 can be further improved.
  • the flatness of 1753 is symmetrical with respect to the main body of the first anode 1751, that is, the effective light-emitting area of the first light-emitting element 311 along the bisector of the second direction, so that the first light-emitting element can be further improved.
  • the flatness of the effective light-emitting area of the 311; the third and fourth overlaps are symmetric
  • the orthographic projection of the fourth conductive portion 1624 on the base substrate 110 passes through the center of the orthographic projection of the fourth anode 1754 on the base substrate 110, and the fourth conductive portion 1624 extends along the first
  • the orthographic projection of the bisecting line of the two directions on the base substrate 110 coincides with the orthographic projection of the bisecting line of the effective light-emitting area of the fourth light-emitting element 314 along the second direction on the base substrate 110. Therefore, the flatness of the fourth anode 1754 can also be improved.
  • the second conductive layer 160 further includes a fifth conductive portion 1625 and a sixth conductive portion 1626 extending along the first direction; the fifth conductive portion 1625 and the second conductive portion 1622 and the third conductive portion 1625
  • the conductive portions 1623 are connected to each other and are located between the second anode 1752 and the third anode 1753; the sixth conductive portion 1626 is connected to the third conductive portion 1623 and the fourth conductive portion 1624, respectively, and is located adjacent in the second direction. Between the first anode 1751 and the fourth anode 1754.
  • the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, the fourth conductive portion 1624, the fifth conductive portion 1625, and the sixth conductive portion 1626 can form a mesh structure, thereby further reducing the first conductive portion.
  • the electrical resistance of the power line in the conductive layer can further improve the electrical performance of the display substrate.
  • the second conductive portion 1622 includes a main body portion 1622A, a spacer block 1622B, and a connecting block 1622C extending in the second direction, and the spacer block 1622B is located on the side of the main body portion 1622A close to the first anode 1751 , And spaced apart from the main body portion 1622A, the spacer block 1622B is connected to the main body portion 1622A through a connecting block 1622C. Since the size (ie width) of the general first anode in the first direction is small, and the distance between the main body of the first conductive part and the second conductive part is relatively large, the first anode can be improved by providing the above-mentioned spacer. The symmetry of the first conductive part and the second conductive part on both sides can improve the flatness of the first anode.
  • the first light emitting element is configured to emit light of a first color
  • the second light emitting element and the third light emitting element are configured to emit light of a second color
  • the fourth light emitting element is configured to emit light of a third color. Light.
  • the first color is red (R)
  • the second color is green (G)
  • the third color is blue (B).
  • the display substrate adopts a GGRB pixel arrangement structure.
  • FIG. 8 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 400 includes the display substrate 100 of any one of the above.
  • the display device has beneficial effects corresponding to the beneficial effects of the display substrate.
  • the display device can ensure the flatness of the first anode located in the effective light-emitting area of the first light-emitting element, thereby avoiding color shift; it can reduce the fourth anode and the fourth connection located in the effective light-emitting area of the fourth light-emitting element.
  • the resistance between the electrodes and can also increase the distance between the first anode and the fourth anode, so as to prevent the first anode and the fourth anode from being short-circuited due to the residue left by the manufacturing process.
  • the display device may be a display panel, or may be an electronic product with a display function, such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • the inventor of the present application found that because the second source and drain metal layer under the anode is thicker and unevenly distributed, the second source and drain metal layer may also cause unevenness in the anode.
  • FIG. 9 is a schematic partial cross-sectional view of another display substrate
  • FIG. 10 is a schematic partial cross-sectional view of another display substrate.
  • the second source-drain metal layer 160 includes a plurality of traces 168. If there is a trace 168 on one side under the anode 175, and there is no trace 168 on the other side, a height will be generated on both sides of the anode 175. The difference causes the anode 175 to produce a "tilt" phenomenon, which in turn causes a color shift phenomenon. As shown in FIG.
  • the anode 175 can ensure high flatness, thereby ensuring that the luminous intensity of the anode 175 in different directions is consistent. In turn, the color cast can be effectively improved.
  • inventions of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, a first conductive layer, a first flat layer, a second conductive layer, a second flat layer and a plurality of light-emitting element groups; the first conductive layer is located on the base substrate; the first flat layer is located on the A conductive layer is located on the side away from the base substrate; the second conductive layer is located on the side of the first flat layer away from the first conductive layer; the second flat layer is located on the side of the second conductive layer away from the first flat layer; multiple light emitting The element group is located on the side of the second flat layer away from the second conductive layer.
  • a plurality of light-emitting element groups are arranged along a first direction to form a plurality of light-emitting element columns, and a plurality of light-emitting element groups are arranged along a second direction to form a plurality of light-emitting element rows.
  • Each light-emitting element group includes a first light-emitting element, a second light-emitting element, and a first light-emitting element.
  • the first light-emitting element includes a first anode
  • the second conductive layer includes a first conductive portion and a second conductive portion extending in a second direction. The first conductive portion is located on one side of the first anode.
  • the second conductive portion is located on the side of the first anode away from the first conductive portion
  • the first conductive portion includes an extension portion and an offset portion
  • the effective light-emitting area of the first light-emitting element is positive on a straight line extending in the second direction
  • the projection is covered by the orthographic projection of the offset portion on the straight line.
  • the orthographic projection of the offset portion on the base substrate is spaced apart from the orthographic projection of the first anode on the base substrate.
  • the extension is close to the second conductive portion and along the The straight line on which the edge extending in the second direction is located is the first straight line, and the offset part is spaced apart from the first straight line and is located on the side of the first straight line away from the second conductive part.
  • the first conductive part is located on the side of the first anode
  • the second conductive part is located on the side of the first anode away from the first conductive part
  • the orthographic projection of the offset part on the base substrate is in line with the first anode.
  • the orthographic projections on the base substrate are arranged at intervals, so the first conductive portion and the second conductive portion in the second conductive layer have less influence on the flatness of the first anode, so that the first anode can ensure a higher level of flatness In order to ensure the uniformity of the luminous intensity of the first anode in different directions, the color shift phenomenon can be effectively improved.
  • An embodiment of the present disclosure provides a display substrate.
  • 11 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure
  • FIG. 12A is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure along the HH direction in FIG. 11
  • FIG. 12B is an implementation of the present disclosure
  • the example provides a schematic cross-sectional view of a display substrate along the JJ direction in FIG. 11
  • FIG. 13 is a schematic plan view of another display substrate provided according to an embodiment of the present disclosure
  • FIG. 14 only shows the second conductive layer and the anode layer.
  • the display substrate 100 includes a base substrate 110, a first conductive layer 150, a first flat layer 241, a second conductive layer 160, a second flat layer 242, and a plurality of light-emitting element groups 310;
  • the two conductive layers 160 are located on the base substrate 110;
  • the second flat layer 242 is located on the side of the second conductive layer 160 away from the base substrate 110;
  • the multiple light-emitting element groups 310 are located on the side of the second flat layer 242 away from the base substrate 110 .
  • the multiple light-emitting element groups 310 are arranged along the first direction to form multiple light-emitting element columns 320, and are arranged along the second direction to form multiple light-emitting element rows 330.
  • Each light-emitting element group 310 includes a first light-emitting element 311 and a second light-emitting element 311.
  • the fourth light-emitting element 314 includes a fourth anode 1754, the second anode 1752 and the third anode 1753 are arranged in the second direction to form an anode pair 1755, and the first anode 1751, the anode pair 1755 and the fourth anode 1754 are arranged in the first direction.
  • the second conductive layer 160 includes a first conductive portion 1621 and a second conductive portion 1622 extending in the second direction.
  • the first conductive portion 1621 is located on the side of the first anode 1751 away from the anode pair 1755, and the second conductive portion 1622 is located at the first Between the anode 1751 and the anode pair 1755, that is, the side of the first anode 1751 away from the first conductive portion 1621.
  • the first conductive portion 1621 includes an extension portion 1621A and an offset portion 1621B.
  • the orthographic projection of the effective light-emitting area of the first light-emitting element 311 on a straight line extending in the second direction is covered by the orthographic projection of the offset portion 1621B on the straight line.
  • the orthographic projection of the effective light-emitting area of the first light-emitting element 311 on the first conductive portion 1621 is located at the position where the offset portion 1621B is located, that is, the offset portion 1621B corresponds to the effective light-emitting area of the first light-emitting element 311.
  • the orthographic projection of the offset portion 1621B on the base substrate 110 is spaced apart from the orthographic projection of the first anode 1751 on the base substrate 110.
  • the extension portion 1621A is close to the second conductive portion 1622 and extends along the second direction. It is the first straight line 302, and the offset portion 1621B is spaced apart from the first straight line 302 and is located on the side of the first straight line 302 away from the second conductive portion 1622. It should be noted that the above-mentioned first conductive layer and second conductive layer are sequentially stacked along the direction away from the base substrate.
  • the first conductive portion is located on the side of the first anode
  • the second conductive portion is located on the side of the first anode away from the first conductive portion
  • the offset portion is on the base substrate
  • the orthographic projection of the first anode is spaced apart from the orthographic projection of the first anode on the base substrate. Therefore, the first conductive portion and the second conductive portion in the second conductive layer have less influence on the flatness of the first anode, thereby making the first anode
  • An anode can ensure a high degree of flatness, thereby ensuring that the luminous intensity of the first anode in different directions is consistent, thereby effectively improving the color shift phenomenon.
  • the offset part is spaced apart from the first straight line and is located on the side of the first straight line away from the second conductive part, the offset part is offset in the direction away from the first anode, which provides a Therefore, the first anode can ensure high flatness while realizing the close arrangement of the anodes.
  • the first light emitting element 311 is configured to emit light of a first color
  • the second light emitting element 312 and the third light emitting element 313 are configured to emit light of a second color
  • the fourth light emitting element 314 is configured to emit light.
  • the third color of light is configured to emit light.
  • the first color is red
  • the second color is green
  • the third color is blue
  • the orthographic projection of the first straight line 302 on the base substrate 110 passes through the orthographic projection of the first anode 1751 on the base substrate 110.
  • the display substrate can realize the close arrangement of the anodes while ensuring the high flatness of the first anodes.
  • the straight line on which the bisector of the extension portion 1621A extends in the second direction is the second straight line 303
  • the offset portion 1621B is spaced apart from the second straight line 303 and is located in the second straight line 303.
  • the orthographic projection of the second straight line 303 on the base substrate 110 passes through the orthographic projection of the first anode 1751 on the base substrate 110.
  • the display substrate can realize the close arrangement of the anodes while ensuring the high flatness of the first anodes.
  • the first anode 1751 extends in the second direction
  • the second conductive portion 1622 includes a main body portion 1622A and a spacer 1622B extending in the second direction.
  • the main body portion 1622A is on the base substrate.
  • the orthographic projection on 110 is spaced apart from the orthographic projection of the first anode 1751 on the base substrate 110.
  • the spacer 1622B is located on the side of the main body 1622A close to the first anode 1751.
  • the orthographic projection of the spacer 1622B on the base substrate 110 The distance from the orthographic projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 and the orthographic projection of the first conductive portion 1621 on the base substrate 110 and the center of the effective light-emitting area of the first light-emitting element 311 The distance of the orthographic projection on the base substrate 110 is approximately equal.
  • the distance between the main body of the first conductive part and the second conductive part is relatively large;
  • the distance between the orthographic projection on the base substrate and the orthographic projection of the center of the effective light-emitting area of the first light-emitting element on the base substrate and the orthographic projection of the first conductive portion on the base substrate and the effective light-emitting area of the first light-emitting element is approximately the same. Therefore, the symmetry of the first conductive portion and the second conductive portion on both sides of the first anode can be improved by providing the above-mentioned spacer, thereby further improving the first anode Flatness.
  • the distance between the orthographic projection of the first conductive portion 1621 on the base substrate 110 and the orthographic projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 It is smaller than the distance between the orthographic projection of the main body portion 1622A on the base substrate 110 and the orthographic projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110.
  • the distance between the orthographic projection of the first conductive portion 1621 on the base substrate 110 and the orthographic projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 and the distance between the main body portion 1622A on the base substrate 110 The ratio of the orthographic projection and the distance of the orthographic projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 is less than or equal to 1/3.
  • the orthographic projection of the spacer block 1622B on the base substrate 110 and the orthographic projection of the main body portion 1622A on the base substrate 110 are spaced apart, and the second conductive portion 1622 further includes a connecting portion 1622C, the cushion block 1622B is connected to the main body 1622A through the connecting portion 1622C. Therefore, because the spacer 1622B is connected to the main body 1622A through the connecting portion 1622C, instead of being formed integrally with the main body 1622A, the second conductive portion 1622 and the underlying film layers, such as semiconductor layers, gate layers, etc., can be avoided. Excessive overlap, so as to avoid aggravating the load of the film layer under the second conductive portion 1622. Therefore, the display substrate can ensure the normal operation of each sub-pixel while adding spacers.
  • the first conductive layer 150 includes a power line 151 and a data line 152 extending in the second direction, a first connection block 1541 and a second connection block 1542.
  • the first connection block 1541 is used to connect the initialization signal line to the corresponding source region in the pixel driving circuit;
  • the second connection block 1542 is used to connect the drain region of the compensation thin film transistor to the first electrode block CE1, the first electrode block CE1 can form a storage capacitor with the second electrode block CE2, and also serves as a gate for driving the thin film transistor.
  • the spacer 1622B is connected to the main body 1622A through the connecting portion 1622C, instead of being formed integrally with the main body 1622A, excessive overlap between the second conductive portion 1622 and the second connecting block 1542 can be avoided, thereby reducing the second conductive portion 1622 and the second connecting block 1542.
  • the load of the two connecting blocks 1542 that is, the load of compensating the drain of the thin film transistor and the gate of the driving thin film transistor, can further improve the performance of the display substrate.
  • the display substrate adopts a 7T1C pixel driving circuit.
  • the embodiments of the present disclosure include but are not limited to this, and the display substrate may adopt other suitable pixel driving circuit structures.
  • the orthographic projection of the offset portion 1621B on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate are spaced apart; the orthographic projection of the spacer 1622B on the base substrate 110 and The orthographic projection of the first anode 1751 on the base substrate 110 is arranged at intervals.
  • the display substrate may further include a passivation layer 364 located between the first conductive layer 150 and the first flat layer 241.
  • the embodiments of the present disclosure include but are not limited thereto, and the display substrate may not be provided with a passivation layer.
  • the distance between the orthographic projection of the spacer 1622B on the base substrate 110 and the orthographic projection of the main body portion 1622A on the base substrate 110 is greater than that of the spacer 1622B on the base substrate 110.
  • the second conductive portion 1622 includes two connecting portions 1622C, and the two connecting portions 1622C are respectively located at both ends of the spacer block 1622B in the second direction.
  • the spacer block 1622B has two The connecting portion 1622C and the main body portion 1622A enclose a rectangular opening. Therefore, the display substrate can further avoid excessive overlap between the second conductive portion 1622 and the underlying film layer, such as the semiconductor layer, the gate layer, etc., so as to avoid aggravating the load of the semiconductor layer, the gate layer, and the like. Therefore, the display substrate can ensure the normal operation of each sub-pixel while adding spacers.
  • the ratio of the width of the cushion block in the first direction to the width of the main body in the first direction is less than or equal to 1/2, and the width of the cushion block in the first direction is greater than the difference between the main body and the cushion block.
  • the ratio of the distance is less than or equal to 1/2.
  • the ratio of the length of the spacer in the second direction to the length of the effective light-emitting area of the first light-emitting element in the second direction is greater than or equal to 7/8.
  • the angle between the effective light-emitting area of the first light-emitting element and the center line of the spacer and the first direction is less than 30 degrees.
  • the angle between the effective light-emitting area of the first light-emitting element and the center line of the pad and the first direction is zero, that is, the effective light-emitting area of the first light-emitting element and the center line of the pad and the first direction are mutually connected. parallel.
  • the orthographic projection of the spacer block on the base substrate and the orthographic projection of the first anode on the base substrate are spaced apart, and the orthographic projection of the first conductive portion on the base substrate is the same as the orthographic projection of the first anode on the base substrate.
  • the interval setting of the orthographic projection is the same as the orthographic projection of the first anode on the base substrate.
  • the overlapping area of the orthographic projection of the spacer block on the base substrate and the orthographic projection of the first anode on the base substrate and the orthographic projection of the first conductive portion on the base substrate are the same as the orthographic projection of the first anode on the base substrate.
  • the overlapping area of the orthographic projection on the base substrate is approximately equal.
  • the second conductive layer 160 further includes a third conductive portion 1623 and a fourth conductive portion 1624 extending in the second direction; the third conductive portion 1623 is located in the anode pair 1755 and the fourth conductive portion 1624. Between the anodes 1754, the fourth conductive portion 1624 overlaps the fourth anode 1754.
  • the orthographic projection of the main body portion 1622A of the second conductive portion 1622 on the base substrate 110 and the bisector of the effective light-emitting area of the second light-emitting element 312 along the second direction are in the line.
  • the distance of the orthographic projection on the base substrate 110 and the orthographic projection of the third conductive portion 162 on the base substrate 110 and the orthographic projection of the bisector of the effective light-emitting area of the second light-emitting element 312 along the second direction on the base substrate 110 The distances are roughly equal.
  • the display substrate can improve the symmetry of the anode to the second conductive portion and the third conductive portion on both sides, so that the flatness of the second anode and the third anode can be further improved.
  • the fourth anode 1754 extends in the second direction, and the orthographic projection of the fourth conductive portion 1624 on the base substrate 110 passes through the effective light-emitting area of the fourth light-emitting element 314 in the liner.
  • the center of the orthographic projection on the base substrate 110 Therefore, although the fourth conductive portion 162 overlaps the fourth anode 1754, the orthographic projection of the fourth conductive portion 1624 on the base substrate 110 passes through the effective light-emitting area of the fourth light-emitting element 314 on the base substrate 110.
  • the fourth conductive part can ensure that the fourth anode has a higher flatness, thereby ensuring that the fourth anode has the same luminous intensity in different directions, and thereby can effectively improve the color shift phenomenon.
  • the second conductive layer 160 further includes a fifth conductive portion 1625 and a sixth conductive portion 1626 extending along the first direction, and the fifth conductive portion 1625 and the main body portion 1622A and the third conductive portion 1625
  • the conductive portions 1623 are respectively connected and located between the second anode 1752 and the third anode 1753 in the anode pair 1755;
  • the sixth conductive portion 1626 is connected to the third conductive portion 1623 and the fourth conductive portion 1624, respectively, and is located in the second Between the first anode 1751 and the fourth anode 1754 adjacent in the direction.
  • the first conductive portion 1621, the second conductive portion 1622, the third conductive portion 1623, the fourth conductive portion 1624, the fifth conductive portion 1625, and the sixth conductive portion 1626 can form a mesh structure, thereby further reducing the first conductive portion.
  • the electrical resistance of the power line in the conductive layer can further improve the electrical performance of the display substrate.
  • the second conductive layer 160 includes a first connection electrode 1611, a second connection electrode 1612, a third connection electrode 1613, and a fourth connection electrode 1614
  • the second flat layer 242 includes a first connection electrode 1611.
  • the first flat layer 241 is located on the side of the second conductive layer 160 close to the base substrate 110; the first conductive layer 150 is located on the side of the first flat layer 241 close to the base substrate 110.
  • the first conductive layer 150 includes a first drain 1511, a second drain 1512, a third drain 1513, and a fourth drain 1514; the first flat layer 241 includes a fifth via 2415, a sixth via 2416, and a seventh drain.
  • the first connection electrode 1611 is connected to the first drain 1511 through the fifth via 2415
  • the second connection electrode 1612 is connected to the second drain 1512 through the sixth via 2416
  • the third connection electrode 1613 is connected to the third drain 1513 through the seventh via hole 2417
  • the fourth connection electrode 1614 is connected to the fourth drain 1514 through the eighth via 2418.
  • the display substrate 100 further includes a first pixel driving circuit 2651, a second pixel driving circuit 2652, a third pixel driving circuit 2653, and a fourth pixel driving circuit 2654;
  • the pole 1511 is a part of the first pixel driving circuit 2651
  • the second drain 1512 is a part of the second pixel driving circuit 2652
  • the third drain 1513 is a part of the third pixel driving circuit 2653
  • the fourth drain 1514 is a fourth Part of the pixel drive circuit 2654.
  • the first pixel driving circuit 2651 is connected to the first anode 1751 through the first connecting electrode 1611, thereby applying a driving signal to the first anode 1751;
  • the second pixel driving circuit 2652 is connected to the second anode 1752 through the second connecting electrode 1612, thereby The second anode 1752 applies a driving signal;
  • the third pixel driving circuit 2653 is connected to the third anode 1753 through the third connecting electrode 1613, thereby applying a driving signal to the third anode 1753;
  • the fourth pixel driving circuit 2654 is connected to the third anode 1753 through the fourth connecting electrode 1614
  • the fourth anode 1754 is connected to apply a driving signal to the fourth anode 1754.
  • the thickness of the second conductive layer may be in the range of 0.6-0.8 micrometers, such as 0.7 micrometers; the thickness of the second flat layer may be in the range of 1.3-1.7 micrometers, such as 1.5 micrometers.
  • FIG. 15 is a schematic plan view of another display substrate provided according to an embodiment of the present disclosure.
  • FIG. 15 only shows the second conductive layer and the anode layer.
  • the second conductive portion 1622 of the second conductive layer 160 is not provided with a spacer.
  • the first conductive portion 1621 of the second conductive layer 160 includes an extension portion 1621A and an offset portion 1621B.
  • the orthographic projection of the light-emitting area on the first conductive portion 1621 is located at the position where the offset portion 1621B is located, that is, the offset portion 1621B corresponds to the effective light-emitting area of the first light-emitting element 311.
  • the orthographic projection of the offset portion 1621B on the base substrate 110 and the orthographic projection of the first anode 1751 on the base substrate 110 are spaced apart, and the straight line where the edge of the extension portion 1621A close to the first anode 1751 and extending in the second direction is located is The first straight line 302, the offset portion 1621B is spaced apart from the first straight line 302 and is located on the side of the first straight line 302 away from the anode pair 1755.
  • the first conductive portion is located on the side of the first anode away from the anode pair
  • the second conductive portion is located between the first anode and the anode pair
  • the offset portion is on the base substrate
  • the orthographic projection of the first anode is spaced apart from the orthographic projection of the first anode on the base substrate. Therefore, the first conductive portion and the second conductive portion in the second conductive layer have less influence on the flatness of the first anode, thereby making the first anode
  • An anode can ensure a high degree of flatness, thereby ensuring that the luminous intensity of the first anode in different directions is consistent, thereby effectively improving the color shift phenomenon.
  • the offset part is spaced apart from the first straight line and is located on the side of the first straight line away from the anode pair, the offset part is offset in a direction away from the first anode, providing space for the installation of the first anode, In this way, the first anode can ensure high flatness while realizing the close arrangement of the anodes.
  • the first anode 1751 may include a main body part 1751A, a connecting part 1751B, and a supplementary part 1751C; Connected to the corresponding pixel driving circuit, the supplemental portion 1751C can cover the potential on the gate G1 of the driving thin film transistor T1 and the drain D3 of the compensation thin film transistor T3 in the corresponding pixel driving circuit, thereby stably driving the gate of the thin film transistor T1 G1 and compensate the potential on the drain D3 of the thin film transistor T3, thereby further improving the long-term light-emitting stability and lifespan of the display substrate.
  • the distance range between the first anode 1751 and the offset portion 1621B may be 2.5-3.2 microns, for example, 2.9 microns; the distance range between the main body portion 1751A of the first anode 1751 and the second conductive portion 1622 may be 9-11 microns, for example, 10.5 microns; the distance between the connecting portion 1751B of the first anode 1751 and the second conductive portion 1622 can be 5-7 microns; the supplementary portion 1751C of the first anode 1751 can be part of the second conductive portion 1622 Overlap, and the width of the overlapped part in the first direction is less than 1 micrometer, for example, 0.79 micrometer. Since the distance between the edge of the supplementary portion close to the second conductive portion and the main body portion is relatively large, the supplementary portion 1751C may partially overlap with the second conductive portion 1622 and has less influence on the flatness of the first anode.
  • FIG. 16 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 400 includes the display substrate 100 of any one of the above.
  • the display device has beneficial effects corresponding to the beneficial effects of the display substrate.
  • the display device can ensure the flatness of the first anode located in the effective light-emitting area of the first light-emitting element, thereby avoiding color shift; it can reduce the fourth anode and the fourth connection located in the effective light-emitting area of the fourth light-emitting element.
  • the resistance between the electrodes and can also increase the distance between the first anode and the fourth anode, so as to prevent the first anode and the fourth anode from being short-circuited due to the residue left by the manufacturing process.
  • the display device may be an electronic product with a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • an evaporation process is usually used to manufacture the light emitting layer.
  • FMM fine metal mask
  • FIG. 17 is a schematic diagram of an evaporation process using a fine metal mask. As shown in FIG.
  • the opening edge 252 of the fine metal mask 250 is located at the top of the spacer 220, which is easy to scratch the top of the spacer 220 and produce foreign matter such as particles; after the evaporation process, it will be formed on the display substrate
  • the encapsulation layer and other film layers, and the generated particles and other foreign matter can easily cause defects such as cracks in the encapsulation layer, thereby reducing the stability and reliability of the product.
  • the embodiments of the present disclosure also provide a display substrate, a manufacturing method thereof, and a display device.
  • the display substrate includes a base substrate, a light-emitting layer and spacers; the light-emitting layer is located on the base substrate and includes a plurality of light-emitting parts; the spacers are located on the side of the light-emitting layer away from the base substrate; the spacers are away from the base substrate.
  • the orthographic projection of the top end on the base substrate and the edge of the orthographic projection of the light-emitting part on the base substrate are spaced apart.
  • the orthographic projection of the opening edge of the fine metal mask on the base substrate and the orthographic projection of the tip of the spacer on the base substrate can prevent the edge of the opening of the fine metal mask from contacting the top of the spacer, and avoid the generation of foreign matter such as particles, thereby improving the yield of the display substrate.
  • FIG. 18 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 19 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure along the CC direction in FIG. 18.
  • the display substrate 100 includes a base substrate 110, a light-emitting layer 180, and spacers 220; the light-emitting layer 180 is located on the base substrate 110 and includes a plurality of light-emitting parts 185; the spacers 220 are located The side of the base substrate 110 where the light-emitting layer 180 is located. The front end 225 of the spacer 220 away from the base substrate 110 is spaced apart from the edge of the orthographic projection of the light-emitting portion 185 on the base substrate 110.
  • the above-mentioned top of the spacer refers to the part of the spacer away from the base substrate, that is, the part with a larger thickness; in addition, the above-mentioned “spaced arrangement” refers to the top of the spacer away from the base substrate
  • the orthographic projection on the base substrate and the orthographic projection of the light-emitting part on the base substrate have a certain interval, and they do not overlap or contact each other.
  • the opening edge 252 of the fine metal mask 250 is at The orthographic projection on the base substrate 110 and the orthographic projection of the top end 225 of the spacer 220 on the base substrate 110 are spaced apart; thus, the opening edge 252 of the fine metal mask 250 can be prevented from contacting the top end 225 of the spacer 220. And avoid foreign matter such as particles.
  • the opening edge 252 of the fine metal mask 250 is located at the edge portion of the spacer 220.
  • the display substrate can improve the stability, reliability and product yield of the display substrate.
  • the size of the middle portion of the spacer 220 in the direction perpendicular to the base substrate 110 is larger than the size of the edge portion of the spacer 220 in the direction perpendicular to the base substrate 110 . That is, the thickness of the middle part of the spacer 220 is greater than the thickness of the edge part of the spacer 220. Therefore, when the orthographic projection of the opening edge of the fine metal mask on the base substrate is spaced from the orthographic projection of the middle part of the spacer (that is, the top of the spacer) on the base substrate, the fine metal mask The edge of the opening can be in a suspended state, without contact with the spacer, so as to avoid the generation of particles and other foreign objects due to scratching.
  • the cross-sectional shape of the spacer 220 in a plane perpendicular to the base substrate 110 may include a semicircle.
  • the embodiments of the present disclosure include but are not limited to this.
  • the slope angle of the semicircle is in the range of 8-10 degrees.
  • the shape of the orthographic projection of the spacer 220 on the base substrate 110 is rectangular, and the orthographic projection of the central axis of the spacer 220 in the length direction on the base substrate 110 is the same as the orthographic projection of the spacer 220 on the base substrate 110.
  • the light emitting parts 185 are arranged at intervals on the edge of the orthographic projection on the base substrate 110. Therefore, the display substrate can prevent the opening edge of the fine metal mask from contacting the tip of the spacer, and avoid the generation of foreign matter such as particles, thereby improving the stability, reliability, and product yield of the display substrate.
  • the shape of the orthographic projection of the spacer on the base substrate in the embodiments of the present disclosure includes but is not limited to the above-mentioned rectangle, and may also be other shapes.
  • the distance between the orthographic projection of the central axis of the spacer 220 in the longitudinal direction on the base substrate 110 and the edge of the orthographic projection of the light-emitting portion 185 on the base substrate 110 is greater than 6 Micrometers. Therefore, the display substrate can effectively prevent the opening edge of the fine metal mask from contacting the tip of the spacer, and avoid the generation of foreign matter such as particles, thereby improving the stability, reliability and product yield of the display substrate.
  • FIG. 20 is a schematic plan view of another display substrate according to an embodiment of the present disclosure
  • FIG. 21 is a schematic cross-sectional view of a display substrate along the DD direction in FIG. 20 according to an embodiment of the present disclosure.
  • the orthographic projection of the top end 225 of the spacer 220 away from the base substrate 110 on the base substrate 110 and the edge of the orthographic projection of the light emitting portion 185 on the base substrate 110 are spaced apart.
  • FIG. 20 is a schematic plan view of another display substrate according to an embodiment of the present disclosure
  • FIG. 21 is a schematic cross-sectional view of a display substrate along the DD direction in FIG. 20 according to an embodiment of the present disclosure.
  • the orthographic projection of the top end 225 of the spacer 220 away from the base substrate 110 on the base substrate 110 and the edge of the orthographic projection of the light emitting portion 185 on the base substrate 110 are spaced apart.
  • FIG. 20 is a schematic plan view of another display substrate according to an embodiment of the present disclosure
  • the opening edge 252 of the fine metal mask 250 is in a suspended state and is not in contact with the spacer 220. Therefore, the display substrate can prevent the edge of the opening of the fine metal mask from contacting the tip of the spacer, and avoid the generation of foreign matter such as particles, thereby further improving the stability, reliability and product yield of the display substrate.
  • the plurality of light-emitting parts 185 includes a plurality of light-emitting groups 1850, which are arranged in a first direction to form a plurality of light-emitting group columns 280, and are arranged in a second direction to form a plurality of light-emitting groups 1850.
  • each light-emitting group 1850 includes a first light-emitting portion 1851, a second light-emitting portion 1852, a third light-emitting portion 1853, and a fourth light-emitting portion 1854;
  • two adjacent light-emitting group rows 290 are misaligned by 1 /2 pitch setting, the above-mentioned pitch is equal to the distance between the centers of two first light-emitting parts 1851 in two light-emitting groups 1850 adjacent in the first direction; the second light-emitting part 1852 and the third light-emitting part 1853
  • the second direction is arranged to form a light-emitting pair 1855, and the first light-emitting portion 1851, the light-emitting pair 1855, and the fourth light-emitting portion 1854 are arranged along the first direction.
  • the orthographic projection of the top end 225 of the spacer 220 on the base substrate 110 is located in the orthographic projection of the first light-emitting portion 1851 on the base substrate 110 and the third light-emitting portion 1853 in a light-emitting group 1850.
  • the orthographic projection on the base substrate 110 is between the orthographic projections on the base substrate 110 of the second light-emitting portion 1852 and the fourth light-emitting portion 1854 in another light-emitting group 1850 adjacent in the second direction.
  • the display substrate can ensure that the orthographic projection of the top end 225 of the spacer 220 on the base substrate 110 is in line with the first light-emitting portion 1851, the second light-emitting portion 1852, the third light-emitting portion 1853, and the fourth light-emitting portion 1854.
  • the orthographic projections on the base substrate 110 are arranged at intervals, and the space on the display substrate is fully utilized.
  • first direction and the second direction are substantially perpendicular. It should be noted that the above-mentioned first direction and second direction are substantially perpendicular, including the case where the angle between the first direction and the second direction is 90 degrees, and also includes the angle range between the first direction and the second direction. In the case of 85-95 degrees.
  • two light-emitting groups 1850 adjacent in the second direction may be a first light-emitting group 1850A and a second light-emitting group 1850B, and the top end 225 of the spacer 220 is at
  • the orthographic projection on the base substrate 110 is the orthographic projection of the first light-emitting portion 1851 of the first light-emitting group 1850A on the base substrate 110, and the orthographic projection of the third light-emitting portion 1853 of the first light-emitting group 1850A on the base substrate 110 between the orthographic projection of the second light-emitting portion 1852 of the second light-emitting group 1850B on the base substrate 110 and the orthographic projection of the fourth light-emitting portion 1854 of the second light-emitting group 1850B on the base substrate 110.
  • the display substrate can ensure that the orthographic projection of the top end 225 of the spacer 220 on the base substrate 110 is in line with the first light-emitting portion 1851, the second light-emitting portion 1852, the third light-emitting portion 1853, and the fourth light-emitting portion 1854.
  • the orthographic projections on the base substrate 110 are arranged at intervals, and the space on the display substrate is fully utilized.
  • the orthographic projection of the spacer 220 on the base substrate 110 may be a rectangle with a length of 20 micrometers and a width of 9.5 micrometers.
  • the distance between the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the third anode 1753 of the first light-emitting group 1850A on the base substrate 110 may range from 8.5 to 9.5 microns, for example, 8.9 Micron;
  • the distance between the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the fourth anode 1754 of the second light-emitting group 1850B on the base substrate 110 may range from 6-7 microns, for example, 6.3 microns .
  • the distance between the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the third light-emitting portion 1853 of the first light-emitting group 1850A on the base substrate 110 may be 0 microns, or even overlap each other.
  • the distance between the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the second light-emitting portion 1852 of the second light-emitting group 1850B on the base substrate 110 may be 0 micrometers or even overlap each other.
  • the display substrate 100 further includes an anode layer 170 and a pixel defining layer 190; the anode layer 170 is located between the base substrate 110 and the spacer 220, and the pixel defining layer 190 is located The anode layer 170 is close to the side of the spacer 220.
  • the anode layer 170 includes a plurality of anodes 175, and the pixel defining layer 190 includes a plurality of openings 195 to expose the plurality of anodes 175.
  • a plurality of anodes 175 are arranged corresponding to the plurality of light-emitting parts 185, and the plurality of openings 195 are arranged corresponding to the plurality of light-emitting parts 185.
  • the plurality of openings 195 include a plurality of opening groups 1950.
  • Each opening group 1950 includes a first opening 1951 Two openings 1952, a third opening 1953, and a fourth opening 1954.
  • a plurality of anodes 175 are arranged corresponding to the plurality of light-emitting parts 185.
  • the plurality of anodes 175 include a plurality of anode groups 1750, and each anode group 1750 includes a first anode 1751.
  • the two openings 1952 cover the exposed second anode 1752, the third light emitting portion 1853 is at least partially located in the third opening 1953 and covers the exposed third anode 1753, and the fourth light emitting portion 1854 is at least partially located in and covers the fourth opening 1954 The fourth anode 1754 is exposed.
  • the orthographic projection of the spacer 220 on the base substrate 110 may partially overlap the orthographic projection of the first anode 1751 on the base substrate 110.
  • the first virtual straight line is parallel to the length direction of the spacer 220 and passes through the center of the spacer 220;
  • the shape of the orthographic projection of the first opening 1951 on the base substrate 110 is roughly An ellipse, the range of the ratio of the distance from the vertex of the ellipse in the major axis direction to the first virtual straight line to the shortest distance from the first opening 1951 to the first virtual straight line is 1.5-1.
  • the distance between the first opening 1951 and the second opening 1952 is in the range of 20-25 micrometers; the distance between the first opening 1951 and the third opening 1953 is also 20-25 micrometers; the first opening 1951 and the fourth opening The distance between 1954 is also in the range of 20-25 microns.
  • the embodiments of the present disclosure include but are not limited to this, and the distance between each opening can be determined according to the actual product size.
  • the orthographic projection of the spacer 220 on the base substrate 110 and the spacer block of the first opening 1951 on the base substrate 110 are arranged. Therefore, in the manufacturing process of the display substrate provided by the embodiments of the present disclosure, when the fine metal mask is used for the vapor deposition process to form the above-mentioned light-emitting part, the display substrate can avoid the opening edges and spacers of the fine metal mask. Contact with the tip of the object, and avoid the generation of foreign objects such as particles.
  • the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the first opening 1951 on the base substrate 110 are spaced apart.
  • the shape of the orthographic projection of the first opening 1951 on the base substrate 110 is approximately elliptical, and the shape of the orthographic projection of the spacer 220 on the base substrate 110 is Rectangle; the angle between the long axis direction of the shape of the orthographic projection of the first opening 1951 on the base substrate 110 and the extension direction of the spacer 220 on the orthographic projection of the base substrate 110 is in the range of 20-70 degrees.
  • the display substrate 100 further includes a pixel circuit layer 260; the pixel circuit layer 260 is located on the side of the anode layer 170 close to the base substrate 110, and includes a plurality of pixel driving circuits 265 A plurality of pixel driving circuits 265 and a plurality of anodes 175 are arranged correspondingly, and each anode 175 is electrically connected to the corresponding pixel driving circuit 265.
  • the first anode 1751 includes a main body portion 1751A and a connection portion 1751B connected to the main body portion 1751A, the first The orthographic projection of the opening 1951 on the base substrate 110 falls within the orthographic projection of the main body portion 1751A on the base substrate 110, and the connection portion 1751B is electrically connected to the corresponding pixel driving circuit 265.
  • the orthographic projection of the spacer 220 on the base substrate 110 and the orthographic projection of the connection portion 1751B on the base substrate 110 at least partially overlap.
  • the display substrate can avoid the contact between the edge of the opening of the fine metal mask and the tip of the spacer, and avoid the generation of foreign matter such as particles, and make full use of the space on the display substrate.
  • the connecting portion 1751B is located at the main body portion 1751A close to the third anode 1753 in the same light emitting group 1850 and the fourth anode 1754 in the light emitting group 1850 adjacent in the second direction. s position.
  • the area defined by the first opening 1951 is the first effective light-emitting area of the first sub-pixel
  • the area defined by the second opening 1952 is the second effective light-emitting area of the second sub-pixel
  • the area defined by the third opening 1953 It is the third effective light-emitting area of the third sub-pixel
  • the area defined by the fourth opening 1954 is the fourth effective light-emitting area of the fourth sub-pixel.
  • the first light-emitting portion is configured to emit light of a first color
  • the second light-emitting portion and the third light-emitting portion are connected and configured to emit light of the second color
  • the fourth light-emitting portion is configured to emit light of the second color.
  • the first color is red (R)
  • the second color is green (G)
  • the third color is blue (B).
  • the display substrate adopts a GGRB pixel arrangement structure.
  • FIG. 22 is a schematic cross-sectional view of a display substrate along the EE direction in FIG. 20 according to an embodiment of the present disclosure.
  • the light-emitting portion 185 (such as the first light-emitting layer 1851 and the fourth light-emitting layer 1854) formed by a fine metal mask will diffuse to form a thinner diffusion portion (such as the diffusion portion). 1851A and 1854A), resulting in that the size of the finally obtained light-emitting layer 185 is larger than the opening size of the fine metal mask, which will overlap with the spacer 220, and even the adjacent light-emitting parts will contact or overlap.
  • the above-mentioned light-emitting layer refers to a portion where the thickness of the light-emitting layer is greater than or equal to the thickness of the diffusion portion, and does not include the diffusion portion.
  • FIG. 23 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 400 includes the display substrate 100 of any one of the above.
  • the display device has beneficial effects corresponding to the beneficial effects of the display substrate.
  • the display device can prevent the opening edge 252 of the fine metal mask from contacting the top of the spacer during the manufacturing process, and avoid the generation of foreign matter such as particles, thereby improving the stability, reliability and product yield of the display substrate. .
  • the display device may be an electronic product with a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • FIG. 24 is a manufacturing method of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 24, the manufacturing method of the display substrate includes the following steps S101-S103.
  • Step S101 forming a pixel defining layer on a base substrate, including a plurality of openings.
  • the base substrate can be a quartz substrate, a glass substrate, a plastic substrate, etc.
  • the pixel defining layer can be made by a vapor deposition process, and multiple openings can be made by an etching process.
  • the embodiments of the present disclosure include but are not limited to this.
  • Step S102 forming spacers on the side of the pixel defining layer away from the base substrate.
  • the spacer and the pixel defining layer can be formed by using the same film layer through a halftone mask or a gray tone mask, so that the masking process can be saved and the cost can be reduced.
  • a layer structure for forming the pixel defining layer and spacers may be formed on the base substrate; then a halftone mask or a gray tone mask may be used to form the first photolithography on the side of the layer structure away from the base substrate.
  • the first photoresist pattern includes a completely retained portion, a partially retained portion, and a completely removed portion; the first photoresist pattern is used to etch the layer structure (for example, a wet etching process), and a portion of the corresponding layer will be completely removed
  • the structure is removed to form a plurality of openings of the pixel defining layer; then an ashing process is performed on the first photoresist pattern to remove part of the remaining part to form a second photoresist pattern; the layer structure is processed using the second photoresist pattern It is further etched to form spacers where a part of the corresponding layer structure is completely retained, and a pixel defining layer is formed where a part of the corresponding layer structure is partially retained.
  • the embodiments of the present disclosure include but are not limited thereto, and the spacer can also be formed separately.
  • Step S103 Place a mask on the side of the spacer away from the base substrate, and use the mask as a mask to evaporate light-emitting materials in a plurality of openings to form a light-emitting layer including a plurality of light-emitting parts, and the mask plate It includes a plurality of mask openings, and the orthographic projection of the top end of the spacer away from the base substrate on the base substrate is spaced from the edge of the orthographic projection of the mask opening on the base substrate.
  • a mask is placed on the side of the spacer away from the base substrate, and the luminescent material is evaporated in a plurality of openings using the mask as a mask to form
  • the orthographic projection of the opening edge of the mask on the base substrate and the orthographic projection of the top of the spacer on the base substrate are spaced apart; thereby avoiding the opening edge of the mask and the The tip of the septum should be in contact with it, and foreign objects such as particles should be avoided.
  • the manufacturing method of the display substrate can improve the stability, reliability and product yield of the display substrate.
  • the aforementioned mask is a fine metal mask (FMM).
  • the shape of the orthographic projection of the spacer on the base substrate is a rectangle, the orthographic projection of the central axis of the spacer in the length direction on the base substrate and the orthographic projection of the light-emitting part on the base substrate The edge interval setting. Therefore, the manufacturing method of the display substrate can prevent the opening edge of the fine metal mask from contacting the tip of the spacer, and avoid the generation of foreign matter such as particles, thereby improving the stability, reliability and product yield of the display substrate.
  • the orthographic projection of the spacer on the base substrate is spaced apart from the edge of the orthographic projection of the light-emitting portion on the base substrate.
  • the display substrate can further prevent the opening edge of the fine metal mask from contacting the tip of the spacer, and avoid the generation of foreign matter such as particles, thereby further improving the stability, reliability and product yield of the display substrate .
  • the mask set includes a first mask 510, a second mask 520, and a third mask 530; the first mask 510 includes a plurality of first mask openings 412.
  • Each first mask opening 412 is used to form the above-mentioned first light-emitting portion 1851;
  • the second mask plate 520 includes a plurality of second mask openings 422, and each of the second mask openings 422 is used to form the above-mentioned second The light-emitting portion 1852 and the third light-emitting portion 1853, that is, the second light-emitting portion 1852 and the third light-emitting portion 1853 can be formed through the same mask opening;
  • the third mask plate 530 includes a plurality of third mask openings 432, each The third mask opening 432 is used to form the fourth light-emitting portion 1854 described above.
  • the above-mentioned step S103 may include: as shown in FIG. 25, placing a first mask on the side of the spacer 220 away from the base substrate 110
  • the first mask 510 is used as a mask to evaporate light-emitting materials in the plurality of openings 1951 to form a plurality of first light-emitting parts 1851; the first mask 510 is removed; as shown in FIG. 26,
  • a second mask 520 is placed on the side of the spacer 220 away from the base substrate 110, and the second mask 520 is used as a mask to evaporate light-emitting materials in the plurality of openings 1951 and 1952 to form a plurality of second light-emitting devices.
  • the mask plate 530 is a mask that evaporates light-emitting materials in the plurality of openings 1954 to form a plurality of fourth light-emitting parts 1854.
  • the orthographic projection of the top end of the spacer 220 away from the base substrate 110 on the base substrate 110 is similar to that of the first light-emitting portion 1851 or the fourth light-emitting portion 1854 on the base substrate 110.
  • the edge interval setting of the orthographic projection is similar to that of the first light-emitting portion 1851 or the fourth light-emitting portion 1854 on the base substrate 110.
  • the load of the gate layer affects the charging time of the pixel driving circuit, and the The charging time has a greater influence on the display effect.
  • the load of the gate layer is mainly composed of the load of the gate line and the reset signal line.
  • the load of the data line (or the source line) is directly related to the power consumption of the IC. The greater the load of the data line, the higher the requirement for IC driving, and the greater the power consumption of the IC. Therefore, controlling the load between the gate line and the reset signal line and the load on the data line can improve the display effect of the organic light emitting diode display device, and can reduce the power consumption of the organic light emitting diode display device.
  • inventions of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, a first gate layer, a second gate layer, and a first conductive layer; the first gate layer is located on the base substrate, and the second gate layer is located on the first gate layer away from the substrate One side of the substrate; the first conductive layer is located on the side of the second gate layer away from the base substrate; the first gate layer includes a reset signal line extending along the first direction and a first electrode block, and the second gate layer includes The second electrode block, the second electrode block is configured to form a storage capacitor with the first electrode block, the first conductive layer includes a power line extending in a second direction, the reset signal line and the power line have a first overlapping area, and the second The electrode block and the power line have a second overlapping area, the width of the power line located in the first overlapping area is smaller than the width of the power line located in the second overlapping area, and the first direction intersects the second direction.
  • the display substrate can reduce the load of the reset signal line, thereby increasing the charging time of the pixel driving circuit, thereby increasing The display effect of the display substrate.
  • An embodiment of the present disclosure provides a display substrate.
  • 28A is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure
  • FIG. 28B is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure
  • FIG. 29 is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure
  • the anode layer and the second conductive layer are omitted in FIG. 28B.
  • the display substrate 100 includes a base substrate 110, a first gate layer 130, a second gate layer 140, and a first conductive layer 150; the first gate layer 130 is located on the liner On the base substrate 110, the second gate layer 140 is located on the side of the first gate layer 130 away from the base substrate 110; the first conductive layer 150 is located on the side of the second gate layer 140 away from the base substrate 110.
  • the first gate layer 130 includes a reset signal line 131 extending in the first direction and a first electrode block CE1; the second gate layer 140 includes a second electrode block CE2, and the second electrode block CE2 is configured to be the same as the first electrode block CE1.
  • the CE1 forms a storage capacitor;
  • the first conductive layer 150 includes a power line 151 extending in the second direction, the reset signal line 131 and the power line 151 have a first overlap area 351, and the second electrode block CE2 and the power line 151 have a second overlap In the overlapping area 352, the width of the power line 151 located in the first overlapping area 351 is smaller than the width of the power line 151 located in the second overlapping area 352. That is, the width of the power line 151 in the first overlapping area 351 is designed to be reduced; the first direction and the second direction intersect, for example, are perpendicular to each other. It should be noted that the above-mentioned width of the power line refers to the size of the power line in the first direction, and correspondingly, the length of the power line is the size of the power line in the second direction.
  • reducing the width of the power line in the first overlapping area where the reset signal line and the power line overlap can reduce the overlap area of the reset signal line and the power line, thereby reducing The size of the parasitic capacitance between the reset signal line and the power line.
  • the display substrate can reduce the load of the reset signal line, thereby increasing the charging time of the pixel driving circuit, thereby increasing The display effect of the display substrate.
  • the first conductive layer may be a first source/drain metal layer
  • the display substrate may further include a second conductive layer, that is, a second source/drain metal layer.
  • the display substrate shown in FIG. 28A does not show the second conductive layer (second source and drain metal layer); of course, the embodiments of the present disclosure include but not Limited to this, the display substrate may not include the second conductive layer, and may be a display substrate with a single-layer source/drain metal layer.
  • the width of the power line 151 located in the first overlapping area 351 is smaller than the average width of the power line 151.
  • the width of the power line 151 in the first overlap area 351 is less than 5/7 of the maximum width of the power line 151. Therefore, the display substrate can effectively reduce the load of the reset signal line.
  • the power cord 151 includes a main body extension 151A and a narrowed portion 151B.
  • the width of the narrowed portion 151B is smaller than the width of the main body extension 151A.
  • the orthographic projection overlaps with the orthographic projection of the reset signal line 131 on the base substrate 110.
  • the first gate layer 130 further includes a gate line 132 extending in the first direction.
  • the gate line 132 and the power supply line 151 have a third overlapping area 353,
  • the width of the power line 151 in the overlap area 353 is smaller than the width of the power line 151 in the second overlap area 352.
  • the width of the power line in the third overlapping area is also designed to be reduced.
  • the width of the power line 151 in the third overlapping area 353 is smaller than the average width of the power line 151.
  • the width of the power line 151 in the third overlapping area 353 is less than 5/7 of the maximum width of the power line 151. Therefore, the display substrate can effectively reduce the load of the reset signal line.
  • the power cord 151 includes a main body extension portion 151A and a narrowed portion 151B.
  • the width of the narrowed portion 151B is smaller than the width of the main body extension portion 151A.
  • the orthographic projection overlaps with the orthographic projection of the grid line 132 on the base substrate 110.
  • the first conductive layer 150 further includes a data line 152 extending in the second direction.
  • the data line 152 and the reset signal line 131 have a fourth overlapping area 354,
  • the width of the reset signal line 131 of the overlap area 354 is smaller than the average width of the reset signal line 131.
  • reducing the width of the reset signal line in the fourth overlap area can reduce the overlap area of the reset signal line and the data line, thereby reducing the size of the parasitic capacitance between the reset signal line and the data line.
  • the display substrate can reduce the load of the data line, thereby reducing driving power consumption, and thereby reducing the power consumption of the display substrate.
  • the width of the reset signal line mentioned above refers to the size of the reset signal line in the second direction, and correspondingly, the length of the reset signal line is the size of the reset signal line in the first direction.
  • the width of the reset signal line 131 in the fourth overlap area 354 is less than 3/4 of the maximum width of the reset signal line 131. Therefore, the display substrate can effectively reduce the load of the data line.
  • the display substrate 100 further includes a semiconductor layer 120 located on the side of the first gate layer 130 close to the base substrate 110, and the second gate layer 140 includes The initialization signal line 141 extending in the first direction, the data line 152 and the initialization signal line 141 have a fifth overlap area 355, and the initialization signal line 141 and the semiconductor layer 120 have a sixth overlap area 356, which is located in the fifth overlap area 355.
  • the width of the initialization signal line 141 is smaller than the width of the initialization signal line 141 located in the sixth overlapping area 356.
  • reducing the width of the initialization signal line in the fifth overlapping area can reduce the overlap area of the initialization signal line and the data line, thereby reducing the size of the parasitic capacitance between the initialization signal line and the data line. Therefore, by reducing the width of the initialization signal line in the fifth overlapping area, the display substrate can further reduce the load of the data line, thereby reducing driving power consumption, and thereby reducing the power consumption of the display substrate.
  • the above-mentioned width of the initialization signal line refers to the size of the initialization signal line in the second direction, and correspondingly, the length of the initialization signal line is the size of the initialization signal line in the first direction.
  • the width of the initialization signal line 141 located in the fourth overlapping area 354 is smaller than the average width of the initialization signal line 141.
  • the orthographic projection of the narrowing portion 151B overlapping the reset signal line 131 on the base substrate 110 also overlaps the orthographic projection of the initialization signal line 141 on the base substrate 110.
  • the power cord 151 includes a main body extension portion 151A and a narrowed portion 151B.
  • the width of the narrowed portion 151B is smaller than the width of the main body extension portion 151A.
  • the orthographic projection and the orthographic projection of the semiconductor layer 110 on the base substrate 110 do not overlap.
  • the second gate layer 140 further includes a conductive block 143
  • the main body extension 151A includes a connection portion 151C connected to the conductive block 143
  • the connection portion 151C is orthographically projected on the base substrate 110 and The orthographic projection of the semiconductor layer 110 on the base substrate 110 overlaps, and the connecting portion 151C and the narrowing portion 151B are adjacent in the second direction.
  • the connecting portion 151C may be located between the two narrowed portions 151B.
  • the width of the initialization signal line 141 in the fourth overlap area 354 is less than 3/4 of the maximum width of the initialization signal line 151. Therefore, the display substrate can effectively reduce the load of the data line.
  • the semiconductor layer 120 may use a silicon-based semiconductor material, such as polysilicon.
  • a silicon-based semiconductor material such as polysilicon.
  • the embodiments of the present disclosure include but are not limited thereto, and the semiconductor layer can also be made of semiconductor materials.
  • FIGS. 30A-30D are schematic plan views of multiple film layers in a display substrate provided by an embodiment of the present disclosure
  • FIG. 31 is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure.
  • the semiconductor layer 120 includes a first cell 121, a second cell 122, a third cell 123, a fourth cell 124, a fifth cell 125, a sixth cell 126, and a seventh cell 127; 121 includes a first channel region C1, and a first source region S1 and a first drain region D1 located on both sides of the first channel region C1.
  • the second cell 122 includes a second channel region C2 and a second channel region C2.
  • the second source region S2 and the second drain region D2 on both sides of the region C2.
  • the third cell 123 includes a third channel region C3 and a third source region S3 and a third source region S3 and a third channel region C3 on both sides of the third channel region C3.
  • the drain region D3, the fourth cell 124 includes a fourth channel region C4, and a fourth source region S4 and a fourth drain region D4 located on both sides of the fourth channel region C4, and the fifth cell 125 includes a fifth channel Area C5 and the fifth source area S5 and the fifth drain area S5 located on both sides of the fifth channel area C5.
  • the sixth cell 126 includes the sixth channel area C6 and the second area located on both sides of the sixth channel area C6.
  • the seventh unit 127 includes a seventh channel region C7 and a seventh source region S7 and a seventh drain region D7 located on both sides of the seventh channel region C7.
  • the sixth drain region D6 is connected to the third drain region D3, and the third source region S3, the first drain region D1, and the fifth source region S5 are connected to the first The node N1, the first source region S1, the second drain region D2, and the fourth drain region D4 are connected to the second node N2, and the fifth drain region D5 and the seventh drain region D7 are connected.
  • the first gate layer 130 includes a reset signal line 131 extending in a first direction, a gate line 132 extending in the first direction, a first electrode block CE1, and an emission control line extending in the first direction. Line 133.
  • the second gate layer 140 includes an initialization signal line 141, a second electrode block CE2, and a conductive block 143 extending in the first direction.
  • the conductive block 143 may be connected to the power line, thereby reducing the resistance of the power line.
  • the sixth source region S6 and the seventh source region S7 are connected to the initialization signal line 141; the first electrode block CE1 and the second electrode block CE2 can form a storage capacitor Cst.
  • the first conductive layer 150 includes a power line 151 and a data line 152 extending in the second direction, a first connection block 1541, a second connection block 1542, and a third connection block 1543.
  • the first connection block 1541 is used to connect the initialization signal line 141 to the sixth source region S6 and the seventh source region S7;
  • the second connection block 1542 is used to connect the third drain region D3 to the first electrode block CE1;
  • the third connecting block 1543 is connected to the fifth drain region D5, and can be used as a drain to connect to a corresponding anode.
  • the second source region S2 is connected to the data line 152; the fourth source region S4 is connected to the power line 151.
  • the first cell 121, the second cell 122, the third cell 123, the fourth cell 124, the fifth cell 125, the sixth cell 126, and the seventh cell 127 of the semiconductor layer 120 can be connected to the reset signal line 131 and
  • the gate line 132 forms a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, and a seventh thin film transistor T7.
  • a working mode of the pixel driving circuit shown in FIG. 31 will be schematically described below.
  • a reset signal is transmitted to the reset signal line 131 and the seventh thin film transistor T7 is turned on, the residual current flowing through the anode of each sub-pixel is discharged to the sixth thin film transistor T6 through the seventh thin film transistor T7, thereby suppressing the Light emission caused by the residual current flowing through the anode of each sub-pixel.
  • the sixth thin film transistor T6 is turned on, and through the sixth thin film transistor T6 to the first gate of the first thin film transistor T1 and the storage
  • the first electrode block CE1 of the capacitor Cst is applied with the initialization voltage Vint, so that the first gate and the storage capacitor Cst are initialized. Initialization of the first gate can turn on the first thin film transistor T1.
  • both the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the second thin film transistor T2 and the third thin film transistor T3 are connected to the second thin film transistor T2 and the third thin film transistor T3.
  • a data voltage Vd is applied to a gate.
  • the voltage applied to the first gate is the compensation voltage Vd+Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.
  • the power line 151 applies the driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies the compensation voltage Vd+Vth to the first electrode block CE1 so as to be lower than the voltage applied to the two electrodes of the storage capacitor Cst.
  • the charge corresponding to the difference is stored in the storage capacitor Cst, and the first thin film transistor T1 is turned on for a predetermined time.
  • both the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, so that the fourth thin film transistor T4 applies the driving voltage Vel to the fifth thin film transistor T5.
  • the driving voltage Vel passes through the first thin film transistor T1 which is turned on by the storage capacitor Cst, the corresponding driving voltage Vel and the voltage applied to the first gate through the storage capacitor Cst is the difference between the driving current Id and flows through the first thin film transistor In the first drain region D3 of T1, the driving current Id is applied to each sub-pixel through the fifth thin film transistor T5, so that the light-emitting layer of each sub-pixel emits light.
  • the display substrate 100 further includes a first flat layer 241, a second conductive layer 160, a second flat layer 242, and an anode 175; the first flat layer 241 is located in the first conductive layer.
  • the layer 150 is on the side away from the base substrate 110; the second conductive layer 160 is located on the side of the first flat layer 241 away from the first conductive layer 150, and includes the connecting electrode 161; the second flat layer 242 is located on the second conductive layer 160 away from One side of the first flat layer 241; the anode 175 is located on the side of the second flat layer 242 away from the second conductive layer 160, the first flat layer 241 includes a first via H1, and the connecting electrode 161 passes through the first via H1 and the first The five drain regions S5 are connected, the second flat layer 242 includes a second via hole H2, and the anode 175 is connected to the connection electrode 161 through the second via hole H2.
  • FIG. 32 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 400 includes the display substrate 100 of any one of the above.
  • the display device has beneficial effects corresponding to the beneficial effects of the display substrate.
  • the display device can reduce the load of the gate layer, thereby increasing the charging time of the pixel driving circuit, thereby improving the display effect of the display substrate.
  • the display device may be an electronic product with a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • the long-term light-emitting stability of organic light-emitting diode (OLED) display devices is also an important specification or index of organic light-emitting diode display devices.
  • the inventor of the present application noticed that there are many factors that affect the long-term luminescence stability of the organic light-emitting diode display device.
  • the working state of the thin film transistor in the pixel drive circuit has an effect on the luminescence brightness.
  • long-term luminescence stability have a certain degree of influence.
  • inventions of the present disclosure provide a display substrate and a display device.
  • the display substrate includes a base substrate, a pixel circuit layer and an anode layer; the pixel circuit layer is located on the base substrate and includes a plurality of pixel driving circuits; the anode layer is located on a side of the pixel circuit layer away from the base substrate and includes a plurality of anodes.
  • a plurality of pixel driving circuits are arranged in a one-to-one correspondence with a plurality of anodes, and each pixel driving circuit includes a functional thin film transistor; the plurality of pixel driving circuits include a first pixel driving circuit and a second pixel driving circuit arranged adjacently, and the first pixel driving circuit
  • the orthographic projection of the channel region of the functional thin film transistor in the second pixel drive circuit and the channel region of the functional thin film transistor in the second pixel drive circuit on the base substrate is the orthographic projection of the anode corresponding to the first pixel drive circuit on the base substrate overlap.
  • the display substrate simultaneously shields the channel region of the functional thin film transistor in the first pixel drive circuit and the channel region of the functional thin film transistor in the second pixel drive circuit through the anode, thereby improving the stability of the functional thin film transistor. Performance and life, thereby improving the long-term luminescence stability and life of the display substrate.
  • FIG. 33 is a partial schematic diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 34 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure along the KK direction in FIG. 33
  • FIG. 35A is an embodiment of the present disclosure
  • a cross-sectional schematic view of a display substrate along the MM direction in FIG. 33 is provided
  • FIG. 35B is a schematic cross-sectional view of a display substrate along the NN direction in FIG. 33 provided by an embodiment of the present disclosure
  • the display substrate 100 includes a base substrate 110, a pixel circuit layer 260, and an anode layer 170; the pixel circuit layer 260 is located on the base substrate 110 and includes a plurality of pixel driving circuits 265; the anode layer 170 It is located on a side of the pixel circuit layer 260 away from the base substrate 110 and includes a plurality of anodes 175.
  • a plurality of pixel driving circuits 265 and a plurality of anodes 175 are arranged in a one-to-one correspondence, and each pixel driving circuit 256 includes a functional thin film transistor, such as a compensation thin film transistor T3; the plurality of pixel driving circuits 265 include adjacently arranged first pixel driving circuits 2657 and The second pixel drive circuit 2658, the channel region of the compensation thin film transistor T3 in the first pixel drive circuit 2657 and the channel region of the compensation thin film transistor T3 in the second pixel drive circuit 2658 have the same orthographic projections on the base substrate 110.
  • the orthographic projection of the anode 175 corresponding to the first pixel driving circuit 2657 on the base substrate 110 overlaps.
  • first and second in the above-mentioned first pixel drive circuit and the second pixel drive circuit are only used to distinguish the two pixel drive circuits in text. These two pixel drive circuits
  • the specific structure is the same; in addition, the above-mentioned functional thin film transistor may also be other thin film transistors in the pixel driving circuit.
  • the channel region of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658 are on the base substrate 110
  • the orthographic projection on the above overlaps with the orthographic projection of the anode 175 corresponding to the first pixel driving circuit 2657 on the base substrate 110, and the anode 175 corresponding to the first pixel driving circuit 2657 can compensate for the first pixel driving circuit 2657.
  • the channel region of the thin film transistor T3 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658 are partially shielded or completely shielded.
  • the display substrate can improve the stability and life of the compensating thin film transistor T3 in the first pixel driving circuit and the compensating thin film transistor T3 in the second pixel driving circuit 2658, thereby improving the long-term light-emitting stability and durability of the display substrate. life.
  • 30A-30D are schematic plan views of multiple film layers in a display substrate provided by an embodiment of the present disclosure
  • FIG. 31 is an equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure.
  • the pixel drive circuit adopts a 7T1C pixel drive structure.
  • the voltage of the N3 node can control the on-off state of the first thin film transistor T1 (that is, the driving thin film transistor), and the stability of the first thin film transistor T1 directly affects The long-term luminescence stability of the organic light emitting diode display device; in the charging phase, the charging voltage of the N3 node is related to the states of the third thin film transistor T3 (ie, the compensation thin film transistor), the first thin film transistor T1 and the second thin film transistor T2.
  • the third thin film transistor T3 ie, the compensation thin film transistor
  • thin film transistors are particularly sensitive to light. When the thin film transistor (especially the channel region) is exposed to light, the characteristics of the thin film transistor are likely to drift, which affects the normal operation of the pixel driving circuit.
  • the channel region of the compensation thin film transistor is shielded by the anode, which can improve the stability and life of the compensation thin film transistor, thereby improving the long-term light-emitting stability
  • the channel region of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658 both fall into
  • the anode 175 corresponding to the first pixel driving circuit 2657 ie, the fourth anode 1754
  • the anode 175 corresponding to the first pixel driving circuit 2657 can be used to compensate the compensation film in the first pixel driving circuit 2657.
  • the channel region of the transistor T3 and the channel region of the compensation thin film transistor T3 in the second pixel driving circuit 2658 are completely shielded, thereby further improving the stability and lifespan of the compensation thin film transistor, thereby improving the long-term light-emitting stability of the display substrate And longevity.
  • the compensation thin film transistor T3 may be a thin film transistor with a double gate structure, so that the reliability of the compensation thin film transistor may be improved.
  • the channel region of the compensating thin film transistor T3 includes a first channel region C1 and a second channel region C2 arranged at intervals, and the compensating thin film transistor T3 also includes a common channel region between the first channel region C1 and the second channel region C2.
  • Electrode SE As shown in FIGS. 33-35B, the common electrode SE of the compensation thin film transistor T3 in the first pixel driving circuit 2657 and the common electrode SE of the compensation thin film transistor T3 in the second pixel driving circuit 2658 are positive on the base substrate 110.
  • the projections overlap with the orthographic projection of the anode 175 corresponding to the first pixel driving circuit 2657 on the base substrate 110.
  • the anode 175 corresponding to the first pixel driving circuit 2657 can perform the common electrode SE of the compensating thin film transistor T3 in the first pixel driving circuit 2657 and the common electrode SE of the compensating thin film transistor T3 in the second pixel driving circuit 2658. Partially shielded or completely shielded, thereby further improving the stability and life of the compensation thin film transistor, and further improving the long-term light-emitting stability and life of the display substrate.
  • FIG. 36 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure.
  • the plurality of anodes 175 includes a plurality of anode groups 1750, and each anode group 1750 includes a first anode 1751, a second anode 1752, a third anode 1753, and a fourth anode 1754.
  • first anode, second anode, third anode, and fourth anode may be anodes of different shapes and different colors of sub-pixels.
  • first anode, second anode, third anode, and fourth anode may be anodes of sub-pixels of the same shape and the same color.
  • the plurality of anodes 175 includes a plurality of anode groups 1750, which are arranged in a first direction to form a plurality of anode group columns 380, and are arranged in a second direction to form a plurality of anode groups 1750.
  • Anode group rows 390, each anode group 1750 includes a first anode 1751, a second anode 1752, a third anode 1753, and a fourth anode 1754; two adjacent anode group rows 390 are arranged in a staggered 1/2 pitch , The pitch is equal to the distance between the centers of the two first anodes 1751 in the two anode groups 1750 adjacent in the first direction.
  • the second anode 1752 and the third anode 1753 are arranged in the second direction to form an anode pair 1755, and the first anode 1751, the anode pair 1755, and the fourth anode 1754 are arranged in the second direction. Therefore, the display substrate can provide a pixel arrangement structure, thereby improving the display effect of a display device using the display substrate.
  • the anode group provided by the embodiment of the present disclosure includes but is not limited to the pixel arrangement structure described above; in addition, the center of the first anode mentioned above refers to the center of the main body of the first anode, that is, the center of the first anode corresponds to The effective light-emitting area of the first light-emitting element.
  • first direction and the second direction are substantially perpendicular. It should be noted that the above-mentioned first direction and second direction are substantially perpendicular, including the case where the angle between the first direction and the second direction is 90 degrees, and also includes the angle range between the first direction and the second direction. In the case of 85-95 degrees.
  • the first pixel driving circuit 2657 and the second pixel driving circuit 2658 are arranged along the first direction, and the fourth anode 1754 in one anode group 1750 corresponds to the first pixel driving circuit 2657.
  • the second anode 1752 in the other anode group 1750 and the second pixel driving circuit 2658 are correspondingly arranged and electrically connected.
  • the display substrate 100 further includes a pixel defining layer 190; the pixel defining layer 190 is located on a side of the anode layer 170 away from the base substrate 110 and includes a plurality of openings 195
  • the plurality of openings 195 includes a plurality of opening groups 1950, each opening group 1950 includes a first opening 1951, a second opening 1952, a third opening 1953 and a fourth opening 1954, the first opening 1951 and the first anode 1751
  • the first anode 1751 is arranged and exposed correspondingly, the second opening 1952 and the second anode 1752 are arranged correspondingly and the second anode 1752 is arranged correspondingly, the third opening 1953 and the third anode 1753 are arranged correspondingly and the third anode 1753 is exposed, and the fourth opening 1954 is arranged with The fourth anode 1754 is correspondingly arranged and exposed.
  • the first anode 1751 includes a first body portion 1751A and a first connection portion 1751B.
  • the orthographic projection of the first opening 1951 on the base substrate 110 falls into the first body portion 1751A on the base substrate.
  • Orthographic projection on 110, the first connecting portion 1751B is connected to the pixel driving circuit 265 corresponding to the first anode 1751;
  • the second anode 1752 includes a second body portion 1752A and a second connecting portion 1752B, and the second opening 1952 is in the base substrate 110
  • the orthographic projection on the upper part falls into the orthographic projection of the second main body portion 1752A on the base substrate 110, and the second connecting portion 1752B is connected to the pixel driving circuit 265 corresponding to the second anode 1752;
  • the third anode 1753 includes the third main body portion 1753A and The third connecting portion 1753B, the orthographic projection of the third opening 1953 on the base substrate 110 falls into the orthographic projection of the third body portion 1753A on the base substrate 110, the third connecting portion 1753B and the third anode 1753 corresponding to the pixel drive
  • the circuit 265 is connected;
  • the fourth anode 1754 includes a fourth body portion 1754A and a fourth connection portion 1754B, and
  • the shape of the first body portion 1751A is substantially the same as the shape of the first opening 1951; the shape of the second body portion 1752A is substantially the same as the shape of the second opening 1952; and the third The shape of the main body portion 1753A is substantially the same as the shape of the third opening 1953; the shape of the fourth main body portion 1754A is substantially the same as the shape of the fourth opening 1954.
  • the shape of the fourth opening 1954 is a hexagon
  • the shape of the fourth body portion 1754A is also a hexagon.
  • the shapes of the fourth opening and the fourth main body are not limited to hexagons, and may also be other shapes such as ellipse.
  • the fourth anode 1754 further includes a first supplementary portion 1754C, and the fourth anode 1754 corresponds to the first channel region C31 and the second channel region C31 of the compensation thin film transistor T3 in the first pixel driving circuit 2657.
  • the orthographic projections of the two channel regions C32 on the base substrate 110 overlap with the orthographic projections of the first supplementary portion 1754C on the base substrate 110 respectively.
  • the fourth anode can cover the two channel regions of the compensation thin film transistor in the corresponding pixel driving circuit, thereby improving the stability and stability of the compensation thin film transistor. Life, thereby improving the long-term light-emitting stability and life of the display substrate.
  • the first supplementary portion 1754C protrudes from the fourth main body portion 1754A to the third anode 1753, and the first supplementary portion 1754C is located at the fourth connecting portion 1754B close to the fourth main body portion 1754A On the side.
  • the first supplementary portion 1754C is connected to both the fourth main body portion 1754A and the fourth connecting portion 1754B. Therefore, the display substrate can make full use of the area on the display substrate, and the first anode, the second anode, the third anode, and the fourth anode are closely arranged, so that the resolution of the display substrate can be ensured.
  • the orthographic projection of the first supplementary portion 1754C on the base substrate 110 partially overlaps the orthographic projection of the common electrode SE of the compensation thin film transistor T3 on the base substrate 110.
  • the orthographic projection of the first supplementary portion 1754C on the base substrate 110 covers the orthographic projection of the second channel region C32 of the compensation thin film transistor T3 on the base substrate 110.
  • the orthographic projection of the fourth body portion 1754A on the base substrate 110 covers the drain region D3 of the compensation thin film transistor T3.
  • the first conductive layer 150 includes a second connection block 1542.
  • the second connection block 1542 is used to connect the drain region of the compensation thin film transistor to the first electrode block CE1, and the first electrode block CE1 can be connected to the first electrode block CE1.
  • the second electrode block CE2 forms a storage capacitor and also serves as a gate for driving the thin film transistor.
  • connection portion 1752B of the second anode 1752 extends away from the third anode 1753 and overlaps the second connection block 1542, and even covers the second connection block 1542, the connection portion 1752 can stably drive the gate of the thin film transistor. And compensate the potential on the drain electrode of the thin film transistor, thereby further improving the long-term light-emitting stability and lifespan of the display substrate.
  • FIG. 37A is a partial schematic diagram of another display substrate provided according to an embodiment of the present disclosure
  • FIG. 37B is a partial schematic diagram of another display substrate provided according to an embodiment of the present disclosure. In order to clearly show the shape of each anode, FIG. 37B shows only the anode layer.
  • the fourth anode 1754 further includes a second supplementary portion 1754D; the orthographic projection of the second channel region C2 of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 is the same as The orthographic projections of the second supplementary portion 1754D on the base substrate 110 overlap.
  • the fourth anode can partially or even completely cover the second channel region C2 of the compensation thin film transistor T3 in the second pixel driving circuit 2658, thereby improving the stability and stability of the compensation thin film transistor. Life, thereby improving the long-term light-emitting stability and life of the display substrate.
  • the second supplementary portion 1754D protrudes from the fourth main body portion 1754A to the first anode 1751 in the anode group 1750 adjacent in the first direction.
  • the orthographic projection of the first channel region C1 of the compensation thin film transistor T3 in the second pixel driving circuit 2658 on the base substrate 110 may fall into the fourth body portion 1754A. Orthographic projection on the base substrate 110.
  • the common electrode SE of the compensation thin film transistor T3 in the first pixel driving circuit 2657 overlaps the orthographic projection of the first supplementary portion 1754C on the base substrate 110, and the second The orthographic projection of the common electrode SE of the compensating thin film transistor T3 in the pixel drive circuit 2658 on the base substrate 110 corresponds to that of the fourth body portion 1754A of the fourth anode 1754 corresponding to the first pixel drive circuit 2657 on the base substrate 110. The projections overlap.
  • the channel region of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the first anode 1751 is projected on the base substrate 110 into the first body portion 1751A. Orthographic projection on the base substrate 110.
  • the pixel driving circuit 265 further includes a driving thin film transistor T1, and the gate G1 of the driving thin film transistor T1 is connected to the drain D3 of the compensation thin film transistor T3.
  • the first anode 1751 also includes a third supplementary portion 1751C, which protrudes from the first main body portion 1751A to the third anode 1753.
  • the first anode 1751 corresponds to the gate of the driving thin film transistor T1 in the pixel driving circuit 265.
  • the orthographic projection of the electrode G1 and the drain electrode D3 of the compensating thin film transistor T3 on the base substrate 110 falls into the orthographic projection of the third supplementary portion 1751C on the base substrate 110.
  • the display substrate can stably drive the gate G1 of the thin film transistor T1 and compensate the potential on the drain D3 of the thin film transistor T3 through the third supplementary portion 1751C, thereby further improving the long-term light-emitting stability and lifetime of the display substrate.
  • the first channel region C31 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753 is projected on the base substrate 110 into the third body.
  • the third anode 1753 further includes a fourth supplementary portion 1753C, and the second channel region C32 of the compensation thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753 is
  • the orthographic projection on the base substrate 110 falls into the orthographic projection of the fourth supplementary portion 1753C on the base substrate 110.
  • the main body portion and the fourth supplementary portion of the third anode can partially block or partially shield or partially shield or partially shield the first channel region C31 and the second channel region C32 of the compensating thin film transistor T3 in the pixel driving circuit 265 corresponding to the third anode 1753. It is completely shielded, thereby improving the stability and life of the compensation thin film transistor, thereby improving the long-term light-emitting stability and life of the display substrate.
  • the pixel circuit layer 260 further includes a semiconductor layer 120, a first gate layer 130, a second gate layer 140, and a first conductive layer 150; the first gate layer 130 Located on the side of the semiconductor layer 120 away from the base substrate 110, the second gate layer 140 is located on the side of the first gate layer 130 away from the base substrate 110, and the first conductive layer 150 is located on the second gate layer 140 away from the substrate One side of the substrate 110.
  • the semiconductor layer 120 includes a plurality of pixel driving units 1200, which are arranged corresponding to the plurality of anodes 175, and each pixel driving unit 1200 includes a first unit 121, a second unit 122, a third unit 123, and a fourth unit.
  • the electrode region D1 the second cell 122 includes a second channel region C2, and a second source region S2 and a second drain region D2 located on both sides of the second channel region C2
  • the third cell 123 includes a third channel region C3 and the third source region S3 and the third drain region D3 located on both sides of the third channel region C3.
  • the fourth cell 124 includes a fourth channel region C4 and a fourth channel region C4 located on both sides of the fourth channel region C4.
  • the fifth unit 125 includes a fifth channel region C5 and a fifth source region S5 and a fifth drain region S5 located on both sides of the fifth channel region C5.
  • the cell 126 includes a sixth channel region C6 and a sixth source region S6 and a sixth drain region D6 located on both sides of the sixth channel region C6.
  • the seventh cell 127 includes a seventh channel region C7 and a seventh channel region C7. The seventh source region S7 and the seventh drain region D7 on both sides of the track region C7.
  • the sixth drain region D6 is connected to the third drain region D3, and the third source region S3, the first drain region D1, and the fifth source region S5 are connected to the first The node N1, the first source region S1, the second drain region D2, and the fourth drain region D4 are connected to the second node N2, and the fifth drain region D5 and the seventh drain region D7 are connected.
  • the first gate layer 130 includes a reset signal line 131 extending in a first direction, a gate line 132 extending in the first direction, a first electrode block CE1, and an emission control line extending in the first direction.
  • the reset signal line 131 may overlap the seventh channel region C7 and the sixth channel region C6 to form the seventh thin film transistor T7 and the sixth thin film transistor T6 with the seventh cell 127 and the sixth cell 126, and the gate line 132, respectively It overlaps the third channel region C3 and the second channel region C2 to form a third thin film transistor T3 and a second thin film transistor T2 with the third cell 123 and the second cell 122.
  • the first electrode block CE1 and the first trench The track region C1 overlaps with the first cell 121 to form the first thin film transistor T1, and the emission control line 133 overlaps the fourth channel region C4 and the fifth channel region C5 to overlap the fourth cell 124 and the fifth cell 125 forms a fourth thin film transistor T4 and a fifth thin film transistor T5.
  • the aforementioned third thin film transistor T3 is a compensation thin film transistor.
  • the reset signal line 131, the gate line 132, and the emission control line 133 all extend along the first direction, and the reset signal line 131, the gate line 132, the first electrode block CE1 and the emission control line 133 extend along the second direction.
  • the direction is arranged.
  • the second gate layer 140 includes an initialization signal line 141, a second electrode block CE2, and a conductive block 143 extending in the first direction.
  • the conductive block 143 may be connected to the power line, thereby reducing the resistance of the power line.
  • the initialization signal line 141 is connected to the seventh source region S7 and the first source region S1, and the orthographic projection of the second electrode block CE2 on the base substrate 110 is the same as the orthographic projection of the first electrode block CE1 on the base substrate 110.
  • the projections overlap at least partially to form a storage capacitor Cst.
  • the conductive block can also play a role in shielding light; in addition, the conductive block on the leftmost side of FIG. 33 only shows a part, and the shape of the conductive block on the leftmost side of FIG. 33 is the same as that of other conductive blocks.
  • the first conductive layer 150 includes a power line 151 and a data line 152 extending in the second direction, a first connection block 1541, a second connection block 1542, and a third connection block 1543.
  • the data line 152 can be connected to the second source region S2, and the fourth source region S4 is connected to the power line 151;
  • the first connection block 1541 is used to connect the initialization signal line 141 with the sixth source region S6 and the seventh source region S7 is connected;
  • the second connecting block 1542 is used to connect the third drain region D3 with the first electrode block CE1;
  • the third connecting block 1543 is connected with the fifth drain region D5, and can be used as a drain to connect to a corresponding anode.
  • a working mode of the pixel driving circuit shown in FIG. 31 will be schematically described below.
  • a reset signal is transmitted to the reset signal line 131 and the seventh thin film transistor T7 is turned on, the residual current flowing through the anode of each sub-pixel is discharged to the sixth thin film transistor T6 through the seventh thin film transistor T7, thereby suppressing the Light emission caused by the residual current flowing through the anode of each sub-pixel.
  • the sixth thin film transistor T6 is turned on, and through the sixth thin film transistor T6 to the first gate of the first thin film transistor T1 and the storage
  • the first electrode block CE1 of the capacitor Cst is applied with the initialization voltage Vint, so that the first gate and the storage capacitor Cst are initialized. Initialization of the first gate can turn on the first thin film transistor T1.
  • both the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the second thin film transistor T2 and the third thin film transistor T3 are connected to the second thin film transistor T2 and the third thin film transistor T3.
  • a data voltage Vd is applied to a gate.
  • the voltage applied to the first gate is the compensation voltage Vd+Vth, and the compensation voltage applied to the first gate is also applied to the first electrode block CE1 of the storage capacitor Cst.
  • the power line 151 applies the driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies the compensation voltage Vd+Vth to the first electrode block CE1 so as to be lower than the voltage applied to the two electrodes of the storage capacitor Cst.
  • the charge corresponding to the difference is stored in the storage capacitor Cst, and the first thin film transistor T1 is turned on for a predetermined time.
  • both the fourth thin film transistor T4 and the fifth thin film transistor T5 are turned on, so that the fourth thin film transistor T4 applies the driving voltage Vel to the fifth thin film transistor T5.
  • the driving voltage Vel passes through the first thin film transistor T1 that is turned on by the storage capacitor Cst, the corresponding driving voltage Vel and the voltage applied to the first gate through the storage capacitor Cst is the difference between the driving current Id flows through the first thin film transistor In the first drain region D3 of T1, the driving current Id is applied to each sub-pixel through the fifth thin film transistor T5, so that the light-emitting layer of each sub-pixel emits light.
  • the display substrate 100 further includes a first flat layer 241, a second conductive layer 160, a second flat layer 242, and an anode 175; the first flat layer 241 is located in the first conductive layer.
  • the layer 150 is on the side away from the base substrate 110; the second conductive layer 160 is located on the side of the first flat layer 241 away from the first conductive layer 150, and includes the connecting electrode 161; the second flat layer 242 is located on the second conductive layer 160 away from One side of the first flat layer 241; the anode 175 is located on the side of the second flat layer 242 away from the second conductive layer 160, the first flat layer 241 includes a first via H1, and the connecting electrode 161 passes through the first via H1 and the first The six drain regions S6 are connected, the second flat layer 242 includes a second via hole H2, and the anode 175 is connected to the connection electrode 161 through the second via hole H2.
  • the display substrate 100 further includes a light-emitting layer 180, which is located on the side of the anode layer 170 away from the base substrate 110, and includes a plurality of light-emitting parts 185,
  • the light-emitting part 185 includes a plurality of light-emitting groups 1850, and each light-emitting group 1850 includes a first light-emitting part 1851, a second light-emitting part 1852, a third light-emitting part 1853, and a fourth light-emitting part 1854;
  • the first light-emitting part 1851 is at least partially Located in the first opening 1951 and covering the exposed first anode 1751
  • the second light emitting portion 1852 is at least partially located in the second opening 1952 and covers the exposed second anode 1752
  • the third light emitting portion 1753 is at least partially located in the third opening 1953 and Covering the exposed third anode 1753, the fourth light-emitting portion 18
  • the first color is red (R)
  • the second color is green (G)
  • the third color is blue (B).
  • the display substrate adopts a GGRB pixel arrangement structure.
  • the overlapping area of the first conductive portion 1621 located on the side of the first anode 1751 away from the second anode 1752 and the power line 151 located in the first conductive layer 150 is smaller than that of the first anode 1751 located near the first anode 1751.
  • the overlapping area of the second conductive portion 1622 on one side of the second anode 1752 and the power line 151 in the first conductive layer 150 is smaller than that of the first anode 1751 located near the first anode 1751.
  • FIG. 38 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 400 includes the display substrate 100 of any one of the above.
  • the display device has beneficial effects corresponding to the beneficial effects of the display substrate.
  • the display device can improve the stability and life of the compensation thin film transistor, thereby improving the long-term light-emitting stability and life of the display substrate.
  • the display device may be an electronic product with a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • FIG. 39 is a schematic diagram of a display substrate provided by an embodiment of the present disclosure
  • FIG. 40 is a schematic cross-sectional view of a display substrate provided by an embodiment of the present disclosure along line TT in FIG. 39
  • FIG. 41 is provided for an embodiment of the present disclosure
  • the display substrate includes a base substrate 110, a pixel circuit layer 610, a first conductive layer 150, a first flat layer 241 and a second conductive layer 160, a second flat layer 242, and a plurality of light-emitting elements Group 310.
  • the pixel circuit layer 610 includes a plurality of pixel driving circuits 265, and the plurality of pixel driving circuits 265 includes a semiconductor layer 120; the first conductive layer 150 is located on the side of the semiconductor layer 120 away from the base substrate 110; the first flat layer 241 is located in the first conductive layer.
  • the second conductive layer 160 includes a plurality of conductive portions 162 arranged along a first direction, and the size of each conductive portion 162 in the second direction is larger than that in the first direction, the second direction intersects the first direction, and the plurality of conductive portions 162 It includes a first conductive portion 1622, the first conductive portion 1622 includes a closed ring portion 1622E, and the closed ring portion 1622E includes a hollow area 1622H.
  • each light-emitting element group 310 includes a first light-emitting element 311, the first light-emitting element 311 includes a first anode 1751, the orthographic projection of the first anode 1751 on the base substrate 110 and the closed ring portion 1622E
  • the orthographic projections of the base substrate 110 overlap;
  • the plurality of conductive portions 162 further include a second conductive portion 1621 adjacent to the first conductive portion 1622, and the orthographic projection of the second conductive portion 1621 on the base substrate 110 and the first anode
  • the orthographic projection of 1751 on the base substrate 110 overlaps.
  • the first anode 1751 can overlap the closed ring portion 1622E and the second conductive portion 1621 at the same time, so that the first anode 1751 can be kept flat and avoid occurrence Color cast caused by tilt.
  • the closed ring portion 1622E has a hollow design, the light transmittance of the display substrate can be improved, and the under-screen fingerprint recognition device can receive signals.
  • the closed ring portion 1622E and at least one conductive portion 162 adjacent in the first direction are separated from each other in the second conductive layer 160, and the closed ring portion 1622E is separated from each other in the first direction.
  • the size is at least larger than the size of a part of the first conductive portion 1622 in the first direction;
  • the plurality of pixel drive circuits 265 include a first pixel drive circuit 2651.
  • the first pixel drive circuit 2651 has a semiconductor pattern on the semiconductor layer 120, and the first conductive portion
  • the orthographic projection of 1622 on the base substrate 110 overlaps the orthographic projection of the semiconductor pattern of the first pixel driving circuit 2651 on the base substrate 110.
  • the first pixel driving circuit 2651 includes a driving transistor T1, and the first conductive layer 150 includes a first conductive layer.
  • Pattern 1542, the first conductive pattern 1542 and the gate of the driving transistor T3 have the same potential, the first conductive pattern 1542 and the gate of the driving transistor T1 together form the gate potential metal, which encloses the hollow area inside the ring portion 1622E
  • the orthographic projection of 1622H on the base substrate 110 overlaps with the orthographic projection of the gate potential metal on the base substrate.
  • the closed annular portion 1622E can ensure a higher flatness of the first anode 1751, thereby ensuring that the luminous intensity of the first anode 1751 in different directions is consistent, thereby effectively improving Color shift phenomenon; on the other hand, because the orthographic projection of the hollow area 1622H inside the closed ring portion 1622E on the base substrate 110 overlaps with the orthographic projection of the gate potential metal on the base substrate, the gate of the driving transistor can be increased The reset speed and charging speed.
  • the inner side of the closed annular portion 1622E includes a hollow area 1622H
  • the first conductive portion 1622 has a plurality of hollow areas 1622H arranged along the second direction; two adjacent hollow areas
  • the shape and size of the 1622H are roughly the same. Since the first conductive portion 1622 can correspond to a plurality of first anodes 1751, it has a plurality of hollow areas 1622H.
  • the first light-emitting element 311 includes an effective light-emitting area, and a straight line passing through the center of the effective light-emitting area of the first light-emitting element 311 and extending in the second direction is on the front of the base substrate 110.
  • the projection is located between the orthographic projections of the first conductive portion 1622 and the second conductive portion 1621 on the base substrate 110.
  • the two edges of the closed ring portion 1622E in the first direction overlap with the orthographic projections of the anodes of the multiple light emitting elements in the light emitting element group on the base substrate, respectively, and the closed ring
  • the hollow area 1622H of the portion 1622E is separated from the orthographic projection of the plurality of light-emitting elements on the base substrate 110 (that is, arranged at intervals).
  • the first conductive layer 150 further includes a conductive metal 152 configured to provide power to the pixel driving circuit 265, the first flat layer 241 includes a conductive metal via 241S, and a conductive portion 162 It is electrically connected to the conductive metal 152 through the power line via 241S; the first pixel driving circuit 2651 also includes a first light emission control transistor T4 and a storage capacitor Cst.
  • the storage capacitor includes a first electrode block CE1 and a second electrode block CE2.
  • the electrode block CE2 is located on the side of the first electrode block CE1 away from the base substrate 110, and the conductive metal 152 is electrically connected to the source of the first light-emitting control transistor T4 and the second electrode block CE2, respectively. Therefore, the display substrate can reduce the resistance of the conductive metal through the multiple conductive portions of the second conductive layer, reduce the voltage drop, and improve the uniformity of the entire display panel.
  • the orthographic projection of the closed ring portion 1622E on the base substrate 110 overlaps the orthographic projection of the first electrode block CE1 on the base substrate 110;
  • the second electrode block CE2 includes The opening 620, the orthographic projection of the opening 620 on the base substrate 110 overlaps the orthographic projection of the first electrode block CE1 on the base substrate 110, the orthographic projection and the opening of the closed ring portion 1622E on the base substrate 110
  • the orthographic projection of 620 on the base substrate 110 also overlaps. Therefore, by shielding the capacitor electrode, the capacitor can be prevented from being excessively irradiated by light, which has the effect of stabilizing the capacitor potential and fast charging and discharging speed.
  • the first pixel driving circuit 2651 further includes a data writing transistor T2, a compensation transistor T3, a reset transistor T6, an anode initialization transistor T7, and a second light emission control transistor T5.
  • the display substrate further includes: a reset signal line 131, which is respectively connected to the gate of the reset transistor T6 and the gate of the anode initialization transistor T7; and a gate line 132, which is respectively connected to the gate of the compensation transistor T3 and the gate of the data writing transistor T2
  • the light-emitting control line 133 respectively connected to the gate of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5; and the initialization signal line 141, respectively, with the source of the reset transistor T6 and the source of the anode initialization transistor T7
  • the poles are connected, and the orthographic projection of the closed ring portion 1622E on the base substrate 110 overlaps the orthographic projections of the reset signal line 131, the gate line
  • one end of the first conductive pattern 1542 is electrically connected to the gate of the driving transistor T1 through the opening 620, and the other end of the first conductive pattern 1542 is connected to the drain of the compensation transistor T3. Or the source is electrically connected.
  • the first conductive pattern 1542 has the same potential as the gate of the driving transistor T1.
  • the closed annular portion 1622E includes a first part 631 and a second part 632 arranged in a first direction, and a third part 633 and a fourth part 634 arranged in a second direction;
  • the first part 631, the third part 633, the second part 632 and the fourth part 634 are connected end to end to form a closed ring part 1622E.
  • the orthographic projection of the first part 631 and the second part 632 on the base substrate 110 is the same as the second electrode block CE2
  • the orthographic projections on the base substrate 110 overlap. As a result, the capacitance of the storage capacitor Cst can be increased.
  • the orthographic projection of the third part 633 on the base substrate 110 overlaps the orthographic projection of the second electrode block CE2 on the base substrate 110, thereby further increasing the capacitance of the storage capacitor Cst.
  • the orthographic projection of the first portion 631 on the base substrate 110 overlaps the orthographic projection of the first conductive pattern 1542 on the base substrate 110, and the first conductive pattern 1542 and the second
  • the shape of a conductive pattern 1542 is a long strip, and the extending direction of the long side of the first conductive pattern 1542 is the same as the extending direction of the long side of the first portion 631.
  • the first conductive layer 150 further includes a second conductive pattern 1541, and the second conductive pattern 1541 is respectively connected to the initialization signal line 141 and the source of the reset transistor T6; the third portion 633
  • the orthographic projection on the base substrate 110 overlaps with the orthographic projection of the initialization signal line 141 on the base substrate 110.
  • the orthographic projection of the third portion 633 on the base substrate 110 is the same as the second conductive pattern 1541 on the base substrate 110.
  • the orthographic projection of the fourth portion 634 overlaps the orthographic projection of the fourth portion 634 on the base substrate 110 and the orthographic projection of the first conductive pattern 1542 on the base substrate 110 overlaps.
  • the orthographic projection of the hollow area 1622H on the base substrate 110 overlaps with the orthographic projection of the initialization signal line 141 on the base substrate 110, and the hollow area 1622H is on the base substrate 110.
  • the orthographic projection on the base substrate 110 overlaps with the orthographic projection of the second conductive pattern 1541 on the base substrate 110, and the orthographic projection of the hollow area 1622H on the base substrate 110 intersects with the orthographic projection of the second electrode block CE2 on the base substrate 110. Stacked.
  • the display substrate further includes: a second flat layer 242 located on the side of the second conductive layer 160 away from the base substrate 110; and a plurality of light emitting element groups 310 located on the first The side of the two flat layers 242 away from the second conductive layer 160.
  • the multiple light-emitting element groups 310 are arranged along the first direction to form multiple light-emitting element columns 320, and are arranged along the second direction to form multiple light-emitting element rows 330.
  • Each light-emitting element group 310 includes a first light-emitting element 311 and a second light-emitting element 311.
  • the light-emitting element 312, a third light-emitting element 313 and a fourth light-emitting element 314, the second light-emitting element 312 and the third light-emitting element 313 are arranged in the second direction to form a light-emitting element pair 315, a first light-emitting element 311, a light-emitting element pair 315 And the fourth light-emitting element 314 are arranged along the first direction, the first light-emitting element 311 includes a first anode 1751, the second light-emitting element 312 includes a second anode 1752, the third light-emitting element 313 includes a third anode 1753, and the fourth light-emitting element 314 Including the fourth anode 1754, the second conductive layer 160 includes the first connecting electrode 1611, the second connecting electrode 1612, the third connecting electrode 1613 and the fourth connecting electrode 1614, the second flat layer 242 includes the first via 2421, the second Via 2422, third via 24
  • the first anode 1751 includes a main body, and the orthographic projection of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 is located inside the orthographic projection of the main body of the first anode 1751 on the base substrate 110, and The main body of the first anode 1751 and the first anode 1751 have at least part of the same boundary;
  • the second anode 1752 includes a main body, and the effective light-emitting area of the second light-emitting element 312 is located on the base substrate 110 by the orthographic projection of the second anode 1752.
  • the main body is inside the orthographic projection of the base substrate 110, and the main body of the second anode 1752 and the second anode 1752 have at least partially the same boundary;
  • the third anode 1753 includes the main body, and the effective light-emitting area of the third light-emitting element 311
  • the orthographic projection on the base substrate 110 is located inside the main body of the third anode 1753 in the orthographic projection of the base substrate 110, and the main body of the third anode 1753 and the third anode 1753 have at least partially the same boundary;
  • the fourth anode 1754 includes a main body, the effective light-emitting area of the fourth light-emitting element 314 in the orthographic projection of the base substrate 110 is located inside the main body of the fourth anode 1754 in the orthographic projection of the base substrate 110, and the main body of the fourth anode 1754 and The fourth anode 1754 has at least partially the same boundary.
  • the plurality of conductive portions 162 includes a second conductive portion 1621, and the first conductive portion 1621 and the second conductive portion 1622 are respectively located on both sides of the effective light-emitting area of the first light-emitting element 311 in the first direction, and a closed loop
  • the distance between the orthographic projection of the portion 1622E on the base substrate 110 and the orthographic projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 and the orthographic projection of the second conductive portion 1621 on the base substrate 110 The distance of the orthographic projection of the center of the effective light-emitting area of the first light-emitting element 311 on the base substrate 110 is approximately the same. Therefore, the closed annular portion 1622E can ensure the first anode 1751 to ensure high flatness, thereby ensuring that the first anode 1751 has the same luminous intensity in different directions, thereby effectively improving the color shift.
  • the orthographic projection of the first anode 1751 on the base substrate 110 overlaps with the orthographic projection of the light emission control line 133 of the first pixel driving circuit 2651 on the base substrate 110.
  • the connecting electrode of the first anode located in the second conductive layer can be moved downward, so that the center of the third conductive pattern in the first conductive layer overlaps the light-emitting control line. The flatness of the third conductive pattern is ensured, and the effectiveness of via connection is improved.
  • a fourth light-emitting element 314 is provided at a position adjacent to the center of the hollow area 1622H in the second direction, and the fourth light-emitting element 314 (for example, the fourth light-emitting element 314
  • the orthographic projection of the fourth anode 1754) on the base substrate 110 overlaps the orthographic projections of the gate line 132, the reset signal line 131, and the initialization signal line 141 on the base substrate 110.
  • the first conductive layer 151 further includes a third conductive pattern 1543
  • the second conductive layer 160 further includes an anode connecting portion 161, that is, the above-mentioned connecting electrode.
  • the drain of the second light emission control transistor T5 is connected to the anode connection part 161.
  • the orthographic projection of the gate line 132 on the base substrate 110 overlaps the orthographic projection of the first conductive pattern 1542 on the base substrate 110.
  • the orthographic projection of the first electrode block CE1 and the second electrode block CE2 on the base substrate 110 is located on the orthographic projection of the gate line 132 on the base substrate 110 and the light emission control line 133 is between the orthographic projections on the base substrate 110, that is, the orthographic projection of the storage capacitor Cst on the base substrate 110 and the orthographic projection of the gate line 132 on the base substrate 110 and the light emission control line 133 on the base substrate Between the orthographic projections on the 110, the space can be used rationally.
  • the orthographic projection of the reset signal line 131 on the base substrate 110 is located on the orthographic projection of the gate line 132 on the base substrate 110 and the initialization signal line 141 is on the base substrate 110.
  • the light-emitting control line 133, the first electrode block CE1, the gate line 132, the reset signal line 131 and the initialization signal line 141 are arranged along the second direction, which can be used reasonably Show the space on the substrate.
  • the plurality of pixel driving circuits 265 include a second gate layer 140, the second electrode block CE2 is located on the second gate layer 140, and at least two second electrode blocks CE2 are located on the second gate layer 140. Connected in one direction.
  • the at least two second electrode blocks CE2 located on the second gate layer 140 can be electrically connected to each other, so that the uniformity of the storage capacitors of different sub-pixels in the entire display panel can also be improved.
  • the orthographic projection of the effective light-emitting area of the first light-emitting element 312 and the effective light-emitting area of the second light-emitting element 313 on the base substrate 110 and the conductive portion 162 on the base substrate 110 do not overlap. Therefore, it is possible to prevent the conductive portion from adversely affecting the flatness of the first light-emitting element 311 and the second light-emitting element 312.
  • the second light emitting element 313 is configured to emit green light.
  • the orthographic projection of the center of the effective light-emitting area of the fourth light-emitting element 314 on the base substrate 110 overlaps with the orthographic projection of the conductive portion 162 on the base substrate 110.
  • the portion where the conductive portion 162 and the center of the effective light-emitting area of the fourth light-emitting element 314 overlap in the orthographic projection of the base substrate 110 is a solid portion.
  • the overlap of the orthographic projections can prevent the conductive portion from adversely affecting the flatness of the fourth light-emitting element 314.
  • the fourth light emitting element 314 is configured to emit blue light. It should be noted that the above-mentioned "solid part” means that the part does not include hollows.
  • the second light-emitting element 312 includes a second anode 1752
  • the third light-emitting element 313 includes a third anode 1753
  • the main body of the second anode 1752 and the second anode 1752 are in the first
  • the overlapping areas of two adjacent conductive portions 162 in the direction are approximately the same, and the overlapping areas of the main body portion of the third anode 1753 and the two adjacent conductive portions 162 of the second anode 1753 in the first direction are approximately the same.
  • the flatness of the second anode and the third anode can be further improved.
  • the orthographic projection of the hollow area 1622H on the base substrate 110 is located between the effective light-emitting area of the first light-emitting element 311 and the effective light-emitting area of the second light-emitting element 312.
  • the hollow area can avoid the effective light-emitting area, and prevent the anode in the effective light-emitting area from sinking, causing color shift.
  • first light-emitting element and second light-emitting element are the first light-emitting element and the second light-emitting element that are closest in the first direction.
  • the size of the middle portion of the anode (for example, the first anode) of the light emitting element configured to emit red light in the second direction in the first direction is larger than that of the anode in the second direction.
  • the shape of the anode may be approximately a long hexagon;
  • the size of the middle portion in the first direction is larger than the size of the edge portion of the anode in the second direction in the first direction. Therefore, the display substrate can make full use of the space between different anodes, and maximize the area of the anode configured to emit red light and the area of the light emitting element configured to emit blue under the same process accuracy.
  • the orthographic projection of the anode 175 of at least two light-emitting elements on the base substrate 110 and the opening of the second electrode block CE2 are on the base substrate 110.
  • the orthographic projections overlap, therefore, by shielding the opening of the second electrode block, and then shielding the grid of the driving tube, the grid of the driving tube can be prevented from being excessively illuminated by light.
  • the orthographic projection of the effective light-emitting area of the at least one light-emitting element 311, 312, 313, or 314 on the base substrate 110 does not overlap with the orthographic projection of the first electrode block CE1 or the second electrode block CE2 on the base substrate 110, so that It can prevent the capacitor from raising the effective light-emitting area and avoid color shift.
  • the first flat layer 241 has an anode hole, and the anode of the light-emitting element It is connected to the pixel drive circuit corresponding to the light-emitting element through the anode hole.
  • the anode hole (for example, the first via 2421) of the anode (for example, the first anode 1751) of the light emitting element that emits red light is positioned on the base substrate 110.
  • the projection and the orthographic projection of the main body of the anode on the base substrate do not overlap in the second direction, the orthographic projection of the anode hole of the anode on the base substrate 110 and the effective light emission of the light-emitting element configured to emit red light
  • the orthographic projection of the regions on the base substrate 110 does not overlap in the second direction, so that the anode hole configured as the anode of the light-emitting element that emits red light may adversely affect the flatness of the first light-emitting element.
  • an orthographic projection of the anode hole (for example, the fourth via 2424) of the anode (for example, the fourth anode 1754) of the light emitting element that emits blue light on the base substrate 110 The orthographic projection of the main body of the anode on the base substrate does not overlap in the second direction, and the orthographic projection of the anode hole of the anode on the base substrate 110 and the effective light-emitting area of the light-emitting element configured to emit red light.
  • the orthographic projection on the base substrate 110 does not overlap in the second direction, so that the anode hole configured as the anode of the light-emitting element that emits red light may adversely affect the flatness of the first light-emitting element.
  • a data line 152 is arranged between two adjacent conductive portions 162, and the distance between the orthographic projection of the adjacent conductive portion 162 and the data line 152 on the base substrate 110 It is smaller than the distance between the orthographic projections of two adjacent conductive portions 162 on the base substrate 110.
  • FIG. 42 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • the display device 400 includes the display substrate 100 of any one of the above.
  • the display device has beneficial effects corresponding to the beneficial effects of the display substrate.
  • the display device can improve the stability and life of the compensation thin film transistor, thereby improving the long-term light-emitting stability and life of the display substrate.
  • the display device may be an electronic product with a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.
  • a display function such as a TV, a computer, a notebook computer, a flat computer, a mobile phone, a navigator, and an electronic photo frame.

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Abstract

一种显示基板和显示装置。该显示基板包括衬底基板、像素电路层，包括多个像素驱动电路、第一导电层、第一平坦层和第二导电层；第二导电层包括多个导电部，多个导电部包括第一导电部，第一导电部包括封闭环形部，封闭环形部与至少一个在第一方向上相邻的导电部在第二导电层相互分离，各发光元件组包括第一发光元件，第一发光元件包括第一阳极，第一阳极在衬底基板上的正投影与封闭环形部在衬底基板的正投影交叠；多个导电部还包括与第一导电部相邻的第二导电部，第二导电部在衬底基板上的正投影与第一阳极在衬底基板的正投影交叠。由此，该显示基板可有效改善色偏现象。

Description

显示基板和显示装置
本申请要求于2020年03月25日递交的PCT国际申请PCT/CN2020/081154号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种显示基板和显示装置。
背景技术
随着显示技术的不断发展，有机发光二极管(Organic Light Emitting Diode，OLED)显示技术因其自发光、广视角、高对比度、低功耗、高反应速度等优点已经越来越多地被应用于各种电子设备中。
另一方面，随着有机发光二极管显示技术的不断发展，人们对于有机发光二极管显示产品的功耗、色偏、亮度、稳定性等性能提出了更高的要求。
发明内容
本公开实施例提供一种显示基板和显示装置。一方面，封闭环形部可使得第一阳极可保证较高的平坦度，从而保证第一阳极在不同方向的发光强度一致，进而可有效改善色偏现象；另一方面，在由于封闭环形部具有镂空设计，从而可提高该显示基板的透光率，并且有利于屏下指纹识别装置接收信号。
本公开至少一个实施例还提供一种显示基板，其包括：衬底基板；多个像素驱动电路，包括半导体层；第一导电层，位于所述半导体层远离所述衬底基板的一侧；第一平坦层，位于所述第一导电层远离所述衬底基板的一侧；第二导电层，位于所述第一平坦层远离所述第一导电层的一侧；第二平坦层，位于所述第二导电层远离所述衬底基板的一侧；以及多个发光元件组，位于所述第二平坦层远离所述第二导电层的一侧，所述第二导电层包括沿第一方向排列的多个导电部，各所述导电部在第二方向的尺寸大于在第一方向的尺寸，所述第二方向与所述第一方向相交，所述多个导电部包括第一导电部，所述第一导电部包括封闭环形部，所述封闭环形部与至少一个在第一方向上相邻的所述导电部在所述第二导电层相互分离，各所述发光元件组包括第一发光元件，所述第一发光元件包括第一阳极，所述第一阳极在所述衬底基板上的正投影与所述封闭环形部在所述衬底基板的正投影交叠；所述多个导电部还包括与所述第一导电部相邻的第二导电部，所述第二导电部在衬底基板上的正投影与所述第一阳极在所述衬底基板的正投影交叠。
例如，在本公开一实施例提供的显示基板中，所述封闭环形部在所述第一方向上的尺寸至少大于第一导电部的一部分在所述第一方向上的尺寸，所述多个像素驱动电路包括第一像素驱动电路，第一像素驱动电路在所述半导体层具有半导体图案，所述第一导电部在所述衬底基板的正投影与所述第一像素驱动电路的所述半导体图案在所述衬底基 板的正投影交叠，所述第一像素驱动电路包括驱动晶体管，所述第一导电层包括第一导电图案，所述第一导电图案与所述驱动晶体管的栅极具有相同的电位，所述第一导电图案与所述驱动晶体管的栅极共同构成了栅极电位金属，所述封闭环形部内侧的镂空区域在所述衬底基板上正投影与所述栅极电位金属交叠。
例如，在本公开一实施例提供的显示基板中，所述封闭环形部内侧具有镂空区域，所述第一导电部具有沿着所述第二方向排布的多个所述镂空区域，相邻两个所述镂空区域的形状和尺寸大致相同。
例如，在本公开一实施例提供的显示基板中，所述第一发光元件包括有效发光区，经过所述第一发光元件的有效发光区的中心且沿所述第二方向延伸的直线在所述衬底基板的正投影位于所述第一导电部在所述衬底基板上的正投影和所述第二导电部在所述衬底基板上的正投影之间。
例如，在本公开一实施例提供的显示基板中，所述封闭环形部在所述第一方向的两个边缘分别与所述发光元件组中的多个发光元件的阳极在所述衬底基板的正投影交叠，所述封闭环形部的镂空区域与所述多个发光元件的有效发光区在所述衬底基板的正投影分离设置。
例如，在本公开一实施例提供的显示基板中，所述第一导电层还包括导电金属，被配置为向所述像素驱动电路提供电源，所述第一平坦层包括导电金属过孔，所述导电部通过所述导电金属过孔与所述导电金属电性相连，所述第一像素驱动电路还包括第一发光控制晶体管和存储电容，所述存储电容包括第一电极块和第二电极块，所述第二电极块位于所述第一电极块远离所述衬底基板的一侧，所述导电金属与所述第一发光控制晶体管的源极和所述第二电极块分别电性相连。
例如，在本公开一实施例提供的显示基板中，所述封闭环形部在所述衬底基板上的正投影与所述第一电极块在所述衬底基板上的正投影交叠，所述第二电极块包括开孔，所述开孔在所述衬底基板上的正投影与所述第一电极块在所述衬底基板上的正投影交叠，所述封闭环形部在所述衬底基板上的正投影与所述开孔在所述衬底基板上的正投影也交叠。
例如，在本公开一实施例提供的显示基板中，所述第一像素驱动电路还包括数据写入晶体管、补偿晶体管、复位晶体管、阳极初始化晶体管和第二发光控制晶体管，所述显示基板还包括：复位信号线，与所述复位晶体管的栅极相连；栅线，与所述补偿晶体管的栅极相连；发光控制线，与所述第一发光控制晶体管的栅极相连；以及初始化信号线，与所述复位晶体管的源极相连，所述封闭环形部在所述衬底基板上的正投影分别与所述复位信号线、所述栅线和所述初始化信号线在所述衬底基板上的正投影交叠。
例如，在本公开一实施例提供的显示基板中，所述第一导电图案的一端通过所述开孔与所述驱动晶体管的栅极电性相连，所述第一导电图案的另一端与所述补偿晶体管的源极或漏极电性相连。
例如，在本公开一实施例提供的显示基板中，所述封闭环形部包括沿所述第一方向 排列的第一部分和第二部分，以及沿所述第二方向排列的第三部分和第四部分，所述第一部分、所述第三部分、所述第二部分和所述第四部分首尾相连以形成所述封闭环形部，所述第一部分和所述第二部分在所述衬底基板上的正投影与所述第二电极块在所述衬底基板上的正投影交叠。
例如，在本公开一实施例提供的显示基板中，所述第一部分在所述衬底基板上的正投影与所述第一导电图案在所述衬底基板上的正投影交叠，所述第一导电图案和所述第一部分的形状均为长条形，所述第一导电图案的长边的延伸方向与所述第一部分的长边的延伸方向相同。
例如，在本公开一实施例提供的显示基板中，所述第一导电层还包括第二导电图案和第三导电图案，所述第二导电图案分别与所述初始化信号线与所述复位晶体管的源极相连，所述第二导电层还包括阳极连接部，所述第三导电图案与所述第二发光控制晶体管的漏极和所述阳极连接部相连，所述第三部分在所述衬底基板上的正投影与所述初始化信号线在所述衬底基板上的正投影交叠，所述第三部分在所述衬底基板上的正投影与所述第二导电图案在所述衬底基板上的正投影交叠，所述第四部分在所述衬底基板上正投影与所述第一导电图案在所述衬底基板上的正投影交叠。
例如，在本公开一实施例提供的显示基板中，所述镂空区域在所述衬底基板上的正投影与所述初始化信号线在所述衬底基板上的正投影交叠，所述镂空区域在所述衬底基板上的正投影与所述第二导电图案在所述衬底基板上的正投影交叠，所述镂空区域在所述衬底基板上的正投影与所述第二电极块在所述衬底基板上的正投影交叠。
例如，在本公开一实施例提供的显示基板中，所述多个发光元件组沿所述第一方向排列以形成多个发光元件列，沿所述第二方向排列以形成多个发光元件行，各所述发光元件组包括一个所述第一发光元件、一个第二发光元件、一个第三发光元件和一个第四发光元件，所述第一阳极包括主体部，所述第一发光元件的有效发光区在所述衬底基板的正投影位于所述第一阳极的主体部在所述衬底基板的正投影的内部，且所述第一阳极的主体部与所述第一阳极具有至少部分相同的边界，所述多个导电部包括第二导电部，所述第一导电部和所述第二导电部分别位于所述第一发光元件的有效发光区在所述第一方向上的两侧，所述封闭环形部分在衬底基板上的正投影与所述第一发光元件的有效发光区的中心在所述衬底基板上的正投影的距离与所述第二导电部在所述衬底基板上的正投影与所述第一发光元件的有效发光区的中心在所述衬底基板上的正投影的距离大致相等。
例如，在本公开一实施例提供的显示基板中，所述第一阳极在所述衬底基板上的正投影与所述第一像素驱动电路的所述发光控制线在所述衬底基板上的正投影交叠，与所述镂空区域的中心在第二方向相邻的位置设置有一个第四发光元件，所述第四发光元件的阳极在所述衬底基板上的正投影与所述栅线、所述复位信号线、所述初始化信号线在所述衬底基板上的正投影均交叠。
例如，在本公开一实施例提供的显示基板中，所述栅线在所述衬底基板上的正投影 与所述第一导电图案在所述衬底基板上的正投影交叠，在一个所述像素驱动电路中，所述第一电极块和所述第二电极块在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影和所述发光控制线在所述衬底基板上的正投影之间，所述复位信号线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影与所述初始化信号线在所述衬底基板上的正投影之间，所述发光控制线、所述第一电极块、所述栅线、所述复位信号线和所述初始化信号线沿所述第二方向排列。
例如，在本公开一实施例提供的显示基板中，所述多个像素驱动电路还包括位于所述第一导电层靠近所述衬底基板一侧的第二栅电极层，所述第二电极块位于所述第二栅电极层，至少两个所述第二电极块在所述第二栅电极层连接。
例如，在本公开一实施例提供的显示基板中，所述第一发光元件的有效发光区和所述第二发光元件的有效发光区在衬底基板上的正投影与所述导电部在所述衬底基板上的正投影不交叠，所述第二发光元件被配置为发绿光，所述第四发光元件的有效发光区的中心在所述衬底基板上正投影与所述导电部在所述衬底基板上的正投影交叠，所述导电部与所述第四发光元件的有效发光区的中心在所述衬底基板的正投影交叠的部分为实心部分，所述第四发光元件被配置为发蓝光。
例如，在本公开一实施例提供的显示基板中，所述第二发光元件包括第二阳极，所述第二发光元件的有效发光区在所述衬底基板的正投影位于所述第二阳极的主体部在所述衬底基板的正投影的内部，且所述第二阳极的主体部与所述第二阳极具有至少部分相同的边界，所述第二阳极的主体部与所述第二阳极在所述第一方向上相邻的两个所述导电部的交叠面积大致相等。
例如，在本公开一实施例提供的显示基板中，所述镂空区域在所述衬底基板上的正投影位于所述第一发光元件的有效发光区和所述第二发光元件的有效发光区之间，所述第一发光元件和所述第二发光元件为在第一方向上距离最近的所述第一发光元件和所述第二发光元件。
例如，在本公开一实施例提供的显示基板中，被配置为发出红光的发光元件的阳极在所述第二方向上的中间部分在所述第一方向上的尺寸大于所述阳极在所述第二方向上的边缘部分在所述第一方向上的尺寸，被配置为发出蓝光的发光元件的阳极在所述第二方向上的中间部分在所述第一方向上的尺寸大于所述阳极在所述第二方向上的边缘部分在所述第一方向上的尺寸。
例如，在本公开一实施例提供的显示基板中，一个所述发光元件组中，至少两个发光元件的阳极在所述衬底基板上的正投影与所述第二电极块的所述开孔在所述衬底基板上的正投影交叠，至少一个发光元件的有效发光区在所述衬底基板上的正投影与所述第一电极块或所述第二电极块在所述衬底基板上的正投影不交叠。
例如，在本公开一实施例提供的显示基板中，在所述第一发光元件、所述第二发光元件、所述第三发光元件和所述第四发光元件中的任意一个发光元件中，所述第一平坦层具有阳极孔，所述发光元件的阳极通过所述阳极孔与所述发光元件对应的像素驱动电 路连接，被配置为发出红光的发光元件的阳极的阳极孔在所述衬底基板上的正投影与所述阳极的主体部在所述衬底基板上正投影在所述第二方向上不交叠，被配置为发出红光的发光元件的阳极的阳极孔在所述衬底基板上的正投影与被配置为发出红光的发光元件的有效发光区在所述衬底基板上正投影在所述第二方向上不交叠，被配置为发出蓝光的发光元件的阳极的阳极孔在所述衬底基板上的正投影与所述阳极的主体部在所述衬底基板上正投影在所述第二方向上不交叠，被配置为发出蓝光的发光元件的阳极的阳极孔在所述衬底基板上的正投影与被配置为发出蓝光的发光元件的有效发光区在所述衬底基板上正投影在所述第二方向上不交叠。
例如，在本公开一实施例提供的显示基板中，相邻的两条所述导电部之间设置有数据线，相邻的所述导电部与所述数据线在所述衬底基板上的正投影之间的距离小于相邻的两条所述导电部在所述衬底基板上的正投影之间的距离。
本公开至少一个实施例还提供一种显示装置，其包括上述任一项所述的显示基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示基板的局部剖面示意图；
图2示出了如图1所示的显示基板进行发光的示意图；
图3为本公开一实施例提供的一种显示基板的平面示意图；
图4A为本公开一实施例提供的一种显示基板沿图3中AA方向的剖面示意图；
图4B为本公开一实施例提供的另一种显示基板沿图3中AA方向的剖面示意图；
图5A为本公开一实施例提供的一种显示基板沿图3中BB方向的剖面示意图；
图5B为本公开一实施例提供的一种显示基板沿图3中GG方向的剖面示意图；
图6为本公开一实施例提供的一种显示基板中发光元件的平面示意图；
图7为本公开一实施例提供的一种显示基板中的第二导电层和阳极层的平面关系示意图；
图8为根据本公开一实施例提供的一种显示装置的示意图；
图9为另一种显示基板的局部剖面示意图；
图10为另一种显示基板的局部剖面示意图；
图11为本公开一实施例提供的另一种显示基板的平面示意图；
图12A为本公开一实施例提供的一种显示基板沿图11中HH方向的剖面示意图；
图12B为本公开一实施例提供的一种显示基板沿图11中JJ方向的剖面示意图；
图13为根据本公开一实施例提供的另一种显示基板的平面示意图；
图14为根据本公开一实施例提供的另一种显示基板的平面示意图；
图15为根据本公开一实施例提供的另一种显示基板的平面示意图；
图16为根据本公开一实施例提供的一种显示装置的示意图；
图17为一种使用精细金属掩膜进行蒸镀工艺的示意图；
图18为本公开一实施例提供的一种显示基板的平面示意图；
图19为本公开一实施例提供的一种显示基板沿图18中CC方向的剖面示意图；
图20为根据本公开一实施例提供的另一种显示基板的平面示意图；
图21为本公开一实施例提供的一种显示基板沿图20中DD方向的剖面示意图；
图22为本公开一实施例提供的一种显示基板沿图20中EE方向的剖面示意图；
图23为根据本公开一实施例提供的一种显示装置的示意图；
图24为根据本公开一实施例提供的一种显示基板的制作方法；
图25-图27为根据本公开一实施例提供的一种掩膜板组的平面示意图；
图28A为本公开一实施例提供的另一种显示基板的局部示意图；
图28B为本公开一实施例提供的另一种显示基板的局部示意图；
图29为本公开一实施例提供的一种显示基板沿图28A中FF方向的剖面示意图；
图30A-图30D为本公开一实施例提供的一种显示基板中多个膜层的平面示意图；
图31为本公开一实施例提供的一种显示基板中的像素驱动电路的等效示意图；
图32为根据本公开一实施例提供的一种显示装置的示意图；
图33为本公开一实施例提供的一种显示基板的局部示意图；
图34为本公开一实施例提供的一种显示基板沿图33中KK方向的剖面示意图；
图35A为本公开一实施例提供的一种显示基板沿图33中MM方向的剖面示意图；
图35B为本公开一实施例提供的一种显示基板沿图33中NN方向的剖面示意图；
图35C为本公开一实施例提供的一种显示基板沿图33中QQ方向的剖面示意图；
图36为本公开一实施例提供的另一种显示基板的平面示意图；
图37A为本公开一实施例提供的另一种显示基板的局部示意图；
图37B为本公开一实施例提供的另一种显示基板的局部示意图；
图38为根据本公开一实施例提供的一种显示装置的示意图；
图39为本公开一实施例提供的一种显示基板的示意图；
图40为本公开一实施例提供的一种显示基板沿图39中TT线的剖面示意图；
图41为本公开一实施例提供的一种显示基板中第二导电层和阳极层的示意图；以及
图42为根据本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有 一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。
显示装置有功耗、亮度、色坐标等诸多性能规格，而色偏是其中的一个重要参数。通常，影响有机发光二极管(OLED)显示装置的色偏的因素有很多，从显示基板(机发光二极管的阵列基板或背板)的设计角度而言，阳极的平坦度对色偏有很大影响。
图1为一种显示基板的局部剖面示意图；图2示出了如图1所示的显示基板进行发光的示意图。如图1所示，该显示基板的子像素包括依次设置的衬底基板110、半导体层120、第一栅极层130、第二栅极层140、第一导电层150、第一平坦层241、第二导电层160、第二平坦层242、阳极175和像素限定层190。半导体层120、第一栅极层130、第二栅极层140和第一导电层150可形成包括薄膜晶体管和存储电容的像素驱动电路，第二导电层160包括连接电极161，连接电极161通过第一平坦层241中的过孔(未示出)与像素驱动电路相连，阳极170通过第二平坦层242中的过孔271与连接电极161相连。像素限定层190包括开口191以暴露部分阳极170，当后续的有机发光层180形成在开口191中时，阳极175可与有机发光层180接触并驱动有机发光层进行发光；开口191限定的区域为该子像素的有效发光区。
第二平坦层242中的过孔271会影响阳极175的平坦性，如果过孔271与开口191(也即有效发光区)的距离较近，则会使得开口191所在位置处的阳极175产生“倾斜”现象，从而导致该子像素的发光方向出现偏移。如果不同颜色的子像素中的阳极的“倾斜”的方向不同，则会导致不同颜色(例如红绿蓝)的子像素向不同方向发出的光的强度不匹配，从而产生色偏现象。例如从包括该显示基板的显示装置的一侧进行观察时显示画面发红，从而该显示装置的另一侧观察时显示画面发青的现象。
对此，本公开实施例提供一种显示基板和显示装置。该显示基板包括衬底基板、第一导电层、第一平坦层、第二导电层、第二平坦层和多个发光元件组；第一导电层位于衬底基板上；第一平坦层位于第一导电层远离衬底基板的一侧；第二导电层位于第一平坦层远离第一导电层的一侧；第二平坦层位于第二导电层远离第一平坦层的一侧；多个发光元件组位于第二平坦层远离衬底基板的一侧。多个发光元件组沿第一方向排列以形成多个发光元件列，沿第二方向排列以形成多个发光元件行，各发光元件组包括一个第一发光元件、一个第二发光元件、一个第三发光元件和一个第四发光元件，第二发光元件和第三发光元件沿第二方向排列形成发光元件对，第一发光元件、发光元件对和第三发光元件沿第一方向排列，第一发光元件包括第一阳极，第二发光元件包括第二阳极，第三发光元件包括第三阳极，第四发光元件包括第四阳极，第二导电层包括第一连接电极、第二连接电极、第三连接电极和第四连接电极，第二平坦层包括第一过孔，第二过孔，第三过孔和第四过孔，第一阳极通过第一过孔与第一连接电极相连，第二阳极通过第二过孔与第二连接电极相连，第三阳极通过第三过孔与第三连接电极相连，第四阳极 通过第四过孔与第四连接电极相连，一个发光元件行对应的多个第三过孔大致位于沿第一方向延伸的第一直线上，与第一直线距离最近的第四过孔在衬底基板上的正投影位于第一直线靠近第四过孔对应的第四阳极的一侧。由此，该显示基板通过将第四过孔的位置向靠近第四阳极的方向移动，增加了第四过孔与相邻的第一发光元件的有效发光区的距离，从而保证了位于第一发光元件的有效发光区的第一阳极的平坦性，进而避免发生色偏现象；减少了第四过孔与第四发光元件的有效发光区的距离，从而降低了位于第四发光元件的有效发光区的第四阳极和第四连接电极之间的电阻；并且还增加了第一阳极和第四阳极之间的距离，从而可避免第一阳极和第四阳极因制作过程留下的残留造成短接。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图3为本公开一实施例提供的一种显示基板的平面示意图；图4A和图4B为本公开一实施例提供的一种显示基板沿图3中AA方向的剖面示意图；图5A为本公开一实施例提供的一种显示基板沿图3中BB方向的剖面示意图；图5B为本公开一实施例提供的一种显示基板沿图3中GG方向的剖面示意图；图6为本公开一实施例提供的一种显示基板中发光元件的平面示意图。
如图3、图4A、图4B、图5A、图5B和图6所示，该显示基板100包括衬底基板110、第一导电层150、第一平坦层241、第二导电层160、第二平坦层242和多个发光元件组310；第一导电层150位于衬底基板110上；第一平坦层241位于第一导电层150远离衬底基板110的一侧；第二导电层160位于第一平坦层241远离第一导电层150的一侧；第二平坦层242位于第二导电层160远离第一平坦层241的一侧；多个发光元件组310位于第二平坦层242远离衬底基板110的一侧。多个发光元件组310沿第一方向排列以形成多个发光元件列320，沿第二方向排列以形成多个发光元件行330，各发光元件组310包括一个第一发光元件311、一个第二发光元件312、一个第三发光元件313和一个第四发光元件314，第二发光元件312和第三发光元件313沿第二方向排列形成发光元件对315，第一发光元件311、发光元件对315和第四发光元件314沿第一方向排列，第一发光元件311包括第一阳极1751，第二发光元件312包括第二阳极1752，第三发光元件313包括第三阳极1753，第四发光元件314包括第四阳极1754，第二导电层160包括第一连接电极1611、第二连接电极1612、第三连接电极1613和第四连接电极1614，第二平坦层242包括第一过孔2421，第二过孔2422，第三过孔2423和第四过孔2424，第一阳极1751通过第一过孔2421与第一连接电极1611相连，第二阳极1752通过第二过孔2422与第二连接电极1612相连，第三阳极1753通过第三过孔2423与第三连接电极1613相连，第四阳极1754通过第四过孔2424与第四连接电极1614相连，一个发光元件行330对应的多个第三过孔2423大致位于沿第一方向延伸的第一直线301上，与第一直线301距离最近的第四过孔2424在衬底基板110上的正投影位于第一直线301靠近第四过孔2424对应的第四阳极1754的一侧。需要说明的是，上述的第一导电层和第二导电层是沿着远离衬底基板的方向依次层叠设置的。
在本公开实施例提供的显示基板中，第二发光元件和第三发光元件沿第二方向排列形成发光元件对，第一发光元件、发光元件对和第三发光元件沿第一方向排列，也就是说，第二阳极和第三阳极沿第二方向排列形成阳极对，第一阳极、阳极对和第三阳极沿第一方向排列。与第一直线距离最近的第四过孔在衬底基板上的正投影位于第一直线靠近第四阳极的一侧，即该显示基板将第四过孔的位置向靠近第四阳极的方向移动。由此，该显示基板具有以下有益效果：(1)增加了第四过孔与相邻的第一发光元件的有效发光区的距离，从而保证了位于第一发光元件的有效发光区的第一阳极的平坦性，进而避免发生色偏现象；(2)减少了第四过孔与第四发光元件的有效发光区的距离，从而降低了位于第四发光元件的有效发光区的第四阳极和第四连接电极之间的电阻；(3)增加了第一阳极和第四阳极之间的距离，从而可避免第一阳极和第四阳极因制作过程留下的残留造成短接。
例如，如图5A、图5B和图6所示，该显示基板将第四过孔2424的位置向靠近第四阳极1754的方向移动，因此第四过孔2424与相邻的第一发光元件的有效发光区(即开口1951限定的区域)的距离增加。并且，由于第四阳极具有与其下方的像素驱动电路相连的连接部，将将第四过孔2424的位置向靠近第四阳极1754的方向移动并不会与第四发光元件的有效发光区(即开口1954限定的区域)重叠。此时，第四过孔2424与相邻的第一发光元件的有效发光区和第四发光元件的有效发光区均具有合适的距离，从而可同时保证了位于第一发光元件的有效发光区的第一阳极和位于第四发光元件的有效发光区的第四阳极的平坦性，进而避免发生色偏现象。
例如，如图5A、图5B和图6所示，该显示基板通过将第四过孔2424的位置向靠近第四阳极1754的方向移动，还减少了第四过孔2424与第四发光元件的有效发光区的距离，从而降低了位于第四发光元件的有效发光区的第四阳极和第四连接电极之间的电阻。另一方面，该显示基板通过将第四过孔2424的位置向靠近第四阳极1754的方向移动，还增加了第一阳极1751和第四阳极1754之间的距离，从而可避免第一阳极1751和第四阳极1754因制作过程留下的残留造成短接。
例如，第一阳极在衬底基板上的正投影和相邻的第四阳极在衬底基板上的正投影的最短距离大于第一发光元件的有效发光区在第一方向上的宽度的0.8倍，从而可有效避免第一阳极和第四阳极因制作过程留下的残留造成短接。
例如，如图6所示，第四阳极1754包括主体部1754A和连接部1754B，第四发光元件314的有效发光区落入主体部1754A在衬底基板110的正投影之内，连接部1754B通过第四过孔2424与对应的第四连接电极1614相连，连接部1754B位于第一直线301靠近主体部1754A的一侧，从而可有效地降低连接部的面积，从而降低了位于第四发光元件的有效发光区的第四阳极和第四连接电极之间的电阻。例如，如图6所示，第四阳极1754还包括第一增补部1754C，第一增补部1754C可以覆盖对应的像素驱动电路中的补偿薄膜晶体管的两个沟道区，从而可提高补偿薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
在一些示例中，如图6所示，第一增补部1754C从第四主体部1754A向第三阳极1753凸出，第一增补部1754C位于第四连接部1754B靠近第四主体部1754A的一侧。
在一些示例中，如图6所示，第一增补部1754C与第四主体部1754A和第四连接部1754B均相连。由此，该显示基板可充分利用显示基板上的面积，将第一阳极、第二阳极、第三阳极和第四阳极紧密地排列，从而可保证显示基板的分辨率。
例如，如图4A所示，该显示基板包括依次设置的衬底基板110、半导体层120、第一绝缘层361、第一栅极层130、第二绝缘层362、第二栅极层140、层间绝缘层363、第一导电层150、第一平坦层241、第二导电层160和第二平坦层242。第一栅极层130可包括栅线131和第一电极块CE1，第二栅极层可包括第二栅极块CE2，第一电极块CE1在衬底基板110上的正投影与第二电极块CE2在衬底基板110上的正投影至少部分重叠，从而可形成存储电容。
例如，如图4A所示，第一导电层150还可包括电源线和数据线，第二导电层160可包括与电源线交叠的导电部，该导电部可与电源线电性相连，从而可降低电源线的电阻。
例如，如图4B所示，该显示基板还可包括钝化层364，位于第一导电层150和第一平坦层241之间。当然，本公开实施例包括但不限于此，该显示基板也可不设置钝化层。
在一些示例中，如图6所示，与第一直线301对应的发光元件行330相邻的发光元件行330对应的多个第二过孔2422也大致位于第一直线301上。
在一些示例中，如图3所示，一个发光元件组310中的第四过孔2424位于与该发光元件组310在第二方向上相邻的发光元件组310中的第一阳极1751沿第二方向的平分线线的一侧，例如第一阳极1751沿第二方向的平分线靠近该第一阳极1751所在的发光元件组310的第二阳极1752的一侧。也就是说，一个发光元件组中的第四过孔位于与发光元件组在第二方向上相邻的发光元件组中的第一阳极沿第二方向的平分线的一侧。在一些示例中，如图3所示，在一个发光元件组310中，第一过孔2421位于第一阳极1751沿第二方向的平分线的一侧，例如第一阳极1751沿第二方向的平分线靠近第三阳极1753的一侧；第二过孔2422位于第二阳极1752沿第二方向的平分线靠近第一阳极1751的一侧；第三过孔2423位于第三阳极1753沿第二方向的平分线靠近第一阳极1751的一侧。
在一些示例中，如图6所示，一个发光元件行330对应的多个第四过孔2424大致位于沿第一方向延伸的直线上，该直线穿过该发光元件行330对应的多个第一阳极1751或多个第一过孔2421。
在一些示例中，如图6所示，一个发光元件列320对应的多个第四过孔2424大致位于沿第二方向延伸的第二直线上，第二直线穿过该发光元件列320对应的多个第一阳极1751或多个第一发光元件311的有效发光区。
在一些示例中，如图6所示，第四阳极1754到距离其最近的第一阳极1751之间的距离小于位于同一行的第一阳极1751到距离其最近的第四阳极1754之间的距离。
在一些示例中，如图6所示，发光元件组310包括在第二方向上相邻的第一发光元 件组和第二发光元件组，第一发光元件组和第二发光元件组分别设置相邻的两个发光元件行330中；第一发光元件组中的第四阳极1754的连接部与第二发光元件组中的第一阳极1751的连接部均位于该第四阳极1754沿第二方向的平分线的同一侧。也就是说，第四阳极的主体部沿第二方向的平分线的同一侧设置有第四阳极的连接部和在第二方向上与第四阳极相邻的第一阳极的连接部。
在一些示例中，如图6所示，第一阳极1751的主体部的形状包括六边形，第一阳极1751与在第二方向上与第一阳极1751相邻的第四阳极1754距离最近的点为六边形的顶点。
在一些示例中，如图6所示，相邻的两个发光元件行330错位1/2节距设置，上述的节距等于在第一方向相邻的两个发光元件组310中两个第一发光元件311的有效发光区的中心之间的距离。
在一些示例中，如图6所示，第一直线301位于相邻的两个发光元件行330之间。
在一些示例中，如图5A、图5B和图6所示，与第一直线301距离最近的第一过孔2421在衬底基板110上的正投影位于第一直线301靠近该第一过孔2421对应的第一阳极1751的一侧。也就是说，即该显示基板将第一过孔的位置向靠近第一阳极的方向移动。由此，该显示基板具有以下有益效果：(1)增加了第一过孔与在第二方向上距离最近的第四发光元件的有效发光区的距离，从而保证了位于相邻的第四发光元件的有效发光区的第四阳极的平坦性，进而避免发生色偏现象；(2)减少了第一过孔与第一发光元件的有效发光区的距离，从而降低了位于第一发光元件的有效发光区的第一阳极和第一连接电极之间的电阻；(3)增加了第一阳极和第四阳极之间的距离，从而可避免第一阳极和第四阳极因制作过程留下的残留造成短接。当然，本公开实施例包括不限于此，第一过孔在衬底基板上的正投影也可位于第一直线上。
在一些示例中，如图6所示，第四过孔2424在衬底基板110上的正投影与第一直线301在衬底基板110上的正投影的距离大于第一过孔2421在衬底基板110上的正投影与第一直线301在衬底基板110上的正投影的距离。也就是说，相对于第一直线，第四过孔偏移的量更大。当然，本公开实施例包括但不限于此，相对于第一直线，第四过孔偏移的量也可与第一过孔偏移的量相等。
在一些示例中，如图6所示，第二发光元件312的有效发光区在衬底基板110上的正投影与第二过孔2422在衬底基板110上的正投影具有第一最短距离L1，第三发光元件313的有效发光区在衬底基板110上的正投影与所述第三过孔2423在衬底基板110上的正投影具有第二最短距离L2，第一最短距离L1和第二最短距离L2大致相等。需要说明的是，上述的第一最短距离和第二最短距离大致相等包括第一最短距离和第二最短距离完全相等的情况，也包括第一最短距离和第二最短距离之差小于1微米的情况。
由此，该显示基板可使得位于第二发光元件的有效发光区的第二阳极和位于第三发光元件的有效发光区的第三阳极的倾斜程度相同，倾斜方向相反，从而可有效地避免色偏现象的发生。需要说明的是，当位于第二发光元件的有效发光区的第二阳极和位于第 三发光元件的有效发光区的第三阳极不产生倾斜时，可认为第二发光元件的有效发光区的第二阳极和位于第三发光元件的有效发光区的第三阳极的倾斜程度为零；另外，上述的第二发光元件的有效发光区在衬底基板上的正投影与第二过孔在衬底基板上的正投影的第一最短距离可为第二发光元件的有效发光区在衬底基板上的正投影的边缘与第二过孔在衬底基板上的正投影的边缘之间的最短距离；同样地，第三发光元件的有效发光区在衬底基板上的正投影与所述第三过孔在衬底基板上的正投影之间的第二最短距离可为第三发光元件的有效发光区在衬底基板上的正投影的边缘与所述第三过孔在衬底基板上的正投影的边缘之间的最短距离。
在一些示例中，如图6所示，第四过孔2424在衬底基板110上的正投影与在第二方向相邻的第一发光元件311的有效发光区在衬底基板110上的正投影之间的距离C大于在第二方向相邻的第一发光元件311的有效发光区在第一方向上的宽度A的1.2倍。由此，该显示基板可保证位于第一发光元件的有效发光区的第一阳极具有较好的平坦性。
在一些示例中，如图6所示，一个发光元件组310中的第四过孔2424与相邻的发光元件组310中第一阳极1751的最短距离B小于该发光元件组310中第四过孔2424和对应的第四发光元件314的有效发光区之间的距离E。
在一些示例中，如图6所示，一个发光元件组310中的第四阳极1754与在第二方向上和该四阳极1754距离最近的的发光元件组310中第一阳极1751的最短距离为相邻的发光元件组310中第一阳极1751的顶点与发光元件组310中的第四阳极1754的距离。也就是说，相邻的发光元件组310中第一阳极1751的顶点为距离发光元件组310中的第四阳极1754的距离最近的点。例如，第一阳极1751在衬底基板110上的正投影的形状为六边形，上述的顶点为六边形的长轴上的顶点。
在一些示例中，如图3、图4A、图4B、图5A、图5B和图6所示，该显示基板100还包括像素限定层190；像素限定层190位于第一阳极1751、第二阳极1752、第三阳极1753和第四阳极1754远离衬底基板110的一侧；像素限定层190包括第一开口1951、第二开口1952、第三开口1953和第四开口1954。第一发光元件311包括第一发光部1851，第二发光元件312包括第二发光部1852，第三发光元件313包括第三发光部1853，第四发光元件314包括第四发光部1854。第一开口1951落入第一阳极1751在衬底基板110上的正投影之内，第一发光部1851的至少一部分位于第一开口1951并覆盖第一阳极1751被暴露的部分，第二开口1952落入第二阳极1752在衬底基板110上的正投影之内，第二发光部1852的至少一部分位于第二开口1952并覆盖第二阳极1752被暴露的部分，第三开口1953落入第三阳极1753在衬底基板110上的正投影之内，第三发光部1853的至少一部分位于第三开口1953并覆盖第三阳极1753被暴露的部分，第四开口1954落入第四阳极1754在衬底基板110上的正投影之内，第四发光部1854的至少一部分位于第四开口1954并覆盖第四阳极1754被暴露的部分。第一开口1951限定的区域为第一发光元件313的有效发光区，第二开口1952限定的区域为第二发光元件312的有效发光区，第三开口1953限定的区域为第三发光元件313的有效发光区，第四开口1954限定的区域 第四发光元件314的有效发光区。
在一些示例中，如图6所示，第四过孔2424在衬底基板110上的正投影与在第二方向相邻的第一开口1951在衬底基板110上的正投影之间的距离C大于第一开口1951在第一方向上的宽度A的1.2倍。由此，该显示基板可保证位于第一开口的第一阳极(也即第一阳极被第一开口暴露的部分)具有较好的平坦性。
在一些示例中，如图3、图4A、图4B、图5A、图5B和图6所示，该显示基板100包括第一平坦层241和第一导电层150；第一平坦层241位于第二导电层160靠近衬底基板110的一侧；第一导电层150位于第一平坦层241靠近衬底基板110的一侧。第一导电层150包括第一漏极1511、第二漏极1512、第三漏极1513和第四漏极1514；第一平坦层241包括第五过孔2415、第六过孔2416、第七过孔2417和第八过孔2418，第一连接电极1611通过第五过孔2415与第一漏极1511相连，第二连接电极1612通过第六过孔2416与第二漏极1512相连，第三连接电极1613通过第七过孔2417与第三漏极1513相连，第四连接电极1614通过第八过孔2418与第四漏极1514相连。
在一些示例中，如图4A和图4B所示，该显示基板100还包括第一像素驱动电路2651、第二像素驱动电路2652、第三像素驱动电路2653和第四像素驱动电路2654；第一漏极1511为第一像素驱动电路2651的一部分，第二漏极1512为第二像素驱动电路2652的一部分，第三漏极1513为第三像素驱动电路2653的一部分，第四漏极1514为第四像素驱动电路2654的一部分。第一像素驱动电路2651通过第一连接电极1611与第一阳极1751相连，从而向第一阳极1751施加驱动信号；第二像素驱动电路2652通过第二连接电极1612与第二阳极1752相连，从而向第二阳极1752施加驱动信号；第三像素驱动电路2653通过第三连接电极1613与第三阳极1753相连，从而向第三阳极1753施加驱动信号；第四像素驱动电路2654通过第四连接电极1614与第四阳极1754相连，从而向第四阳极1754施加驱动信号。
图7为本公开一实施例提供的一种显示基板中的第二导电层和阳极层的平面关系示意图。如图6和图7所示，第二阳极1752和第三阳极1753沿第二方向排列形成阳极对1755，第一阳极1751、阳极对1755和第四阳极1754沿第一方向排列；第二导电层160还包括沿第二方向延伸的第一导电部1621、第二导电部1622、第三导电部1623和第四导电部1624，第一导电部1621位于第一阳极1751远离阳极对1755的一侧，第二导电部1622位于第一阳极1751和阳极对1755之间，第三导电部1623位于阳极对1755与第四阳极1754之间，第四导电部1624与第四阳极1754交叠。在该显示基板中，沿第二方向延伸的第一导电部1621、第二导电部1622、第三导电部1623和第四导电部1624可与第一导电层150中的电源线相连，从而降低电源线的电阻。
在一些示例中，如图7所示，第一导电部1621和第二导电部1622在衬底基板110上的正投影与第一阳极1751在衬底基板110上的正投影不交叠，第二导电部1622和第三导电部1623在衬底基板110上的正投影与所述阳极对1755在衬底基板110上的正投影不交叠。由此，第一导电部1621和第二导电部1622对第一阳极175的平坦性影响较 小；第二导电部1622和第三导电部1623对阳极对1755中的第二阳极1752和第三阳极1753的平坦性影响较小。当然，本公开实施例包括但不限于此，第一导电部、第二导电部和第三导电部也可与阳极交叠。
例如，第一导电部1621和第二导电部1622在衬底基板110上的正投影分别与第一阳极1751在衬底基板110上的正投影具有第一交叠部和第二交叠部，第一交叠部和第二交叠部的面积大致相等，从而也可提高第一阳极1751的平坦性。同样地，第二导电部1622和第三导电部1623在衬底基板110上的正投影分别与阳极对1755在衬底基板110上的正投影具有第三交叠部和第四交叠部，第三交叠部和第四交叠部的面积大致相等，从而也可提高阳极对1755的第二阳极1752和第三阳极1753的平坦性。需要说明的是，上述的“大致相等”包括完全相等的情况和两者的差值小于两者的平均值的10％的情况。
例如，第一交叠部和第二交叠部关于第一阳极1751的主体部，也即第一发光元件311的有效发光区沿第二方向的平分线对称，从而可进一步提高第一发光元件311的有效发光区的平坦性；第三交叠部和第四交叠部关于阳极对1755沿第二方向的平分线对称，从而也可进一步提高阳极对1755的第二阳极1752和第三阳极1753的平坦性。
在一些示例中，如图7所示，第四导电部1624在衬底基板110上的正投影穿过第四阳极1754在衬底基板110上的正投影的中心，第四导电部1624沿第二方向的平分线在衬底基板110上的正投影与第四发光元件314的有效发光区沿第二方向的平分线在衬底基板110上的正投影重合。从而也可提高第四阳极1754的平坦性。
在一些示例中，如图7所示，第二导电层160还包括沿第一方向延伸的第五导电部1625和第六导电部1626；第五导电部1625与第二导电部1622和第三导电部1623分别相连，并且位于第二阳极1752和第三阳极1753之间；第六导电部1626与第三导电部1623和第四导电部1624分别相连，并且位于在第二方向上相邻的第一阳极1751和第四阳极1754之间。由此，上述第一导电部1621、第二导电部1622、第三导电部1623、第四导电部1624、第五导电部1625和第六导电部1626可形成网状结构，从而进一步降低第一导电层中的电源线的电阻，进而可提高该显示基板的电学性能。
在一些示例中，如图7所示，第二导电部1622包括沿第二方向延伸的主体部1622A、垫块1622B和连接块1622C，垫块1622B位于主体部1622A靠近第一阳极1751的一侧，且与主体部1622A间隔设置，垫块1622B通过连接块1622C与主体部1622A连接。由于通常的第一阳极在第一方向上的尺寸(即宽度)较小，第一导电部和第二导电部的主体部之间的距离较大，通过设置上述的垫块可提高第一阳极两侧的第一导电部和第二导电部的对称性，从而可提高第一阳极的平坦性。
在一些示例中，第一发光元件被配置为发出第一颜色的光，第二发光元件和第三发光元件被配置为发出第二颜色的光，第四发光元件被配置为发出第三颜色的光。
例如，第一颜色为红色(R)，第二颜色为绿色(G)，第三颜色为蓝色(B)。也就是说，该显示基板采用GGRB的像素排列结构。
本公开一实施例还提供一种显示装置。图8为根据本公开一实施例提供的一种显示 装置的示意图。如图8所示，该显示装置400包括上述任一项的显示基板100。由此，该显示装置具有与该显示基板的有益效果对应的有益效果。例如，该显示装置可保证位于第一发光元件的有效发光区的第一阳极的平坦性，从而避免发生色偏现象；可降低位于第四发光元件的有效发光区的第四阳极和第四连接电极之间的电阻；并且还可增加了第一阳极和第四阳极之间的距离，从而可避免第一阳极和第四阳极因制作过程留下的残留造成短接。
例如，该显示装置可为显示面板，也可为电视、电脑、笔记本电脑、平坦电脑、手机、导航仪、电子相框等具有显示功能的电子产品。
另一方面，本申请的发明人发现，因为阳极下方的第二源漏金属层厚度较大并且分布不均，因此第二源漏金属层也会导致阳极出现不平坦现象。
图9为另一种显示基板的局部剖面示意图；图10为另一种显示基板的局部剖面示意图。如图9所示，第二源漏金属层160包括多条走线168，如果阳极175下方一侧存在走线168，而另一侧没有走线168，则该阳极175的两侧会产生高度差异，从而导致阳极175产生“倾斜”现象，进而会导致色偏现象。如图10所示，若阳极175的两侧均存在走线168或者阳极175下方不设置走线168，阳极175则可保证较高的平坦度，从而保证阳极175在不同方向的发光强度一致，进而可有效改善色偏现象。
对此，本公开实施例提供一种显示基板和显示装置。该显示基板包括衬底基板、第一导电层、第一平坦层、第二导电层、第二平坦层和多个发光元件组；第一导电层位于衬底基板上；第一平坦层位于第一导电层远离衬底基板的一侧；第二导电层位于第一平坦层远离第一导电层的一侧；第二平坦层位于第二导电层远离第一平坦层的一侧；多个发光元件组位于第二平坦层远离第二导电层的一侧。多个发光元件组沿第一方向排列以形成多个发光元件列，沿第二方向排列以形成多个发光元件行，各发光元件组包括一个第一发光元件、一个第二发光元件、一个第三发光元件和一个第四发光元件，第一发光元件包括第一阳极，第二导电层包括沿第二方向延伸的第一导电部和第二导电部，第一导电部位于第一阳极的一侧，第二导电部位于第一阳极远离第一导电部的一侧，第一导电部包括延伸部和偏移部，第一发光元件的有效发光区在沿第二方向延伸的直线上的正投影被偏移部在该直线上的正投影覆盖，，偏移部在衬底基板上的正投影与第一阳极在衬底基板上的正投影间隔设置，延伸部靠近第二导电部且沿第二方向延伸的边缘所在的直线为第一直线，偏移部与第一直线间隔设置且位于第一直线远离第二导电部的一侧。由此，由于第一导电部位于第一阳极的一侧，第二导电部位于第一阳极远离第一导电部的一侧，并且偏移部在衬底基板上的正投影与第一阳极在衬底基板上的正投影间隔设置，因此第二导电层中的第一导电部和第二导电部对第一阳极的平坦度造成的影响较小，从而使得第一阳极可保证较高的平坦度，从而保证第一阳极在不同方向的发光强度一致，进而可有效改善色偏现象。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图11为本公开一实施例提供的另一种显示基板 的平面示意图；图12A为本公开一实施例提供的一种显示基板沿图11中HH方向的剖面示意图；图12B为本公开一实施例提供的一种显示基板沿图11中JJ方向的剖面示意图；图13为根据本公开一实施例提供的另一种显示基板的平面示意图；图14为根据本公开一实施例提供的另一种显示基板的平面示意图。为了清楚地表现第二导电层中各个导电部和阳极的位置关系，图14仅示出了第二导电层和阳极层。
如图11-14所示，该显示基板100包括衬底基板110、第一导电层150、第一平坦层241、第二导电层160、第二平坦层242和多个发光元件组310；第二导电层160位于衬底基板110上；第二平坦层242位于第二导电层160远离衬底基板110一侧；多个发光元件组310位于第二平坦层242远离衬底基板110的一侧。多个发光元件组310沿第一方向排列以形成多个发光元件列320，沿第二方向排列以形成多个发光元件行330，各发光元件组310包括一个第一发光元件311、一个第二发光元件312、一个第三发光元件313和一个第四发光元件314，第一发光元件311包括第一阳极1751，第二发光元件312包括第二阳极1752，第三发光元件313包括第三阳极1753，第四发光元件314包括第四阳极1754，第二阳极1752和第三阳极1753沿第二方向排列形成阳极对1755，第一阳极1751、阳极对1755和第四阳极1754沿第一方向排列。第二导电层160包括沿第二方向延伸的第一导电部1621和第二导电部1622，第一导电部1621位于第一阳极1751远离阳极对1755的一侧，第二导电部1622位于第一阳极1751和阳极对1755之间，即第一阳极1751远离第一导电部1621的一侧。第一导电部1621包括延伸部1621A和偏移部1621B，第一发光元件311的有效发光区在沿第二方向延伸的直线上的正投影被偏移部1621B在直线上的正投影覆盖，即第一发光元件311的有效发光区在第一导电部1621上的正投影位于偏移部1621B所在的位置，也就是说，偏移部1621B与第一发光元件311的有效发光区对应。偏移部1621B在衬底基板110上的正投影与第一阳极1751在衬底基板110上的正投影间隔设置，延伸部1621A靠近第二导电部1622且沿第二方向延伸的边缘所在的直线为第一直线302，偏移部1621B与第一直线302间隔设置且位于第一直线302远离第二导电部1622的一侧。需要说明的是，上述的第一导电层和第二导电层是沿着远离衬底基板的方向依次层叠设置的。
在本公开实施例提供的显示基板中，由于第一导电部位于第一阳极的一侧，第二导电部位于第一阳极远离第一导电部的一侧，并且偏移部在衬底基板上的正投影与第一阳极在衬底基板上的正投影间隔设置，因此第二导电层中的第一导电部和第二导电部对第一阳极的平坦度造成的影响较小，从而使得第一阳极可保证较高的平坦度，从而保证第一阳极在不同方向的发光强度一致，进而可有效改善色偏现象。另外，由于偏移部与第一直线间隔设置且位于第一直线远离第二导电部的一侧，偏移部向远离第一阳极的方向进行偏移，为第一阳极的设置提供的空间，从而可在实现阳极的紧密排列的同时使得第一阳极可保证较高的平坦度。
需要说明的是，上述的多个发光元件的排列方式可参见图6所示的排列方式，即相邻的两个发光元件行错位1/2节距设置，上述的节距等于在第一方向相邻的两个发光元 件组中两个第一发光元件的有效发光区的中心之间的距离。
在一些示例中，第一发光元件311被配置为发第一颜色的光，第二发光元件312和第三发光元件313被配置为发第二颜色的光，第四发光元件314被配置为发第三颜色的光。
在一些示例中，第一颜色为红色，第二颜色为绿色，第三颜色为蓝色。
在一些示例中，如图11-14所示，第一直线302在衬底基板110上的正投影穿过第一阳极1751在衬底基板110上的正投影。由此，该显示基板可在实现阳极的紧密排列的同时使得第一阳极可保证较高的平坦度。
在一些示例中，如图11-14所示，延伸部1621A沿第二方向延伸的平分线所在的直线为第二直线303，偏移部1621B与第二直线303间隔设置且位于第二直线303远离第二导电部1622的一侧。由此，由于偏移部与第二直线间隔设置且位于第二直线远离阳极对的一侧，偏移部向远离第一阳极的方向进行偏移，为第一阳极的设置提供的空间，从而可在实现阳极的紧密排列的同时使得第一阳极可保证较高的平坦度。
在一些示例中，如图11-14所示，第二直线303在衬底基板110上的正投影穿过第一阳极1751在衬底基板110上的正投影。由此，该显示基板可在实现阳极的紧密排列的同时使得第一阳极可保证较高的平坦度。
在一些示例中，如图11-14所示，第一阳极1751沿第二方向延伸，第二导电部1622包括沿第二方向延伸的主体部1622A和垫块1622B，主体部1622A在衬底基板110上的正投影与第一阳极1751在衬底基板110上的正投影间隔设置，垫块1622B位于主体部1622A靠近第一阳极1751的一侧，垫块1622B在衬底基板110上的正投影和第一发光元件311的有效发光区的中心在衬底基板110上的正投影的距离与第一导电部1621在衬底基板110上的正投影和第一发光元件311的有效发光区的中心在衬底基板110上的正投影的距离大致相等。
在该显示基板中，由于通常的第一阳极在第一方向上的尺寸(即宽度)较小，第一导电部和第二导电部的主体部之间的距离较大；由于垫块在衬底基板上的正投影与第一发光元件的有效发光区的中心在衬底基板上的正投影的距离与第一导电部在衬底基板上的正投影与第一发光元件的有效发光区的中心在衬底基板上的正投影的距离大致相等，因此通过设置上述的垫块可提高第一阳极两侧的第一导电部和第二导电部的对称性，从而可进一步提高第一阳极的平坦性。
在一些示例中，如图11-14所示，第一导电部1621在衬底基板110上的正投影和第一发光元件311的有效发光区的中心在衬底基板110上的正投影的距离小于主体部1622A在衬底基板110上的正投影和第一发光元件311的有效发光区的中心在衬底基板110上的正投影的距离。
例如，第一导电部1621在衬底基板110上的正投影和第一发光元件311的有效发光区的中心在衬底基板110上的正投影的距离与主体部1622A在衬底基板110上的正投影和第一发光元件311的有效发光区的中心在衬底基板110上的正投影的距离的比值小于 等于1/3。
在一些示例中，如图11-14所示，垫块1622B在衬底基板110上的正投影与主体部1622A在衬底基板110上的正投影间隔设置，第二导电部1622还包括连接部1622C，垫块1622B通过连接部1622C与主体部1622A连接。由此，由于垫块1622B通过连接部1622C与主体部1622A连接，而并非与主体部1622A形成为一体，从而可避免第二导电部1622与下方的膜层，例如半导体层、栅极层等存在过多的交叠，从而避免加重第二导电部1622下方的膜层的负载。由此，该显示基板可在增加垫块的同时，确保各个子像素的正常工作。
例如，如图12B所示，第一导电层150包括沿第二方向延伸的电源线151和数据线152、第一连接块1541和第二连接块1542。第一连接块1541用于将初始化信号线与像素驱动电路中对应的源极区相连；第二连接块1542用于将补偿薄膜晶体管的漏极区与第一电极块CE1相连，第一电极块CE1可与第二电极块CE2形成存储电容，也同时作为驱动薄膜晶体管的栅极。因此，由于垫块1622B通过连接部1622C与主体部1622A连接，而并非与主体部1622A形成为一体，从而可避免第二导电部1622与第二连接块1542存在过多交叠，从而可降低第二连接块1542的负载，即补偿薄膜晶体管的漏极和驱动薄膜晶体管的栅极的负载，进而可提高该显示基板的性能。需要说明的是，该显示基板采用的是7T1C的像素驱动电路，当然，本公开实施例包括但不限与此，该显示基板可采用其他合适的像素驱动电路结构。
例如，如图12B所示，偏移部1621B在衬底基板110上的正投影与第一阳极1751在衬底基板上的正投影间隔设置；垫块1622B在衬底基板110上的正投影与第一阳极1751在衬底基板110上的正投影间隔设置。例如，如图12B所示，该显示基板还可包括钝化层364，位于第一导电层150和第一平坦层241之间。当然，本公开实施例包括但不限于此，该显示基板也可不设置钝化层。
在一些示例中，如图11-14所示，垫块1622B在衬底基板110上的正投影与主体部1622A在衬底基板110上的正投影之间的距离大于垫块1622B在衬底基板110上的正投影沿所述第一方向的宽度。由此，该显示基板可进一步避免第二导电部1622与下方的膜层，例如半导体层、栅极层等存在过多的交叠，从而避免加重半导体层、栅极层等膜层的负载。由此，该显示基板可在增加垫块的同时，确保各个子像素的正常工作。
在一些示例中，如图11-14所示，第二导电部1622包括两个连接部1622C，两个连接部1622C分别位于垫块1622B在第二方向上的两端，垫块1622B，两个连接部1622C和主体部1622A围成一个矩形开口。由此，该显示基板可进一步避免第二导电部1622与下方的膜层，例如半导体层、栅极层等存在过多的交叠，从而避免加重半导体层、栅极层等的负载。由此，该显示基板可在增加垫块的同时，确保各个子像素的正常工作。
在一些示例中，垫块在第一方向上的宽度与主体部在第一方向上的宽度的比值小于等于1/2，垫块在第一方向上的宽度与主体部和垫块之间的距离的比值小于等于1/2。
在一些示例中，垫块在第二方向上的长度与第一发光元件的有效发光区在第二方向 的长度的比值大于等于7/8。
在一些示例中，第一发光元件的有效发光区和垫块的中心连线与第一方向之间的夹角小于30度。例如，第一发光元件的有效发光区和垫块的中心连线与第一方向之间的夹角为零，即第一发光元件的有效发光区和垫块的中心连线与第一方向相互平行。
在一些示例中，垫块在衬底基板上的正投影与第一阳极在衬底基板上的正投影间隔设置，第一导电部在衬底基板上的正投影与第一阳极在衬底基板上的正投影间隔设置。
在一些示例中，垫块在衬底基板上的正投影与第一阳极在衬底基板上的正投影的交叠面积与第一导电部在衬底基板上的正投影与第一阳极在衬底基板上的正投影的交叠面积大致相等。在一些示例中，如图11-14所示，第二导电层160还包括沿第二方向延伸的第三导电部1623和第四导电部1624；第三导电部1623位于阳极对1755与第四阳极1754之间，第四导电部1624与第四阳极1754交叠。
在一些示例中，如图11-14所示，第二导电部1622的主体部1622A在衬底基板110上的正投影与第二发光元件312的有效发光区沿第二方向的平分线在衬底基板110上的正投影的距离与第三导电部162在衬底基板110上的正投影与第二发光元件312的有效发光区沿第二方向的平分线在衬底基板110上的正投影的距离大致相等。由此，该显示基板可提高阳极对两侧的第二导电部和第三导电部的对称性，从而可进一步提高第二阳极和第三阳极的平坦性。
在一些示例中，如图11-14所示，第四阳极1754沿第二方向延伸，第四导电部1624在衬底基板110上的正投影穿过第四发光元件314的有效发光区在衬底基板110上的正投影的中心。由此，虽然第四导电部162与第四阳极1754存在交叠，但是由于第四导电部1624在衬底基板110上的正投影穿过第四发光元件314的有效发光区在衬底基板110上的正投影的中心，第四导电部可保证第四阳极具有较高的平坦度，从而保证第四阳极在不同方向的发光强度一致，进而可有效改善色偏现象。
在一些示例中，如图11-14所示，第二导电层160还包括沿第一方向延伸的第五导电部1625和第六导电部1626，第五导电部1625与主体部1622A和第三导电部1623分别相连，并位于阳极对1755中的第二阳极1752和第三阳极1753之间；第六导电部1626与第三导电部1623和第四导电部1624分别相连，并位于在第二方向上相邻的第一阳极1751和第四阳极1754之间。由此，上述第一导电部1621、第二导电部1622、第三导电部1623、第四导电部1624、第五导电部1625和第六导电部1626可形成网状结构，从而进一步降低第一导电层中的电源线的电阻，进而可提高该显示基板的电学性能。
在一些示例中，如图11-14所示，第二导电层160包括第一连接电极1611、第二连接电极1612、第三连接电极1613和第四连接电极1614，第二平坦层242包括第一过孔2421，第二过孔2422，第三过孔2423和第四过孔2424，第一阳极1751通过第一过孔2421与第一连接电极1611相连，第二阳极1752通过第二过孔2422与第二连接电极1612相连，第三阳极1753通过第三过孔2423与第三连接电极1613相连，第四阳极1754通过第四过孔2424与第四连接电极1614相连。
在一些示例中，如图11-14所示，第一平坦层241位于第二导电层160靠近衬底基板110的一侧；第一导电层150位于第一平坦层241靠近衬底基板110的一侧。第一导电层150包括第一漏极1511、第二漏极1512、第三漏极1513和第四漏极1514；第一平坦层241包括第五过孔2415、第六过孔2416、第七过孔2417和第八过孔2418，第一连接电极1611通过第五过孔2415与第一漏极1511相连，第二连接电极1612通过第六过孔2416与第二漏极1512相连，第三连接电极1613通过第七过孔2417与第三漏极1513相连，第四连接电极1614通过第八过孔2418与第四漏极1514相连。
在一些示例中，如图11-14所示，该显示基板100还包括第一像素驱动电路2651、第二像素驱动电路2652、第三像素驱动电路2653和第四像素驱动电路2654；第一漏极1511为第一像素驱动电路2651的一部分，第二漏极1512为第二像素驱动电路2652的一部分，第三漏极1513为第三像素驱动电路2653的一部分，第四漏极1514为第四像素驱动电路2654的一部分。第一像素驱动电路2651通过第一连接电极1611与第一阳极1751相连，从而向第一阳极1751施加驱动信号；第二像素驱动电路2652通过第二连接电极1612与第二阳极1752相连，从而向第二阳极1752施加驱动信号；第三像素驱动电路2653通过第三连接电极1613与第三阳极1753相连，从而向第三阳极1753施加驱动信号；第四像素驱动电路2654通过第四连接电极1614与第四阳极1754相连，从而向第四阳极1754施加驱动信号。
例如，第二导电层的厚度范围可为0.6-0.8微米，例如0.7微米；第二平坦层的厚度范围可为1.3-1.7微米，例如1.5微米。
图15为根据本公开一实施例提供的另一种显示基板的平面示意图。为了清楚地表现第二导电层中各个导电部和阳极的位置关系，图15仅示出了第二导电层和阳极层。如图15所示，第二导电层160的第二导电部1622没有设置垫块，第二导电层160的第一导电部1621包括延伸部1621A和偏移部1621B，第一发光元件311的有效发光区在第一导电部1621上的正投影位于偏移部1621B所在的位置，也就是说，偏移部1621B与第一发光元件311的有效发光区对应。偏移部1621B在衬底基板110上的正投影与第一阳极1751在衬底基板110上的正投影间隔设置，延伸部1621A靠近第一阳极1751且沿第二方向延伸的边缘所在的直线为第一直线302，偏移部1621B与第一直线302间隔设置且位于第一直线302远离阳极对1755的一侧。
在本公开实施例提供的显示基板中，由于第一导电部位于第一阳极远离阳极对的一侧，第二导电部位于第一阳极和阳极对之间，并且偏移部在衬底基板上的正投影与第一阳极在衬底基板上的正投影间隔设置，因此第二导电层中的第一导电部和第二导电部对第一阳极的平坦度造成的影响较小，从而使得第一阳极可保证较高的平坦度，从而保证第一阳极在不同方向的发光强度一致，进而可有效改善色偏现象。另外，由于偏移部与第一直线间隔设置且位于第一直线远离阳极对的一侧，偏移部向远离第一阳极的方向进行偏移，为第一阳极的设置提供的空间，从而可在实现阳极的紧密排列的同时使得第一阳极可保证较高的平坦度。
例如，如图15所示，第一阳极1751可包括主体部1751A、连接部1751B和增补部1751C；第一发光元件的有效发光区落入主体部1751A，连接部1751B用于将第一阳极1751与对应的像素驱动电路相连，增补部1751C可覆盖对应的像素驱动电路中的驱动薄膜晶体管T1的栅极G1和补偿薄膜晶体管T3的漏极D3上的电位，从而稳定驱动薄膜晶体管T1的栅极G1和补偿薄膜晶体管T3的漏极D3上的电位，从而进一步提高该显示基板的长期发光稳定性和寿命。
例如，如图15所示，第一阳极1751与偏移部1621B的距离范围可为2.5-3.2微米，例如2.9微米；第一阳极1751的主体部1751A与第二导电部1622的距离范围可为9-11微米，例如，10.5微米；第一阳极1751的连接部1751B与第二导电部1622的距离范围可为5-7微米；第一阳极1751的增补部1751C可与第二导电部1622部分重叠，且重叠的部分在第一方向上的宽度小于1微米，例如，0.79微米。由于增补部靠近第二导电部的边缘与主体部的距离较大，因此增补部1751C可与第二导电部1622部分重叠对第一阳极的平坦性的影响较小。
本公开一实施例还提供一种显示装置。图16为根据本公开一实施例提供的一种显示装置的示意图。如图16所示，该显示装置400包括上述任一项的显示基板100。由此，该显示装置具有与该显示基板的有益效果对应的有益效果。例如，该显示装置可保证位于第一发光元件的有效发光区的第一阳极的平坦性，从而避免发生色偏现象；可降低位于第四发光元件的有效发光区的第四阳极和第四连接电极之间的电阻；并且还可增加了第一阳极和第四阳极之间的距离，从而可避免第一阳极和第四阳极因制作过程留下的残留造成短接。
例如，该显示装置可为电视、电脑、笔记本电脑、平坦电脑、手机、导航仪、电子相框等具有显示功能的电子产品。
另一方面，在制作有机发光二极管显示装置的过程中，通常采用蒸镀工艺来制作发光层。并且，为了防止精细金属掩膜(FMM)在蒸镀工艺中触碰并损伤有机发光二极管显示基板，通常需要在有机发光二极管显示基板上形成隔垫物，并将精细金属掩膜放置在隔垫物上。此时，隔垫物可起到支撑精细金属掩膜的作用，从而可起到保护有机发光二极管显示基板的作用。
然而，在研究中，本申请的发明人注意到，通常的隔垫物位于子像素的有效发光区的直边的中间位置，当使用精细金属掩膜进行蒸镀工艺时，精细金属掩膜的开口边缘位于隔垫物的中间位置；而隔垫物的中间位置因其制备工艺等原因通常为隔垫物的厚度最大的位置(即隔垫物的顶端)，精细金属掩膜的开口边缘恰好与隔垫物的顶端接触，从而容易刮蹭隔垫物并产生颗粒物(Particle)等异物。图17为一种使用精细金属掩膜进行蒸镀工艺的示意图。如图17所示，精细金属掩膜250的开口边缘252位于隔垫物220的顶端，容易刮蹭隔垫物220的顶端并产生颗粒物等异物；在蒸镀工艺之后，会在显示基板上形成封装层等膜层，而产生的颗粒物等异物容易导致封装层产生裂缝(Crack)等不良，从而造成产品的稳定性和信赖性降低。
对此，本公开实施例还提供一种显示基板及其制作方法和显示装置。该显示基板包括衬底基板、发光层和隔垫物；发光层位于衬底基板上且包括多个发光部；隔垫物位于发光层远离衬底基板的一侧；隔垫物远离衬底基板的顶端在衬底基板上的正投影与发光部在衬底基板上的正投影的边缘间隔设置。由此，在采用精细金属掩膜进行蒸镀工艺以形成上述的发光部时，精细金属掩膜的开口边缘在衬底基板上的正投影与隔垫物的顶端在衬底基板上的正投影间隔设置，从而可避免精细金属掩膜的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物，进而可提高该显示基板的良率。
下面，结合附图对本公开实施例提供的显示基板及其制作方法和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图18为本公开一实施例提供的一种显示基板的平面示意图；图19为本公开一实施例提供的一种显示基板沿图18中CC方向的剖面示意图。
如图18和图19所示，该显示基板100包括衬底基板110、发光层180和隔垫物220；发光层180位于衬底基板110上且包括多个发光部185；隔垫物220位于衬底基板110上发光层180所在的一侧。隔垫物220远离衬底基板110的顶端225在衬底基板110上的正投影与发光部185在衬底基板110上的正投影的边缘间隔设置。需要说明的是，上述的隔垫物的顶端是指隔垫物远离衬底基板的部分，即厚度较大的部分；另外，上述的“间隔设置”是指隔垫物远离衬底基板的顶端在衬底基板上的正投影与发光部在衬底基板上的正投影具有一定的间隔，相互不重叠或者接触。
在本公开实施例提供的显示基板的制作过程中，在采用精细金属掩膜250进行蒸镀工艺以形成上述的发光部185时，如图19所示，精细金属掩膜250的开口边缘252在衬底基板110上的正投影与隔垫物220的顶端225在衬底基板110上的正投影间隔设置；从而可避免精细金属掩膜250的开口边缘252与隔垫物220的顶端225接触，并避免产生颗粒物等异物。例如，如图11所示，精细金属掩膜250的开口边缘252位于隔垫物220的边缘部分，由于隔垫物220的边缘部分的厚度小于隔垫物220的顶端225的厚度，精细金属掩膜250的开口边缘252处于悬空状态，与隔垫物220没有接触，从而可避免因刮蹭而产生颗粒物等异物。由此，该显示基板可提高显示基板的稳定性、信赖性和产品的良率。
在一些示例中，如图19所示，隔垫物220的中间部分在垂直于衬底基板110的方向上的尺寸大于隔垫物220的边缘部分在垂直于衬底基板110的方向上的尺寸。也就是说，隔垫物220的中间部分的厚度大于隔垫物220的边缘部分的厚度。由此，当精细金属掩膜的开口边缘在衬底基板上的正投影与隔垫物的中间部分(即隔垫物的顶端)在衬底基板上的正投影间隔设置时，精细金属掩膜的开口边缘可处于悬空状态，与隔垫物没有接触，从而可避免因刮蹭而产生颗粒物等异物。
例如，如图19所示，隔垫物220在垂直于衬底基板110的平面中的横截面形状可包括半圆形。当然，本公开实施例包括但不限于此。例如，当隔垫物220的横截面形状为 半圆形时，该半圆形的坡度角的范围为8-10度。
在一些示例中，如图18所示，隔垫物220在衬底基板110上的正投影的形状为矩形，隔垫物220在长度方向上的中轴线在衬底基板110上的正投影与发光部185在衬底基板110上的正投影的边缘间隔设置。由此，该显示基板可避免精细金属掩膜的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物，从而可提高显示基板的稳定性、信赖性和产品的良率。当然，本公开实施例中的隔垫物在衬底基板上的正投影的形状包括但不限于上述的矩形，也可为其他形状。
在一些示例中，如图18所示，隔垫物220在长度方向上的中轴线在衬底基板110上的正投影与发光部185在衬底基板110上的正投影的边缘的距离大于6微米。由此，该显示基板可有效地避免精细金属掩膜的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物，从而可提高显示基板的稳定性、信赖性和产品的良率。
图20为根据本公开一实施例提供的另一种显示基板的平面示意图；图21为本公开一实施例提供的一种显示基板沿图20中DD方向的剖面示意图。为了清楚地示出隔垫物与发光部之间的关系，图20中仅示出了衬底基板、阳极层、发光层和隔垫物。如图20所示，隔垫物220远离衬底基板110的顶端225在衬底基板110上的正投影与发光部185在衬底基板110上的正投影的边缘间隔设置。如图21所示，在采用精细金属掩膜进行蒸镀工艺以形成上述的发光部时，精细金属掩膜250的开口边缘252处于悬空状态，与隔垫物220没有接触。因此，该显示基板可避免精细金属掩膜的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物，从而可进一步地提高显示基板的稳定性、信赖性和产品的良率。
在一些示例中，如图20所示，多个发光部185包括多个发光组1850，多个发光组1850沿第一方向排列以形成多个发光组列280，沿第二方向排列以形成多个发光组行290；各发光组1850包括一个第一发光部1851、一个第二发光部1852、一个第三发光部1853和一个第四发光部1854；相邻的两个发光组行290错位1/2节距设置，上述的节距等于在第一方向相邻的两个发光组1850中两个第一发光部1851的中心之间的距离；第二发光部1852和第三发光部1853沿第二方向排列形成发光对1855，第一发光部1851、发光对1855和第四发光部1854沿第一方向排列。如图20所示，隔垫物220的顶端225在衬底基板110上的正投影位于一个发光组1850中的第一发光部1851在衬底基板110上的正投影和第三发光部1853在衬底基板110上的正投影，和在第二方向相邻的另个一个发光组1850中的第二发光部1852和第四发光部1854在衬底基板110上的正投影之间。由此，该显示基板可保证隔垫物220的顶端225在衬底基板110上的正投影与第一发光部1851、第二发光部1852、第三发光部1853和第四发光部1854在衬底基板110上的正投影均间隔设置，并充分利用显示基板上的空间。
例如，第一方向和第二方向大致垂直。需要说明的是，上述的第一方向和第二方向大致垂直包括第一方向和第二方向之间的夹角为90度的情况，也包括第一方向和第二方向之间的夹角范围在85-95度的情况。
例如，如图20所示，在该显示基板100中，在第二方向上相邻的两个发光组1850可为第一发光组1850A和第二发光组1850B，隔垫物220的顶端225在衬底基板110上的正投影位于第一发光组1850A的第一发光部1851在衬底基板110上的正投影、第一发光组1850A的第三发光部1853在衬底基板110上的正投影、第二发光组1850B的第二发光部1852在衬底基板110上的正投影和第二发光组1850B的第四发光部1854在衬底基板110上的正投影之间。由此，该显示基板可保证隔垫物220的顶端225在衬底基板110上的正投影与第一发光部1851、第二发光部1852、第三发光部1853和第四发光部1854在衬底基板110上的正投影均间隔设置，并充分利用显示基板上的空间。
例如，隔垫物220在衬底基板110上的正投影可为长度为20微米，宽度为9.5微米的矩形。此时，隔垫物220在衬底基板110上的正投影与第一发光组1850A的第三阳极1753在衬底基板110上的正投影之间的距离范围可为8.5-9.5微米，例如8.9微米；隔垫物220在衬底基板110上的正投影与第二发光组1850B的第四阳极1754在衬底基板110上的正投影之间的距离范围可为6-7微米，例如6.3微米。
例如，隔垫物220在衬底基板110上的正投影与第一发光组1850A的第三发光部1853在衬底基板110上的正投影之间的距离范围可为0微米，甚至相互交叠。隔垫物220在衬底基板110上的正投影与第二发光组1850B的第二发光部1852在衬底基板110上的正投影之间的距离范围可为0微米，甚至相互交叠。
在一些示例中，如图20和图21所示，该显示基板100还包括阳极层170和像素限定层190；阳极层170位于衬底基板110和隔垫物220之间，像素限定层190位于阳极层170靠近隔垫物220的一侧。阳极层170包括多个阳极175，像素限定层190包括多个开口195以暴露多个阳极175。多个阳极175与多个发光部185对应设置，多个开口195与多个发光部185对应设置，多个开口195包括多个开口组1950，各开口组1950包括一个第一开口1951、一个第二开口1952、一个第三开口1953和一个第四开口1954，多个阳极175与多个发光部185对应设置，多个阳极175包括多个阳极组1750，各阳极组1750包括一个第一阳极1751、一个第二阳极1752、一个第三阳极1753和一个第四阳极1754；第一发光部1851至少部分位于第一开口1951中并覆盖暴露的第一阳极1751，第二发光部1852至少部分位于第二开口1952中并覆盖暴露的第二阳极1752，第三发光部1853至少部分位于第三开口1953中并覆盖暴露的第三阳极1753，第四发光部1854至少部分位于第四开口1954中并覆盖暴露的第四阳极1754。
例如，如图20和图21所示，隔垫物220在衬底基板110上的正投影可与第一阳极1751在衬底基板110上的正投影部分重叠。
例如，如图20和图21所示，第一虚拟直线与隔垫物220的长度方向平行且经过隔垫物220的中心；第一开口1951在衬底基板110上的正投影的形状大致为椭圆形，该椭圆形在长轴方向的顶点到第一虚拟直线的距离与第一开口1951到第一虚拟直线的最短距离的比值的范围是：1.5-1。
例如，第一开口1951和第二开口1952之间的距离范围为20-25微米；第一开口1951 和第三开口1953之间的距离也为20-25微米；第一开口1951与第四开口1954之间的距离范围也为20-25微米。当然，本公开实施例包括但不限于此，各个开口之间的距离可根据实际的产品尺寸确定。
在一些示例中，如图20和图21所示，隔垫物220在衬底基板110上的正投影与第一开口1951在衬底基板110上的垫块设置。由此，在本公开实施例提供的显示基板的制作过程中，在采用精细金属掩膜进行蒸镀工艺以形成上述的发光部时，该显示基板可避免精细金属掩膜的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物。
例如，如图20和图21所示，隔垫物220在衬底基板110上的正投影与第一开口1951在衬底基板110上的正投影间隔设置。
在一些示例中，如图20和图21所示，第一开口1951在衬底基板110上的正投影的形状为近似椭圆形，隔垫物220在衬底基板110上的正投影的形状为矩形；第一开口1951在衬底基板110上的正投影的形状的长轴方向与隔垫物220在衬底基板110上的正投影的延伸方向之间的夹角范围为20-70度。
在一些示例中，如图20和图21所示，该显示基板100还包括像素电路层260；像素电路层260位于阳极层170靠近衬底基板110的一侧，且包括多个像素驱动电路265；多个像素驱动电路265与多个阳极175对应设置，各阳极175与对应的像素驱动电路265电性相连，第一阳极1751包括主体部1751A和与主体部1751A相连的连接部1751B，第一开口1951在衬底基板110上的正投影落入主体部1751A在衬底基板110上的正投影之内，连接部1751B与对应的像素驱动电路265电性相连。
在一些示例中，如图20和图21所示，隔垫物220在衬底基板110上的正投影与连接部1751B在衬底基板110上的正投影至少部分重叠。由此，该显示基板可在避免精细金属掩膜的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物的同时，并充分利用显示基板上的空间。
在一些示例中，如图20和图21所示，连接部1751B位于主体部1751A靠近相同发光组1850中的第三阳极1753和在第二方向相邻的发光组1850中的第四阳极1754所在的位置。
在一些示例中，第一开口1951限定的区域为第一子像素的第一有效发光区，第二开口1952限定的区域为第二子像素的第二有效发光区，第三开口1953限定的区域为第三子像素的第三有效发光区，第四开口1954限定的区域为第四子像素的第四有效发光区。由此，上述的多个发光组、多个开口组和多个阳极组分别对应多个像素结构。
在一些示例中，第一发光部被配置为发出第一颜色的光，第二发光部和第三发光部相连，并被配置为发出第二颜色的光，第四发光部被配置为发出第三颜色的光。
例如，第一颜色为红色(R)，第二颜色为绿色(G)，第三颜色为蓝色(B)。也就是说，该显示基板采用GGRB的像素排列结构。
图22为本公开一实施例提供的一种显示基板沿图20中EE方向的剖面示意图。如图22所示，在实际的制作过程中，通过精细金属掩膜形成的发光部185(例如第一发光层 1851和第四发光层1854)会扩散形成厚度较薄的扩散部(例如扩散部1851A和1854A)，导致最后得到的发光层185的尺寸大于精细金属掩膜的开口尺寸，从而会与隔垫物220发生交叠，甚至相邻的发光部会接触或者交叠。此时，上述的发光层是指发光层的厚度大于或等于扩散部的厚度的部分，而并不包括扩散部。
本公开一实施例还提供一种显示装置。图23为根据本公开一实施例提供的一种显示装置的示意图。如图23所示，该显示装置400包括上述任一项的显示基板100。由此，该显示装置具有与该显示基板的有益效果对应的有益效果。例如，该显示装置可避免在制作过程中精细金属掩膜的开口边缘252与隔垫物的顶端接触，并避免产生颗粒物等异物，从而可提高显示基板的稳定性、信赖性和产品的良率。
例如，该显示装置可为电视、电脑、笔记本电脑、平坦电脑、手机、导航仪、电子相框等具有显示功能的电子产品。
本公开一实施例还提供一种显示基板的制作方法。图24为根据本公开一实施例提供的一种显示基板的制作方法。如图24所示，该显示基板的制作方法包括以下步骤S101-S103。
步骤S101：在衬底基板上形成像素限定层，包括多个开口。
例如，衬底基板可采用石英基板、玻璃基板、塑料基板等；像素限定层可采用气相沉积工艺制作，多个开口可通过刻蚀工艺制作。当然，本公开实施例包括但不限于此。
步骤S102：在像素限定层远离衬底基板的一侧形成隔垫物。
例如，隔垫物可与像素限定层采用同一膜层经过半色调掩膜或灰色调掩膜形成，从而可节省掩膜工艺，降低成本。例如，可先在衬底基板上形成用于形成像素限定层和隔垫物的层结构；然后利用半色调掩膜或灰色调掩膜在层结构远离衬底基板的一侧形成第一光刻胶图案，该第一光刻胶图案包括完全保留部分、部分保留部分和完全去除部分；利用第一光刻胶图案对层结构进行刻蚀(例如湿刻工艺)，将完全去除部分对应的层结构去除，从而形成像素限定层的多个开口；然后对第一光刻胶图案进行灰化工艺，去除部分保留部分以形成第二光刻胶图案；利用第二光刻胶图案对层结构进行进一步刻蚀，以在完全保留部分对应的层结构处形成隔垫物，在部分保留部分对应的层结构处形成像素限定层。当然，本公开实施例包括但不限于此，隔垫物也可单独形成。
步骤S103：在隔垫物远离衬底基板的一侧放置掩膜板，并以掩膜板为掩膜在多个开口中蒸镀发光材料以形成包括多个发光部的发光层，掩膜板包括多个掩膜开口，隔垫物远离衬底基板的顶端在衬底基板上的正投影与掩膜开口在衬底基板上的正投影的边缘间隔设置。
在本公开实施例提供的显示基板的制作过程中，在隔垫物远离衬底基板的一侧放置掩膜板，并以掩膜板为掩膜在多个开口中蒸镀发光材料以形成包括多个发光部的发光层时，掩膜板的开口边缘在衬底基板上的正投影与隔垫物的顶端在衬底基板上的正投影间隔设置；从而可避免掩膜板的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物。由此，该显示基板的制作方法可提高显示基板的稳定性、信赖性和产品的良率。
在一些示例中，上述的掩膜板为精细金属掩膜(FMM)。
在一些示例中，隔垫物在衬底基板上的正投影的形状为矩形，隔垫物在长度方向上的中轴线在衬底基板上的正投影与发光部在衬底基板上的正投影的边缘间隔设置。由此，该显示基板的制作方法可避免精细金属掩膜的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物，从而可提高显示基板的稳定性、信赖性和产品的良率。
在一些示例中，隔垫物在衬底基板上的正投影与发光部在衬底基板上的正投影的边缘间隔设置。由此，该显示基板可进一步地避免精细金属掩膜的开口边缘与隔垫物的顶端接触，并避免产生颗粒物等异物，从而可进一步地提高显示基板的稳定性、信赖性和产品的良率。
图25-图27为根据本公开一实施例提供的一种掩膜板组的平面示意图。如图25-图27所示，该掩膜板组包括第一掩膜板510、第二掩膜板520和第三掩膜板530；第一掩膜板510包括多个第一掩膜开口412，各第一掩膜开口412用于形成上述的第一发光部1851；第二掩膜板520包括多个第二掩膜开口422，各第二掩膜开口422用于形成上述的第二发光部1852和第三发光部1853，也就是说，第二发光部1852和第三发光部1853可通过同一掩膜开口形成；第三掩膜板530包括多个第三掩膜开口432，各第三掩膜开口432用于形成上述的第四发光部1854。
例如，如图25-图27所示，在该显示基板的制作方法中，上述的步骤S103可包括：如图25所示，在隔垫物220远离衬底基板110的一侧放置第一掩膜板510，并以第一掩膜板510为掩膜在多个开口1951中蒸镀发光材料以形成多个第一发光部1851；撤去第一掩膜板510；如图26所示，在隔垫物220远离衬底基板110的一侧放置第二掩膜板520，并以第二掩膜板520为掩膜在多个开口1951和1952中蒸镀发光材料以形成多个第二发光部1852和多个第三发光部1853；撤去第二掩膜板520；如图27所示，在隔垫物220远离衬底基板110的一侧放置第三掩膜板530，并以第三掩膜板530为掩膜在多个开口1954中蒸镀发光材料以形成多个第四发光部1854。
例如，如图25-图27所示，隔垫物220远离衬底基板110的顶端在衬底基板110上的正投影与第一发光部1851或者第四发光部1854在衬底基板110上的正投影的边缘间隔设置。
另一方面，随着有机发光二极管(OLED)显示技术的不断发展，人们对显示效果的要求也越来越高。在研究中，本申请的发明人注意到：影响有机发光二极管显示装置的显示效果的因素有很多，其中栅极层的负载(Loading)的大小影响像素驱动电路的充电时间，而像素驱动电路的充电时间对显示效果的影响较大。通常，栅极层的负载主要是由栅线和复位信号线的负载构成。另一方面，数据线(或源极线)的负载的大小直接关系到IC的功耗，数据线的负载越大，对IC驱动的要求则越高，从而使得IC的功耗也越大。因此，控制栅线和复位信号线之间的负载和数据线上的负载可提高有机发光二极管显示装置的显示效果，并可降低有机发光二极管显示装置的功耗。
对此，本公开实施例提供一种显示基板和显示装置。该显示基板包括衬底基板、第 一栅极层、第二栅极层和第一导电层；第一栅极层位于衬底基板上，第二栅极层位于第一栅极层远离衬底基板的一侧；第一导电层位于第二栅极层远离衬底基板的一侧；第一栅极层包括沿第一方向延伸的复位信号线和第一电极块，第二栅极层包括第二电极块，第二电极块被配置为与第一电极块形成存储电容，第一导电层包括沿第二方向延伸的电源线，复位信号线与电源线具有第一交叠区域，第二电极块与电源线具有第二交叠区域，位于第一交叠区域的电源线的宽度小于位于第二交叠区域的电源线的宽度，第一方向与第二方向相交。由此，通过减小复位信号线与电源线交叠的第一交叠区域中的电源线的宽度，该显示基板可降低复位信号线的负载，从而可提高像素驱动电路的充电时间，进而提高该显示基板的显示效果。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图28A为本公开一实施例提供的另一种显示基板的局部示意图；图28B为本公开一实施例提供的另一种显示基板的局部示意图；图29为本公开一实施例提供的一种显示基板沿图28A中FF方向的剖面示意图。为了清楚地示出该显示基板中的像素驱动电路结构中各个膜层的层叠结构，图28B省去了阳极层和第二导电层。
如图28A、图28B和图29所示，该显示基板100包括衬底基板110、第一栅极层130、第二栅极层140和第一导电层150；第一栅极层130位于衬底基板110上，第二栅极层140位于第一栅极层130远离衬底基板110的一侧；第一导电层150位于第二栅极层140远离衬底基板110的一侧。第一栅极层130包括沿第一方向延伸的复位信号线131和第一电极块CE1；第二栅极层140包括第二电极块CE2，第二电极块CE2被配置为与第一电极块CE1形成存储电容；第一导电层150包括沿第二方向延伸的电源线151，复位信号线131与电源线151具有第一交叠区域351，第二电极块CE2与电源线151具有第二交叠区域352，位于第一交叠区域351的电源线151的宽度小于位于第二交叠区域352的电源线151的宽度。也就是说，电源线151在第一交叠区域351的宽度进行了缩小设计；第一方向与第二方向相交，例如相互垂直。需要说明的是，上述的电源线的宽度是指电源线沿第一方向上的尺寸，相应地，电源线的长度是电源线沿第二方向上的尺寸。
在本公开实施例提供的显示基板中，减小复位信号线与电源线交叠的第一交叠区域中的电源线的宽度可减小复位信号线和电源线的重叠面积，从而可减小复位信号线和电源线之间的寄生电容的大小。由此，通过减小复位信号线与电源线交叠的第一交叠区域中的电源线的宽度，该显示基板可降低复位信号线的负载，从而可提高像素驱动电路的充电时间，进而提高该显示基板的显示效果。
在一些示例中，第一导电层可为第一源漏金属层，该显示基板还可以包括第二导电层，即第二源漏金属层。需要说明的是，为了清楚地示出显示基板上的膜层结构，图28A示出的显示基板没有示出第二导电层(第二源漏金属层)；当然，本公开实施例包括但不限于此，该显示基板也可不包括第二导电层，为单层源漏金属层的显示基板。
在一些示例中，位于第一交叠区域351的电源线151的宽度小于电源线151的平均 宽度。
在一些示例中，如图28A和图28B所示，在第一交叠区域351的电源线151的宽度小于电源线151的最大宽度的5/7。由此，该显示基板可有效地降低复位信号线的负载。
在一些示例中，如图28B所示，电源线151包括主体延伸部151A和缩窄部151B，缩窄部151B的宽度小于主体延伸部151A的宽度，缩窄部151B在衬底基板110上的正投影与复位信号线131在衬底基板110上的正投影交叠。
在一些示例中，如图28A和图28B所示，第一栅极层130还包括沿第一方向延伸的栅线132，栅线132与电源线151具有第三交叠区域353，在第三交叠区域353的电源线151的宽度小于位于第二交叠区域352的电源线151的宽度。也就是说，第三交叠区域的电源线的宽度也进行了缩小设计。由此，通过减小栅线与电源线交叠的第二交叠区域中的电源线的宽度，该显示基板可降低栅线的负载，从而可进一步提高像素驱动电路的充电时间，进而提高该显示基板的显示效果。
在一些示例中，在第三交叠区域353的电源线151的宽度小于电源线151的平均宽度。
在一些示例中，如图28A和图28B所示，在第三交叠区域353的电源线151的宽度小于电源线151的最大宽度的5/7。由此，该显示基板可有效地降低复位信号线的负载。
在一些示例中，如图28B所示，电源线151包括主体延伸部151A和缩窄部151B，缩窄部151B的宽度小于主体延伸部151A的宽度，缩窄部151B在衬底基板110上的正投影与栅线132在衬底基板110上的正投影交叠。
在一些示例中，如图28A和图28B所示，第一导电层150还包括沿第二方向延伸的数据线152，数据线152与复位信号线131具有第四交叠区域354，在第四交叠区域354的复位信号线131的宽度小于复位信号线131的平均宽度。在该显示基板中，减小第四交叠区域的复位信号线的宽度可减小复位信号线和数据线的重叠面积，从而可减小复位信号线和数据线之间的寄生电容的大小。由此，通过减小第四交叠区域的复位信号线的宽度，该显示基板可降低数据线的负载，从而可降低驱动功耗，进而降低该显示基板的功耗。需要说明的是，上述的复位信号线的宽度是指复位信号线沿第二方向上的尺寸，相应地，复位信号线的长度是复位信号线沿第一方向上的尺寸。
在一些示例中，如图28A和图28B所示，在第四交叠区域354的复位信号线131的宽度小于复位信号线131的最大宽度的3/4。由此，该显示基板可有效地降低数据线的负载。
在一些示例中，如图28A和图28B所示，该显示基板100还包括半导体层120，位于第一栅极层130靠近衬底基板110的一侧，第二栅极层140包括沿所述第一方向延伸的初始化信号线141，数据线152与初始化信号线141具有第五交叠区域355，初始化信号线141与半导体层120具有第六交叠区域356，位于第五交叠区域355的初始化信号线141的宽度小于位于第六交叠区域356的初始化信号线141的宽度。在该显示基板中，减小第五交叠区域的初始化信号线的宽度可减小初始化信号线和数据线的重叠面积，从而 可减小初始化信号线和数据线之间的寄生电容的大小。由此，通过减小第五交叠区域的初始化信号线的宽度，该显示基板可进一步降低数据线的负载，从而可降低驱动功耗，进而降低该显示基板的功耗。需要说明的是，上述的初始化信号线的宽度是指初始化信号线沿第二方向上的尺寸，相应地，初始化信号线的长度是初始化信号线沿第一方向上的尺寸。
在一些示例中，位于第四交叠区域354的初始化信号线141的宽度小于初始化信号线141的平均宽度。
例如，如图28B所示，与复位信号线131交叠的缩窄部151B在衬底基板上110的正投影同时还与初始化信号线141在衬底基板110上的正投影交叠。
在一些示例中，如图28B所示，电源线151包括主体延伸部151A和缩窄部151B，缩窄部151B的宽度小于主体延伸部151A的宽度，缩窄部151B在衬底基板110上的正投影与半导体层110在衬底基板110上的正投影不交叠。
在一些示例中，如图28B所示，第二栅极层140还包括导电块143，主体延伸部151A包括与导电块143相连的连接部151C，连接部151C在衬底基板110上正投影与半导体层110在衬底基板110上的正投影部分交叠，连接部151C与缩窄部151B在第二方向上相邻。
例如，如图28B所示，连接部151C可位于两个缩窄部151B之间。
在一些示例中，如图28A和图28B所示，在第四交叠区域354的初始化信号线141的宽度小于初始化信号线151的最大宽度的3/4。由此，该显示基板可有效地降低数据线的负载。
例如，半导体层120可采用硅基半导体材料，例如多晶硅。当然，本公开实施例包括但不限于此，半导体层还可采用半导体材料。
图30A-图30D为本公开一实施例提供的一种显示基板中多个膜层的平面示意图；图31为本公开一实施例提供的一种显示基板中的像素驱动电路的等效示意图。
例如，如图30A所示，半导体层120包括第一单元121、第二单元122、第三单元123、第四单元124、第五单元125、第六单元126和第七单元127；第一单元121包括第一沟道区C1和位于第一沟道区C1两侧的第一源极区S1和第一漏极区D1，第二单元122包括第二沟道区C2和位于第二沟道区C2两侧的第二源极区S2和第二漏极区D2，第三单元123包括第三沟道区C3和位于第三沟道区C3两侧的第三源极区S3和第三漏极区D3，第四单元124包括第四沟道区C4和位于第四沟道区C4两侧的第四源极区S4和第四漏极区D4，第五单元125包括第五沟道区C5和位于第五沟道区C5两侧的第五源极区S5和第五漏极区S5，第六单元126包括第六沟道区C6和位于第六沟道区C6两侧的第六源极区S6和第六漏极区D6，第七单元127包括第七沟道区C7和位于第七沟道区C7两侧的第七源极区S7和第七漏极区D7。
例如，如图30A和图31所示，第六漏极区D6和第三漏极区D3相连，第三源极区S3、第一漏极区D1和第五源极区S5连接至第一节点N1，第一源极区S1、第二漏极区 D2和第四漏极区D4连接至第二节点N2，第五漏极区D5和第七漏极区D7相连。
例如，如图30B所示，第一栅极层130包括沿第一方向延伸的复位信号线131、沿第一方向延伸的栅线132、第一电极块CE1和沿第一方向延伸的发射控制线133。
例如，如图30C所示，第二栅极层140包括沿第一方向延伸的初始化信号线141、第二电极块CE2和导电块143。例如，导电块143可与电源线相连，从而降低电源线的电阻。
如图31所示，第六源极区S6和第七源极区S7与初始化信号线141相连；第一电极块CE1和第二电极块CE2可形成存储电容Cst。
例如，如图30D所示，第一导电层150包括沿第二方向延伸的电源线151和数据线152、第一连接块1541、第二连接块1542和第三连接块1543。第一连接块1541用于将初始化信号线141与第六源极区S6和第七源极区S7相连；第二连接块1542用于将第三漏极区D3与第一电极块CE1相连；第三连接块1543与第五漏极区D5相连，可作为漏极与对应的阳极相连。
例如，如图31所示，第二源极区S2与数据线152相连；第四源极区S4与电源线151相连。由此，半导体层120的第一单元121、第二单元122、第三单元123、第四单元124、第五单元125、第六单元126和第七单元127可与上述的复位信号线131和栅线132形成第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5、第六薄膜晶体管T6和第七薄膜晶体管T7。
下面将对图31所示的像素驱动电路的一种工作方式进行示意性描述。首先，当向复位信号线131传输复位信号并使得第七薄膜晶体管T7导通时，流经各个子像素的阳极的剩余电流通过第七薄膜晶体管T7放电到第六薄膜晶体管T6，从而可抑制由于流经各个子像素的阳极的剩余电流导致的发光。然后，当向复位信号线131传输复位信号并向初始化信号线141传输初始化信号时，第六薄膜晶体管T6导通，并且通过第六薄膜晶体管T6向第一薄膜晶体管T1的第一栅极和存储电容Cst的第一电极块CE1施加初始化电压Vint，使得第一栅极和存储电容Cst初始化。第一栅极初始化可使得第一薄膜晶体管T1导通。
随后，当向栅线132传输栅极信号并向数据线152传输数据信号时，第二薄膜晶体管T2和第三薄膜晶体管T3都导通，通过第二薄膜晶体管T2和第三薄膜晶体管T3向第一栅极施加数据电压Vd。此时，施加到第一栅极的电压是补偿电压Vd+Vth，并且施加到第一栅极的补偿电压也被施加到存储电容Cst的第一电极块CE1。
随后，电源线151向存储电容Cst的第二电极块CE2施加驱动电压Vel，向第一电极块CE1施加补偿电压Vd+Vth，使得与分别施加到存储电容Cst的两个电极的电压之间的差对应的电荷存储在存储电容Cst中，第一薄膜晶体管T1导通达到预定时间。
随后，当向发射控制线133施加发射控制信号时，第四薄膜晶体管T4和第五薄膜晶体管T5都导通，使得第四薄膜晶体管T4向第五薄膜晶体管T5施加驱动电压Vel。驱动电压Vel穿过由存储电容Cst导通的第一薄膜晶体管T1时，对应的驱动电压Vel与通过 存储电容Cst向第一栅极施加的电压之间的差驱动电流Id流经第一薄膜晶体管T1的第一漏极区D3，驱动电流Id通过第五薄膜晶体管T5施加到各个子像素，使得各个子像素的发光层发光。
在一些示例中，如图29和图31所示，该显示基板100还包括第一平坦层241、第二导电层160、第二平坦层242和阳极175；第一平坦层241位于第一导电层150远离衬底基板110的一侧；第二导电层160位于第一平坦层241远离第一导电层150的一侧，且包括连接电极161；第二平坦层242位于第二导电层160远离第一平坦层241的一侧；阳极175位于第二平坦层242远离第二导电层160的一侧，第一平坦层241包括第一过孔H1，连接电极161通过第一过孔H1与第五漏极区S5相连，第二平坦层242包括第二过孔H2，阳极175通过第二过孔H2与连接电极161相连。
本公开一实施例还提供一种显示装置。图32为根据本公开一实施例提供的一种显示装置的示意图。如图32所示，该显示装置400包括上述任一项的显示基板100。由此，该显示装置具有与该显示基板的有益效果对应的有益效果。例如，该显示装置可降低栅极层的负载，从而可提高像素驱动电路的充电时间，进而提高该显示基板的显示效果。
例如，该显示装置可为电视、电脑、笔记本电脑、平坦电脑、手机、导航仪、电子相框等具有显示功能的电子产品。
另一方面，有机发光二极管(OLED)显示装置的长期发光稳定性也是有机发光二极管显示装置的一个重要的规格或指标。在研究中，本申请的发明人注意到：影响有机发光二极管显示装置的长期发光稳定性的因素有很多，除了发光材料本身的寿命之外，像素驱动电路中的薄膜晶体管的工作状态对发光亮度和长期发光稳定性都有一定程度的影响。
对此，本公开实施例提供一种显示基板和显示装置。该显示基板包括衬底基板、像素电路层和阳极层；像素电路层位于衬底基板上且包括多个像素驱动电路；阳极层位于像素电路层远离衬底基板的一侧且包括多个阳极。多个像素驱动电路与多个阳极一一对应设置，各像素驱动电路包括功能薄膜晶体管；多个像素驱动电路包括相邻设置的第一像素驱动电路和第二像素驱动电路，第一像素驱动电路中的功能薄膜晶体管的沟道区和第二像素驱动电路中的功能薄膜晶体管的沟道区在衬底基板上的正投影均与第一像素驱动电路对应的阳极在衬底基板上的正投影交叠。由此，该显示基板通过阳极对第一像素驱动电路中的功能薄膜晶体管的沟道区和第二像素驱动电路中的功能薄膜晶体管的沟道区同时进行遮挡，从而可提高功能薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
下面，结合附图对本公开实施例提供的显示基板和显示装置进行详细的说明。
本公开一实施例提供一种显示基板。图33为本公开一实施例提供的一种显示基板的局部示意图；图34为本公开一实施例提供的一种显示基板沿图33中KK方向的剖面示意图；图35A为本公开一实施例提供的一种显示基板沿图33中MM方向的剖面示意图；图35B为本公开一实施例提供的一种显示基板沿图33中NN方向的剖面示意图；图35C 为本公开一实施例提供的一种显示基板沿图33中QQ方向的剖面示意图。
如图33和图34所示，该显示基板100包括衬底基板110、像素电路层260和阳极层170；像素电路层260位于衬底基板110上且包括多个像素驱动电路265；阳极层170位于像素电路层260远离衬底基板110的一侧且包括多个阳极175。多个像素驱动电路265与多个阳极175一一对应设置，各像素驱动电路256包括功能薄膜晶体管，例如补偿薄膜晶体管T3；多个像素驱动电路265包括相邻设置的第一像素驱动电路2657和第二像素驱动电路2658，第一像素驱动电路2657中的补偿薄膜晶体管T3的沟道区和第二像素驱动电路2658中的补偿薄膜晶体管T3的沟道区在衬底基板110上的正投影均与第一像素驱动电路2657对应的阳极175在衬底基板110上的正投影交叠。需要说明的是，上述的第一像素驱动电路和第二像素驱动电路中的“第一”和“第二”仅用于在文字上将两个像素驱动电路进行区分，这两个像素驱动电路的具体结构相同；另外，上述的功能薄膜晶体管也可为像素驱动电路中的其他的薄膜晶体管。
在本公开实施例提供的显示基板中，由于第一像素驱动电路2657中的补偿薄膜晶体管T3的沟道区和第二像素驱动电路2658中的补偿薄膜晶体管T3的沟道区在衬底基板110上的正投影均与第一像素驱动电路2657对应的阳极175在衬底基板110上的正投影交叠，第一像素驱动电路2657对应的阳极175则可对第一像素驱动电路2657中的补偿薄膜晶体管T3的沟道区和第二像素驱动电路2658中的补偿薄膜晶体管T3的沟道区进行部分遮挡或完全遮挡。由此，该显示基板可提高第一像素驱动电路中的补偿薄膜晶体管T3和第二像素驱动电路2658中的补偿薄膜晶体管T3的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。图30A-图30D为本公开一实施例提供的一种显示基板中多个膜层的平面示意图；图31为本公开一实施例提供的一种显示基板中的像素驱动电路的等效示意图。该像素驱动电路采用7T1C的像素驱动结构，在发光阶段，N3节点的电压可控制第一薄膜晶体管T1(即驱动薄膜晶体管)的开启关断状态，而第一薄膜晶体管T1的稳定性直接影响了有机发光二极管显示装置的长期发光稳定性；在充电阶段，N3节点的充电电压与第三薄膜晶体管T3(即补偿薄膜晶体管)、第一薄膜晶体管T1和第二薄膜晶体管T2的状态有关。通常，薄膜晶体管对光照特别敏感，当薄膜晶体管(特别是沟道区)受到光照时容易使得薄膜晶体管的特性产生漂移，影响像素驱动电路的正常工作。本公开实施例通过阳极对补偿薄膜晶体管的沟道区进行遮挡，可提高补偿薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
在一些示例中，如图33-图35C所示，第一像素驱动电路2657中的补偿薄膜晶体管T3的沟道区和第二像素驱动电路2658中的补偿薄膜晶体管T3的沟道区均落入第一像素驱动电路2657对应的阳极175(即第四阳极1754)在衬底基板110上的正投影，第一像素驱动电路2657对应的阳极175则可对第一像素驱动电路2657中的补偿薄膜晶体管T3的沟道区和第二像素驱动电路2658中的补偿薄膜晶体管T3的沟道区进行完全遮挡，从而进一步提高补偿薄膜晶体管的稳定性和寿命，进而可提高该显示基板的长期发光稳定性和寿命。
在一些示例中，如图30A所示，补偿薄膜晶体管T3可为双栅结构的薄膜晶体管，从而可提高补偿薄膜晶体管的可靠性。补偿薄膜晶体管T3的沟道区包括间隔设置的第一沟道区C1和第二沟道区C2，补偿薄膜晶体管T3还包括位于第一沟道区C1和第二沟道区C2之间的共用电极SE。如图33-图35B所示，第一像素驱动电路2657中的补偿薄膜晶体管T3的共用电极SE和第二像素驱动电路2658中的补偿薄膜晶体管T3的共用电极SE在衬底基板110上的正投影均与第一像素驱动电路2657对应的阳极175在衬底基板110上的正投影交叠。由此，第一像素驱动电路2657对应的阳极175则可对第一像素驱动电路2657中的补偿薄膜晶体管T3的共用电极SE和第二像素驱动电路2658中的补偿薄膜晶体管T3的共用电极SE进行部分遮挡或完全遮挡，从而进一步提高补偿薄膜晶体管的稳定性和寿命，进而可提高该显示基板的长期发光稳定性和寿命。
图36为本公开一实施例提供的另一种显示基板的平面示意图。如图36所示，多个阳极175包括多个阳极组1750，各阳极组1750包括一个第一阳极1751、一个第二阳极1752、一个第三阳极1753和一个第四阳极1754。需要说明的是，上述的第一阳极、第二阳极、第三阳极和第四阳极可为不同形状和不同颜色子像素的阳极。当然，本公开实施例包括但不限于此，上述的第一阳极、第二阳极、第三阳极和第四阳极中的至少两个可为相同形状和相同颜色子像素的阳极。
在一些示例中，如图36所示，多个阳极175包括多个阳极组1750，多个阳极组1750沿第一方向排列以形成多个阳极组列380，沿第二方向排列以形成多个阳极组行390，各阳极组1750包括一个第一阳极1751、一个第二阳极1752、一个第三阳极1753和一个第四阳极1754；相邻的两个阳极组行390错位1/2节距设置，节距等于在第一方向相邻的两个阳极组1750中两个第一阳极1751的中心之间的距离。第二阳极1752和第三阳极1753沿第二方向排列以形成阳极对1755，第一阳极1751、阳极对1755和第四阳极1754沿第二方向排列。由此，该显示基板可提供一种像素排列结构，从而可提高采用该显示基板的显示装置的显示效果。需要说明的是，本公开实施例提供的阳极组包括但不限于上述的像素排列结构；另外，上述的第一阳极的中心是指第一阳极的主体部的中心，也即第一阳极对应的第一发光元件的有效发光区。例如，第一方向和第二方向大致垂直。需要说明的是，上述的第一方向和第二方向大致垂直包括第一方向和第二方向之间的夹角为90度的情况，也包括第一方向和第二方向之间的夹角范围在85-95度的情况。
在一些示例中，如图33所示，第一像素驱动电路2657和第二像素驱动电路2658沿所述第一方向设置，一个阳极组1750中的第四阳极1754与第一像素驱动电路2657对应设置且电性相连，另一个阳极组1750中的第二阳极1752与第二像素驱动电路2658对应设置且电性相连。
在一些示例中，如图33、图34和图36所示，该显示基板100还包括像素限定层190；像素限定层190位于阳极层170远离衬底基板110的一侧且包括多个开口195；多个开口195包括多个开口组1950，各开口组1950包括一个第一开口1951、一个第二开口1952、一个第三开口1953和一个第四开口1954，第一开口1951与第一阳极1751对应设置并暴 露第一阳极1751，第二开口1952与第二阳极1752对应设置并暴露第二阳极1752，第三开口1953与第三阳极1753对应设置并暴露第三阳极1753，第四开口1954与第四阳极1754对应设置并暴露第四阳极1754。
如图33和图36所示，第一阳极1751包括第一主体部1751A和第一连接部1751B，第一开口1951在衬底基板110上的正投影落入第一主体部1751A在衬底基板110上的正投影，第一连接部1751B与第一阳极1751对应的像素驱动电路265相连；第二阳极1752包括第二主体部1752A和第二连接部1752B，第二开口1952在衬底基板110上的正投影落入第二主体部1752A在衬底基板110上的正投影，第二连接部1752B与第二阳极1752对应的像素驱动电路265相连；第三阳极1753包括第三主体部1753A和第三连接部1753B，第三开口1953在衬底基板110上的正投影落入第三主体部1753A在衬底基板110上的正投影，第三连接部1753B与第三阳极1753对应的像素驱动电路265相连；第四阳极1754包括第四主体部1754A和第四连接部1754B，第四开口1954在衬底基板110上的正投影落入第四主体部1754A在衬底基板110上的正投影，第四连接部1754B与第四阳极1754对应的像素驱动电路265(例如，上述的第一像素驱动电路2657)相连。
在一些示例中，如图33和图36所示，第一主体部1751A的形状与第一开口1951的形状大致相同；第二主体部1752A的形状与第二开口1952的形状大致相同；第三主体部1753A的形状与第三开口1953的形状大致相同；第四主体部1754A的形状与第四开口1954的形状大致相同。例如，当第四开口1954的形状为六边形时，第四主体部1754A的形状也为六边形。当然，第四开口和第四主体部的形状也不限于六边形，例如还可为椭圆形等其他形状。
例如，如图33-图36所示，第四阳极1754还包括第一增补部1754C，第四阳极1754对应的第一像素驱动电路2657中的补偿薄膜晶体管T3的第一沟道区C31和第二沟道区C32在衬底基板110上正投影分别与第一增补部1754C在衬底基板110上的正投影交叠。在该显示基板中，通过在第四阳极增加第一增补部，使得第四阳极可以覆盖对应的像素驱动电路中的补偿薄膜晶体管的两个沟道区，从而可提高补偿薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
在一些示例中，如图33-图36所示，第一增补部1754C从第四主体部1754A向第三阳极1753凸出，第一增补部1754C位于第四连接部1754B靠近第四主体部1754A的一侧。在一些示例中，如图33-图36所示，第一增补部1754C与第四主体部1754A和第四连接部1754B均相连。由此，该显示基板可充分利用显示基板上的面积，将第一阳极、第二阳极、第三阳极和第四阳极紧密地排列，从而可保证显示基板的分辨率。
例如，如图35A所示，第一增补部1754C在衬底基板110上的正投影与补偿薄膜晶体管T3的共用电极SE在衬底基板110上的正投影部分重叠。
例如，如图35A所示，第一增补部1754C在衬底基板110上的正投影覆盖补偿薄膜晶体管T3的第二沟道区C32在衬底基板110上的正投影。
例如，如图35A所示，第四主体部1754A在衬底基板110上的正投影覆盖补偿薄膜 晶体管T3的漏极区D3。例如，如图35C所示，第一导电层150包括第二连接块1542，第二连接块1542用于将补偿薄膜晶体管的漏极区与第一电极块CE1相连，第一电极块CE1可与第二电极块CE2形成存储电容，也同时作为驱动薄膜晶体管的栅极。由于第二阳极1752的连接部1752B向远离第三阳极1753的方向延伸并与上述的第二连接块1542交叠，甚至覆盖上述的第二连接块1542，连接部1752可稳定驱动薄膜晶体管的栅极和补偿薄膜晶体管的漏极上的电位，从而进一步提高该显示基板的长期发光稳定性和寿命。
图37A为根据本公开一实施例提供的另一种显示基板的局部示意图；图37B为根据本公开一实施例提供的另一种显示基板的局部示意图。为了清楚地表示各个阳极的形状，图37B仅示出了阳极层。
如图37A和图37B所示，第四阳极1754还包括第二增补部1754D；第二像素驱动电路2658中的补偿薄膜晶体管T3的第二沟道区C2在衬底基板110上的正投影与第二增补部1754D在衬底基板110上的正投影交叠。通过在第四阳极增加第二增补部，使得第四阳极可以部分甚至完全覆盖第二像素驱动电路2658中的补偿薄膜晶体管T3的第二沟道区C2，从而可提高补偿薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
在一些示例中，如图37A和图37B所示，第二增补部1754D从第四主体部1754A向在第一方向上相邻的阳极组1750中的第一阳极1751凸出。
需要说明的是，如图37A和图37B所示，第二像素驱动电路2658中的补偿薄膜晶体管T3的第一沟道区C1在衬底基板110上的正投影可落入第四主体部1754A在衬底基板110上的正投影。
在一些示例中，如图37A和图37B所示，第一像素驱动电路2657中的补偿薄膜晶体管T3的共用电极SE与第一增补部1754C在衬底基板110上的正投影交叠，第二像素驱动电路2658中的补偿薄膜晶体管T3的共用电极SE在衬底基板110上的正投影与第一像素驱动电路2657对应的第四阳极1754的第四主体部1754A在衬底基板110上的正投影交叠。
在一些示例中，如图37A和图37B所示，第一阳极1751对应的像素驱动电路265中的补偿薄膜晶体管T3的沟道区在衬底基板110上正投影落入第一主体部1751A在衬底基板110上的正投影。
在一些示例中，如图31所示，像素驱动电路265还包括驱动薄膜晶体管T1，驱动薄膜晶体管T1的栅极G1与补偿薄膜晶体管T3的漏极D3相连。如图37A所示，第一阳极1751还包括第三增补部1751C，从第一主体部1751A向第三阳极1753凸出，第一阳极1751对应的像素驱动电路265中的驱动薄膜晶体管T1的栅极G1和补偿薄膜晶体管T3的漏极D3在衬底基板110上正投影落入第三增补部1751C在衬底基板110上的正投影。由此，该显示基板可通过第三增补部1751C来稳定驱动薄膜晶体管T1的栅极G1和补偿薄膜晶体管T3的漏极D3上的电位，从而进一步提高该显示基板的长期发光稳定性和寿命。
在一些示例中，如图37A和图37B所示，第三阳极1753对应的像素驱动电路265中的补偿薄膜晶体管T3的第一沟道区C31在衬底基板110上正投影落入第三主体部1753A在衬底基板110上的正投影。
在一些示例中，如图37A和图37B所示，第三阳极1753还包括第四增补部1753C，第三阳极1753对应的像素驱动电路265中的补偿薄膜晶体管T3的第二沟道区C32在衬底基板110上正投影落入第四增补部1753C在衬底基板110上的正投影。由此，第三阳极的主体部和第四增补部可对第三阳极1753对应的像素驱动电路265中的补偿薄膜晶体管T3的第一沟道区C31和第二沟道区C32进行部分遮挡或完全遮挡，从而提高补偿薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
在一些示例中，如图33和图34所示，像素电路层260还包括半导体层120、第一栅极层130、第二栅极层140和第一导电层150；第一栅极层130位于半导体层120远离衬底基板110的一侧，第二栅极层140位于第一栅极层130远离衬底基板110的一侧，第一导电层150位于第二栅极层140远离衬底基板110的一侧。
例如，如图30A所示，半导体层120包括多个像素驱动单元1200，与多个阳极175对应设置，各像素驱动单元1200包括第一单元121、第二单元122、第三单元123、第四单元124、第五单元125、第六单元126和第七单元127；第一单元121包括第一沟道区C1和位于第一沟道区C1两侧的第一源极区S1和第一漏极区D1，第二单元122包括第二沟道区C2和位于第二沟道区C2两侧的第二源极区S2和第二漏极区D2，第三单元123包括第三沟道区C3和位于第三沟道区C3两侧的第三源极区S3和第三漏极区D3，第四单元124包括第四沟道区C4和位于第四沟道区C4两侧的第四源极区S4和第四漏极区D4，第五单元125包括第五沟道区C5和位于第五沟道区C5两侧的第五源极区S5和第五漏极区S5，第六单元126包括第六沟道区C6和位于第六沟道区C6两侧的第六源极区S6和第六漏极区D6，第七单元127包括第七沟道区C7和位于第七沟道区C7两侧的第七源极区S7和第七漏极区D7。
例如，如图30A和图31所示，第六漏极区D6和第三漏极区D3相连，第三源极区S3、第一漏极区D1和第五源极区S5连接至第一节点N1，第一源极区S1、第二漏极区D2和第四漏极区D4连接至第二节点N2，第五漏极区D5和第七漏极区D7相连。
例如，如图30B所示，第一栅极层130包括沿第一方向延伸的复位信号线131、沿第一方向延伸的栅线132、第一电极块CE1和沿第一方向延伸的发射控制线133。复位信号线131可与第七沟道区C7和第六沟道区C6交叠，以与第七单元127和第六单元126形成第七薄膜晶体管T7和第六薄膜晶体管T6，栅线132分别与第三沟道区C3和第二沟道区C2交叠，以与第三单元123和第二单元122形成第三薄膜晶体管T3和第二薄膜晶体管T2，第一电极块CE1与第一沟道区C1交叠，以与第一单元121形成第一薄膜晶体管T1，发射控制线133与第四沟道区C4和第五沟道区C5交叠，以与第四单元124和第五单元125形成第四薄膜晶体管T4和第五薄膜晶体管T5。可见，上述的第三薄膜晶体管T3为补偿薄膜晶体管。
例如，如图30B所示，复位信号线131、栅线132和发射控制线133均沿第一方向延伸，复位信号线131、栅线132、第一电极块CE1和发射控制线133沿第二方向排列。
例如，如图30C所示，第二栅极层140包括沿第一方向延伸的初始化信号线141、第二电极块CE2和导电块143。例如，导电块143可与电源线相连，从而降低电源线的电阻。另外，初始化信号线141与第七源极区S7和第一源极区S1相连，第二电极块CE2在衬底基板110上的正投影与第一电极块CE1在衬底基板110上的正投影至少部分重叠以形成存储电容Cst。需要说明的是，导电块也可起到一定的遮光作用；另外，图33最左侧的导电块仅示出了一部分，图33最左侧的导电块的形状与其他导电块的形状相同。
例如，如图30D所示，第一导电层150包括沿第二方向延伸的电源线151和数据线152、第一连接块1541、第二连接块1542和第三连接块1543。数据线152可与第二源极区S2相连，第四源极区S4与电源线151相连；第一连接块1541用于将初始化信号线141与第六源极区S6和第七源极区S7相连；第二连接块1542用于将第三漏极区D3与第一电极块CE1相连；第三连接块1543与第五漏极区D5相连，可作为漏极与对应的阳极相连。
下面将对图31所示的像素驱动电路的一种工作方式进行示意性描述。首先，当向复位信号线131传输复位信号并使得第七薄膜晶体管T7导通时，流经各个子像素的阳极的剩余电流通过第七薄膜晶体管T7放电到第六薄膜晶体管T6，从而可抑制由于流经各个子像素的阳极的剩余电流导致的发光。然后，当向复位信号线131传输复位信号并向初始化信号线141传输初始化信号时，第六薄膜晶体管T6导通，并且通过第六薄膜晶体管T6向第一薄膜晶体管T1的第一栅极和存储电容Cst的第一电极块CE1施加初始化电压Vint，使得第一栅极和存储电容Cst初始化。第一栅极初始化可使得第一薄膜晶体管T1导通。
随后，当向栅线132传输栅极信号并向数据线152传输数据信号时，第二薄膜晶体管T2和第三薄膜晶体管T3都导通，通过第二薄膜晶体管T2和第三薄膜晶体管T3向第一栅极施加数据电压Vd。此时，施加到第一栅极的电压是补偿电压Vd+Vth，并且施加到第一栅极的补偿电压也被施加到存储电容Cst的第一电极块CE1。
随后，电源线151向存储电容Cst的第二电极块CE2施加驱动电压Vel，向第一电极块CE1施加补偿电压Vd+Vth，使得与分别施加到存储电容Cst的两个电极的电压之间的差对应的电荷存储在存储电容Cst中，第一薄膜晶体管T1导通达到预定时间。
随后，当向发射控制线133施加发射控制信号时，第四薄膜晶体管T4和第五薄膜晶体管T5都导通，使得第四薄膜晶体管T4向第五薄膜晶体管T5施加驱动电压Vel。驱动电压Vel穿过由存储电容Cst导通的第一薄膜晶体管T1时，对应的驱动电压Vel与通过存储电容Cst向第一栅极施加的电压之间的差驱动电流Id流经第一薄膜晶体管T1的第一漏极区D3，驱动电流Id通过第五薄膜晶体管T5施加到各个子像素，使得各个子像素的发光层发光。
在一些示例中，如图33和图34所示，该显示基板100还包括第一平坦层241、第二 导电层160、第二平坦层242和阳极175；第一平坦层241位于第一导电层150远离衬底基板110的一侧；第二导电层160位于第一平坦层241远离第一导电层150的一侧，且包括连接电极161；第二平坦层242位于第二导电层160远离第一平坦层241的一侧；阳极175位于第二平坦层242远离第二导电层160的一侧，第一平坦层241包括第一过孔H1，连接电极161通过第一过孔H1与第六漏极区S6相连，第二平坦层242包括第二过孔H2，阳极175通过第二过孔H2与连接电极161相连。
在一些示例中，如图33、图34和图36所示，该显示基板100还包括发光层180，位于阳极层170远离衬底基板110的一侧，且包括多个发光部185，多个发光部185包括多个发光组1850，各发光组1850包括一个第一发光部1851、一个第二发光部1852、一个第三发光部1853和一个第四发光部1854；第一发光部1851至少部分位于第一开口1951并覆盖被暴露的第一阳极1751，第二发光部1852至少部分位于第二开口1952并覆盖被暴露的第二阳极1752，第三发光部1753至少部分位于第三开口1953并覆盖被暴露的第三阳极1753，第四发光部1854至少部分位于第四开口1954并覆盖被暴露的第四阳极1754；第一发光部1851被配置为发出第一颜色的光，第二发光部1852和第三发光部1853被配置为发出第二颜色的光，第四发光部1854被配置为发出第三颜色的光。
例如，第一颜色为红色(R)，第二颜色为绿色(G)，第三颜色为蓝色(B)。也就是说，该显示基板采用GGRB的像素排列结构。
例如，如图34所示，位于第一阳极1751远离第二阳极1752的一侧的第一导电部1621和位于第一导电层150中的电源线151的重叠面积小于位于第一阳极1751靠近第二阳极1752的一侧的第二导电部1622与第一导电层150中的电源线151的重叠面积。
本公开一实施例还提供一种显示装置。图38为根据本公开一实施例提供的一种显示装置的示意图。如图38所示，该显示装置400包括上述任一项的显示基板100。由此，该显示装置具有与该显示基板的有益效果对应的有益效果。例如，该显示装置可提高补偿薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
例如，该显示装置可为电视、电脑、笔记本电脑、平坦电脑、手机、导航仪、电子相框等具有显示功能的电子产品。
本公开一实施例还提供一种显示基板。图39为本公开一实施例提供的一种显示基板的示意图；图40为本公开一实施例提供的一种显示基板沿图39中TT线的剖面示意图；图41为本公开一实施例提供的一种显示基板中第二导电层和阳极层的示意图。
如图39-41所示，该显示基板包括衬底基板110、像素电路层610、第一导电层150、第一平坦层241和第二导电层160、第二平坦层242和多个发光元件组310。像素电路层610包括多个像素驱动电路265，多个像素驱动电路265包括半导体层120；第一导电层150位于半导体层120远离衬底基板110的一侧；第一平坦层241位于第一导电层150远离半导体层120的一侧；第二导电层160位于第一平坦层241远离第一导电层150的一侧；第二平坦层242位于第二导电层162远离衬底基板110的一侧；多个发光元件组310位于第二平坦层242远离第二导电层162的一侧。第二导电层160包括沿第一方向排 列的多个导电部162，各导电部162在第二方向的尺寸大于在第一方向的尺寸，第二方向与第一方向相交，多个导电部162包括第一导电部1622，第一导电部1622包括封闭环形部1622E，封闭环形部1622E包括镂空区域1622H。
如图39-41所示，各发光元件组310包括第一发光元件311，第一发光元件311包括第一阳极1751，第一阳极1751在衬底基板110上的正投影与封闭环形部1622E在衬底基板110的正投影交叠；多个导电部162还包括与第一导电部1622相邻的第二导电部1621，第二导电部1621在衬底基板110上的正投影与第一阳极1751在衬底基板110的正投影交叠。
在本公开实施例提供的显示基板中，通过设置封闭环形部1622E，第一阳极1751可同时与封闭环形部1622E和第二导电部1621交叠，从而可使得第一阳极1751保持平坦，避免发生倾斜导致的色偏。另外，由于封闭环形部1622E具有镂空设计，从而可提高该显示基板的透光率，并且有利于屏下指纹识别装置接收信号。
在一些示例中，如图39-41所示，封闭环形部1622E与至少一个在第一方向上相邻的导电部162在第二导电层160相互分离，封闭环形部1622E在第一方向上的尺寸至少大于第一导电部1622的一部分在第一方向上的尺寸；多个像素驱动电路265包括第一像素驱动电路2651，第一像素驱动电路2651在半导体层120具有半导体图案，第一导电部1622在衬底基板110的正投影与第一像素驱动电路2651的半导体图案在衬底基板110的正投影交叠，第一像素驱动电路2651包括驱动晶体管T1，第一导电层150包括第一导电图案1542，第一导电图案1542与驱动晶体管T3的栅极具有相同的电位，第一导电图案1542与所述驱动晶体管T1的栅极共同构成了栅极电位金属，封闭环形部1622E内侧的镂空区域1622H在衬底基板110上正投影与栅极电位金属在衬底基板上的正投影交叠。
在本公开实施例提供的显示基板中，一方面，封闭环形部1622E可使得第一阳极1751可保证较高的平坦度，从而保证第一阳极1751在不同方向的发光强度一致，进而可有效改善色偏现象；另一方面，由于封闭环形部1622E内侧的镂空区域1622H在衬底基板110上正投影与栅极电位金属在衬底基板上的正投影交叠，从而可提高驱动晶体管的栅极的复位速度和充电速度。
在一些示例中，如图39-41所示，封闭环形部1622E内侧包括镂空区域1622H，第一导电部1622具有沿着第二方向排布的多个镂空区域1622H；相邻的两个镂空区域1622H的形状和尺寸大致相同。由于第一导电部1622可对应多个第一阳极1751，因此具有多个镂空区域1622H。
在一些示例中，如图39-41所示，第一发光元件311包括有效发光区，经过第一发光元件311的有效发光区的中心且沿第二方向延伸的直线在衬底基板110的正投影位于第一导电部1622和第二导电部1621在衬底基板110的正投影之间。
在一些示例中，如图39-41所示，封闭环形部1622E在第一方向的两个边缘分别与发光元件组中的多个发光元件的阳极在衬底基板的正投影交叠，封闭环形部1622E的镂 空区域1622H与多个发光元件的有效发光区在衬底基板110的正投影分离(即间隔设置)。由此，该显示基板一方面可充分利用显示基板上的空间，另一方面又可避免对发光元件的显示造成不利影响。
在一些示例中，如图39-41所示，第一导电层150还包括导电金属152，被配置为向像素驱动电路265提供电源，第一平坦层241包括导电金属过孔241S，导电部162通过电源线过孔241S与导电金属152电性相连；第一像素驱动电路2651还包括第一发光控制晶体管T4和存储电容Cst，存储电容包括第一电极块CE1和第二电极块CE2，第二电极块CE2位于第一电极块CE1远离衬底基板110的一侧，导电金属152与第一发光控制晶体管T4的源极和第二电极块CE2分别电性相连。由此，该显示基板通过第二导电层的多个导电部可降低导电金属的电阻，降低压降，提高整个显示面板的均一性。
在一些示例中，如图39-41所示，封闭环形部1622E在衬底基板110上的正投影与第一电极块CE1在衬底基板110上的正投影交叠；第二电极块CE2包括开孔620，开孔620在衬底基板110上的正投影与第一电极块CE1在衬底基板110上的正投影交叠，封闭环形部1622E在衬底基板110上的正投影与开孔620在衬底基板110上的正投影也交叠。由此，通过对电容电极的遮挡，可以避免电容被光线过渡照射，起到使电容电位稳定，充放电速度快的作用。
在一些示例中，如图39-41所示，第一像素驱动电路2651还包括数据写入晶体管T2、补偿晶体管T3、复位晶体管T6、阳极初始化晶体管T7和第二发光控制晶体管T5。显示基板还包括：复位信号线131，分别与复位晶体管T6的栅极和阳极初始化晶体管T7的栅极相连；栅线132，分别与补偿晶体管T3的栅极和数据写入晶体管T2的栅极相连；发光控制线133，分别与第一发光控制晶体管T4的栅极和第二发光控制晶体管T5的栅极相连；以及初始化信号线141，分别与复位晶体管T6的源极和阳极初始化晶体管T7的源极相连，封闭环形部1622E在衬底基板110上的正投影分别与复位信号线131、栅线132和初始化信号线133在衬底基板110上的正投影交叠。由于封闭环形部是镂空的，因此与复位信号线131、栅线132和初始化信号线133的交叠较小，可以避免对这些信号线的电位干扰。需要说明的是，上述的像素驱动电路的分层示意图以及各个晶体管的连接关系可参见图30A-30D和图31的相关描述。
在一些示例中，如图39-41所示，第一导电图案1542的一端通过开孔620与驱动晶体管T1的栅极电性相连，第一导电图案1542的另一端与补偿晶体管T3的漏极或源极电性相连。由此，第一导电图案1542具有与驱动晶体管T1的栅极具有相同的电位。
在一些示例中，如图39-41所示，封闭环形部1622E包括沿第一方向排列的第一部分631和第二部分632，以及沿第二方向排列的第三部分633和第四部分634；第一部分631、第三部分633、第二部分632和第四部分634首尾相连以形成封闭环形部1622E，第一部分631和第二部分632在衬底基板110上的正投影与第二电极块CE2在衬底基板110上的正投影交叠。由此，可增加存储电容Cst的电容量。
例如，第三部分633在衬底基板110上的正投影与第二电极块CE2在衬底基板110 上的正投影交叠，从而可进一步增加存储电容Cst的电容量。
在一些示例中，如图39-41所示，第一部分631在衬底基板110上的正投影与第一导电图案1542在衬底基板110上的正投影交叠，第一导电图案1542和第一导电图案1542的形状均为长条形，第一导电图案1542的长边的延伸方向与第一部分631的长边的延伸方向相同。通过使第一部分与第一导电图案的延伸方向相同，使得二者的交叠面积尽可能小，从而减少驱动晶体管的栅极的负载，从而可提高驱动管栅极的复位速度和充电速度。
在一些示例中，如图39-41所示，第一导电层150还包括第二导电图案1541，第二导电图案1541分别与初始化信号线141与复位晶体管T6的源极相连；第三部分633在衬底基板110上的正投影与初始化信号线141在衬底基板110上的正投影交叠，第三部分633在衬底基板110上的正投影与第二导电图案1541在衬底基板110上的正投影交叠，第四部分634在衬底基板110上正投影与第一导电图案1542在衬底基板110上的正投影交叠。
在一些示例中，如图39-41所示，镂空区域1622H在衬底基板110上的正投影与初始化信号线141在衬底基板110上的正投影交叠，镂空区域1622H在衬底基板110上的正投影与第二导电图案1541在衬底基板110上的正投影交叠，镂空区域1622H在衬底基板110上的正投影与第二电极块CE2在衬底基板110上的正投影交叠。
在一些示例中，如图39-41所示，该显示基板还包括：第二平坦层242，位于第二导电层160远离衬底基板110的一侧；以及多个发光元件组310，位于第二平坦层242远离第二导电层160的一侧。多个发光元件组310沿第一方向排列以形成多个发光元件列320，沿第二方向排列以形成多个发光元件行330，各发光元件组310包括一个第一发光元件311、一个第二发光元件312、一个第三发光元件313和一个第四发光元件314，第二发光元件312和第三发光元件313沿第二方向排列形成发光元件对315，第一发光元件311、发光元件对315和第四发光元件314沿第一方向排列，第一发光元件311包括第一阳极1751，第二发光元件312包括第二阳极1752，第三发光元件313包括第三阳极1753，第四发光元件314包括第四阳极1754，第二导电层160包括第一连接电极1611、第二连接电极1612、第三连接电极1613和第四连接电极1614，第二平坦层242包括第一过孔2421，第二过孔2422，第三过孔2423和第四过孔2424，第一阳极1751通过第一过孔2421与第一连接电极1611相连，第二阳极1752通过第二过孔2422与第二连接电极1612相连，第三阳极1753通过第三过孔2423与第三连接电极1613相连，第四阳极1754通过第四过孔2424与第四连接电极1614相连。
在一些示例中，第一阳极1751包括主体部，第一发光元件311的有效发光区在衬底基板110的正投影位于第一阳极1751的主体部在衬底基板110的正投影的内部，且第一阳极1751的主体部与第一阳极1751具有至少部分相同的边界；第二阳极1752包括主体部，第二发光元件312的有效发光区在衬底基板110的正投影位于第二阳极1752的主体部在衬底基板110的正投影的内部，且第二阳极1752的主体部与第二阳极1752具有至 少部分相同的边界；第三阳极1753包括主体部，第三发光元件311的有效发光区在衬底基板110的正投影位于第三阳极1753的主体部在衬底基板110的正投影的内部，且第三阳极1753的主体部与第三阳极1753具有至少部分相同的边界；第四阳极1754包括主体部，第四发光元件314的有效发光区在衬底基板110的正投影位于第四阳极1754的主体部在衬底基板110的正投影的内部，且第四阳极1754的主体部与第四阳极1754具有至少部分相同的边界。
在一些示例中，多个导电部162包括第二导电部1621，第一导电部1621和第二导电部1622分别位于第一发光元件311的有效发光区在第一方向上的两侧，封闭环形部分1622E在衬底基板110上的正投影与第一发光元件311的有效发光区的中心在衬底基板110上的正投影的距离与第二导电部1621在衬底基板110上的正投影与第一发光元件311的有效发光区的中心在衬底基板110上的正投影的距离大致相等。由此，封闭环形部1622E可使得第一阳极1751可保证较高的平坦度，从而保证第一阳极1751在不同方向的发光强度一致，进而可有效改善色偏现。
在一些示例中，如图39-41所示，第一阳极1751在衬底基板110上的正投影与第一像素驱动电路2651的发光控制线133在衬底基板110上的正投影交叠。通过使第一阳极与发光控制线交叠，可使得位于第二导电层的第一阳极的连接电极下移，进而使得第一导电层中的第三导电图案的中心与发光控制线交叠，保证第三导电图案的平坦性，提高过孔连接的有效性。
在一些示例中，如图39-41所示，与镂空区域1622H的中心在第二方向相邻的位置设置有一个第四发光元件314，该第四发光元件314(例如第四发光元件314的第四阳极1754)在衬底基板110上的正投影与栅线132、复位信号线131、初始化信号线141在衬底基板110上的正投影均交叠。
在一些示例中，如图39-41所示，第一导电层151还包括第三导电图案1543，第二导电层160还包括阳极连接部161，即上述的连接电极，第三导电图案1543与第二发光控制晶体管T5的漏极和阳极连接部161相连。
在一些示例中，如图39-41所示，栅线132在衬底基板110上的正投影与第一导电图案1542在衬底基板110上的正投影交叠。
在一些示例中，如图39-41所示，第一电极块CE1和第二电极块CE2在衬底基板110上的正投影位于栅线132在衬底基板110上的正投影和发光控制线133在衬底基板110上的正投影之间，也就是说，存储电容Cst在衬底基板110上的正投影栅线132在衬底基板110上的正投影和发光控制线133在衬底基板110上的正投影之间，从而可合理利用空间。
在一些示例中，如图39-41所示，复位信号线131在衬底基板110上的正投影位于栅线132在衬底基板110上的正投影与初始化信号线141在衬底基板110上的正投影之间；并且，在一个像素驱动电路265中，发光控制线133、第一电极块CE1、栅线132、复位信号线131和初始化信号线141沿第二方向排列，从而可合理利用显示基板上的空 间。
在一些示例中，如图39-41所示，多个像素驱动电路265包括第二栅极层140，第二电极块CE2位于第二栅极层140，至少两个第二电极块CE2在第一方向上相连。也就是说，位于第二栅极层140的至少两个第二电极块CE2可相互电连接，从而也可提高整个显示面板中不同子像素的存储电容的均一性。
在一些示例中，如图39-41所示，第一发光元件312的有效发光区和第二发光元件313的有效发光区在衬底基板110上的正投影与导电部162在衬底基板110上的正投影不交叠。由此，可避免导电部对第一发光元件311和第二发光元件312的平坦性造成不利影响。例如，第二发光元件313被配置为发绿光。
在一些示例中，如图39-41所示，第四发光元件314的有效发光区的中心在衬底基板110上正投影与导电部162在衬底基板110上的正投影交叠。导电部162与第四发光元件314的有效发光区的中心在衬底基板110的正投影交叠的部分为实心部分。由此，虽然第四发光元件314的有效发光区与导电部162交叠，但是第四发光元件314的有效发光区的中心在衬底基板110上正投影与导电部162在衬底基板110上的正投影交叠，可避免导电部对第四发光元件314的平坦性造成不利影响。例如，第四发光元件314被配置为发蓝光。需要说明的是，上述的“实心部分”是指该部分不包括镂空。
在一些示例中，如图39-41所示，第二发光元件312包括第二阳极1752，第三发光元件313包括第三阳极1753；第二阳极1752的主体部与第二阳极1752在第一方向上相邻的两个导电部162的交叠面积大致相等，第三阳极1753的主体部与第二阳极1753在第一方向上相邻的两个导电部162的交叠面积大致相等。由此，可进一步提高第二阳极和第三阳极的平坦性。
在一些示例中，如图39-41所示，镂空区域1622H在衬底基板110上的正投影位于第一发光元件311的有效发光区和第二发光元件312的有效发光区之间。由此，镂空区域可避开有效发光区，避免有效发光区内的阳极发生凹陷，造成色偏。需要说明的是，上述的第一发光元件和第二发光元件为在第一方向上距离最近的第一发光元件和第二发光元件。
在一些示例中，如图39-41所示，被配置为发红光的发光元件的阳极(例如第一阳极)在第二方向上的中间部分在第一方向上的尺寸大于该阳极在第二方向上的边缘部分在第一方向上的尺寸，例如，该阳极的形状可大致为长六边形；被配置为发蓝光的发光元件的阳极(例如第四阳极)在第二方向上的中间部分在第一方向上的尺寸大于该阳极在第二方向上的边缘部分在第一方向上的尺寸。由此，该显示基板可充分利用不同阳极之间的空间，在同样的工艺精度下，最大化被配置为发红光的发光元件的阳极和被配置为发蓝光的发光元件的面积。
在一些示例中，如图39-41所示，一个发光元件组中，至少两个发光元件的阳极175在衬底基板110上的正投影与第二电极块CE2的开孔在衬底基板110上的正投影交叠，因此，通过对第二电极块的开孔的遮挡，进而遮挡驱动管的栅极，可以避免驱动管的栅 极被光线过度照射。至少一个发光元件311、312、313或314的有效发光区域在衬底基板110上的正投影与第一电极块CE1或第二电极块CE2在衬底基板110上的正投影不交叠，从而可避免电容垫高有效发光区，避免色偏。
在一些示例中，在第一发光元件311、第二发光元件312、第三发光元件313和第四发光元件314中的任意一个发光元件中，第一平坦层241具有阳极孔，发光元件的阳极通过阳极孔与发光元件对应的像素驱动电路连接。
在一些示例中，如图39-41所示，被配置为发红光的发光元件的阳极(例如第一阳极1751)的阳极孔(例如第一过孔2421)在衬底基板110上的正投影与该阳极的主体部在衬底基板上正投影在第二方向上不交叠，该阳极的阳极孔在衬底基板110上的正投影与被配置为发红光的发光元件的有效发光区在衬底基板110上正投影在第二方向上不交叠，从而可避免被配置为发红光的发光元件的阳极的阳极孔对第一发光元件的平坦性造成不利影响。
在一些示例中，如图39-41所示，被配置为发蓝光的发光元件的阳极(例如第四阳极1754)的阳极孔(例如第四过孔2424)在衬底基板110上的正投影与该阳极的主体部在衬底基板上正投影在第二方向上不交叠，该阳极的阳极孔在衬底基板110上的正投影与被配置为发红光的发光元件的有效发光区在衬底基板110上正投影在第二方向上不交叠，从而可避免被配置为发红光的发光元件的阳极的阳极孔对第一发光元件的平坦性造成不利影响。
在一些示例中，如图39-41所示，相邻的两条导电部162之间设置有数据线152，相邻的导电部162与数据线152在衬底基板110上的正投影的距离小于相邻的两条导电部162在衬底基板110上的正投影之间的距离。
本公开一实施例还提供一种显示装置。图42为根据本公开一实施例提供的一种显示装置的示意图。如图42所示，该显示装置400包括上述任一项的显示基板100。由此，该显示装置具有与该显示基板的有益效果对应的有益效果。例如，该显示装置可提高补偿薄膜晶体管的稳定性和寿命，从而可提高该显示基板的长期发光稳定性和寿命。
例如，该显示装置可为电视、电脑、笔记本电脑、平坦电脑、手机、导航仪、电子相框等具有显示功能的电子产品。
有以下几点需要说明：
(1)本公开的实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (25)

  1. 一种显示基板，包括：
    衬底基板；
    多个像素驱动电路，包括半导体层；
    第一导电层，位于所述半导体层远离所述衬底基板的一侧；
    第一平坦层，位于所述第一导电层远离所述衬底基板的一侧；
    第二导电层，位于所述第一平坦层远离所述第一导电层的一侧；
    第二平坦层，位于所述第二导电层远离所述衬底基板的一侧；以及
    多个发光元件组，位于所述第二平坦层远离所述第二导电层的一侧，
    其中，所述第二导电层包括沿第一方向排列的多个导电部，各所述导电部在第二方向的尺寸大于在第一方向的尺寸，所述第二方向与所述第一方向相交，所述多个导电部包括第一导电部，所述第一导电部包括封闭环形部，所述封闭环形部与至少一个在第一方向上相邻的所述导电部在所述第二导电层相互分离，
    各所述发光元件组包括第一发光元件，所述第一发光元件包括第一阳极，所述第一阳极在所述衬底基板上的正投影与所述封闭环形部在所述衬底基板的正投影交叠；所述多个导电部还包括与所述第一导电部相邻的第二导电部，所述第二导电部在衬底基板上的正投影与所述第一阳极在所述衬底基板的正投影交叠。
  2. 根据权利要求1所述的显示基板，其中，所述封闭环形部在所述第一方向上的尺寸至少大于第一导电部的一部分在所述第一方向上的尺寸，所述多个像素驱动电路包括第一像素驱动电路，第一像素驱动电路在所述半导体层具有半导体图案，所述第一导电部在所述衬底基板的正投影与所述第一像素驱动电路的所述半导体图案在所述衬底基板的正投影交叠，所述第一像素驱动电路包括驱动晶体管，所述第一导电层包括第一导电图案，所述第一导电图案与所述驱动晶体管的栅极具有相同的电位，所述第一导电图案与所述驱动晶体管的栅极共同构成了栅极电位金属，所述封闭环形部内侧的镂空区域在所述衬底基板上正投影与所述栅极电位金属交叠。
  3. 根据权利要求1所述的显示基板，其中，所述封闭环形部内侧具有镂空区域，所述第一导电部具有沿着所述第二方向排布的多个所述镂空区域，相邻两个所述镂空区域的形状和尺寸大致相同。
  4. 根据权利要求1-3中任一项所述的显示基板，其中，所述第一发光元件包括有效发光区，经过所述第一发光元件的有效发光区的中心且沿所述第二方向延伸的直线在所述衬底基板的正投影位于所述第一导电部在所述衬底基板上的正投影和所述第二导电部在所述衬底基板上的正投影之间。
  5. 根据权利要求1-4中任一项所述的显示基板，其中，所述封闭环形部在所述第一方向的两个边缘分别与所述发光元件组中的多个发光元件的阳极在所述衬底基板的正投影交叠，所述封闭环形部的镂空区域与所述多个发光元件的有效发光区在所述衬底基板的正投影分离设置。
  6. 根据权利要求1-5中任一项所述的显示基板，其中，所述第一导电层还包括导电金属，被配置为向所述像素驱动电路提供电源，所述第一平坦层包括导电金属过孔，所述导电部通过所述导电金属过孔与所述导电金属电性相连，
    所述第一像素驱动电路还包括第一发光控制晶体管和存储电容，所述存储电容包括第一电极块和第二电极块，所述第二电极块位于所述第一电极块远离所述衬底基板的一侧，所述导电金属与所述第一发光控制晶体管的源极和所述第二电极块分别电性相连。
  7. 根据权利要求6所述的显示基板，其中，所述封闭环形部在所述衬底基板上的正投影与所述第一电极块在所述衬底基板上的正投影交叠，
    所述第二电极块包括开孔，所述开孔在所述衬底基板上的正投影与所述第一电极块在所述衬底基板上的正投影交叠，所述封闭环形部在所述衬底基板上的正投影与所述开孔在所述衬底基板上的正投影也交叠。
  8. 根据权利要求7所述的显示基板，其中，所述第一像素驱动电路还包括数据写入晶体管、补偿晶体管、复位晶体管、阳极初始化晶体管和第二发光控制晶体管，
    所述显示基板还包括：
    复位信号线，与所述复位晶体管的栅极相连；
    栅线，与所述补偿晶体管的栅极相连；
    发光控制线，与所述第一发光控制晶体管的栅极相连；以及
    初始化信号线，与所述复位晶体管的源极相连，
    其中，所述封闭环形部在所述衬底基板上的正投影分别与所述复位信号线、所述栅线和所述初始化信号线在所述衬底基板上的正投影交叠。
  9. 根据权利要求8所述的显示基板，其中，所述第一导电图案的一端通过所述开孔与所述驱动晶体管的栅极电性相连，所述第一导电图案的另一端与所述补偿晶体管的源极或漏极电性相连。
  10. 根据权利要求8所述的显示基板，其中，所述封闭环形部包括沿所述第一方向排列的第一部分和第二部分，以及沿所述第二方向排列的第三部分和第四部分，
    所述第一部分、所述第三部分、所述第二部分和所述第四部分首尾相连以形成所述 封闭环形部，所述第一部分和所述第二部分在所述衬底基板上的正投影与所述第二电极块在所述衬底基板上的正投影交叠。
  11. 根据权利要求10所述的显示基板，其中，所述第一部分在所述衬底基板上的正投影与所述第一导电图案在所述衬底基板上的正投影交叠，
    所述第一导电图案和所述第一部分的形状均为长条形，所述第一导电图案的长边的延伸方向与所述第一部分的长边的延伸方向相同。
  12. 根据权利要求10所述的显示基板，其中，所述第一导电层还包括第二导电图案和第三导电图案，所述第二导电图案分别与所述初始化信号线与所述复位晶体管的源极相连，所述第二导电层还包括阳极连接部，所述第三导电图案与所述第二发光控制晶体管的漏极和所述阳极连接部相连，
    所述第三部分在所述衬底基板上的正投影与所述初始化信号线在所述衬底基板上的正投影交叠，所述第三部分在所述衬底基板上的正投影与所述第二导电图案在所述衬底基板上的正投影交叠，所述第四部分在所述衬底基板上正投影与所述第一导电图案在所述衬底基板上的正投影交叠。
  13. 根据权利要求10-12中任一项所述的显示基板，其中，所述镂空区域在所述衬底基板上的正投影与所述初始化信号线在所述衬底基板上的正投影交叠，所述镂空区域在所述衬底基板上的正投影与所述第二导电图案在所述衬底基板上的正投影交叠，所述镂空区域在所述衬底基板上的正投影与所述第二电极块在所述衬底基板上的正投影交叠。
  14. 根据权利要求8-13中任一项所述的显示基板，其中，所述多个发光元件组沿所述第一方向排列以形成多个发光元件列，沿所述第二方向排列以形成多个发光元件行，各所述发光元件组包括一个所述第一发光元件、一个第二发光元件、一个第三发光元件和一个第四发光元件，所述第一阳极包括主体部，所述第一发光元件的有效发光区在所述衬底基板的正投影位于所述第一阳极的主体部在所述衬底基板的正投影的内部，且所述第一阳极的主体部与所述第一阳极具有至少部分相同的边界，
    所述多个导电部包括第二导电部，所述第一导电部和所述第二导电部分别位于所述第一发光元件的有效发光区在所述第一方向上的两侧，所述封闭环形部分在衬底基板上的正投影与所述第一发光元件的有效发光区的中心在所述衬底基板上的正投影的距离与所述第二导电部在所述衬底基板上的正投影与所述第一发光元件的有效发光区的中心在所述衬底基板上的正投影的距离大致相等。
  15. 根据权利要求14所述的显示基板，其中，所述第一阳极在所述衬底基板上的正 投影与所述第一像素驱动电路的所述发光控制线在所述衬底基板上的正投影交叠，与所述镂空区域的中心在第二方向相邻的位置设置有一个第四发光元件，所述第四发光元件的阳极在所述衬底基板上的正投影与所述栅线、所述复位信号线、所述初始化信号线在所述衬底基板上的正投影均交叠。
  16. 根据权利要求14所述的显示基板，其中，所述栅线在所述衬底基板上的正投影与所述第一导电图案在所述衬底基板上的正投影交叠，
    在一个所述像素驱动电路中，所述第一电极块和所述第二电极块在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影和所述发光控制线在所述衬底基板上的正投影之间，
    所述复位信号线在所述衬底基板上的正投影位于所述栅线在所述衬底基板上的正投影与所述初始化信号线在所述衬底基板上的正投影之间，
    所述发光控制线、所述第一电极块、所述栅线、所述复位信号线和所述初始化信号线沿所述第二方向排列。
  17. 根据权利要求14-16中任一项所述的显示基板，其中，所述多个像素驱动电路还包括位于所述第一导电层靠近所述衬底基板一侧的第二栅电极层，所述第二电极块位于所述第二栅电极层，至少两个所述第二电极块在所述第二栅电极层连接。
  18. 根据权利要求14-17中任一项所述的显示基板，其中，所述第一发光元件的有效发光区和所述第二发光元件的有效发光区在衬底基板上的正投影与所述导电部在所述衬底基板上的正投影不交叠，所述第二发光元件被配置为发绿光，
    所述第四发光元件的有效发光区的中心在所述衬底基板上正投影与所述导电部在所述衬底基板上的正投影交叠，所述导电部与所述第四发光元件的有效发光区的中心在所述衬底基板的正投影交叠的部分为实心部分，所述第四发光元件被配置为发蓝光。
  19. 根据权利要求14-18中任一项所述的显示基板，其中，所述第二发光元件包括第二阳极，所述第二发光元件的有效发光区在所述衬底基板的正投影位于所述第二阳极的主体部在所述衬底基板的正投影的内部，且所述第二阳极的主体部与所述第二阳极具有至少部分相同的边界，
    所述第二阳极的主体部与所述第二阳极在所述第一方向上相邻的两个所述导电部的交叠面积大致相等。
  20. 根据权利要求14-19中任一项所述的显示基板，其中，所述镂空区域在所述衬底基板上的正投影位于所述第一发光元件的有效发光区和所述第二发光元件的有效发光区之间，所述第一发光元件和所述第二发光元件为在第一方向上距离最近的所述第一发 光元件和所述第二发光元件。
  21. 根据权利要求14-20中任一项所述的显示基板，其中，被配置为发出红光的发光元件的阳极在所述第二方向上的中间部分在所述第一方向上的尺寸大于所述阳极在所述第二方向上的边缘部分在所述第一方向上的尺寸，
    被配置为发出蓝光的发光元件的阳极在所述第二方向上的中间部分在所述第一方向上的尺寸大于所述阳极在所述第二方向上的边缘部分在所述第一方向上的尺寸。
  22. 根据权利要求14-21中任一项所述的显示基板，其中，一个所述发光元件组中，至少两个发光元件的阳极在所述衬底基板上的正投影与所述第二电极块的所述开孔在所述衬底基板上的正投影交叠，至少一个发光元件的有效发光区在所述衬底基板上的正投影与所述第一电极块或所述第二电极块在所述衬底基板上的正投影不交叠。
  23. 根据权利要求19所述的显示基板，其中，在所述第一发光元件、所述第二发光元件、所述第三发光元件和所述第四发光元件中的任意一个发光元件中，所述第一平坦层具有阳极孔，所述发光元件的阳极通过所述阳极孔与所述发光元件对应的像素驱动电路连接，
    被配置为发出红光的发光元件的阳极的阳极孔在所述衬底基板上的正投影与所述阳极的主体部在所述衬底基板上正投影在所述第二方向上不交叠，被配置为发出红光的发光元件的阳极的阳极孔在所述衬底基板上的正投影与被配置为发出红光的发光元件的有效发光区在所述衬底基板上正投影在所述第二方向上不交叠，
    被配置为发出蓝光的发光元件的阳极的阳极孔在所述衬底基板上的正投影与所述阳极的主体部在所述衬底基板上正投影在所述第二方向上不交叠，被配置为发出蓝光的发光元件的阳极的阳极孔在所述衬底基板上的正投影与被配置为发出蓝光的发光元件的有效发光区在所述衬底基板上正投影在所述第二方向上不交叠。
  24. 根据权利要求1-23中任一项所述的显示基板，其中，相邻的两条所述导电部之间设置有数据线，相邻的所述导电部与所述数据线在所述衬底基板上的正投影之间的距离小于相邻的两条所述导电部在所述衬底基板上的正投影之间的距离。
  25. 一种显示装置，包括根据权利要求1-24中任一项所述的显示基板。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114355690A (zh) * 2022-03-16 2022-04-15 惠科股份有限公司 阵列基板及显示装置
CN114551769A (zh) * 2022-04-22 2022-05-27 北京京东方技术开发有限公司 显示基板和显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023159509A1 (zh) * 2022-02-25 2023-08-31 京东方科技集团股份有限公司 显示基板、显示面板及显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070035239A1 (en) * 2005-08-11 2007-02-15 Samsung Sdi Co., Ltd. Flat panel display and method of manufacturing the same
CN107579099A (zh) * 2017-08-28 2018-01-12 上海天马微电子有限公司 一种显示面板、其制备方法及显示装置
CN107871757A (zh) * 2016-09-23 2018-04-03 京东方科技集团股份有限公司 有机发光二极管（oled）阵列基板及其制备方法、显示装置
CN108123062A (zh) * 2016-11-29 2018-06-05 乐金显示有限公司 有机发光显示装置
KR20180062897A (ko) * 2016-12-01 2018-06-11 엘지디스플레이 주식회사 유기 발광 표시 장치
CN109037280A (zh) * 2018-07-24 2018-12-18 云谷（固安）科技有限公司 有机电致发光显示面板及其制作方法、显示装置
CN110112202A (zh) * 2019-05-24 2019-08-09 京东方科技集团股份有限公司 显示基板及其制备方法
CN110610980A (zh) * 2019-10-23 2019-12-24 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001109404A (ja) 1999-10-01 2001-04-20 Sanyo Electric Co Ltd Ｅｌ表示装置
CN100394612C (zh) 2003-02-17 2008-06-11 友达光电股份有限公司 顶部发光型主动式有机发光显示元件及其制造方法
KR101308466B1 (ko) 2007-10-08 2013-09-16 엘지디스플레이 주식회사 유기전계발광소자 및 그 제조방법
US20090091254A1 (en) 2007-10-08 2009-04-09 Lg.Display Co., Ltd. Organic electroluminescence device and method for manufacturing the same
JP2009175198A (ja) 2008-01-21 2009-08-06 Sony Corp Ｅｌ表示パネル及び電子機器
KR101238010B1 (ko) 2008-09-10 2013-03-04 엘지디스플레이 주식회사 백라이트 유닛과 이를 이용한 액정표시장치
KR101634791B1 (ko) * 2008-11-28 2016-06-30 삼성디스플레이 주식회사 접촉 감지 기능이 있는 유기 발광 표시 장치
US9065077B2 (en) 2012-06-15 2015-06-23 Apple, Inc. Back channel etch metal-oxide thin film transistor and process
US9239501B2 (en) 2012-07-26 2016-01-19 Innocom Technology(Shenzhen) Co., Ltd. Liquid crystal display device
KR102083432B1 (ko) 2013-05-30 2020-03-03 삼성디스플레이 주식회사 유기 발광 표시 장치
CN103353683B (zh) 2013-06-26 2016-02-10 京东方科技集团股份有限公司 一种阵列基板以及包括该阵列基板的显示装置
KR20150005264A (ko) 2013-07-05 2015-01-14 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
KR102127149B1 (ko) 2013-10-01 2020-07-08 삼성디스플레이 주식회사 액정표시장치
CN103762223A (zh) 2013-12-31 2014-04-30 深圳市华星光电技术有限公司 一种具有氧化物薄膜电晶体的发光装置及其制造方法
KR102270081B1 (ko) 2014-09-16 2021-06-29 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102372774B1 (ko) 2015-03-26 2022-03-11 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102290483B1 (ko) 2015-04-28 2021-08-17 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 구동 방법
CN110137214A (zh) * 2018-02-09 2019-08-16 京东方科技集团股份有限公司 显示基板和显示装置
US11448807B2 (en) 2016-02-18 2022-09-20 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, fine metal mask set and manufacturing method thereof
KR102617379B1 (ko) 2016-05-02 2023-12-27 삼성디스플레이 주식회사 유기발광 표시장치 및 이의 제조 방법
CN105892188A (zh) 2016-06-17 2016-08-24 厦门天马微电子有限公司 一种液晶显示面板及装置
CN105867012B (zh) 2016-06-27 2019-02-19 京东方科技集团股份有限公司 显示基板及其制作方法以及显示装置
CN105957878A (zh) 2016-07-08 2016-09-21 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
US10224386B2 (en) * 2016-09-23 2019-03-05 Apple Inc. Display with power supply mesh
KR102600982B1 (ko) 2016-10-28 2023-11-13 삼성전자주식회사 디스플레이 장치
KR102559096B1 (ko) 2016-11-29 2023-07-26 삼성디스플레이 주식회사 표시 장치
JP6807726B2 (ja) * 2016-12-16 2021-01-06 株式会社ジャパンディスプレイ 有機ｅｌ表示装置
CN108428704B (zh) 2017-02-15 2020-10-30 朱夏青 显示装置
KR102391918B1 (ko) 2017-05-23 2022-04-29 삼성디스플레이 주식회사 유기발광표시장치
CN107480639B (zh) 2017-08-16 2020-06-02 上海天马微电子有限公司 一种触控显示面板和显示装置
CN207052608U (zh) 2017-08-24 2018-02-27 京东方科技集团股份有限公司 一种显示基板及显示装置
KR102461360B1 (ko) 2017-12-15 2022-11-02 삼성디스플레이 주식회사 표시 장치 및 그의 제조 방법
CN207883217U (zh) 2018-02-09 2018-09-18 京东方科技集团股份有限公司 显示基板和显示装置
KR102623339B1 (ko) 2018-07-17 2024-01-11 삼성디스플레이 주식회사 화소 및 그것을 포함하는 유기 발광 표시 장치
CN109166865B (zh) 2018-08-08 2020-11-10 深圳市华星光电技术有限公司 阵列基板及其制造方法、显示面板
US20200103698A1 (en) 2018-09-30 2020-04-02 HKC Corporation Limited Color filter and display panel
CN208705615U (zh) 2018-09-30 2019-04-05 惠科股份有限公司 彩色滤光片和显示面板
KR20200137071A (ko) * 2019-05-28 2020-12-09 삼성디스플레이 주식회사 표시 장치
CN110034132B (zh) * 2019-06-12 2019-10-29 成都京东方光电科技有限公司 一种阵列基板、显示面板及显示装置
CN110265458B (zh) 2019-06-27 2021-12-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板及显示装置
CN110611047A (zh) 2019-08-29 2019-12-24 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
KR20210032608A (ko) * 2019-09-16 2021-03-25 삼성디스플레이 주식회사 표시 장치
CN114203784A (zh) * 2019-11-07 2022-03-18 京东方科技集团股份有限公司 一种显示基板和显示装置
CN110854173A (zh) 2019-11-26 2020-02-28 深圳市华星光电半导体显示技术有限公司 一种oled显示面板

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070035239A1 (en) * 2005-08-11 2007-02-15 Samsung Sdi Co., Ltd. Flat panel display and method of manufacturing the same
CN107871757A (zh) * 2016-09-23 2018-04-03 京东方科技集团股份有限公司 有机发光二极管（oled）阵列基板及其制备方法、显示装置
CN108123062A (zh) * 2016-11-29 2018-06-05 乐金显示有限公司 有机发光显示装置
KR20180062897A (ko) * 2016-12-01 2018-06-11 엘지디스플레이 주식회사 유기 발광 표시 장치
CN107579099A (zh) * 2017-08-28 2018-01-12 上海天马微电子有限公司 一种显示面板、其制备方法及显示装置
CN109037280A (zh) * 2018-07-24 2018-12-18 云谷（固安）科技有限公司 有机电致发光显示面板及其制作方法、显示装置
CN110112202A (zh) * 2019-05-24 2019-08-09 京东方科技集团股份有限公司 显示基板及其制备方法
CN110610980A (zh) * 2019-10-23 2019-12-24 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4131404A4

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114355690A (zh) * 2022-03-16 2022-04-15 惠科股份有限公司 阵列基板及显示装置
US11966134B2 (en) 2022-03-16 2024-04-23 HKC Corporation Limited Array substrate and display device
CN114551769A (zh) * 2022-04-22 2022-05-27 北京京东方技术开发有限公司 显示基板和显示装置
CN114551769B (zh) * 2022-04-22 2022-08-26 北京京东方技术开发有限公司 显示基板和显示装置

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