WO2021184431A1 - 像素及液晶显示面板 - Google Patents

像素及液晶显示面板 Download PDF

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Publication number
WO2021184431A1
WO2021184431A1 PCT/CN2020/083109 CN2020083109W WO2021184431A1 WO 2021184431 A1 WO2021184431 A1 WO 2021184431A1 CN 2020083109 W CN2020083109 W CN 2020083109W WO 2021184431 A1 WO2021184431 A1 WO 2021184431A1
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WIPO (PCT)
Prior art keywords
sub
pixel
switch
node
electrode
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Application number
PCT/CN2020/083109
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English (en)
French (fr)
Inventor
陈亚妮
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Tcl华星光电技术有限公司
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Priority to US16/759,418 priority Critical patent/US20210294168A1/en
Publication of WO2021184431A1 publication Critical patent/WO2021184431A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • This application relates to the field of display technology, and in particular to a pixel and a liquid crystal display panel.
  • the birefringence of liquid crystal molecules at different viewing angles is quite different, resulting in a large viewing angle deviation in the vertical alignment liquid crystal display panel, especially the large-size vertical alignment type
  • the liquid crystal display panel has a color shift in the vertical viewing angle.
  • the purpose of this application is to provide a pixel and a display panel to improve the vertical viewing angle of a large-size liquid crystal display panel.
  • the present application provides a pixel and a liquid crystal display panel
  • a pixel includes at least one sub-pixel, and each of the sub-pixels includes a main sub-pixel, a first sub-pixel, and a second sub-pixel,
  • the main sub-pixel includes a first switch and a first liquid crystal capacitor, a control terminal of the first switch is connected to a scan line, a first terminal of the first switch is connected to a data line, and a second terminal of the first switch is connected to a second terminal.
  • a node, the first liquid crystal capacitor is connected between the first node and the first common electrode;
  • the first sub-pixel includes a second switch, a first voltage dividing unit, and a second liquid crystal capacitor, a control terminal of the second switch is connected to the scan line, and a first terminal of the second switch is connected to the data Line, the second terminal of the second switch is connected to a second node, the second liquid crystal capacitor is connected between the second node and the first common electrode, and the first voltage dividing unit is connected to the first Between the two nodes and the shared electrode;
  • the second sub-pixel includes a third switch, a second voltage dividing unit, and a third liquid crystal capacitor, a control terminal of the third switch is connected to the scan line, and a first terminal of the third switch is connected to the data Line, the second end of the third switch is connected to a third node, the third liquid crystal capacitor is connected between the third node and the first common electrode, and the second voltage dividing unit is connected to the Between the third node and the shared electrode;
  • the first voltage dividing unit is used to control the potential of the second node through a voltage dividing action
  • the second voltage dividing unit is used to control the potential of the third node through a voltage dividing action, so that the voltage of the first node is The electric potential, the electric potential of the second node, and the electric potential of the third node are different.
  • the first voltage dividing unit is a first thin film transistor
  • the second voltage dividing unit is a second thin film transistor
  • the control terminal of the first thin film transistor is connected to the scan line, the first terminal is connected to the second node, and the second terminal is connected to the shared electrode;
  • the control terminal of the second thin film transistor is connected to the scan line, the first terminal is connected to the third node, and the second terminal is connected to the shared electrode;
  • the ratio of the channel width to the channel length of the first thin film transistor is different from the ratio of the channel width to the channel length of the second thin film transistor.
  • the main subpixel includes a main subpixel electrode
  • the first subpixel includes a first subpixel electrode
  • the second subpixel includes a second subpixel electrode.
  • the first sub-pixel electrode is located between the main sub-pixel electrode and the second sub-pixel electrode, and the main sub-pixel electrode, the first sub-pixel electrode, and the second sub-pixel electrode are present Arranged in a straight line, the main sub-pixel electrode is electrically connected to the second end of the first switch, the first sub-pixel electrode is electrically connected to the second end of the second switch, and the second sub-pixel electrode is electrically connected to the second end of the second switch.
  • the pixel electrode is electrically connected to the second end of the third switch, and the ratio of the channel width to the channel length of the first thin film transistor is smaller than the ratio of the channel width to the channel length of the second thin film transistor.
  • the two data lines are located on opposite sides of the main sub-pixel electrode, the first sub-pixel electrode, and the second sub-pixel electrode, and the main sub-pixel electrode includes two side electrodes The two side electrodes extend to opposite sides of the first sub-pixel electrode and are located between the data line and the first sub-pixel electrode.
  • the main sub-pixel electrode, the first sub-pixel electrode, and the second sub-pixel electrode all have four domains.
  • the shared electrode and the data line are provided in the same layer.
  • the first switch, the second switch, and the third switch are all thin film transistors, and the first switch, the second switch, and the third switch are all the same.
  • the capacitance value of the first liquid crystal capacitor, the capacitance value of the second liquid crystal capacitor, and the capacitance value of the third liquid crystal capacitor are all the same.
  • the sub-pixel further includes a first storage capacitor, a second storage capacitor, and a third storage capacitor.
  • the first storage capacitor is connected between the first node and the second common electrode.
  • Two storage capacitors are connected between the second node and the second common electrode, and the third storage capacitor is connected between the third node and the second common electrode.
  • a liquid crystal display panel includes pixels, the pixels include at least one sub-pixel, and each of the sub-pixels includes a main sub-pixel, a first sub-pixel, and a second sub-pixel,
  • the main sub-pixel includes a first switch and a first liquid crystal capacitor, a control terminal of the first switch is connected to a scan line, a first terminal of the first switch is connected to a data line, and a second terminal of the first switch is connected to a second terminal.
  • a node, the first liquid crystal capacitor is connected between the first node and the first common electrode;
  • the first sub-pixel includes a second switch, a first voltage dividing unit, and a second liquid crystal capacitor, a control terminal of the second switch is connected to the scan line, and a first terminal of the second switch is connected to the data Line, the second terminal of the second switch is connected to a second node, the second liquid crystal capacitor is connected between the second node and the first common electrode, and the first voltage dividing unit is connected to the first Between the two nodes and the shared electrode;
  • the second sub-pixel includes a third switch, a second voltage dividing unit, and a third liquid crystal capacitor, a control terminal of the third switch is connected to the scan line, and a first terminal of the third switch is connected to the data Line, the second end of the third switch is connected to a third node, the third liquid crystal capacitor is connected between the third node and the first common electrode, and the second voltage dividing unit is connected to the Between the third node and the shared electrode;
  • the first voltage dividing unit is used to control the potential of the second node through a voltage dividing action
  • the second voltage dividing unit is used to control the potential of the third node through a voltage dividing action, so that the first The potential of the node, the potential of the second node, and the potential of the third node are different.
  • the first voltage dividing unit is a first thin film transistor
  • the second voltage dividing unit is a second thin film transistor
  • the control terminal of the first thin film transistor is connected to the scan line, the first terminal is connected to the second node, and the second terminal is connected to the shared electrode;
  • the control terminal of the second thin film transistor is connected to the scan line, the first terminal is connected to the third node, and the second terminal is connected to the shared electrode;
  • the ratio of the channel width to the channel length of the first thin film transistor is different from the ratio of the channel width to the channel length of the second thin film transistor.
  • the main sub-pixel includes a main sub-pixel electrode
  • the first sub-pixel includes a first sub-pixel electrode
  • the second sub-pixel includes a second sub-pixel electrode.
  • the first sub-pixel electrode is located between the main sub-pixel electrode and the second sub-pixel electrode, and the main sub-pixel electrode, the first sub-pixel electrode, and the second sub-pixel electrode
  • the pixel electrodes are arranged in a straight line
  • the main sub-pixel electrode is electrically connected to the second end of the first switch
  • the first sub-pixel electrode is electrically connected to the second end of the second switch
  • the first sub-pixel electrode is electrically connected to the second end of the second switch.
  • the secondary sub-pixel electrode is electrically connected to the second end of the third switch, and the ratio of the channel width to the channel length of the first thin film transistor is smaller than the channel width and the channel length of the second thin film transistor Ratio.
  • the two data lines are located on opposite sides of the main sub-pixel electrode, the first sub-pixel electrode, and the second sub-pixel electrode, and the main sub-pixel electrode includes two Side electrodes, the two side electrodes extend to opposite sides of the first sub-pixel electrode and are located between the data line and the first sub-pixel electrode.
  • the main sub-pixel electrode, the first sub-pixel electrode, and the second sub-pixel electrode all have four domains.
  • the shared electrode and the data line are arranged in the same layer.
  • the first switch, the second switch, and the third switch are all thin film transistors, and the first switch, the second switch, and the third switch are all the same.
  • the capacitance value of the first liquid crystal capacitor, the capacitance value of the second liquid crystal capacitor, and the capacitance value of the third liquid crystal capacitor are all the same.
  • the sub-pixel further includes a first storage capacitor, a second storage capacitor, and a third storage capacitor, the first storage capacitor is connected between the first node and the second common electrode, so The second storage capacitor is connected between the second node and the second common electrode, and the third storage capacitor is connected between the third node and the second common electrode.
  • the present application provides a pixel and a liquid crystal display panel.
  • the pixel includes at least one sub-pixel.
  • Each sub-pixel includes a main sub-pixel, a first sub-pixel, and a second sub-pixel.
  • the secondary pixel includes a second voltage dividing unit, the first voltage dividing unit controls the potential of the second node, and the second voltage dividing unit controls the potential of the third node, so that the potential of the first node, the potential of the second node, and the third
  • the potentials of the nodes are different, so that the voltage after the first liquid crystal capacitor is charged, the voltage after the second liquid crystal capacitor is charged, and the voltage after the third liquid crystal capacitor is charged are different, so that the driving voltage of the main sub-pixel and the voltage of the first sub-pixel are different.
  • the driving voltage and the driving voltage of the second sub-pixel are different, and the potential difference of the three sub-pixels is realized, and the viewing angle of the liquid crystal display panel during display is greatly improved, especially the vertical viewing angle of the large-size liquid crystal display panel.
  • the first voltage dividing unit and the second voltage dividing unit are both connected to the shared electrode. By controlling the potential of the shared electrode, the potential of the second node and the third node can be adjusted according to actual needs, thereby controlling the first sub-pixel And the driving voltage of the second sub-pixel is adjustable.
  • the first voltage dividing unit and the second voltage dividing unit share a common electrode, which can increase the aperture ratio of the sub-pixel.
  • Fig. 1 is a schematic plan view of a pixel according to an embodiment of the application
  • Fig. 2 is a circuit diagram corresponding to the sub-pixel shown in Fig. 1.
  • the present application provides a pixel.
  • the pixel includes at least one sub-pixel.
  • the sub-pixels may be red sub-pixels, blue sub-pixels, and green sub-pixels. Please refer to FIGS. 1 and 2.
  • FIG. 1 is a schematic plan view of a pixel according to an embodiment of the application
  • FIG. 2 is a circuit diagram corresponding to the sub-pixel shown in FIG.
  • Each sub-pixel includes a main sub-pixel, a first sub-pixel, and a second sub-pixel.
  • the driving voltages of the main pixel, the first sub-pixel, and the second sub-pixel are different from each other, so that the voltage difference between any two of the main pixel, the first sub-pixel, and the second sub-pixel is not equal to 0, and the sub-pixel is
  • the liquid crystal display panel has a wider viewing angle, especially to improve the vertical viewing angle of a large-size liquid crystal display panel.
  • the main sub-pixel includes a first switch T1, a first liquid crystal capacitor Clc1, and a first storage capacitor Cst1.
  • the control terminal of the first switch T1 is connected to the scan line S, the first terminal of the first switch T1 is connected to the data line D1, and the second terminal of the first switch T1 is connected to the first node Q1.
  • the first liquid crystal capacitor Clc1 is connected between the first node Q1 and the first common electrode CFcom.
  • the first storage capacitor Cst1 is connected between the first node Q1 and the second common electrode Acom.
  • the first sub-pixel includes a second switch T2, a first voltage dividing unit 1, a second liquid crystal capacitor Clc2, and a second storage capacitor Cst2.
  • the control terminal of the second switch T2 is connected to the scan line S, the first terminal of the second switch T2 is connected to the data line D1, and the second terminal of the second switch T2 is connected to the second node Q2.
  • the second liquid crystal capacitor Clc2 is connected between the second node Q2 and the first common electrode CFcom.
  • the second storage capacitor Cst2 is connected between the second node Q2 and the second common electrode Acom.
  • the first voltage dividing unit 1 is connected between the second node Q2 and the shared electrode SB (Sharebar).
  • the second secondary pixel includes a third switch T3, a second voltage dividing unit 2, a third liquid crystal capacitor Clc3, and a third storage capacitor Cst3.
  • the control terminal of the third switch T3 is connected to the scan line S, the first terminal of the third switch T3 is connected to the data line D1, and the second terminal of the third switch T3 is connected to the third node Q3.
  • the third liquid crystal capacitor Clc3 is connected between the third node Q3 and the first common electrode CFcom.
  • the third storage capacitor Cst3 is connected between the third node Q3 and the second common electrode Acom.
  • the second voltage dividing unit 2 is connected between the third node Q3 and the shared electrode SB.
  • the first voltage dividing unit 1 is used to control the potential of the second node Q2 through the voltage dividing action
  • the second voltage dividing unit 2 is used to control the potential of the third node Q3 through the voltage dividing action, so that the first node Q1 and the second node The potential of Q2 and the potential of the third node Q3 are different.
  • the first voltage dividing unit 1 and the second voltage dividing unit 2 are both connected to the shared electrode SB. By controlling the potential of the shared electrode SB, the potential of the second node Q2 and the third node Q3 can be adjusted according to actual needs.
  • the driving voltage of the first sub-pixel and the second sub-pixel of the present application It is adjustable.
  • the first voltage dividing unit 1 is a first thin film transistor T4, and the second voltage dividing unit 2 is a second thin film transistor T5.
  • the control terminal of the first thin film transistor T4 is connected to the scan line, the first terminal is connected to the second node Q2, and the second terminal is connected to the shared electrode SB.
  • the control terminal of the second thin film transistor T5 is connected to the scan line S, the first terminal is connected to the third node Q3, and the second terminal is connected to the shared electrode SB.
  • the ratio of the channel width to the channel length of the first thin film transistor T4 is smaller than the ratio of the channel width to the channel length of the second thin film transistor T5.
  • the leakage capability of the first thin film transistor T4 is different from that of the second thin film transistor T5. Ability is different.
  • the ratio of the channel width to the channel length of the first thin film transistor T4 is smaller than the ratio of the channel width to the channel length of the second thin film transistor T5.
  • Both the first thin film transistor T4 and the second thin film transistor T5 are polysilicon thin film transistors.
  • the first end and the second end of the first thin film transistor T4 and the second thin film transistor T5 are both strip-shaped, and the active layers of the first thin film transistor T4 and the second thin film transistor T5 are both rectangular.
  • the main sub-pixel includes the main sub-pixel electrode M.
  • the first sub-pixel includes the first sub-pixel electrode Sub1.
  • the second sub-pixel includes a second sub-pixel electrode Sub2.
  • the first sub-pixel electrode Sub1 is located between the main sub-pixel electrode M and the second sub-pixel Sub2, and the main sub-pixel electrode M, the first sub-pixel electrode Sub1, and the second sub-pixel electrode Sub2 are arranged in a straight line .
  • a first switch T1, a second switch T2, a third switch T3, a first voltage dividing unit 1 and a second voltage dividing unit 2 are arranged between the first sub-pixel electrode Sub1 and the second sub-pixel Sub2, so that the sub-pixel The pixel aperture ratio is larger.
  • the main sub-pixel electrode M, the first sub-pixel electrode Sub1 and the second sub-pixel electrode Sub2 are arranged in the same layer, and are obtained by patterning the same transparent conductive layer, and the transparent conductive layer is an indium tin oxide layer.
  • the second switch T2 is disposed close to the first sub-pixel electrode Sub1, so that the second end of the second switch T2 is connected to the first sub-pixel electrode Sub1, and the third switch T3 is close to the second sub-pixel electrode Sub2. So that the second end of the third switch T3 is connected to the second sub-pixel electrode Sub2.
  • the main sub-pixel electrode M is electrically connected to the second end of the first switch T1.
  • the main sub-pixel electrode M has four domains, and the main sub-pixel electrode M includes a first vertical main electrode, a first horizontal main electrode, two side electrodes 3 and a first branch electrode.
  • the first vertical main electrode perpendicularly intersects the first horizontal main body and divides into four first branch areas.
  • the first branch electrodes are arranged in the four first branch areas.
  • One end of the first branch electrode is connected to the first vertical main electrode or/ Connected to the first horizontal main electrode, the other end of the first branch electrode is connected to the side electrode, the angle between the first branch electrode and the first horizontal main electrode or the first vertical main electrode is 45 degrees, two adjacent areas
  • the first branch electrode is symmetrically arranged with respect to the first horizontal main electrode or the first vertical main electrode, the two side electrodes are located on opposite sides of the first vertical main electrode, and one side electrode 3 extends to the first switch T1 through the via hole It is electrically connected to the first switch T1.
  • the first sub-pixel electrode Sub1 is electrically connected to the second end of the second switch T2.
  • the first sub-pixel electrode has four domains.
  • the first sub-pixel electrode Sub1 includes a second vertical main electrode, a second horizontal main electrode, and a second branch electrode.
  • the second vertical main electrode perpendicularly intersects the second horizontal main electrode and divides into four second branch areas.
  • the second branch electrode is disposed in the second branch area.
  • One end of the second branch electrode is connected to the second vertical main electrode or the second One of the horizontal main electrodes is connected, one end of the second branch electrode is connected to one of the second vertical main electrode or the second horizontal main electrode, between the second branch electrode and the second horizontal main electrode or the second vertical main electrode.
  • the included angle is 45 degrees, and the second branch electrodes of two adjacent areas are symmetrically arranged with respect to the second horizontal main electrode or the second vertical main electrode.
  • a second branch electrode extends to the second switch T2, and is electrically connected to the second terminal of the second switch T2 through a via hole.
  • the second sub-pixel electrode Sub2 is electrically connected to the second end of the third switch T3.
  • the second sub-pixel Sub2 has four domains.
  • the second sub-pixel electrode Sub2 is the same as the first sub-pixel electrode Sub1, and will not be described in detail here.
  • two data lines are located on opposite sides of the main sub-pixel electrode M, the first sub-pixel electrode Sub1, and the second sub-pixel electrode Sub2.
  • the two side electrodes 3 extend to opposite sides of the first sub-pixel electrode Sub1 and are located between the data line and the first sub-pixel electrode Sub1.
  • one side electrode 3 serves to connect the main sub-pixel electrode M and the first switch. The function of the second end of T1.
  • the two side electrodes 3 are symmetrically arranged on opposite sides of the first pixel electrode Sub1 to act as a shield to avoid loading of the two data lines (data line D1 and data line D2)
  • the electric signal interferes with the electric field formed by the first sub-pixel electrode Sub1 and the first common electrode CFcom.
  • the shared electrode SB and the data line are arranged in the same layer.
  • the shared electrode SB and the data line are obtained by patterning the second metal layer.
  • the portion of the shared electrode SB overlaps with the first vertical main electrode of the main sub-pixel electrode M, the second vertical main electrode of the first sub-pixel electrode Sub1, and the third vertical main electrode of the second sub-pixel electrode Sub2 to improve the sub-pixel At the same time, it prevents the voltage on the shared electrode SB from affecting the electric field formed by the main sub-pixel electrode M, the first sub-pixel electrode Sub1, and the second sub-pixel electrode Sub2.
  • the first switch T1, the second switch T2, and the third switch T3 are all thin film transistors. Specifically, the first switch T1, the second switch T2, and the third switch T3 are all polysilicon thin film transistors. The first terminal of the first switch T1, the first terminal of the second switch T2, and the first terminal of the third switch T3 are all sources. The second terminal of the first switch T1, the second terminal T2 of the second switch, and the second terminal of the third switch T3 are all drains. The first switch T1, the second switch T2, and the third switch T3 are all the same, so that the ratio of the channel width to the channel length of the first switch T1, the second switch T2, and the third switch T3 is the same. The leakage capability of the second switch T2 and the third switch T3 are the same. The first terminals of the first switch T1, the second switch T2, and the third switch T3 are C-shaped. The active layers of the first switch T1, the second switch T2, and the third switch T3 are all semicircular.
  • the first liquid crystal capacitor Clc1, the second liquid crystal capacitor Clc2, and the third liquid crystal capacitor Clc3 are the same.
  • the capacitance value of the first liquid crystal capacitor Clc1, the capacitance value of the second liquid crystal capacitor Clc2, and the third liquid crystal capacitor Clc3 are the same.
  • the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 are the same.
  • the capacitance value of the first storage capacitor Cst1, the capacitance value of the second storage capacitor Cst2, and the third storage capacitor Cst3 are the same.
  • the first common electrode CFcom is located on the color filter substrate of the liquid crystal display panel
  • the second common electrode Acom is located on the array substrate of the liquid crystal display panel
  • the voltage applied to the first common electrode CFcom and the second common electrode Acom is All are constant pressure.
  • Each sub-pixel of this application is composed of three four-domain Y-shaped sub-pixels (main sub-pixel, first sub-pixel, and second sub-pixel), including three identical charging thin film transistors and two leakage thin film transistors, which is conducive to The leakage capability of the two leakage thin film transistors is different, and the potential difference between the main sub-pixel, the first sub-pixel, and the second sub-pixel is realized, and a twelve-domain display area is obtained, which greatly improves the viewing angle.
  • the application also provides a liquid crystal display panel, which is a vertical alignment type liquid crystal display panel.
  • the liquid crystal display panel includes the above-mentioned pixels.

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Abstract

一种像素及液晶显示面板，像素包括至少一个子像素，每个子像素包括一个主子像素、第一次子像素以及第二次子像素，主子像素的驱动电压、第一次子像素的驱动电压以及第二次子像素的驱动电压均相异，实现三个子像素的电位差，大幅度改善大尺寸液晶显示面板显示时的垂直视角。

Description

像素及液晶显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素及液晶显示面板。
 背景技术
对于垂直配向型（Vertical Alignment，VA）液晶显示面板，液晶分子在不同视野角度下的双折射的差异较大，导致垂直配向型液晶显示面板出现大视角色偏，特别是，大尺寸垂直配向型液晶显示面板存在垂直视角的色偏。
目前，随着液晶显示面板的快速发展，满足垂直配向型液晶显示面板日益增加的广视角需求是需要解决的问题。
 技术问题
本申请的目的在于提供一种像素及显示面板，以改善大尺寸液晶显示面板垂直视角。
 技术解决方案
为实现上述目的，本申请提供一种像素及液晶显示面板，
一种像素，所述像素包括至少一个子像素，每个所述子像素包括主子像素、第一次子像素以及第二次子像素，
所述主子像素包括第一开关以及第一液晶电容器，所述第一开关的控制端连接扫描线，所述第一开关的第一端连接数据线，所述第一开关的第二端连接第一节点，所述第一液晶电容器连接于所述第一节点和第一公共电极之间；
所述第一次子像素包括第二开关、第一分压单元以及第二液晶电容器，所述第二开关的控制端连接所述扫描线，所述第二开关的第一端连接所述数据线，所述第二开关的第二端连接第二节点，所第二液晶电容器连接于所述第二节点和所述第一公共电极之间，所述第一分压单元连接于所述第二节点和共享电极之间；
所述第二次子像素包括第三开关、第二分压单元以及第三液晶电容器，所述第三开关的控制端连接所述扫描线，所述第三开关的第一端连接所述数据线，所述第三开关的第二端连接第三节点，所述第三液晶电容器连接于所述第三节点和所述第一公共电极之间，所述第二分压单元连接于所述第三节点和所述共享电极之间；
所述第一分压单元用于通过分压作用控制所述第二节点的电位，所述第二分压单元用于通过分压作用控制所述第三节点的电位，以使第一节点的电位、所述第二节点的电位以及所述第三节点的电位相异。
在上述像素中，所述第一分压单元为第一薄膜晶体管，所述第二分压单元为第二薄膜晶体管；
所述第一薄膜晶体管的控制端连接所述扫描线，第一端连接所述第二节点，第二端连接所述共享电极；
所述第二薄膜晶体管的控制端连接所述扫描线，第一端连接所述第三节点，第二端连接所述共享电极；
所述第一薄膜晶体管的沟道宽度与沟道长度之比与所述第二薄膜晶体管的沟道宽度与沟道长度之比相异。
在上述像素中所述主子像素包括主子像素电极，所述第一次子像素包括第一次子像素电极，所述第二次子像素包括第二次子像素电极，同一所述子像素中，所述第一次子像素电极位于所述主子像素电极和所述第二次子像素电极之间且所述主子像素电极、所述第一次子像素电极以及所述第二次子像素电极呈直线设置，所述主子像素电极与所述第一开关的第二端电性连接，所述第一次子像素电极与所述第二开关的第二端电性连接，所述第二次子像素电极与所述第三开关的第二端电性连接，所述第一薄膜晶体管的沟道宽度与沟道长度之比小于所述第二薄膜晶体管的沟道宽度与沟道长度之比。
在上述像素中，两个所述数据线位于所述主子像素电极、所述第一次子像素电极以及所述第二次子像素电极的相对两侧，所述主子像素电极包括两个侧电极，两个所述侧电极延伸至所述第一次子像素电极的相对两侧且位于所述数据线和所述第一次子像素电极之间。
在上述像素中，所述主子像素电极、第一次子像素电极以及第二次子像素电极均具有四畴。
在上述像素中，所述共享电极与所述数据线同层设置。
在上述像素中，所述第一开关、第二开关以及所述第三开关均为薄膜晶体管，且所述第一开关、第二开关以及所述第三开关均相同。
在上述像素中，所述第一液晶电容器的电容值、所述第二液晶电容器的电容值以及所述第三液晶电容器的电容值均相同。
在上述像素中，所述子像素还包括第一存储电容器、第二存储电容器以及第三存储电容器，所述第一存储电容器连接于所述第一节点和第二公共电极之间，所述第二存储电容器连接于所述第二节点和所述第二公共电极之间，所述第三存储电容器连接于所述第三节点和所述第二公共电极之间。
一种液晶显示面板，所述液晶显示面板包括像素，所述像素包括至少一个子像素，每个所述子像素包括一主子像素、第一次子像素以及第二次子像素，
所述主子像素包括第一开关以及第一液晶电容器，所述第一开关的控制端连接扫描线，所述第一开关的第一端连接数据线，所述第一开关的第二端连接第一节点，所述第一液晶电容器连接于所述第一节点和第一公共电极之间；
所述第一次子像素包括第二开关、第一分压单元以及第二液晶电容器，所述第二开关的控制端连接所述扫描线，所述第二开关的第一端连接所述数据线，所述第二开关的第二端连接第二节点，所第二液晶电容器连接于所述第二节点和所述第一公共电极之间，所述第一分压单元连接于所述第二节点和共享电极之间；
所述第二次子像素包括第三开关、第二分压单元以及第三液晶电容器，所述第三开关的控制端连接所述扫描线，所述第三开关的第一端连接所述数据线，所述第三开关的第二端连接第三节点，所述第三液晶电容器连接于所述第三节点和所述第一公共电极之间，所述第二分压单元连接于所述第三节点和所述共享电极之间；
所述第一分压单元用于通过分压作用控制所述第二节点的电位，所述第二分压单元用于通过分压作用控制所述第三节点的电位，以使所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位相异。
在上述液晶显示面板中，所述第一分压单元为第一薄膜晶体管，所述第二分压单元为第二薄膜晶体管；
所述第一薄膜晶体管的控制端连接所述扫描线，第一端连接所述第二节点，第二端连接所述共享电极；
所述第二薄膜晶体管的控制端连接所述扫描线，第一端连接所述第三节点，第二端连接所述共享电极；
所述第一薄膜晶体管的沟道宽度与沟道长度之比与所述第二薄膜晶体管的沟道宽度与沟道长度之比相异。
在上述液晶显示面板中，所述主子像素包括主子像素电极，所述第一次子像素包括第一次子像素电极，所述第二次子像素包括第二次子像素电极，同一所述子像素中，所述第一次子像素电极位于所述主子像素电极和所述第二次子像素电极之间且所述主子像素电极、所述第一次子像素电极以及所述第二次子像素电极呈直线设置，所述主子像素电极与所述第一开关的第二端电性连接，所述第一次子像素电极与所述第二开关的第二端电性连接，所述第二次子像素电极与所述第三开关的第二端电性连接，所述第一薄膜晶体管的沟道宽度与沟道长度之比小于所述第二薄膜晶体管的沟道宽度与沟道长度之比。
在上述液晶显示面板中，两个所述数据线位于所述主子像素电极、所述第一次子像素电极以及所述第二次子像素电极的相对两侧，所述主子像素电极包括两个侧电极，两个所述侧电极延伸至所述第一次子像素电极的相对两侧且位于所述数据线和所述第一次子像素电极之间。
在上述液晶显示面板中，所述主子像素电极、第一次子像素电极以及第二次子像素电极均具有四畴。
在上述液晶显示面板中，所述共享电极与所述数据线同层设置。
在上述液晶显示面板中，所述第一开关、第二开关以及所述第三开关均为薄膜晶体管，且所述第一开关、第二开关以及所述第三开关均相同。
在上述液晶显示面板中，所述第一液晶电容器的电容值、所述第二液晶电容器的电容值以及所述第三液晶电容器的电容值均相同。
在上述液晶显示面板中，所述子像素还包括第一存储电容器、第二存储电容器以及第三存储电容器，所述第一存储电容器连接于所述第一节点和第二公共电极之间，所述第二存储电容器连接于所述第二节点和所述第二公共电极之间，所述第三存储电容器连接于所述第三节点和所述第二公共电极之间。
 有益效果
本申请提供一种像素及液晶显示面板，像素包括至少一个子像素，每个子像素包括一个主子像素、第一次子像素以及第二次子像素，第一次像素包括第一分压单元，第二次像素包括第二分压单元，第一分压单元控制第二节点的电位，第二分压单元控制第三节点的电位，以使第一节点的电位、第二节点的电位以及第三节点的电位相异，以使第一液晶电容器充电后的电压、第二液晶电容充电后的电压以及第三液晶电容器充电后的电压相异，使得主子像素的驱动电压、第一次子像素的驱动电压以及第二次子像素的驱动电压均相异，实现三个子像素的电位差，大幅度改善液晶显示面板显示时的视角，特别是大尺寸液晶显示面板的垂直视角。另外，第一分压单元和第二分压单元均与共享电极连接，通过控制共享电极的电位，使得第二节点和第三节点的电位可以根据实际需要进行调整，从而控制第一次子像素和第二次子像素的驱动电压具有可调节性。而且，同一子像素中，第一分压单元和第二分压单元共用一条共享电极，可以提高子像素的开口率。
 附图说明
图1为本申请实施例子像素的平面示意图；
图2为图1所示子像素对应的电路图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请提供一种像素，像素包括至少一个子像素，子像素可以为红色子像素、蓝色子像素以及绿色子像素。请参阅图1及图2，图1为本申请实施例子像素的平面示意图，图2为图1所示子像素对应的电路图。
每个子像素包括主子像素、第一次子像素以及第二次子像素。主像素、第一次子像素以及第二次子像素的驱动电压互异，使得主像素、第一次像素以及第二次像素中任意两者之间的电压差不等于0，具有该子像素的液晶显示面板具有更宽广的视角，特别是能改善大尺寸液晶显示面板的垂直视角。
主子像素包括第一开关T1、第一液晶电容器Clc1以及第一存储电容器Cst1。第一开关T1的控制端连接扫描线S，第一开关T1的第一端连接数据线D1，第一开关T1的第二端连接第一节点Q1。第一液晶电容器Clc1连接于第一节点Q1和第一公共电极CFcom之间。第一存储电容器Cst1连接于第一节点Q1和第二公共电极Acom之间。
第一次像素包括第二开关T2、第一分压单元1、第二液晶电容器Clc2以及第二存储电容器Cst2。第二开关T2的控制端连接扫描线S，第二开关T2的第一端连接数据线D1，第二开关T2的第二端连接第二节点Q2。第二液晶电容器Clc2连接于第二节点Q2和第一公共电极CFcom之间。第二存储电容器Cst2连接于第二节点Q2和第二公共电极Acom之间。第一分压单元1连接于第二节点Q2和共享电极SB(Sharebar)之间。
第二次像素包括第三开关T3、第二分压单元2、第三液晶电容器Clc3以及第三存储电容器Cst3。第三开关T3的控制端连接扫描线S，第三开关T3的第一端连接数据线D1，第三开关T3的第二端连接第三节点Q3。第三液晶电容器Clc3连接于第三节点Q3和第一公共电极CFcom之间。第三存储电容器Cst3连接于第三节点Q3和第二公共电极Acom之间。第二分压单元2连接于第三节点Q3和共享电极SB之间。
扫描线S载入扫描信号以使第一开关T1、第二开关T2以及第三开关T3打开后，数据线D1向第一开关T1、第二开关T2以及第三开关T3中写入驱动信号，第一分压单元1用于通过分压作用控制第二节点Q2的电位，第二分压单元2用于通过分压作用控制第三节点Q3的电位，以使第一节点Q1、第二节点Q2的电位以及第三节点Q3的电位相异，第一液晶电容器Clc1充电后的电压、第二液晶电容器Clc2以及第三液晶电容器Clc3充电后的电压相异，主子像素的驱动电压、第一次子像素的驱动电压以及第二次子像素的驱动电压均相异，实现三个子像素的电压差，大幅度改善大尺寸液晶显示面板显示时的垂直视角。另外，第一分压单元1和第二分压单元2均与共享电极SB连接，通过控制共享电极SB的电位，使得第二节点Q2和第三节点Q3的电位可以根据实际需要进行调整，相对于第一分压单元1和第二单元2与具有固定电位的电极（例如第一公共电极CFcom和第二公共电极Acom）连接，本申请第一次子像素和第二次子像素的驱动电压具有可调节性。
在本实施例中，第一分压单元1为第一薄膜晶体管T4，第二分压单元2为第二薄膜晶体管T5。第一薄膜晶体管T4的控制端连接扫描线，第一端连接第二节点Q2，第二端连接共享电极SB。第二薄膜晶体管T5的控制端连接扫描线S，第一端连接第三节点Q3，第二端连接共享电极SB。第一薄膜晶体管T4的沟道宽度与沟道长度之比小于第二薄膜晶体管T5的沟道宽度与沟道长度之比相异，第一薄膜晶体管T4的漏电能力与第二薄膜晶体管T5的漏电能力相异。具体地，第一薄膜晶体管T4的沟道宽度与沟道长度之比小于第二薄膜晶体管T5的沟道宽度与沟道长度之比。第一薄膜晶体管T4和第二薄膜晶体管T5均为多晶硅薄膜晶体管。第一薄膜晶体管T4和第二薄膜晶体管T5的第一端和第二端均为条状，第一薄膜晶体管T4和第二薄膜晶体管T5的有源层均为矩形。
在本实施例中，主子像素包括主子像素电极M。第一次子像素包括第一次子像素电极Sub1。第二次子像素包括第二次子像素电极Sub2。同一子像素中，第一次子像素电极Sub1位于主子像素电极M和第二次子像素Sub2之间且主子像素电极M、第一次子像素电极Sub1以及第二次子像素电极Sub2呈直线设置。第一次子像素电极Sub1和第二次子像素Sub2之间设置有第一开关T1、第二开关T2、第三开关T3、第一分压单元1以及第二分压单元2，以使得子像素的开口率更大。主子像素电极M、第一次子像素电极Sub1以及第二次子像素电极Sub2同层设置，且通过图案化同一透明导电层得到，透明导电层为氧化铟锡层。第二开关T2靠近第一次子像素电极Sub1设置，以便于第二开关T2的第二端与第一次子像素电极Sub1之间连接，第三开关T3靠近第二次子像素电极Sub2连接，以便于第三开关T3的第二端与第二次子像素电极Sub2连接。
主子像素电极M与第一开关T1的第二端电性连接。主子像素电极M具有四畴，主子像素电极M包括一个第一垂直主干电极、一个第一水平主干电极、两个侧电极3以及第一分支电极。第一垂直主干电极与第一水平主干垂直相交，且划分出四个第一分支区，第一分支电极设置于四个第一分支区，第一分支电极的一端与第一垂直主干电极或/和第一水平主干电极连接，第一分支电极的另一端与侧电极连接，第一分支电极与第一水平主干电极或第一垂直主干电极之间的夹角为45度，相邻两个区的第一分支电极关于第一水平主干电极或第一垂直主干电极对称设置，两个侧电极位于第一垂直主干电极的相对两侧，其中一侧电极3延伸至第一开关T1，通过过孔与第一开关T1电性连接。
第一次子像素电极Sub1与第二开关T2的第二端电性连接。第一次子像素电极具有四畴。第一次子像素电极Sub1包括一个第二垂直主干电极、第二水平主干电极以及第二分支电极。第二垂直主干电极与第二水平主干电极垂直相交，且划分出四个第二分支区，第二分支电极设置于第二分支区，第二分支电极的一端与第二垂直主干电极或第二水平主干电极中的一者连接，第二分支电极的一端与第二垂直主干电极或第二水平主干电极中的一者，第二分支电极与第二水平主干电极或第二垂直主干电极之间的夹角为45度，相邻两个区的第二分支电极关于第二水平主干电极或第二垂直主干电极对称设置。其中，一个第二分支电极延伸至第二开关T2，通过过孔与第二开关T2的第二端电性连接。
第二次子像素电极Sub2与第三开关T3的第二端电性连接。第二次子像素Sub2具有四畴。第二次子像素电极Sub2与第一次子像素电极Sub1相同，此处不作详述。
如图1所示，两个数据线(数据线D1和数据线D2)位于主子像素电极M、第一次子像素电极Sub1以及第二次子像素电极Sub2的相对两侧，主子像素电极M的两个侧电极3延伸至第一次子像素电极Sub1的相对两侧且位于数据线和第一次子像素电极Sub1之间，一方面一个侧电极3起到连接主子像素电极M与第一开关T1的第二端的作用，另一方面，两个侧电极3对称设置于第一次像素电极Sub1的相对两侧起到屏蔽作用，避免两个数据线（数据线D1和数据线D2）载入电信号时干扰第一次子像素电极Sub1与第一公共电极CFcom形成的电场。
在本实施例中，共享电极SB与数据线同层设置。共享电极SB与数据线是通过图案化第二金属层得到。共享电极SB的部分与主子像素电极M的第一垂直主干电极、第一次子像素电极Sub1的第二垂直主干电极以及第二次子像素电极Sub2的第三垂直主干电极重合，以提高子像素的开口率的同时，避免共享电极SB上的电压影响主子像素电极M、第一次子像素电极Sub1以及第二次子像素电极Sub2形成的电场。
第一开关T1、第二开关T2以及第三开关T3均为薄膜晶体管。具体地，第一开关T1、第二开关T2以及第三开关T3均为多晶硅薄膜晶体管。第一开关T1的第一端、第二开关T2的第一端以及第三开关T3的第一端均为源极。第一开关T1的第二端、第二开关的第二端T2以及第三开关的T3的第二端均为漏极。第一开关T1、第二开关T2以及第三开关T3均相同，使得第一开关T1、第二开关T2以及第三开关T3的沟道宽度与沟道长度之比相同，第一开关T1、第二开关T2以及第三开关T3的漏电能力相同。第一开关T1、第二开关T2以及第三开关T3的第一端呈C型。第一开关T1、第二开关T2以及第三开关T3的有源层均为半圆形。
在本实施例中，第一液晶电容器Clc1、第二液晶电容器Clc2以及第三液晶电容器Clc3均相同，第一液晶电容器Clc1的电容值、第二液晶电容器Clc2的电容值以及第三液晶电容器Clc3的电容值均相同。
在本实施例中，第一存储电容器Cst1、第二存储电容器Cst2以及第三存储电容器Cst3均相同，第一存储电容器Cst1的电容值、第二存储电容器Cst2的电容值以及第三存储电容器Cst3的电容值均相同。
在本实施例中，第一公共电极CFcom位于液晶显示面板的彩膜基板上，第二公共电极Acom位于液晶显示面板的阵列基板上，第一公共电极CFcom和第二公共电极Acom载入的电压均为恒压。
本申请每个子像素由三个四畴米字型的子像素（主子像素、第一次子像素以及第二次子像素）组成，包括三个相同的充电薄膜晶体管以及两个漏电薄膜晶体管，利于两个漏电薄膜晶体管的漏电能力不同，实现主子像素、第一次子像素以及第二次子像素的电位差，而获得十二畴显示分区，大幅度改善视角。
本申请还提供一种液晶显示面板，液晶显示面板为垂直配向型液晶显示面板。液晶显示面板包括上述像素。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种像素，其中，所述像素包括至少一个子像素，每个所述子像素包括一主子像素、第一次子像素以及第二次子像素，
    所述主子像素包括第一开关以及第一液晶电容器，所述第一开关的控制端连接扫描线，所述第一开关的第一端连接数据线，所述第一开关的第二端连接第一节点，所述第一液晶电容器连接于所述第一节点和第一公共电极之间；
    所述第一次子像素包括第二开关、第一分压单元以及第二液晶电容器，所述第二开关的控制端连接所述扫描线，所述第二开关的第一端连接所述数据线，所述第二开关的第二端连接第二节点，所第二液晶电容器连接于所述第二节点和所述第一公共电极之间，所述第一分压单元连接于所述第二节点和共享电极之间；
    所述第二次子像素包括第三开关、第二分压单元以及第三液晶电容器，所述第三开关的控制端连接所述扫描线，所述第三开关的第一端连接所述数据线，所述第三开关的第二端连接第三节点，所述第三液晶电容器连接于所述第三节点和所述第一公共电极之间，所述第二分压单元连接于所述第三节点和所述共享电极之间；
    所述第一分压单元用于通过分压作用控制所述第二节点的电位，所述第二分压单元用于通过分压作用控制所述第三节点的电位，以使所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位相异。
  2. 根据权利要求1所述的像素，其中，所述第一分压单元为第一薄膜晶体管，所述第二分压单元为第二薄膜晶体管；
    所述第一薄膜晶体管的控制端连接所述扫描线，第一端连接所述第二节点，第二端连接所述共享电极；
    所述第二薄膜晶体管的控制端连接所述扫描线，第一端连接所述第三节点，第二端连接所述共享电极；
    所述第一薄膜晶体管的沟道宽度与沟道长度之比与所述第二薄膜晶体管的沟道宽度与沟道长度之比相异。
  3. 根据权利要求2所述的像素，其中，所述主子像素包括主子像素电极，所述第一次子像素包括第一次子像素电极，所述第二次子像素包括第二次子像素电极，同一所述子像素中，所述第一次子像素电极位于所述主子像素电极和所述第二次子像素电极之间且所述主子像素电极、所述第一次子像素电极以及所述第二次子像素电极呈直线设置，所述主子像素电极与所述第一开关的第二端电性连接，所述第一次子像素电极与所述第二开关的第二端电性连接，所述第二次子像素电极与所述第三开关的第二端电性连接，所述第一薄膜晶体管的沟道宽度与沟道长度之比小于所述第二薄膜晶体管的沟道宽度与沟道长度之比。
  4. 根据权利要求3所述的像素，其中，两个所述数据线位于所述主子像素电极、所述第一次子像素电极以及所述第二次子像素电极的相对两侧，所述主子像素电极包括两个侧电极，两个所述侧电极延伸至所述第一次子像素电极的相对两侧且位于所述数据线和所述第一次子像素电极之间。
  5. 根据权利要求3所述的像素，其中，所述主子像素电极、第一次子像素电极以及第二次子像素电极均具有四畴。
  6. 根据权利要求1所述的像素，其中，所述共享电极与所述数据线同层设置。
  7. 根据权利要求1所述的像素，其中，所述第一开关、第二开关以及所述第三开关均为薄膜晶体管，且所述第一开关、第二开关以及所述第三开关均相同。
  8. 根据权利要求1所述的像素，其中，所述第一液晶电容器的电容值、所述第二液晶电容器的电容值以及所述第三液晶电容器的电容值均相同。
  9. 根据权利要求1所述的像素，其中，所述子像素还包括第一存储电容器、第二存储电容器以及第三存储电容器，所述第一存储电容器连接于所述第一节点和第二公共电极之间，所述第二存储电容器连接于所述第二节点和所述第二公共电极之间，所述第三存储电容器连接于所述第三节点和所述第二公共电极之间。
  10. 一种液晶显示面板，其中，所述液晶显示面板包括像素，所述像素包括至少一个子像素，每个所述子像素包括一主子像素、第一次子像素以及第二次子像素，
    所述主子像素包括第一开关以及第一液晶电容器，所述第一开关的控制端连接扫描线，所述第一开关的第一端连接数据线，所述第一开关的第二端连接第一节点，所述第一液晶电容器连接于所述第一节点和第一公共电极之间；
    所述第一次子像素包括第二开关、第一分压单元以及第二液晶电容器，所述第二开关的控制端连接所述扫描线，所述第二开关的第一端连接所述数据线，所述第二开关的第二端连接第二节点，所第二液晶电容器连接于所述第二节点和所述第一公共电极之间，所述第一分压单元连接于所述第二节点和共享电极之间；
    所述第二次子像素包括第三开关、第二分压单元以及第三液晶电容器，所述第三开关的控制端连接所述扫描线，所述第三开关的第一端连接所述数据线，所述第三开关的第二端连接第三节点，所述第三液晶电容器连接于所述第三节点和所述第一公共电极之间，所述第二分压单元连接于所述第三节点和所述共享电极之间；
    所述第一分压单元用于通过分压作用控制所述第二节点的电位，所述第二分压单元用于通过分压作用控制所述第三节点的电位，以使所述第一节点的电位、所述第二节点的电位以及所述第三节点的电位相异。
  11. 根据权利要求10所述的液晶显示面板，其中，所述第一分压单元为第一薄膜晶体管，所述第二分压单元为第二薄膜晶体管；
    所述第一薄膜晶体管的控制端连接所述扫描线，第一端连接所述第二节点，第二端连接所述共享电极；
    所述第二薄膜晶体管的控制端连接所述扫描线，第一端连接所述第三节点，第二端连接所述共享电极；
    所述第一薄膜晶体管的沟道宽度与沟道长度之比与所述第二薄膜晶体管的沟道宽度与沟道长度之比相异。
  12. 根据权利要求11所述的液晶显示面板，其中，所述主子像素包括主子像素电极，所述第一次子像素包括第一次子像素电极，所述第二次子像素包括第二次子像素电极，同一所述子像素中，所述第一次子像素电极位于所述主子像素电极和所述第二次子像素电极之间且所述主子像素电极、所述第一次子像素电极以及所述第二次子像素电极呈直线设置，所述主子像素电极与所述第一开关的第二端电性连接，所述第一次子像素电极与所述第二开关的第二端电性连接，所述第二次子像素电极与所述第三开关的第二端电性连接，所述第一薄膜晶体管的沟道宽度与沟道长度之比小于所述第二薄膜晶体管的沟道宽度与沟道长度之比。
  13. 根据权利要求12所述的液晶显示面板，其中，两个所述数据线位于所述主子像素电极、所述第一次子像素电极以及所述第二次子像素电极的相对两侧，所述主子像素电极包括两个侧电极，两个所述侧电极延伸至所述第一次子像素电极的相对两侧且位于所述数据线和所述第一次子像素电极之间。
  14. 根据权利要求12所述的液晶显示面板，其中，所述主子像素电极、第一次子像素电极以及第二次子像素电极均具有四畴。
  15. 根据权利要求10所述的液晶显示面板，其中，所述共享电极与所述数据线同层设置。
  16. 根据权利要求10所述的液晶显示面板，其中，所述第一开关、第二开关以及所述第三开关均为薄膜晶体管，且所述第一开关、第二开关以及所述第三开关均相同。
  17. 根据权利要求10所述的液晶显示面板，其中，所述第一液晶电容器的电容值、所述第二液晶电容器的电容值以及所述第三液晶电容器的电容值均相同。
  18. 根据权利要求10所述的液晶显示面板，其中，所述子像素还包括第一存储电容器、第二存储电容器以及第三存储电容器，所述第一存储电容器连接于所述第一节点和第二公共电极之间，所述第二存储电容器连接于所述第二节点和所述第二公共电极之间，所述第三存储电容器连接于所述第三节点和所述第二公共电极之间。
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CN113823239B (zh) * 2021-09-27 2023-02-28 惠州华星光电显示有限公司 显示面板及显示装置
US11978414B2 (en) 2021-09-27 2024-05-07 Huizhou China Star Optoelectronics Display Co., Ltd. Display panel and display device
CN113985669A (zh) * 2021-10-27 2022-01-28 Tcl华星光电技术有限公司 一种阵列基板及显示面板
CN113985669B (zh) * 2021-10-27 2022-09-27 Tcl华星光电技术有限公司 一种阵列基板及显示面板
US12038658B2 (en) 2021-10-27 2024-07-16 Tcl China Star Optoelectronics Technology Co., Ltd. Array substrate and display panel

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