WO2021179747A1 - 阵列基板、显示装置及其控制方法 - Google Patents
阵列基板、显示装置及其控制方法 Download PDFInfo
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- WO2021179747A1 WO2021179747A1 PCT/CN2020/140386 CN2020140386W WO2021179747A1 WO 2021179747 A1 WO2021179747 A1 WO 2021179747A1 CN 2020140386 W CN2020140386 W CN 2020140386W WO 2021179747 A1 WO2021179747 A1 WO 2021179747A1
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- array substrate
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133308—Support structures for LCD panels, e.g. frames or bezels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
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- G—PHYSICS
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- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
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- G09G2320/02—Improving the quality of display appearance
- G09G2320/0257—Reduction of after-image effects
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45528—Indexing scheme relating to differential amplifiers the FBC comprising one or more passive resistors and being coupled between the LC and the IC
Definitions
- the present disclosure relates to the field of display technology, and in particular to an array substrate, a display device and a control method thereof.
- liquid crystal display technology has been successfully applied to display products such as notebook computers, monitors, and televisions.
- display products such as notebook computers, monitors, and televisions.
- people have put forward higher requirements for the display quality of liquid crystal products.
- an array substrate has a display area and a binding area located on one side of the display area, the display area includes a remote area away from the binding area; the array substrate includes: a substrate, which is disposed on the substrate and is located The common electrode of the display area, and the first common signal line and the feedback signal line provided on the substrate.
- the first common signal line and the feedback signal line are coupled to a portion of the common electrode located in the remote area, and the first common signal line and the feedback signal line extend to the binding area To be coupled to the circuit board.
- the feedback signal line is configured to monitor a common voltage signal of a part of the common electrode located in the remote area, and transmit the monitored common voltage signal to the circuit board.
- the first common signal line is configured to transmit the compensated common voltage signal to the part of the common electrode located in the remote area; the compensated common voltage signal is used by the circuit board according to the
- the common voltage signal obtained by monitoring is a signal obtained by compensating the common voltage signal.
- the array substrate includes two feedback signal lines, and the two feedback signal lines are respectively disposed on two opposite sides of the display area.
- the array substrate includes two first common signal lines, and the two first common signal lines are respectively disposed on two opposite sides of the display area; the first common signal line The position coupled with the common electrode is located on the side of the common electrode away from the binding area.
- the display area further includes a proximal area close to the binding area;
- the array substrate further includes: a second common signal line disposed on the substrate.
- the second common signal line is coupled to a portion of the common electrode located in the proximal region, and the second common signal line extends to the bonding area to be coupled to the circuit board;
- the two common signal lines are configured to transmit a common voltage signal or a compensated common voltage signal to a portion of the common electrode located in the proximal region.
- the array substrate includes two second common signal lines, and the two second common signal lines are respectively disposed on the opposite side of the proximal region close to the binding region. Both ends.
- the display area further includes a middle area located between the distal area and the proximal area;
- the array substrate further includes: a third common signal line provided on the substrate.
- the third common signal line extends to the bonding area to be coupled to the circuit board; the third common signal line is coupled to a portion of the common electrode located in the middle region; the third The common signal line is configured to transmit the compensated common voltage signal to the portion of the common electrode located in the middle region.
- the array substrate includes two third common signal lines, and the two third common signal lines are respectively disposed on two opposite sides of the display area.
- the feedback signal line and the first common signal line have the same material and are arranged in the same layer.
- the array substrate further includes: connecting leads and a conductive frame.
- the connecting lead is arranged outside the distal area of the display area, and the first common signal line and the feedback signal line are coupled with the connecting lead.
- the conductive frame surrounds the display area, and a part of the connection lead and the common electrode located in the remote area is coupled to the conductive frame, so that the first common signal line passes through the connection lead And the conductive frame is coupled to a portion of the common electrode located in the remote area, and the feedback signal line is coupled to a portion of the common electrode located in the remote area through the conductive frame.
- the first common signal line, the connecting lead and the conductive frame are made of the same material and arranged in the same layer.
- the resistance of the first common signal line, the resistance of the second common signal line, and the The resistance of the third common signal line is less than or equal to 300 ⁇ ; the resistance of the feedback signal line is less than or equal to 1000 ⁇ .
- the array substrate further includes: a data line disposed on the substrate. In a direction perpendicular to the substrate, the data line is closer to the substrate relative to the common electrode; the data line and the orthographic projection of the common electrode on the substrate at least partially overlap.
- the array substrate has a plurality of sub-pixel regions; the common electrode includes a plurality of sub-electrodes and a plurality of first conductive patterns; one sub-electrode is located in at least one sub-pixel region, and adjacent sub-electrodes pass through At least one first conductive pattern is coupled.
- a display device in another aspect, includes: the array substrate and the circuit board as described in any of the above embodiments.
- the circuit board is coupled to the array substrate through the binding area in the array substrate; the circuit board includes a control circuit, the control circuit and the first common signal line and the feedback signal line in the array substrate Coupled; the control circuit is configured to generate a first compensation common voltage signal according to the common voltage signal monitored by the feedback signal line, and transmit it to the first common signal line.
- the control circuit includes: an inverter and a first operational amplifier.
- the inverter is coupled to the feedback signal line; the inverter is configured to invert the monitored common voltage signal transmitted by the feedback signal line.
- the first operational amplifier is coupled to the inverter and the first common signal line; the first operational amplifier is configured to amplify the inverted signal from the inverter to generate the A first compensation common voltage signal, and the first compensation common voltage signal is transmitted to the first common signal line.
- the control circuit when the array substrate further includes a second common electrode line, the control circuit further includes a second operational amplifier.
- the second operational amplifier is coupled to the inverter and the second common signal line; the second operational amplifier is configured to amplify the inverted signal from the inverter to generate a second compensation common Voltage signal, and transmit the second compensation common voltage signal to the second common signal line; the amplification factor of the second operational amplifier is smaller than the amplification factor of the first operational amplifier.
- the control circuit when the array substrate further includes a third common electrode line, the control circuit further includes a third operational amplifier.
- the third operational amplifier is coupled to the inverter and the third common signal line; the third operational amplifier is configured to amplify the inverted signal from the inverter to generate a third compensation common Voltage signal, and transmit the third compensation common voltage signal to the third common signal line; the amplification factor of the third operational amplifier is smaller than the amplification factor of the first operational amplifier; the control circuit further includes In the case of the second operational amplifier, the amplification factor of the third operational amplifier is greater than the amplification factor of the second operational amplifier.
- a method for controlling a display device as described in any of the above embodiments including: a feedback signal line monitors a common voltage signal of a part of a common electrode located in a remote area, and monitors the obtained common voltage signal
- the control circuit is transmitted to the control circuit in the circuit board; the control circuit generates a first compensation common voltage signal according to the common voltage signal monitored by the feedback signal line, and transmits it to the first common signal line to detect the common electrode
- the common voltage signal of the part of the remote area is compensated.
- control circuit generates a second compensation common voltage signal based on the common voltage signal monitored by the feedback signal line, and transmits the second compensation common voltage signal to the second common signal line, so as to correct the common electrode at the proximal end. And/or, the control circuit generates a third compensation common voltage signal according to the common voltage signal monitored by the feedback signal line, and transmits it to the third common signal line to compensate The common voltage signal in the part of the common electrode located in the middle end region is compensated.
- FIG. 1 is a top view of an array substrate according to some embodiments
- FIG. 2 is another top view of an array substrate according to some embodiments.
- FIG. 3 is another top view of the array substrate according to some embodiments.
- FIG. 4 is a comparison waveform diagram of a common voltage signal in an array substrate according to some embodiments.
- FIG. 5 is still another top view of the array substrate according to some embodiments.
- FIG. 6 is another top view of an array substrate according to some embodiments.
- FIG. 7 is still another top view of an array substrate according to some embodiments.
- FIG. 8 is still another top view of an array substrate according to some embodiments.
- FIG. 9 is another top view of an array substrate according to some embodiments.
- FIG. 10 is still another top view of an array substrate according to some embodiments.
- FIG. 11 is still another top view of an array substrate according to some embodiments.
- FIG. 12 is a cross-sectional view of the array substrate in FIG. 11 along the direction C-C';
- FIG. 13 is a structural diagram of a display device according to some embodiments.
- FIG. 14 is another structural diagram of a display device according to some embodiments.
- FIG. 15 is another structural diagram of a display device according to some embodiments.
- Fig. 16 is a structural diagram of a control circuit according to some embodiments.
- FIG. 17 is another structural diagram of a display device according to some embodiments.
- Figure 18 is another structural diagram of a control circuit according to some embodiments.
- FIG. 19 is another structural diagram of a display device according to some embodiments.
- Fig. 20 is another structural diagram of a control circuit according to some embodiments.
- first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
- the expressions “coupled” and “connected” and their extensions may be used.
- the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
- the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
- the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
- the embodiments disclosed herein are not necessarily limited to the content of this document.
- At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
- a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
- the frame is relatively narrow (for example, the frame width is 3.5 mm).
- the width of the signal line is smaller, the resistance of the signal line is increased, and the recovery ability of the signal line is weakened.
- the resolution of the display device is relatively high (for example, the resolution is (2560 ⁇ 1440)), and the coupling capacitance (for example, the coupling capacitance formed between the data line and the common electrode) in the display device is relatively large, resulting in the signal transmission process
- the signal is distorted and the potential drift occurs, which affects the normal charging and discharging of the pixels, making the display device in the display stage, there will be line afterimages and it is difficult to eliminate.
- the residual image is the image retention, which is a static picture that remains on the screen for a long time. This phenomenon will change with the passage of time and the change of the picture, and finally disappear.
- the pixel electrode in a display device may accumulate charge due to coupling capacitors and other reasons. The long-term accumulation of charge will cause a potential difference and electric field between the pixel electrode and the common electrode to form, causing the liquid crystal to continue to flip, and these charges will gradually After-images appear in the process of disappearing, which affects the display effect.
- an embodiment of the present disclosure provides an array substrate 100.
- the array substrate 100 has a display area (AA; AA area for short; also called an effective display area) and a binding located on one side of the AA area.
- Set area B The AA area includes a remote area F away from the binding area B.
- the array substrate 100 includes a substrate 10, a common electrode 20, a first common signal line 30 and a feedback signal line 40.
- the common electrode 20 is disposed on the substrate 10 and located in the AA area.
- the material of the common electrode 20 may be a transparent conductive material including ITO (Indium Tin Oxide).
- the first common signal line 30 and the feedback signal line 40 are provided on the substrate 10.
- the first common signal line 30 and the feedback signal line 40 are coupled to the portion of the common electrode 20 located in the distal region F.
- the first common signal line 30 and the feedback signal line 40 extend to the bonding area B to be coupled with the circuit board.
- the feedback signal line 40 is configured to monitor the common voltage signal of the part of the common electrode 20 located in the remote area F, and transmit the monitored common voltage signal to the circuit board.
- the first common signal line 30 is configured to transmit the compensated common voltage signal to the portion of the common electrode 20 located in the remote area F.
- the compensated common voltage signal is a signal obtained by the circuit board compensating the common voltage signal according to the monitored common voltage signal.
- the area of the distal region F occupies 1/8 to 1/5 of the area of the AA region, for example, the area of the distal region F occupies 1/6 of the area of the AA region.
- the feedback signal line 40 monitors the common voltage signal of the part of the common electrode 20 located in the remote area F, and transmits the monitored common voltage signal to the circuit board, and the circuit board obtains the common voltage signal according to the monitored common voltage signal
- the compensated common voltage signal is transmitted to the part of the common electrode 20 located in the remote area F through the first common signal line 30, and the common voltage to the part of the common electrode 20 located in the remote area F
- the signal is compensated to avoid the delay of the common voltage signal in the part of the common electrode 20 located in the remote area F, thereby improving the display effect.
- the array substrate 100 provided by the embodiment of the present disclosure includes a first common signal line 30 and a feedback signal line 40.
- the first common signal line 30 and the feedback signal line 40 are coupled to the part of the common electrode 20 located in the remote area F. catch.
- the feedback signal line 40 monitors the common voltage signal of the part of the common electrode 20 located in the remote area F, and transmits the monitored common voltage signal to the circuit board to generate a compensated common voltage signal.
- the first common signal line 30 will compensate The latter common voltage signal is transmitted to the part of the common electrode 20 located in the remote area F, and the common voltage signal of the part of the common electrode 20 located in the remote area F is compensated to avoid the part of the common electrode 20 located in the remote area F.
- the delay of the common voltage signal can also avoid the afterimage of the display due to the potential drift of the common voltage signal, thereby improving the display effect.
- the array substrate 100 includes two feedback signal lines 40, and the two feedback signal lines 40 are respectively disposed on opposite sides of the AA area.
- the feedback signal line 40 monitors the common voltage signal of the part of the common electrode 20 located in the remote area F, and transmits the monitored common voltage signal to the circuit board
- the monitored common voltage can be shortened
- the signal transmission time quickly transmits the monitored common voltage signal to the circuit board, improving the compensation efficiency of the common voltage signal.
- the array substrate 100 includes two first common signal lines 30, and the two first common signal lines 30 are respectively disposed on opposite sides of the AA area.
- the position where the first common signal line 30 is coupled to the common electrode 20 is located on the side of the common electrode 20 away from the binding area B.
- the position where the first common signal line 30 is coupled to the common electrode 20 is the position of the common electrode 20 that is located at the remote area F farthest from the binding area B.
- the first common signal line 30 inputs the compensated common voltage signal from the part of the common electrode 20 that is located at the far end area F away from the binding area B. Compensating the common voltage signal in the part of the area F can improve the serious delay of the common voltage signal in the part of the common electrode 20 located in the remote area F, and avoid the distortion of the common voltage signal.
- the two first common signal lines 30 can shorten the time for compensating the common voltage signal of the part of the common electrode 20 located in the remote area F, and improve the compensation efficiency of the common voltage signal of the common electrode 20.
- part (a) in FIG. 4 is a waveform diagram before the common voltage signal in the array substrate 100 is compensated, and part (b) in FIG. 4 is after the common voltage signal in the array substrate 100 is compensated.
- the abscissa represents time ( ⁇ s)
- the ordinate represents the voltage (V) of the common voltage signal.
- one of the two first common signal lines 30 is the common voltage signal Vleft of one of the two opposite sides of the AA area (for example, the left side of the array substrate 100 in FIG. 3)
- the other one of the two first common signal lines 30 is located on the other side of the two opposite sides of the AA area (for example, the right side of the array substrate 100 in FIG. 3).
- the common voltage signal Vright may be It can be seen that the signal delay of the waveform of the common voltage signal in part (a) of Fig. 4 is relatively large, and the waveform of the common voltage signal in part (b) of Fig. 4 is compared with that of part (a) in Fig. 4 The potential drift of the waveform of the common voltage signal is significantly reduced, which avoids distortion of the common voltage signal and improves the recovery capability of the first common signal line 30.
- the AA area further includes a proximal area N close to the binding area B.
- the array substrate 100 further includes a second common signal line 50.
- the second common signal line 50 is coupled to a portion of the common electrode 20 located in the proximal region N, and the second common signal line 50 extends to the bonding area B to be coupled to the circuit board.
- the second common signal line 50 is configured to transmit the common voltage signal or the compensated common voltage signal to the portion of the common electrode 20 located in the proximal region N.
- the area of the proximal region N accounts for 1/8 to 1/5 of the area of the AA region, for example, the area of the proximal region N accounts for 1/6 of the area of the AA region.
- the feedback signal line 40 monitors the common voltage signal of the part of the common electrode 20 located in the remote area F, and transmits the monitored common voltage signal to the circuit board, and the circuit board obtains the common voltage signal according to the monitored common voltage signal
- the compensated common voltage signal is transmitted to the portion of the common electrode 20 located in the proximal region N through the second common signal line 50, and the common voltage to the portion of the common electrode 20 located in the proximal region N
- the signal is compensated to avoid the delay of the common voltage signal in the portion of the common electrode 20 located in the proximal region N, thereby improving the display effect.
- the array substrate 100 includes two second common signal lines 50, and the two second common signal lines 50 are respectively disposed on the opposite side of the proximal region N close to the bonding region B. The ends.
- the two first common signal lines 30 can shorten the compensated common voltage.
- the transmission time of the signal enables the common voltage signal of the part of the common electrode 20 located in the remote area F to be compensated relatively quickly, thereby improving the compensation efficiency of the common voltage signal of the common electrode 20.
- the AA region further includes a middle region M located between the distal region F and the proximal region N.
- the array substrate 100 further includes a third common signal line 60 provided on the substrate 10.
- the third common signal line 60 extends to the bonding area B to be coupled with the circuit board.
- the third common signal line 60 is coupled to a portion of the common electrode 20 located in the middle region M.
- the third common signal line 60 is configured to transmit the compensated common voltage signal to the portion of the common electrode 20 located in the middle region M.
- the area of the middle region M occupies 1/8 to 1/5 of the area of the AA region, for example, the area of the middle region M occupies 1/6 of the area of the AA region.
- the feedback signal line 40 monitors the common voltage signal of the part of the common electrode 20 located in the remote area F, and transmits the monitored common voltage signal to the circuit board.
- the circuit board responds to the monitored common voltage signal
- the common voltage signal is compensated to obtain the compensated common voltage signal.
- the third common signal line 60 transmits the compensated common voltage signal to the part of the common electrode 20 located in the central area M, and to the part of the common electrode 20 located in the central area M.
- Part of the common voltage signal is compensated to avoid the delay of the common voltage signal in the part of the common electrode 20 located in the middle region M, and improve the display effect.
- the array substrate 100 includes two third common signal lines 60, and the two third common signal lines 60 are respectively disposed on opposite sides of the AA area.
- the third common signal line 60 transmits the compensated common voltage signal to the part of the common electrode 20 located in the central region M
- the two third common signal lines 60 can shorten the compensated common voltage signal.
- the transmission time of the common electrode 20 allows the common voltage signal of the portion of the common electrode 20 located in the central region M to be compensated relatively quickly, thereby improving the efficiency of compensating the common voltage signal of the common electrode 20.
- the array substrate 100 includes two first common signal lines 30, two second common signal lines 50, two third common signal lines 60, and two feedback signal lines 40, The beneficial effects are similar to the above, and will not be repeated here.
- the feedback signal line 40 and the first common signal line 30 have the same material and are arranged in the same layer.
- the materials of the feedback signal line 40 and the first common signal line 30 may include copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr), tungsten (W), etc. metallic material.
- the feedback signal line 40 and the first common signal line 30 can be formed synchronously, so that the production process can be simplified in terms of process.
- the second common signal line 50 and the first common signal line 30 have the same material and are arranged in the same layer.
- the second common signal line 50 and the first common signal line 30 can be formed synchronously, so that the production process can be simplified in terms of process.
- the third common signal line 60 and the first common signal line 30 have the same material and are arranged in the same layer.
- the third common signal line 60 and the first common signal line 30 can be formed synchronously, so that the production process can be simplified in terms of process.
- the array substrate 100 further includes connecting leads 70 and a conductive frame 80.
- the connecting lead 70 is arranged outside the distal area F of the AA area, and the first common signal line 30 and the feedback signal line 40 are coupled to the connecting lead 70.
- the conductive frame 80 surrounds the AA area, and the part of the connecting lead 70 and the common electrode 20 located in the distal area F is coupled to the conductive frame 80, so that the first common signal line 30 passes through the connecting lead 70 and the conductive frame 80 and the common electrode 20
- the portion located in the remote area F is coupled, and the feedback signal line 40 is coupled to the portion located in the remote area F of the common electrode 20 through the conductive frame 80.
- the conductive frame 80 may be made of a metal material, such as copper, aluminum, or molybdenum.
- the first common signal line 30 is coupled to the part of the common electrode 20 located in the remote area F through the connecting lead 70 and the conductive frame 80, and the feedback signal
- the wire 40 is coupled to the part of the common electrode 20 located in the remote area F through the conductive frame 80, which can reduce the contact resistance between the first common signal line 30 and the feedback signal line 40 and the common electrode 20, and reduce the first common signal line 30 And feedback the loss of signal transmission between the signal line 40 and the common electrode 20.
- the second common signal line 50 and the third common signal line 60 pass through the conductive frame. 80 is coupled to the common electrode 20.
- the contact resistance between the second common signal line 50 and the third common signal line 60 and the common electrode 20 can be reduced, and the contact resistance between the second common signal line 50 and the third common signal line 60 and the common electrode 20 can be reduced. Loss of signal transmission.
- the first common signal line 30, the connecting lead 70 and the conductive frame 80 are made of the same material and arranged in the same layer.
- the first common signal line 30, the connecting lead 70 and the conductive frame 80 can be formed simultaneously, thereby reducing the production process in terms of process.
- the resistance of the first common signal line 30, the resistance of the second common signal line 50, and the third common signal line is less than or equal to 300 ⁇ .
- the resistance of the feedback signal line 40 is less than or equal to 1000 ⁇ .
- the resistance of the first common signal line 30 is 200 ⁇
- the resistance of the second common signal line 50 is 100 ⁇
- the resistance of the third common signal line 60 is 200 ⁇
- the resistance of the feedback signal line 40 is 500 ⁇ .
- the array substrate 100 has a plurality of sub-pixel regions P.
- the common electrode 20 includes a plurality of sub-electrodes 202 and a plurality of first conductive patterns 201.
- one sub-electrode 202 is located in at least one sub-pixel region P. Adjacent sub-electrodes 202 are coupled through at least one first conductive pattern 201.
- the sub-electrodes 202 in all the sub-pixel regions P may be connected as a whole through the first conductive pattern 201. Therefore, when the first common signal line 30 transmits the compensated common voltage signal to the sub-electrodes 202 located in the remote area F, the compensated common voltage signal can be transmitted to all the sub-electrodes 202, and all the sub-electrodes 202 can be The common voltage signal in the sub-electrode 202 is compensated so as to prevent the common voltage signal in the sub-electrode 202 from being delayed.
- the array substrate 100 further includes a data line 90 disposed on the substrate 10.
- the data line 90 is closer to the substrate 10 relative to the common electrode 20.
- the data line 90 and the orthographic projection of the common electrode 20 on the substrate 10 at least partially overlap.
- the display device 300 when the array substrate 100 is applied to a display device, as shown in FIG. 13, the display device 300 includes a counter substrate 400 disposed opposite to the array substrate 100, and is disposed between the array substrate 100 and the counter substrate 400.
- the liquid crystal layer 500 in between, and the backlight module 600 disposed on the side of the array substrate 100 away from the counter substrate 400.
- the opposite substrate 400 includes a black matrix (BM).
- the array substrate 100 further includes a thin film transistor (TFT) disposed in the sub-pixel region P.
- TFT thin film transistor
- a plurality of sub-pixel areas P may be arranged in an array.
- the sub-pixel areas P arranged in a row along the horizontal direction X are called sub-pixel areas in the same row, and the sub-pixel areas arranged in a row along the vertical direction Y P is called the sub-pixel area in the same column.
- the TFTs in the sub-pixel area of the same row can be electrically connected to one gate line 91.
- the TFTs in the sub-pixel area of the same column can be electrically connected to one data line 90.
- one sub-electrode 202 may be located in the same row of sub-pixel regions, and two adjacent rows of sub-electrodes 202 are coupled by the first conductive pattern 201.
- the first common signal line 30 and the gate line 91 have the same material and are arranged in the same layer. Therefore, in terms of process, the first common signal line 30 and the gate line 91 can be formed synchronously.
- the array substrate 100 further includes a pixel electrode 21 disposed on the side of the common electrode 20 close to the substrate 10.
- the TFT includes a gate electrode 12, an active layer 16, a source electrode 13, and a drain electrode 14 arranged on the substrate 10 in sequence.
- the pixel electrode 21 is coupled to the drain electrode 14 of the TFT through the second conductive pattern 17, and the second conductive pattern 17 and the common electrode 20 are made of the same material and arranged in the same layer.
- the array substrate 100 further includes a semiconductor pattern 22 located on the side of the data line 90 close to the substrate 10.
- the semiconductor pattern 22 and the active layer 16 of the TFT are made of the same material and arranged in the same layer.
- a pixel electrode 21 is formed on the substrate 10.
- the gate electrode 12 of the TFT and the active layer 16 are sequentially formed on the side of the pixel electrode 21 away from the substrate.
- a single slit mask (SSM), source 13 and drain 14 are used to form a passivation layer 11 on the side of the TFT away from the substrate 10.
- the embodiment of the present disclosure also provides a display device 300.
- the display device 300 includes the array substrate 100 and the circuit board 200 in any of the above-mentioned embodiments.
- the circuit board 200 is coupled to the array substrate 100 through the bonding area B in the array substrate 100.
- the circuit board 200 includes a control circuit 210 that is coupled to the first common signal line 30 and the feedback signal line 40 in the array substrate 100.
- the control circuit 210 is configured to form a first compensation common voltage signal according to the common voltage signal monitored by the feedback signal line 40 and transmit it to the first common signal line 30.
- the first compensation common voltage signal is obtained by the control circuit 210 after compensating the common voltage signal according to the monitored common voltage signal.
- the feedback signal line 40 and the first common signal line 30 are coupled to the part of the common electrode 20 located in the remote area F.
- the circuit board 200 may be a printed circuit board (Printed Circuit Board, PCB) or a flexible circuit board (Flexible Printed Circuit, FPC), etc.
- PCB printed Circuit Board
- FPC Flexible Printed Circuit
- the first compensation common voltage signal formed by the control electrode 210 according to the common voltage signal monitored by the feedback signal line 40 is transmitted to the part of the common electrode 20 located in the remote area F through the first common signal line 30 to communicate with the common
- the common voltage signal of the part of the electrode 20 located in the remote area F is compensated to avoid the delay of the common voltage signal of the portion of the common electrode 20 located in the remote area F, thereby improving the display effect.
- control circuit 210 includes an inverter 211 and a first operational amplifier 212.
- the inverter 211 is coupled to the feedback signal line 40.
- the first operational amplifier 212 is coupled to the inverter 211 and the first common signal line 30.
- the inverter 211 is configured to invert the monitored common voltage signal transmitted by the feedback signal line 40.
- the first operational amplifier 212 is configured to amplify the inverted signal from the inverter 211, generate a first compensation common voltage signal, and transmit the first compensation common voltage signal to the first common signal line 30.
- the monitored common voltage signal transmitted by the feedback signal line 40 that is, the common voltage signal of the part of the common electrode 20 located in the remote area F
- the monitored common voltage signal is distorted and potential drift occurs
- the generated first compensation common voltage signal can compensate for the distorted common voltage signal in the portion of the common electrode 20 located in the remote area F, thereby avoiding the common electrode 20
- the inverter 211 includes: an N-type transistor TN and a P-type transistor T P.
- the control electrode of the N-type transistor TN is coupled to the first input terminal IN1, the first electrode of the N-type transistor TN is coupled to the first voltage terminal VSS, and the second electrode of the N-type transistor TN is coupled to the first output terminal Out1 Coupling.
- the control electrode of the P-type transistor TP is coupled to the first input terminal Out1, the first electrode of the P-type transistor TP is coupled to the second voltage terminal VDD, and the second electrode of the P-type transistor TP is coupled to the first output terminal Out1 Coupling.
- the first input terminal IN1 is coupled to the feedback signal line 40, and the first output terminal Out1 is coupled to the first operational amplifier 212.
- the voltage of the first voltage terminal VSS and the voltage of the second voltage terminal VDD are the operating voltages of the inverter 211.
- the voltage of the first voltage terminal VSS is at a low DC level and can be used as the negative pole of the power supply
- the voltage at the second voltage terminal VDD is at a high DC level and can be used as the positive pole of the power supply.
- the N-type transistor T N when the voltage of the common voltage signal to monitor the transmission of a feedback signal line 40 is obtained so that the N-type transistor T N is turned on, P-type transistor T P is turned off, the common voltage signal to a high level signal, the N-type transistor TN transmits the first voltage signal received at the first voltage terminal VSS to the first output terminal Out1, and the signal at the first output terminal Out1 is a low-level signal, which realizes the inversion of the common voltage signal.
- the P-type transistor TP when the voltage of the monitored common voltage signal transmitted by the feedback signal line 40 causes the P-type transistor TP to be turned on, the N-type transistor TN is turned on and off, the common voltage signal is a low-level signal, and the P-type transistor T P transmits the second voltage signal received at the second voltage terminal VDD to the first output terminal Out1, and the signal at the first output terminal Out1 is a high-level signal, which realizes the inversion of the common voltage signal.
- the first operational amplifier 212 includes: a first amplifier OP1, a first resistor R1, a second resistor R2, and a third resistor R3.
- the positive input terminal of the first amplifier OP1 is coupled to the second terminal of the third resistor R3, and the negative input terminal of the first amplifier OP1 is coupled to the first terminal of the first resistor R1 and the first terminal of the second resistor R2.
- the output terminal of an amplifier OP1 is coupled to the first compensation common voltage signal output terminal Outf1.
- the second end of the first resistor R1 is grounded.
- the second terminal of the second resistor R2 is coupled to the first compensation common voltage signal output terminal Outf1.
- the first terminal of the third resistor R3 is coupled to the second input terminal IN2.
- the second input terminal IN2 is coupled to the first output terminal Out1 of the inverter 211, and the first compensation common voltage signal output terminal Outf1 is coupled to the first common signal line 20.
- the signal V IN2 received at the second input terminal IN2 is an inverted signal of the inverter 211, and the inverted signal is a common voltage signal obtained by inverting monitoring.
- the first compensation common voltage signal V f1 generated by the first operational amplifier 212 (1+R2/R1)V IN2 , and the amplification factor of the first operational amplifier 212 is (1+R2/R1).
- control circuit 210 when the array substrate 100 further includes the second common electrode line 50, the control circuit 210 further includes: a second operational amplifier 213.
- the second operational amplifier 213 is coupled to the inverter 211 and the second common signal line 50.
- the second operational amplifier 213 is configured to amplify the inverted signal from the inverter 211, generate a second compensation common voltage signal, and transmit the second compensation common voltage signal to the second common signal line 50.
- the amplification factor of the second operational amplifier 213 is smaller than the amplification factor of the first operational amplifier 212.
- the monitored common voltage signal transmitted by the feedback signal line 40 that is, the common voltage signal of the part of the common electrode 20 located in the remote area F
- the monitored common voltage signal is distorted and potential drift occurs
- the delay degree of the common voltage signal in the portion of the common electrode 20 located in the proximal region N is less than the degree of delay of the common voltage signal in the portion of the common electrode 20 located in the distal region F
- the inverted signal passes through the second operation
- the generated second compensation common voltage signal can compensate for the distorted common voltage signal in the portion of the common electrode 20 located in the proximal region N, thereby avoiding the common voltage signal in the portion of the common electrode 20 located in the proximal region N Delay.
- the second operational amplifier 213 includes: a second amplifier OP2, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.
- the positive input terminal of the second amplifier OP2 is coupled to the second terminal of the sixth resistor R6, and the negative input terminal of the second amplifier OP2 is coupled to the first terminal of the fourth resistor R4 and the first terminal of the fifth resistor R5.
- the output terminal of the second amplifier OP2 is coupled to the second compensation common voltage signal output terminal Outf2.
- the second end of the fourth resistor R4 is grounded.
- the second terminal of the fifth resistor R5 is coupled to the second compensation common voltage signal output terminal Outf2.
- the first terminal of the sixth resistor R6 is coupled to the second input terminal IN2.
- the second compensation common voltage signal output terminal Outf2 is coupled to the second common signal line 50.
- the second compensation common voltage signal V f2 generated by the second operational amplifier 213 (1+R5/R4)V IN2 , and the amplification factor of the second operational amplifier 213 is (1+R5/R4).
- control circuit 210 when the array substrate 100 further includes the third common electrode line 60, the control circuit 210 further includes: a third operational amplifier 214.
- the third operational amplifier 214 is coupled to the inverter 211 and the third common signal line 60.
- the third operational amplifier 214 is configured to amplify the inverted signal from the inverter 211, generate a third compensation common voltage signal, and transmit the third compensation common voltage signal to the third common signal line 60.
- the amplification factor of the third operational amplifier 214 is smaller than the amplification factor of the first operational amplifier 212.
- control circuit 210 further includes the second operational amplifier 213, the amplification factor of the third operational amplifier 214 is greater than the amplification factor of the second operational amplifier 213.
- the monitored common voltage signal transmitted by the feedback signal line 40 that is, the common voltage signal of the part of the common electrode 20 located in the remote area F
- the monitored common voltage signal is distorted and potential drift occurs
- the delay degree of the common voltage signal in the portion of the common electrode 20 located in the middle region M is smaller than the delay degree of the common voltage signal in the portion of the common electrode 20 located in the distal region F, and greater than that of the common electrode 20 located in the proximal region N
- the degree of delay of part of the common voltage signal is amplified by the third operational amplifier 214, the third compensation common voltage signal generated can compensate for the distorted common voltage signal in the portion of the common electrode 20 located in the central region M. , Thereby avoiding the delay of the common voltage signal in the portion of the common electrode 20 located in the middle region M.
- the third operational amplifier 214 includes: a third amplifier OP3, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.
- the positive input end of the third amplifier OP3 is coupled to the second end of the ninth resistor R9, and the negative input end of the third amplifier OP3 is coupled to the first end of the seventh resistor R7 and the second end of the eighth resistor R8.
- the output terminal of the three amplifier OP3 is coupled to the third compensation common voltage signal output terminal Outf3.
- the second end of the seventh resistor R7 is grounded.
- the second terminal of the eighth resistor R8 is coupled to the third compensation common voltage signal output terminal Outf3.
- the first terminal of the ninth resistor R9 is coupled to the second input terminal IN2.
- the third compensation common voltage signal output terminal Outf3 is coupled to the third common signal line 60.
- the three-compensated common voltage signal V f3 (1+R8/R7)V IN2 generated by the third operational amplifier 214, and the amplification factor of the third operational amplifier 214 is (1+R8/R7).
- the relationships among the amplification factors of the first operational amplifier 212, the second operational amplifier 213, and the third operational amplifier 214 in different display devices are different.
- the value ranges of the magnification factor of the first operational amplifier 212, the magnification factor of the second operational amplifier 213, and the magnification factor of the third operational amplifier 214 can be determined according to the actual situation of the display device, such as the resolution and pixel structure, and Through multiple experimental tests before the display device leaves the factory, the first resistor R1 and the second resistor R2 in the first operational amplifier 212, the fourth resistor R4 and the fifth resistor R5 in the second operational amplifier 213, and the first resistor R5 are set in advance.
- the resistance values of the seventh resistor R7 and the eighth resistor R8 in the three operational amplifier 214 are set in advance.
- the above-mentioned display device 300 may be any device that displays images whether in motion (for example, video) or fixed (for example, still images), and regardless of text or images. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, and personal data assistants (PDAs).
- PDAs personal data assistants
- Handheld or portable computers GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, TV monitors, flat panel displays, computer monitors, car monitors (e.g., Odometer display, etc.), navigator, cockpit controller and/or display, camera view display (for example, the display of a rear-view camera in a vehicle), electronic photos, electronic billboards or signs, projectors, building structures, packaging And aesthetic structure (for example, a display of the image of a piece of jewelry), etc.
- the embodiments of the present disclosure also provide a control method of the display device 300 as in any of the foregoing embodiments, including:
- the feedback signal line 40 monitors the common voltage signal of the part of the common electrode 20 located in the remote area F, and transmits the monitored common voltage signal to the control circuit 210 in the circuit board 200.
- the control circuit 210 generates a first compensation common voltage signal according to the common voltage signal monitored by the feedback signal line 40, and transmits it to the first common signal line 30, so as to correct the common voltage signal of the part of the common electrode 20 located in the remote area F. Make compensation.
- control method of the display device 300 further includes:
- the control circuit 210 generates a second compensation common voltage signal according to the common voltage signal monitored by the feedback signal line, and transmits it to the second common signal line 50, so as to perform processing on the common voltage signal of the portion of the common electrode 20 located in the proximal region N. compensate.
- control method of the display device 300 further includes:
- the control circuit 210 generates a third compensation common voltage signal according to the common voltage signal monitored by the feedback signal line 40, and transmits it to the third common signal line 60, so as to correct the common voltage signal of the part of the common electrode 20 located in the middle region M. Make compensation.
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Abstract
Description
Claims (19)
- 一种阵列基板,具有显示区和位于所述显示区一侧的绑定区,所述显示区包括远离所述绑定区的远端区域;所述阵列基板包括:衬底;设置于所述衬底上且位于所述显示区的公共电极;设置于所述衬底上的第一公共信号线和反馈信号线;所述第一公共信号线和所述反馈信号线与所述公共电极中位于所述远端区域的部分耦接,所述第一公共信号线和所述反馈信号线延伸至所述绑定区以与电路板耦接;其中,所述反馈信号线被配置为,监测所述公共电极中位于所述远端区域的部分的公共电压信号,并将监测得到的公共电压信号传输至所述电路板;所述第一公共信号线被配置为,将补偿后的公共电压信号传输至所述公共电极中位于所述远端区域的部分;所述补偿后的公共电压信号为所述电路板根据所述监测得到的公共电压信号,对公共电压信号进行补偿得到的信号。
- 根据权利要求1所述的阵列基板,其中,所述阵列基板包括两条所述反馈信号线,两条所述反馈信号线分别设置于所述显示区的相对的两侧。
- 根据权利要求1或2所述的阵列基板,其中,所述阵列基板包括两条所述第一公共信号线,两条所述第一公共信号线分别设置于所述显示区的相对的两侧;所述第一公共信号线与所述公共电极耦接的位置,位于所述公共电极远离所述绑定区的一侧。
- 根据权利要求1~3中任一项所述的阵列基板,其中,所述显示区还包括靠近所述绑定区的近端区域;所述阵列基板还包括:设置于所述衬底上的第二公共信号线,所述第二公共信号线与所述公共电极中位于所述近端区域的部分耦接,所述第二公共信号线延伸至所述绑定区以与所述电路板耦接;所述第二公共信号线被配置为,将公共电压信号或补偿后的公共电压信号传输至所述公共电极中位于所述近端区域的部分。
- 根据权利要求4所述的阵列基板,其中,所述阵列基板包括两条所述第二公共信号线,两条所述第二公共信号线分别设置于所述近端区域靠近所述绑定区的一侧的相对的两端。
- 根据权利要求1~5中任一项所述的阵列基板,其中,所述显示区还包括位于远端区域和近端区域之间的中部区域;所述阵列基板还包括:设置于所述衬底上的第三公共信号线,所述第三公共信号线延伸至所述绑定区以与所述电路板耦接;所述第三公共信号线与所述公共电极中位于所述中部区域的部分耦接;所述第三公共信号线被配置为,将补偿后的公共电压信号传输至所述公共电极中位于所述中部区域的部分。
- 根据权利要求6所述的阵列基板,其中,所述阵列基板包括两条所述第三公共信号线,两条所述第三公共信号线分别设置于所述显示区的相对的两侧。
- 根据权利要求1~7中任一项所述的阵列基板,其中,所述反馈信号线与所述第一公共信号线材料相同且同层设置。
- 根据权利要求1~8中任一项所述的阵列基板,还包括:连接引线,所述连接引线设置于所述显示区的远端区域的外侧,所述第一公共信号线及所述反馈信号线与所述连接引线耦接;导电框,所述导电框围绕所述显示区,所述连接引线及所述公共电极中位于所述远端区域的部分与所述导电框耦接,以使所述第一公共信号线通过所述连接引线及所述导电框与所述公共电极中位于所述远端区域的部分耦接,所述反馈信号线通过所述导电框与所述公共电极中位于所述远端区域的部分耦接。
- 根据权利要求9所述的阵列基板,其中,所述第一公共信号线、所述连接引线和所述导电框的材料相同且同层设置。
- 根据权利要求1~10中任一项所述的阵列基板,其中,在所述阵列基板还包括第二公共信号线和第三公共信号线的情况下,所述第一公共信号线的电阻、所述第二公共信号线的电阻和所述第三公共信号线的电阻均小于或等于300Ω;所述反馈信号线的电阻小于或等于1000Ω。
- 根据权利要求1~11中任一项所述的阵列基板,还包括:设置于所述衬底上的数据线,在垂直于所述衬底的方向上,所述数据线相对于所述公共电极更靠近所述衬底;所述数据线与所述公共电极在所述衬底上的正投影至少部分重叠。
- 根据权利要求1~12中任一项所述的阵列基板,其中,所述阵列基板具有多个亚像素区域;所述公共电极包括多个子电极和多个第一导电图案;一个子电极至少位于一个亚像素区域内,相邻的子电极通过至少一个第一导电图案耦接。
- 一种显示装置,包括:如权利要求1~13中任一项所述的阵列基板;和电路板,所述电路板通过所述阵列基板中的绑定区与所述阵列基板耦接;所述电路板包括控制电路,所述控制电路与所述阵列基板中的第一公共信号线和反馈信号线耦接;所述控制电路被配置为,根据所述反馈信号线监测得到的公共电压信号,生成第一补偿公共电压信号,并传输至所述第一公共信号线。
- 根据权利要求14所述的显示装置,其中,所述控制电路包括:反相器,所述反相器与所述反馈信号线耦接;所述反相器被配置为,将所述反馈信号线传输的监测得到的公共电压信号进行反相;第一运算放大器,所述第一运算放大器与所述反相器和所述第一公共信号线耦接;所述第一运算放大器被配置为,将来自所述反相器反相的信号进行放大,生成所述第一补偿公共电压信号,并将所述第一补偿公共电压信号传输至所述第一公共信号线。
- 根据权利要求14或15所述的显示装置,其中,在所述阵列基板还包括第二公共电极线的情况下,所述控制电路还包括:第二运算放大器,所述第二运算放大器与反相器和所述第二公共信号线耦接;所述第二运算放大器被配置为,将来自所述反相器反相的信号进行放大,生成第二补偿公共电压信号,并将所述第二补偿公共电压信号传输至所述第二公共信号线;所述第二运算放大器的放大倍数小于第一运算放大器的放大倍数。
- 根据权利要求14~16中任一项所述的显示装置,其中,在所述阵列基板还包括第三公共电极线的情况下,所述控制电路还包括:第三运算放大器,所述第三运算放大器与反相器和所述第三公共信号线耦接;所述第三运算放大器被配置为,将来自所述反相器反相的信号进行放大,生成第三补偿公共电压信号,并将所述第三补偿公共电压信号传输至所述第三公共信号线;所述第三运算放大器的放大倍数小于所述第一运算放大器的放大倍数;在所述控制电路还包括第二运算放大器的情况下,所述第三运算放大器的放大倍数大于所述第二运算放大器的放大倍数。
- 一种如权利要求14~17中任一项所述的显示装置的控制方法,包括:反馈信号线监测公共电极中位于远端区域的部分的公共电压信号,并将监测得到的公共电压信号传输至电路板中的控制电路;所述控制电路根据所述反馈信号线监测得到的公共电压信号,生成第一补偿公共电压信号,并传输至第一公共信号线,以对公共电极中位于所述远端区域的部分的公共电压信号进行补偿。
- 根据权利要求18所述的控制方法,还包括:所述控制电路根据所述反馈信号线监测得到的公共电压信号,生成第二补偿公共电压信号,并传输至第二公共信号线,以对所述公共电极中位于近端区域的部分的公共电压信号进行补偿;和/或,所述控制电路根据所述反馈信号线监测得到的公共电压信号,生成第三补偿公共电压信号,并传输至第三公共信号线,以对所述公共电极中位于中端区域的部分的公共电压信号进行补偿。
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US11645995B2 (en) | 2023-05-09 |
US20230237974A1 (en) | 2023-07-27 |
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US11984094B2 (en) | 2024-05-14 |
CN111308820B (zh) | 2022-07-05 |
CN111308820A (zh) | 2020-06-19 |
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