WO2021159627A1 - 一种半导体器件的缺陷检查方法、装置和可读存储介质 - Google Patents

一种半导体器件的缺陷检查方法、装置和可读存储介质 Download PDF

Info

Publication number
WO2021159627A1
WO2021159627A1 PCT/CN2020/090992 CN2020090992W WO2021159627A1 WO 2021159627 A1 WO2021159627 A1 WO 2021159627A1 CN 2020090992 W CN2020090992 W CN 2020090992W WO 2021159627 A1 WO2021159627 A1 WO 2021159627A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor wafer
defect inspection
pattern
information
exposure
Prior art date
Application number
PCT/CN2020/090992
Other languages
English (en)
French (fr)
Inventor
冈崎信次
卢意飞
赵宇航
李铭
王建国
Original Assignee
上海集成电路研发中心有限公司
上海先综检测有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海集成电路研发中心有限公司, 上海先综检测有限公司 filed Critical 上海集成电路研发中心有限公司
Priority to JP2022548496A priority Critical patent/JP7448671B2/ja
Publication of WO2021159627A1 publication Critical patent/WO2021159627A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491—Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/70—Determining position or orientation of objects or cameras
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor defect inspection method and device.
  • EUV Extrem ultraviolet exposure technology
  • ArF immersion exposure technology and EUV exposure technology use reduced projection exposure technology, and the resolution of the reduced projection exposure technology is determined by the wavelength used for exposure and the numerical aperture of the optical system used for exposure.
  • the ArF liquid immersion exposure device is 1.35 and the numerical aperture of the EUV exposure device is 0.33, the ArF liquid immersion exposure device is about 4 times that of the EUV exposure device, but because the wavelength of ArF liquid immersion exposure is 193nm, the wavelength of EUV exposure It is 13.5nm, so there is a 3.5 times difference in resolution between the two. Therefore, the EUV exposure wavelength is definitely dominant.
  • the photosensitive mechanism, absorption coefficient, types of materials constituting the resist, the molecular weight of the resist and/or the thickness of the resist film, etc. of the resist material included in the process information are also the same as
  • the fluctuation of the exposure pattern of semiconductor wafers is related. This is because most of the anti-etching agents are called chemically amplified anti-etching agents, which are based on high-molecular polymer resins, and some of the resins are provided with functional groups that can be decomposed by acid corrosion, and mixed
  • the acid generator and quencher in the resin can predict changes in the mixing ratio of these materials and the spatial distribution of the material components. These materials are commonly referred to as acid-catalyzed resist materials.
  • the size of these polymer materials is similar to the minimum processing size of the semiconductor wafer exposure pattern.
  • the minimum processing size of the semiconductor wafer exposure pattern is about 10 times the size of the polymer material or less. Therefore, the spatial location of the photosensitive material is caused.
  • the fluctuation of the semiconductor wafer has a great relationship with the formation of the exposure pattern of the semiconductor wafer.
  • not all incident photons can be absorbed by the resist layer.
  • the absorption amount that is, the number of photons, is determined by the absorption coefficient, which is determined by the thickness of the resist film and the elements constituting the material.
  • the mask pattern information which is the basis of exposure, will also have a great impact on the actual exposure size. That is, the size and position error of the mask pattern are also information related to the occurrence of defects.
  • the inspection frequency is usually increased as much as possible to perform all pattern defect inspections on the corresponding semiconductor wafers, especially the semiconductor wafers that are predicted to have a higher defect frequency.
  • this inspection frequency has the problem of long inspection time.
  • the inspection frequency is not the optimal inspection frequency.
  • the purpose of the present invention is to provide a defect inspection method that overcomes the problems existing in the prior art.
  • the technical scheme of the present invention is as follows:
  • a method for inspecting semiconductor wafer defects which is used to determine the defect inspection frequency of a pattern that uses DUV light or electron beam energy rays to perform process processing such as photolithography processing on the semiconductor wafer; it includes the following steps:
  • Step S1 receiving process information of the exposure pattern of the semiconductor wafer, mask pattern information, and/or information of the defect frequency of the wafer that has the same exposure pattern as the semiconductor wafer and has been processed in the same process;
  • Step S2 Determine the defect inspection position of the semiconductor wafer exposure pattern, simulate and count the fluctuation probability of the semiconductor wafer exposure pattern under the process information condition, and/or the semiconductor wafer exposure pattern is The probability of fluctuation caused by the mask pattern information condition;
  • Step S3 Set the current exposure of the semiconductor wafer based on the combined value of the fluctuation probability and the defect inspection frequency of the wafer that has the same exposure pattern as the semiconductor wafer and has been processed in the same process Defect inspection frequency of graphics.
  • the semiconductor wafer defect inspection method further includes step S4: performing defect inspection on part or all of the semiconductor wafer exposure pattern at the defect inspection position according to the defect inspection frequency.
  • the process information includes the radiation energy in the exposure process, the exposure amount, the photosensitive mechanism of the resist material, the absorption coefficient, the type of material constituting the resist, the respective molecular weight of the resist and/or The resist film thickness.
  • the anti-etchant material includes an acid-catalyzed anti-corrosion material.
  • the acid-catalyzed anti-corrosive material includes a chemically amplified resist, base resin, PAG of sensitizer, and/or quencher.
  • the resist material includes a metal oxide resist or a main chain rupture type resist.
  • the mask information is the size of the mask pattern and/or the position coordinates of the mask pattern.
  • a semiconductor wafer defect inspection device which is used to determine the defect inspection frequency of a pattern that uses DUV light or electron beam energy rays to perform process processing such as photolithography processing on the semiconductor wafer; it includes:
  • An input module for receiving process information of the exposure pattern of the semiconductor wafer, mask pattern information, and/or information on the defect inspection frequency of a wafer that has the same exposure pattern as the semiconductor wafer and has been processed in the same process ;
  • the statistics module is used to determine the defect inspection position of the semiconductor wafer exposure pattern, simulate and count the fluctuation probability of the semiconductor wafer exposure pattern under the process information condition, and/or the semiconductor wafer exposure The probability of pattern fluctuation caused by the mask pattern information condition;
  • the determination module sets the current exposure of the semiconductor wafer based on the combined value of the fluctuation probability and the defect inspection frequency information of the wafer that has the same exposure pattern as the semiconductor wafer and has been processed in the same process Defect inspection frequency of graphics.
  • the semiconductor wafer defect inspection device further includes an execution module for performing defect inspection on part or all of the semiconductor wafer exposure pattern at the defect inspection position according to the defect inspection frequency.
  • a readable storage medium stores executable instructions, and the executable instructions are used to execute the above-mentioned semiconductor wafer defect inspection method.
  • the semiconductor wafer defect inspection method grasps in advance the defect frequency of the semiconductor wafer inspected in the past that is the same as the inspected object, the pattern exposure of the inspected object, and the resistance
  • the resist material information such as the molecular weight of the base resin of the etchant material or the acid generator dose, the resist film thickness, the size information of the mask pattern and other process information, as well as various information related to the exposure pattern, are used in the semiconductor
  • the defect inspection frequency corresponding to the fluctuation caused by using this information is set, and the defect inspection position of the semiconductor wafer exposure pattern is inspected. Therefore, the present invention can avoid defect inspection on the overall semiconductor wafer exposure pattern, achieve an industrially acceptable inspection time, realize the best inspection frequency, and achieve the purpose of shortening the inspection time.
  • FIG. 1 shows a flowchart of a method for inspecting defects of a semiconductor wafer in an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the structure of the semiconductor wafer defect inspection device in the first embodiment of the present invention
  • FIG. 3 is a schematic diagram showing the structure of the semiconductor wafer defect inspection device in the second embodiment of the present invention
  • FIG. 4 is a schematic diagram of the structure of the semiconductor wafer defect inspection device in the third embodiment of the present invention.
  • FIG. 1 is a flowchart of a semiconductor wafer defect inspection method according to an embodiment of the present invention.
  • the defect inspection method of the semiconductor wafer is used to determine the defect inspection frequency when using DUV light or electron beam energy rays to perform photolithographic processing on the semiconductor wafer, and use this frequency to perform the patterning
  • the semiconductor wafer pattern is inspected for defects; the method specifically includes the following steps:
  • Step S1 receiving process information of the exposure pattern of the semiconductor wafer, mask pattern information and/or information of the defect frequency of the wafer that has the same exposure pattern as the semiconductor wafer and has been processed in the same process.
  • the method for inspecting semiconductor wafer defects needs to grasp the process information and/or mask information of manufacturing the semiconductor wafer in advance, so as to set the inspection frequency corresponding to the size value after the above-mentioned wave synthesis. .
  • the process information may include the ray energy and exposure amount in the exposure process.
  • EUV exposure technology is a micro-size processing process with a minimum size of 20 nm or less. Because the size of the semiconductor wafer exposure pattern is very small, the number of photons irradiated to the micro pattern is rapidly reduced, which is statistically significant. The problem of volatility has become increasingly apparent.
  • the process information may also include the photosensitive mechanism of the resist material, the absorption coefficient, the types of materials constituting the resist material, their respective molecular weights, and/or the resist film thickness.
  • the photosensitive mechanism is to irradiate the photoresist material through these photons, the size of the photosensitive photoresist material and the base resin constituting the substrate itself, and 20nm as the size of the exposure pattern of the semiconductor wafer Located at the same level.
  • the main material of the resist may include a catalytic type resist material, a metal oxide resist or a main chain rupture type resist.
  • the catalytic type anti-corrosion material can be a chemically amplified material.
  • the materials based on chemically amplified materials it is based on a high molecular polymer as a matrix resin, and a part of the resin is provided with functional groups that can be corroded and decomposed by acid, and The resin is mixed with acid generator and quencher, etc. to be used together.
  • the size of the exposure pattern of the semiconductor wafer is about 10 times the size of the polymer material or less, the fluctuation of the position of the photosensitive material is greatly related to the formation of the size of the exposure pattern of the semiconductor wafer.
  • the absorption amount that is, the number of photons
  • the absorption coefficient which is determined by the resist film thickness and the elements constituting the material. Therefore, in the era of EUV exposure, the fluctuation in the number of photons incident and absorbed by the resist layer through exposure and the fluctuation caused by the resist material are greatly related to the frequency of defects in the exposure pattern of the semiconductor wafer.
  • the main material of the anti-etching agent may be a metal oxide type anti-etching agent or a main chain scission type anti-etching agent. Since these types of resists do not use acid-catalyzed reactions, they have the advantage of not having to consider the influence of fluctuations in the location of photosensitive substances.
  • the metal oxide type resist is different from the metal materials that have been used in the semiconductor industry, and there is a problem of industrial application practicability.
  • the main chain scission resist has low sensitivity, and there are very few examples of it being supplied to industrial applications.
  • the size of the mask pattern which is the basis for exposure, will also have a great impact on the actual exposure size. Therefore, the size and position of the mask pattern are also information related to the occurrence of defects.
  • Step S2 Determine the defect inspection position of the semiconductor wafer exposure pattern, simulate and count the fluctuation probability of the semiconductor wafer exposure pattern under the process information condition, and/or the semiconductor wafer exposure pattern is The probability of fluctuation caused by the mask pattern information condition.
  • Step S3 Set the current exposure of the semiconductor wafer based on the combined value of the fluctuation probability and the defect inspection frequency of the wafer that has the same exposure pattern as the semiconductor wafer and has been processed in the same process Defect inspection frequency of graphics.
  • the defect inspection frequency obtained in the embodiment of the present invention can be regarded as the optimal defect inspection frequency for defect inspection of the semiconductor wafer exposure pattern, and the semiconductor wafer exposure pattern can be understood as the semiconductor wafer exposure pattern.
  • the part of the pattern may also be the entire exposed pattern of the semiconductor wafer.
  • Step S4 Perform defect inspection on part or all of the exposed pattern of the semiconductor wafer at the defect inspection position according to the defect inspection frequency.
  • the semiconductor wafer defect inspection device used in the following three embodiments includes an input module, a statistics module, a determination module, and an execution module.
  • the input module is used to receive process information of the exposure pattern of the semiconductor wafer, mask pattern information and/or information on the defect frequency of the wafer that has the same exposure pattern as the semiconductor wafer and has been processed in the same process;
  • a statistics module Used to determine the defect inspection position of the semiconductor wafer exposure pattern, simulate and count the fluctuation probability of the semiconductor wafer exposure pattern under the process information condition, and/or the semiconductor wafer exposure pattern caused by the mask pattern information condition Fluctuation probability;
  • the determination module sets the current inspection frequency of the semiconductor wafer based on the composite value of the fluctuation probability and the defect inspection frequency of the wafer that has the same exposure pattern as the semiconductor wafer and has been processed in the same process.
  • the execution module performs defect inspection on part or all of the semiconductor wafer exposure pattern at the defect inspection position according to the defect inspection frequency.
  • FIG. 2 is a schematic structural diagram of a semiconductor wafer defect inspection apparatus in Embodiment 1 of the present invention.
  • the used resist material information is a chemically amplified resist
  • adamantane resin is used as the base resin
  • PAG ((PAG, PhotoAcid Generator, for example, triphenyl The concentration of trifluoromethanesulfonate) is 20% by weight
  • the main material of the input resist is a chemically amplified resist
  • the film thickness of the input resist is 50nm, which uses a high molecular polymer as the matrix resin.
  • Part of the resin is provided with functional groups that can be decomposed by acid attack, and the resin is mixed with acid generators and quenchers, etc., and the EUV light absorption coefficient of the chemically amplified resist is 50%.
  • the minimum pattern size of the semiconductor wafer exposure pattern is 9.5 nm square, and the position of the pattern is input as the mask information.
  • the fluctuation in the size of the semiconductor wafer exposure pattern can be directly calculated by simulation software, and the maximum size change can be predicted to be 26.5%.
  • This digital value represents the semiconductor wafer exposure pattern experience
  • the frequency of defects produced after the process is very high. Therefore, it is necessary to locally set corresponding defect inspection frequencies for patterns with large dimensional information errors including mask patterns, and use a defect inspection frequency for this local semiconductor wafer exposure pattern for defect inspection, and to expose patterns for all semiconductor wafers.
  • the inspection time can be shortened to less than 1/10. In other words, performing defect inspection on areas where the size of the exposed pattern of the local semiconductor wafer is predicted to change greatly can greatly shorten the defect inspection time.
  • Embodiment 1 of the present invention first, the probability of fluctuation caused by the exposure pattern of the semiconductor wafer under the condition of the process information is simulated and counted. Assuming that the number of incident photons is 20mJ/cm 2 , it is 1360 in the 10nm square contact hole pattern with the smallest processing size, and the number of photons absorbed in the resist is 680. If the photon fluctuation under the shot noise is calculated, the ⁇ value is 3.8%. Considering 3 ⁇ , the fluctuation caused by the number of incident photons is 11.5%.
  • the information on the resist is that the size of a molecule of adamantane resin is about 0.6nm cubic.
  • the molecular weight of the adamantane resin is about 3.3 times, and the number of PAG is About 6%, about 1200.
  • shot noise can also be used to calculate the same fluctuations as photons.
  • the ⁇ value is 3%. Taking into account 3 ⁇ , there is a 9% fluctuation in the resist material. If the 9% fluctuation in the resist material is combined with the 11.5% fluctuation in the number of incident photons, these fluctuations can predict that the largest pattern change of the semiconductor wafer exposure pattern size is 21.5%.
  • the maximum change can be predicted to be 26.5%.
  • FIG. 3 is a schematic structural diagram of a semiconductor wafer defect inspection apparatus in Embodiment 2 of the present invention.
  • EUV light with a wavelength of 13.5nm is used to expose a semiconductor wafer with a minimum processing size of 10nm square contact hole pattern.
  • the semiconductor wafer process The exposure level included in the information is 20mJ/cm 2 , the resist material used is a chemically amplified resist, adamantane resin is used as the base resin, and PAG (triphenyltrifluoromethanesulfonic acid) is used as a photosensitizer.
  • the resist material used is a chemically amplified resist
  • adamantane resin is used as the base resin
  • PAG triphenyltrifluoromethanesulfonic acid
  • the concentration of the salt) is 20wt%
  • the film thickness of the input resist is 50nm, which uses high molecular polymer as the matrix resin, and part of the resin is provided with functional groups that can be decomposed by acid corrosion, and the acid generator is mixed in the resin Used with quenchers, etc.
  • the EUV light absorption coefficient of chemically amplified resist is 50%.
  • simulation software can be used to directly calculate the fluctuation of the semiconductor wafer exposure pattern size, and it can be predicted that the maximum size change is 21.5%. This digital value It means that the frequency of occurrence of defects is very high.
  • the corresponding defect inspection frequency for 80% of the pattern including the size information of the mask pattern, and use the local semiconductor crystal with a defect inspection frequency.
  • the round exposure pattern is used for defect inspection, and the inspection time can be reduced by 20% compared with the semiconductor defect inspection for all semiconductor wafer exposed patterns.
  • FIG. 4 is a schematic structural diagram of a semiconductor wafer defect inspection apparatus in Embodiment 3 of the present invention.
  • EUV light with a wavelength of 13.5nm is used to expose a semiconductor wafer with a minimum processing size of 10nm square contact hole pattern.
  • the semiconductor wafer process The exposure amount included in the information is 20mJ/cm 2 , and the EUV light absorption coefficient of the resist is 80%. That is to say, the fluctuation of incident photons is almost the same as that in Example 1 and Example 2, but because the absorption coefficient of the resist is large, the change caused by shot noise is small.
  • the required semiconductor defect inspection frequency can be set to 10% sampling inspection, so that the semiconductor defect inspection can be performed, and the inspection time can be greatly shortened to 1/10 of the previous.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)

Abstract

一种半导体缺陷检查的装置和方法，该方法包括接收制作半导体晶圆曝光图形的工序信息、掩模图形的信息和与半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷频率的信息；确定半导体晶圆曝光图形的缺陷检查位置，模拟并统计半导体晶圆曝光图形在工序信息条件下所导致的波动几率，半导体晶圆曝光图形在抗刻蚀剂材料信息条件下所导致的波动几率，和/或半导体晶圆曝光图形在掩模图形的尺寸信息条件下所导致的波动几率；根据所述波动几率的合成值和与半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷检查频率的信息，设定当前对半导体晶圆曝光图形的缺陷检查频率；根据缺陷检查频率进行缺陷检查。因此，可以通过预先计算半导体缺陷检查频率来缩短半导体缺陷检查时间。

Description

一种半导体器件的缺陷检查方法、装置和可读存储介质
交叉引用
本申请要求2020年2月10日提交的申请号为202010083820.7的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及半导体制造技术领域，尤其是涉及一种半导体缺陷检查方法和装置。
技术背景
随着半导体集成电路技术节点的发展推动着半导体曝光技术解像度(Half Pitch)的发展，半导体器件的尺寸变的越来越细，迄今为止，最先进的半导体器件，其尺寸已进入了20nm及更微小的年代。
目前，半导体器件的加工制造业已经逐渐开始使用极紫外曝光技术(Extreme Ultra Violet Lithography，简称EUV)。在ArF液浸曝光技术和EUV曝光技术等中均使用了缩小投影曝光技术，该缩小投影曝光技术解像度由用于曝光的波长和用于曝光的光学系统的数值孔径决定。
虽然ArF液浸曝光装置的数值孔径是1.35，EUV曝光装置的数值孔径是0.33，ArF液浸曝光装置大约是EUV曝光装置的4倍，但由于ArF液浸曝光的波长是193nm，EUV曝光的波长是13.5nm，因此两者的解像度有3.5倍左右的差距。因此，EUV曝光的波长绝对是占优势。
与ArF液浸曝光相比，在EUV曝光技术中，为了将曝光装置的吞吐量 (例如，每小时处理吞吐数百十个300mmφ的晶圆)维持在与ArF液浸曝光装置相同的程度，必须维持与ArF液浸曝光相同的剂量，每单位面积的光子数约减少至ArF液浸曝光的1/14。并且，由于需曝光图形的尺寸非常小，结果照射至微细图形的光子数量急速减少，曝光量的波动等所导致的半导体晶圆上的曝光图形波动几率变大，即造成统计性波动的问题日益明显。
通常，工序信息中所包含的抗刻蚀剂材料的感光机制、吸收系数、构成抗刻蚀剂的材料种类、抗刻蚀剂各自的分子量和/或抗刻蚀剂膜厚等，也同样与半导体晶圆曝光图形的波动有关。这是由于在抗刻蚀剂中大多使用被称为化学增幅型的抗刻蚀剂中，是以高分子聚合物为基体树脂，在部分该树脂上设置可被酸侵蚀分解的官能团，以及混合于该树脂中的产酸剂和淬灭剂等，能够预测到这些材料的混合比和材料成分的空间分布的变动。这些材料通常被称为酸催化型抗刻蚀剂材料。这些高分子材料自身的尺寸为半导体晶圆曝光图形最小加工尺寸相接近，通常半导体晶圆曝光图形最小加工尺寸为高分子材料尺寸的10倍左右或更小，因此，感光物质存在空间位置所导致的波动与半导体晶圆曝光图形的形成有极大关系。再加上，并不是所有入射的光子都能被抗刻蚀剂层吸收，其吸收量即光子的数量由吸收系数决定，吸收系数由抗刻蚀剂膜厚及构成材料的元素决定。
此外，作为曝光基础的掩模图形信息，也会对实际的曝光尺寸产生很大影响。即掩模图形的尺寸和位置误差也是与缺陷产生相关的信息。
因此，由于上述各种统计波动因素所引起的半导体晶圆曝光图形发生形变缺陷是难以避免。目前在半导体制造业界，通常采用尽可能提高检查频率来对所对应的、尤其是预测为缺陷频率较高的半导体晶圆进行全部图形的缺 陷检查，然而，这种检查频率存在检查时间长的问题，且检查频率不是最佳的检查频率。
发明概要
本发明的目的在于提供一种克服现有技术存在的问题的缺陷检查方法，本发明的技术方案如下：
一种半导体晶圆缺陷的检查方法，用于确定在采用DUV光或电子束能量射线对所述半导体晶圆进行光刻处理等工序处理的图案的缺陷检查频率；其包括如下步骤：
步骤S1：接收所述半导体晶圆曝光图形的工序信息、掩模图形信息和/或与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷频率的信息；
步骤S2：确定所述半导体晶圆曝光图形的缺陷检查位置，模拟并统计所述半导体晶圆曝光图形在所述工序信息条件下所导致的波动几率，和/或所述半导体晶圆曝光图形在所述掩模图形信息条件下所导致的波动几率；
步骤S3：根据所述波动几率的合成值和与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷检查频率的信息，设定当前对所述半导体晶圆曝光图形的缺陷检查频率。
优选地，所述的半导体晶圆缺陷检查的方法还包括步骤S4：根据所述缺陷检查频率，对所述缺陷检查位置上的所述半导体晶圆曝光图形的部分或全部进行缺陷检查。
优选地，所述的工序信息包括曝光工序中的射线能量、曝光量、抗刻蚀 剂材料的感光机制、吸收系数、构成抗刻蚀剂的材料种类、抗刻蚀剂各自的分子量和/或抗刻蚀剂膜厚。
优选地，所述抗刻蚀剂材料包括酸催化型抗蚀材料。
优选地，所述的酸催化型抗蚀材料包括化学增幅型抗刻蚀剂、基底树脂、感光剂的PAG和/或淬灭剂。
优选地，所述抗刻蚀剂材料包括金属氧化物抗刻蚀剂或主链断裂型抗蚀剂。
优选地，所述掩模信息为掩模图形的尺寸和/或掩模图形的位置坐标。
为实现上述目的，本发明又一的技术方案如下：
一种半导体晶圆缺陷检查装置，用于确定在采用DUV光或电子束能量射线对所述半导体晶圆进行光刻处理等工序处理的图案的缺陷检查频率；其包括：
输入模块，用于接收所述半导体晶圆曝光图形的工序信息、掩模图形信息和/或与所述半导体晶圆具有相同的曝光图案并经相同的工序处理的晶圆的缺陷检查频率的信息；
统计模块，用于确定所述半导体晶圆曝光图形的缺陷检查位置，模拟并统计所述半导体晶圆曝光图形在所述工序信息条件下所导致的波动几率，和/或所述半导体晶圆曝光图形在所述掩模图形信息条件下所导致的波动几率；
确定模块，根据所述波动几率的合成值和与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷检查频率的信息，设定当前对所述半导体晶圆曝光图形的缺陷检查频率。
优选地，上述半导体晶圆缺陷检查装置还包括执行模块，根据所述缺陷 检查频率，对所述缺陷检查位置上的所述半导体晶圆曝光图形的部分或全部进行缺陷检查。
为实现上述目的，本发明又一的技术方案如下：
一种可读存储介质，存储有可执行指令，该可执行指令用于执行上述半导体晶圆缺陷的检查方法。
从上述技术方案可以看出，本发明所提供的半导体晶圆缺陷检查方法，其通过预先掌握与被检查对象相同的过去所检查的半导体晶圆的缺陷频率、被检查对象的图形曝光量、抗刻蚀剂材料的基底树脂分子量或产酸剂量等抗刻蚀剂材料信息、抗刻蚀剂膜厚度、掩模图形的尺寸信息等工序信息、以及与曝光图形相关的各种信息，并在半导体晶圆缺陷的检查装置上，设定与使用这些信息所造成的波动大小相对应的缺陷检查频率，对半导体晶圆曝光图形的缺陷检查位置进行缺陷检查。因此，本发明可以避免对整体的半导体晶圆曝光图形进行的缺陷检查，在工业上可接受的检查时间，实现最佳的检查频率，达到缩短检查时间的目的。
附图说明
图1所示为本发明实施例中半导体晶圆缺陷检查方法流程图
图2所示为本发明实施例1中半导体晶圆缺陷检查装置的结构示意图
图3所示为本发明实施例2中半导体晶圆缺陷检查装置的结构示意图
图4所示为本发明实施例3中半导体晶圆缺陷检查装置的结构示意图
发明内容
下面结合附图，对本发明的具体实施方式作进一步的详细说明。
请参阅图1，图1所示为本发明实施例中半导体晶圆缺陷检查方法流程图。如图所示，该半导体晶圆的缺陷检查方法，用于确定在采用DUV光或电子束能量射线对所述半导体晶圆进行光刻处理的缺陷检查频率，并采用该频率对图形化后的半导体晶圆图形进行缺陷检查；该方法具体包括如下步骤：
步骤S1：接收所述半导体晶圆曝光图形的工序信息、掩模图形信息和/或与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷频率的信息。
在本发明的实施例中，半导体晶圆缺陷的检查方法需要预先掌握制作所述半导体晶圆的工序信息和/或掩模信息，以设定与上述波动合成后的大小值相对应的检查频率。
其中，工序信息可以包括曝光工序中的射线能量和曝光量。在本发明的具体实施方式中，EUV曝光技术是在最小尺寸20nm以下的微细尺寸加工工艺中，由于半导体晶圆曝光图形的尺寸非常小，结果照射至微细图形的光子的数量急速减少，统计性波动的问题日益明显。
工序信息还可以包括抗刻蚀剂材料的感光机制、吸收系数、构成抗刻蚀剂材料的材料种类、各自的分子量和/或抗刻蚀剂膜厚。在本发明的实施例中，其感光机制是通过这些光子照射光刻胶材料，该被感光的光刻胶材料以及构成基底的基础树脂自身的尺寸，与作为半导体晶圆曝光图形的尺寸的20nm位于相同的水平。
在本发明的实施例中，抗刻蚀剂的主材料可以包括催化型抗蚀材料、金 属氧化物抗刻蚀剂或主链断裂型抗蚀剂。催化型抗蚀材料可以为化学增幅型材料，在以化学增幅型材料为主的材料中，其是以高分子聚合物为基体树脂，在部分该树脂上设置可被酸侵蚀分解的官能团，并在该树脂中混合产酸剂和淬灭剂等一起使用的。当半导体晶圆曝光图形尺寸为高分子材料尺寸的10倍左右或更小，感光物质的存在位置的波动与半导体晶圆曝光图形的尺寸的形成有极大关系。
并且，并不是所有入射的光子都被抗刻蚀剂层吸收，其吸收量即光子的数量由吸收系数决定，吸收系数由抗刻蚀剂膜厚及构成材料的元素决定。因此，在EUV曝光的时代，通过曝光入射并被抗刻蚀剂层吸收的光子数量的波动以及构成抗蚀材料所引起的波动，与半导体晶圆曝光图形的缺陷产生频率有极大关系。
需要说明的是，近年来倍受关注的抗刻蚀剂的主要材料可以为金属氧化物型抗刻蚀剂或主链断裂型抗刻蚀剂。这些类型的抗刻蚀剂，由于不使用酸催化反应，因此，具备不需考虑感光性物质的存在位置波动影响的优点。但是，金属氧化物型抗刻蚀剂与半导体产业中一直以来使用的金属材料不同，存在着工业应用实用性的问题。主链断裂型抗刻蚀剂的感光度低，供给于工业应用的实例有也非常少。
此外，作为曝光基础的掩模图形尺寸，也会对实际的曝光尺寸产生很大影响。因此，掩模图形的尺寸和位置也是与缺陷产生相关的信息。
步骤S2：确定所述半导体晶圆曝光图形的缺陷检查位置，模拟并统计所述半导体晶圆曝光图形在所述工序信息条件下所导致的波动几率，和/或所述半导体晶圆曝光图形在所述掩模图形信息条件下所导致的波动几率。
步骤S3：根据所述波动几率的合成值和与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷检查频率的信息，设定当前对所述半导体晶圆曝光图形的缺陷检查频率。
需要说明的是，在本发明实施例中得到的缺陷检查频率，可以认为是对半导体晶圆曝光图形进行缺陷检查的最佳缺陷检查频率，该半导体晶圆曝光图形可以理解为该半导体晶圆曝光图形中的部分，也可以是该半导体晶圆曝光图形的全部。
步骤S4：根据所述缺陷检查频率，对所述缺陷检查位置上的所述半导体晶圆曝光图形的部分或全部进行缺陷检查。
下面通过三个实施例对上述实施方式进行验证性阐述。
下述三个实施例中所采用的半导体晶圆缺陷检查装置，其包括输入模块、统计模块、确定模块和执行模块。输入模块用于接收半导体晶圆曝光图形的工序信息、掩模图形信息和/或与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷频率的信息；统计模块用于确定半导体晶圆曝光图形的缺陷检查位置，模拟并统计半导体晶圆曝光图形在工序信息条件下所导致的波动几率，和/或半导体晶圆曝光图形在掩模图形信息条件下所导致的波动几率；确定模块根据所述波动几率的合成值和与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷检查频率的信息，设定当前对所述半导体晶圆曝光图形的缺陷检查频率；执行模块根据缺陷检查频率，对缺陷检查位置上的半导体晶圆曝光图形的部分或全部进行缺陷检查。
实施例1
请参阅图2，图2所示为本发明实施例1中半导体晶圆缺陷检查装置的结构示意图。在本实施例中，所采用的抗刻蚀剂材料信息为化学增幅型抗刻蚀剂，使用金刚烷树脂作为基底树脂，作为感光剂的PAG((PAG，Photo Acid Generator，例如，三苯基三氟甲磺酸盐)的浓度为20wt％；输入的抗刻蚀剂主材料为化学增幅型抗刻蚀剂，输入抗刻蚀剂膜厚为50nm，其以高分子聚合物为基体树脂，在部分该树脂上设置可被酸侵蚀分解的官能团，并在该树脂中混合产酸剂和淬灭剂等一起使用的，化学增幅型抗刻蚀剂的EUV光吸收系数为50％。并且，作为掩模信息，半导体晶圆曝光图形的最小图形尺寸为9.5nm平方，将该图形位置以掩模信息输入。
根据这些工序信息和掩模图形的尺寸信息等，可以通过模拟软件直接计算半导体晶圆曝光图形尺寸的波动，并可以得到预测其尺寸变化最大为26.5％，该数字值表示半导体晶圆曝光图形经工艺后所产生的缺陷频率非常高。因此，需为包括掩模图形的尺寸信息误差大的图形进行局部设定相应的缺陷检查频率，采用一缺陷检查频率的该局部半导体晶圆曝光图形进行缺陷检查，与对全部半导体晶圆曝光图形进行半导体缺陷检查时相比，其检查时间可以缩短至1/10以下。也就是说，对预测局部半导体晶圆曝光图形尺寸变化大的区域进行缺陷检查，可以大大缩短缺陷检查时间。
下面对上述半导体晶圆曝光图形尺寸波动的计算进行详细说明。
在本发明的实施例1中，首先，模拟并统计半导体晶圆曝光图形在工序信息条件下所导致的波动几率。假设，入射光子数量以20mJ/cm 2计，在具有最小加工尺寸10nm平方接触孔图形中为1360个，抗刻蚀剂内所吸收光子 的数量为680个。若计算该散粒噪声下的光子波动，该σ值为3.8％，考虑到3σ，则以入射光子数所产生的波动为11.5％。
然后，模拟并统计半导体晶圆曝光图形在抗刻蚀剂材料信息条件下所导致的波动几率，假设，在抗刻蚀剂方面的信息为，金刚烷树脂一个分子的尺寸约为0.6nm立方，并且，10nm平方50nm厚度的抗刻蚀剂中存在约20000个抗刻蚀剂分子，其中感光性材料为20wt％，相对于金刚烷树脂的分子量，PAG的分子量约为3.3倍，PAG的数量为6％左右，约1200个。在此，也可用散粒噪声计算与光子同样的波动，该σ值为3％，考虑到3σ，在抗刻蚀剂材料方面产生9％的波动。若该在抗刻蚀剂材料方面产生的9％波动同入射光子数所产生的11.5％波动合成在一起，这些波动可以预测半导体晶圆曝光图形尺寸最大的图形变化为21.5％。
最后，若考虑掩模图形尺寸信息的变化，即可预测到变化最大为26.5％。
实施例2
请参阅图3，图3所示为本发明实施例2中半导体晶圆缺陷检查装置的结构示意图。在本实施例中，在本发明的实施例2中，假设以波长13.5nm的EUV光对具有最小加工尺寸10nm平方接触孔图形的半导体晶圆进行曝光，在工艺过程中，半导体晶圆的工序信息所包括的曝光量20mJ/cm 2，所采用的抗刻蚀剂材料使用化学增幅型抗刻蚀剂，使用金刚烷树脂作为基底树脂，作为感光剂的PAG(三苯基三氟甲磺酸盐)的浓度为20wt％，输入抗刻蚀剂膜厚50nm，其以高分子聚合物为基体树脂，在部分该树脂上设置可被酸侵蚀分解的官能团，并在该树脂中混合产酸剂和淬灭剂等一起使用的，化 学增幅型抗刻蚀剂的EUV光吸收系数为50％。根据这些工序信息、抗刻蚀剂材料信息和掩模图形的尺寸信息等，可以通过模拟软件直接计算半导体晶圆曝光图形尺寸的波动，并可以得到预测其尺寸变化最大为21.5％，该数字值表示表示缺陷的产生频率非常高，因此，作为检查条件，需为包括掩模图形的尺寸信息误差大的80％图形进行局部设定相应的缺陷检查频率，采用一缺陷检查频率的该局部半导体晶圆曝光图形进行缺陷检查，与对全部半导体晶圆曝光图形进行半导体缺陷检查时相比，其检查时间可以降低20％。
实施例3
请参阅图4，图4所示为本发明实施例3中半导体晶圆缺陷检查装置的结构示意图。在本实施例中，在本发明的实施例3中，假设以波长13.5nm的EUV光对具有最小加工尺寸10nm平方接触孔图形的半导体晶圆进行曝光，在工艺过程中，半导体晶圆的工序信息所包括的曝光量为20mJ/cm 2，抗刻蚀剂的EUV光吸收系数为80％。也就是说，入射光子的波动与实施例1及实施例2中几乎相同，但因抗刻蚀剂的吸收系数大，散粒噪声引起的变化小，若计算该散粒噪声下的光子波动，所吸收的光子数量值预测值为在3σ下，以入射光子数所产生的波动为3％。并且，在该实施例中，抗刻蚀剂采用的是金属氧化物材料，金属氧化物材料所构成的分子尺寸非常小，且有可能全部的分子均发生反应，因此，可以忽略散粒噪声的影响，因此，在预测半导体晶圆曝光图形尺寸最大的图形波动时仅考虑由光子散粒噪声决定。根据上述输入的半导体晶圆工序信息，可以将需半导体缺陷检查频率设定为10％的抽样检查，从而进行半导体缺陷检查，可以将检查时间大幅缩短至以 往的1/10。
以上所述仅为本发明的优选实施例，所述实施例并非用于限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明所附权利要求的保护范围内。

Claims (10)

  1. 一种半导体晶圆缺陷的检查方法，用于确定对所述半导体晶圆进行光刻时的缺陷检查频率；其特征在于，包括如下步骤：
    步骤S1：接收所述半导体晶圆曝光图形的工序信息、掩模图形信息和/或与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷检查频率的信息；
    步骤S2：确定所述半导体晶圆曝光图形的缺陷检查位置，模拟并统计所述半导体晶圆曝光图形在所述工序信息条件下所导致的波动几率，和/或所述半导体晶圆曝光图形在所述掩模图形信息条件下所导致的波动几率；
    步骤S3：根据所述波动几率的合成值和与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷检查频率的信息，设定当前对所述半导体晶圆曝光图形的缺陷检查频率。
  2. 根据权利要求1所述的半导体晶圆缺陷检查的方法，其特征在于，在步骤S3后还包括：
    步骤S4：根据所述缺陷检查频率，对所述缺陷检查位置上的所述半导体晶圆曝光图形的部分或全部进行缺陷检查。
  3. 根据权利要求1所述的半导体晶圆缺陷检查的方法，其特征在于，所述的工序信息包括曝光工序中的射线能量、曝光量、抗刻蚀剂材料的感光机制、吸收系数、构成抗刻蚀剂的材料种类、抗刻蚀剂各自的分子量和/或抗刻蚀剂膜厚。
  4. 根据权利要求1、2或3任意一个所述的半导体晶圆缺陷检查的方法，其特征在于，所述抗刻蚀剂材料包括酸催化型抗蚀材料。
  5. 根据权利要求4所述的半导体晶圆缺陷检查的方法，其特征在于，所述的酸催化型抗蚀材料包括化学增幅型抗刻蚀剂、基底树脂、感光剂的PAG和/或淬灭剂。
  6. 根据权利要求1所述的半导体晶圆缺陷检查的方法，其特征在于，所述抗刻蚀剂材料包括金属氧化物抗刻蚀剂或主链断裂型抗蚀剂。
  7. 根据权利要求1所述的半导体晶圆缺陷检查的方法，其特征在于；所述掩模信息为掩模图形的尺寸和/或掩模图形的位置坐标。
  8. 一种半导体晶圆缺陷检查装置，用于确定在采用DUV光或电子束能量射线对所述半导体晶圆进行光刻时的缺陷检查频率；其特征在于，包括：
    输入模块，用于接收所述半导体晶圆曝光图形的工序信息、掩模图形信息和/或与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷频率的信息；
    统计模块，用于确定所述半导体晶圆曝光图形的缺陷检查位置，模拟并统计所述半导体晶圆曝光图形在所述工序信息条件下所导致的波动几率，和/或所述半导体晶圆曝光图形在所述掩模图形信息条件下所导致的波动几率；
    确定模块，根据所述波动几率的合成值和与所述半导体晶圆具有相同的曝光图案并经相同的工序处理后的晶圆的缺陷检查频率的信息，设定当前对所述半导体晶圆曝光图形的缺陷检查频率。
  9. 根据权利要求8所述的半导体晶圆缺陷检查的装置，其特征在于，还包括：
    执行模块，根据所述缺陷检查频率，对所述缺陷检查位置上的所述半导体晶圆曝光图形的部分或全部进行缺陷检查。
  10. 一种可读存储介质，存储有可执行指令，该可执行指令用于执行如权利要求1～7任一项所述的半导体晶圆缺陷的检查方法。
PCT/CN2020/090992 2020-02-10 2020-05-19 一种半导体器件的缺陷检查方法、装置和可读存储介质 WO2021159627A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2022548496A JP7448671B2 (ja) 2020-02-10 2020-05-19 半導体デバイスの欠陥検査方法、装置及び可読記憶媒体

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010083820.7 2020-02-10
CN202010083820.7A CN111275695B (zh) 2020-02-10 2020-02-10 一种半导体器件的缺陷检查方法、装置和可读存储介质

Publications (1)

Publication Number Publication Date
WO2021159627A1 true WO2021159627A1 (zh) 2021-08-19

Family

ID=71003563

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/090992 WO2021159627A1 (zh) 2020-02-10 2020-05-19 一种半导体器件的缺陷检查方法、装置和可读存储介质

Country Status (3)

Country Link
JP (1) JP7448671B2 (zh)
CN (1) CN111275695B (zh)
WO (1) WO2021159627A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335981B1 (en) * 1997-03-24 2002-01-01 Sharp Kabushiki Kaisha Photomask pattern correcting method and photomask corrected by the same and photomask pattern correcting device
US20060245636A1 (en) * 1999-08-26 2006-11-02 Tadashi Kitamura Pattern inspection apparatus and method
US20140307943A1 (en) * 2013-04-16 2014-10-16 Kla-Tencor Corporation Inspecting high-resolution photolithography masks
TW201640077A (zh) * 2015-01-23 2016-11-16 Hitachi High Tech Corp 圖案測定裝置
CN109727881A (zh) * 2017-10-30 2019-05-07 三星电子株式会社 检查缺陷的方法和使用该方法制造半导体器件的方法
CN109839391A (zh) * 2017-11-29 2019-06-04 三星电子株式会社 检测缺陷的方法和用于执行该方法的设备

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000235949A (ja) * 1998-12-17 2000-08-29 Tokyo Electron Ltd 塗布現像処理装置及び塗布現像処理方法
JP2001203144A (ja) * 2000-01-20 2001-07-27 Nikon Corp 露光装置、露光方法、及び記録媒体
JP2001338870A (ja) * 2000-03-24 2001-12-07 Nikon Corp 走査露光装置及び方法、管理装置及び方法、ならびにデバイス製造方法
JP2002260979A (ja) * 2001-02-27 2002-09-13 Toshiba Corp パターン評価方法
US7307001B2 (en) * 2005-01-05 2007-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer repair method using direct-writing
JP2007170827A (ja) * 2005-12-19 2007-07-05 Toppan Printing Co Ltd 周期性パターンの欠陥検査装置
JP4256408B2 (ja) * 2006-07-20 2009-04-22 株式会社東芝 不良確率の算出方法、パターン作成方法及び半導体装置の製造方法
JP5433631B2 (ja) * 2011-05-20 2014-03-05 株式会社日立ハイテクノロジーズ 半導体デバイスの欠陥検査方法およびそのシステム
US10545411B2 (en) * 2014-02-11 2020-01-28 Asml Netherlands, B.V. Model for calculating a stochastic variation in an arbitrary pattern
CN103887213B (zh) * 2014-03-20 2017-05-17 上海华力微电子有限公司 一种调整检测频率的缺陷检测方法
CN110618585B (zh) * 2019-10-17 2022-05-27 上海华力集成电路制造有限公司 监控光刻机晶圆移载台平整度的方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335981B1 (en) * 1997-03-24 2002-01-01 Sharp Kabushiki Kaisha Photomask pattern correcting method and photomask corrected by the same and photomask pattern correcting device
US20060245636A1 (en) * 1999-08-26 2006-11-02 Tadashi Kitamura Pattern inspection apparatus and method
US20140307943A1 (en) * 2013-04-16 2014-10-16 Kla-Tencor Corporation Inspecting high-resolution photolithography masks
TW201640077A (zh) * 2015-01-23 2016-11-16 Hitachi High Tech Corp 圖案測定裝置
CN109727881A (zh) * 2017-10-30 2019-05-07 三星电子株式会社 检查缺陷的方法和使用该方法制造半导体器件的方法
CN109839391A (zh) * 2017-11-29 2019-06-04 三星电子株式会社 检测缺陷的方法和用于执行该方法的设备

Also Published As

Publication number Publication date
CN111275695A (zh) 2020-06-12
JP7448671B2 (ja) 2024-03-12
JP2023513270A (ja) 2023-03-30
CN111275695B (zh) 2023-06-02

Similar Documents

Publication Publication Date Title
De Bisschop et al. Stochastic printing failures in EUV lithography
Thackeray Materials challenges for sub-20-nm lithography
Levinson High-NA EUV lithography: current status and outlook for the future
Hsu et al. EUV resolution enhancement techniques (RETs) for k1 0.4 and below
Robinson et al. Materials and processes for next generation lithography
US10007191B2 (en) Method for computer modeling and simulation of negative-tone-developable photoresists
Lawson et al. Overview of materials and processes for lithography
US8595655B2 (en) Method and system for lithographic simulation and verification
US11403453B2 (en) Defect prediction
WO2021159627A1 (zh) 一种半导体器件的缺陷检查方法、装置和可读存储介质
Popescu et al. Component optimisation in the multi-trigger resist
Bradon et al. Further investigation of EUV process sensitivities for wafer track processing
Jiang et al. Impact of acid statistics on EUV local critical dimension uniformity
Lawson Molecular resists for advanced lithography-design, synthesis, characterization, and simulation
Wu et al. Considerations in the Setting up of Industry Standards for Photolithography Process, Historical Perspectives, Methodologies, and Outlook
TWI825960B (zh) 半導體裝置的製造方法
US20230108447A1 (en) Method for inspecting photosensitive composition and method for producing photosensitive composition
TW201918802A (zh) 在ｅｕｖ遮罩流程中之薄膜置換
Fujimori How to improve ‘chemical stochastic’in EUV lithography?
JP7360799B2 (ja) レジストパターンをシミュレーションする方法、レジスト材料の組成の最適化方法、及び放射線の照射条件又は目標パターンの最適化方法
Severi Ultra-thin film characterization for high resolution patterning in extreme ultraviolet lithography (EUVL)
US20140273310A1 (en) Monitoring pattern for devices
Yang Zinc-based Photoresist for High-resolution EUV (extreme Ultraviolet) Lithography
Cheng et al. Effects of residual aberrations on line-end shortening in 193-nm lithography
JP2001035779A (ja) 微細パターンの形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20918477

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022548496

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20918477

Country of ref document: EP

Kind code of ref document: A1