WO2021153266A1 - 窒化物半導体装置 - Google Patents

窒化物半導体装置 Download PDF

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Publication number
WO2021153266A1
WO2021153266A1 PCT/JP2021/001166 JP2021001166W WO2021153266A1 WO 2021153266 A1 WO2021153266 A1 WO 2021153266A1 JP 2021001166 W JP2021001166 W JP 2021001166W WO 2021153266 A1 WO2021153266 A1 WO 2021153266A1
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Prior art keywords
nitride semiconductor
semiconductor layer
region
film
etching step
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English (en)
French (fr)
Japanese (ja)
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浩隆 大嶽
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to US17/789,786 priority Critical patent/US20230045660A1/en
Priority to DE112021000745.9T priority patent/DE112021000745T5/de
Priority to JP2021574625A priority patent/JPWO2021153266A1/ja
Priority to CN202180009696.2A priority patent/CN114981979A/zh
Publication of WO2021153266A1 publication Critical patent/WO2021153266A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

  • the present invention relates to a nitride semiconductor device composed of a group III nitride semiconductor (hereinafter, may be simply referred to as "nitride semiconductor").
  • the group III nitride semiconductor is a semiconductor that uses nitrogen as a group V element in the group III-V semiconductor. Typical examples are aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). In general, the group III nitride semiconductor can be expressed as Al x In y Ga 1-x ⁇ y N (0 ⁇ x ⁇ 1,0 ⁇ y ⁇ 1,0 ⁇ x + y ⁇ 1).
  • Such a HEMT includes, for example, an electron traveling layer made of GaN and an electron supply layer made of AlGaN epitaxially grown on the electron traveling layer. A pair of source and drain electrodes are formed so as to be in contact with the electron supply layer, and a gate electrode is arranged between them.
  • a two-dimensional electron gas is formed in the electron traveling layer at a position several ⁇ inward from the interface between the electron traveling layer and the electron supply layer. ..
  • the source and drain are connected using this two-dimensional electron gas as a channel.
  • the source and drain are cut off.
  • the control voltage is not applied to the gate electrode, the source and drain are conductive, so that the device is a normally-on type.
  • Patent Document 1 Since devices using nitride semiconductors have features such as high withstand voltage, high temperature operation, large current density, high speed switching and low on-resistance, application to power devices has been proposed, for example, in Patent Document 1.
  • Patent Document 1 a ridge-shaped p-type GaN gate layer (corresponding to the ridge portion of the third nitride semiconductor layer of the present invention) is laminated on an AlGaN electron supply layer, and a gate electrode is arranged on the ridge-shaped p-type GaN gate layer.
  • a configuration that achieves normal off by eliminating channels by a depletion layer extending from the type GaN gate layer.
  • a high-concentration P-type GaN layer and a gate electrode are ohmic-connected.
  • Ohmic GIT Gate Injection Transistor
  • JP-A-2017-73506 Japanese Unexamined Patent Publication No. 2006-339561
  • An object of the present invention is a nitride semiconductor device capable of directly measuring the film thickness of the material film of the third nitride semiconductor layer before forming a ridge portion of the third nitride semiconductor layer, and a method for manufacturing the same. Is to provide.
  • One embodiment of the present invention comprises a substrate, a first nitride semiconductor layer arranged above the substrate and forming an electron traveling layer, and an electron supply layer formed on the first nitride semiconductor layer.
  • the gate electrode and the source electrode and the drain electrode arranged on the second nitride semiconductor layer with the ridge portion interposed therebetween are included, and in a plan view, the active region contributing to the transistor operation and the transistor operation
  • the non-active region has a non-active region that does not contribute, and the non-active region has a first region, and the film thickness of the second nitride semiconductor layer in the first region is the ridge portion of the active region.
  • a nitride semiconductor device having a thickness different from that of the second nitride semiconductor layer in a region where the source electrode and the drain electrode are not formed.
  • the film thickness of the second nitride semiconductor layer in the first region is the first in the active region in which the ridge portion, the source electrode, and the drain electrode are not formed. It is thicker than the film thickness of the nitride semiconductor layer.
  • the film thickness of the second nitride semiconductor layer in the first region is the first in the active region in which the ridge portion, the source electrode, and the drain electrode are not formed. It is thinner than the film thickness of the nitride semiconductor layer.
  • the first region is adjacent to the third nitride semiconductor layer.
  • the nitride semiconductor device has a rectangular shape in a plan view, and the first region is a peripheral edge of the nitride semiconductor device and an active region in a plan view. It exists in between.
  • the third nitride semiconductor layer has an extension region extending from the end of the ridge portion, and in the non-active region, the gate electrode and the gate electrode and the extension region are included in the extension region.
  • An opening is formed that penetrates the third nitride semiconductor layer and reaches the second nitride semiconductor layer, and the first region is a region in which the opening is formed in a plan view.
  • the side edge of the gate electrode on the ridge portion adjacent to the first region on the first region side is the side edge of the first region side on the upper surface of the ridge portion. It recedes inward from the side edge.
  • a passivation film covering the second nitride semiconductor layer, the third nitride semiconductor layer, and the exposed surface of the gate electrode is formed on the second nitride semiconductor layer.
  • a source contact hole and a drain contact hole are formed in the passivation film, the source electrode penetrates the source contact hole and is in contact with the second nitride semiconductor layer, and the drain electrode is the drain electrode. It penetrates the drain contact hole and is in contact with the second nitride semiconductor layer.
  • the source electrode comprises a source main electrode portion that penetrates the source contact hole and contacts the second nitride semiconductor layer, and the gate electrode that extends from and is adjacent to the source main electrode portion. It has an extension to cover.
  • the source main electrode portion extends in parallel with the ridge portion, and extends in the length direction of the source main electrode portion in the width intermediate portion of the surface of the source main electrode portion. A concave portion of the source electrode is formed.
  • the drain electrode extends parallel to the ridge portion, and a drain electrode recess extending in the length direction of the drain electrode is formed in the width intermediate portion of the surface of the drain electrode. ing.
  • the peripheral portion of the nitride semiconductor device penetrates the passivation film and the second nitride semiconductor layer to reach the first nitride semiconductor layer, and the upper surface and the outer surface are open.
  • the first recess is formed, and the outer peripheral edge of the bottom surface of the first recess has a second recess that penetrates the first nitride semiconductor layer and reaches the substrate, and the upper surface and the outer surface are open. It is formed.
  • the film thickness of the third nitride semiconductor layer is larger than 100 nm.
  • the gate electrode is composed of a single film of any one of TiN, TiW, Ti and W, or a composite film composed of any combination of two or more thereof.
  • the second nitride semiconductor layer is composed of an Al x Ga 1-x N (0 ⁇ x1 ⁇ 1) layer, and the second nitride semiconductor layer is composed of a GaN layer.
  • the acceptor impurities are Mg, Zn or codope thereof.
  • One embodiment of the present invention comprises a substrate, a first nitride semiconductor layer arranged above the substrate and forming an electron traveling layer, and an electron supply layer formed on the first nitride semiconductor layer.
  • the gate electrode film and the third nitride semiconductor layer are selectively etched to obtain the second nitride semiconductor layer.
  • a method for manufacturing a nitride semiconductor device which includes a second etching step of forming a ridge-shaped gate electrode portion on a nitride semiconductor layer, and the etching conditions of the first etching step and the second etching step are different. do.
  • the film thickness of the third nitride semiconductor layer is measured using the opening region, and the etching conditions of the second etching step are determined based on the measurement result.
  • the first etching step also serves as an alignment forming step.
  • the first etching step comprises a third etching step of etching the gate electrode film and a fourth etching step of etching the third nitride semiconductor layer, and the second etching step.
  • it is composed of a fifth etching step of etching the gate electrode film and a sixth etching step of etching the third nitride semiconductor layer, and the etching conditions of the third etching step and the fourth etching step are different from each other.
  • the etching conditions of the fifth etching step and the sixth etching step are different from each other.
  • the etching conditions of the fourth etching step and the sixth etching step are different from each other.
  • the etching conditions of the third etching step and the fifth etching step are the same.
  • the peripheral edge of the opening region in the gate electrode film is directed toward the outside of the opening region from the peripheral edge of the opening region in the third nitride semiconductor layer. It has a process for retreating.
  • the opening region is formed over the entire peripheral edge of the gate electrode film.
  • an insulating film is formed on the entire surface after the film thickness of the third nitride semiconductor layer is measured using the opening region between the first etching step and the second etching step. Including a step of selectively forming a resist film on the insulating film so as to cover a region to be formed of a gate electrode and a region outside the region to be prepared of a gate electrode in a plan view. It may be.
  • the gate electrode film has a rectangular shape in a plan view, and in the first etching step, the opening region is formed at a position close to the corner of the gate electrode film.
  • an insulating film is formed on the entire surface after the film thickness of the third nitride semiconductor layer is measured using the opening region between the first etching step and the second etching step.
  • a step of selectively forming a resist film on the insulating film so as to cover a region where a gate electrode is planned to be produced in a plan view may be included.
  • FIG. 1 is a cross-sectional view for explaining the configuration of the nitride semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is an enlarged cross-sectional view taken along the line II-II of FIG.
  • FIG. 3A is a cross-sectional view showing an example of a manufacturing process of the nitride semiconductor device of FIG.
  • FIG. 3B is a cross-sectional view showing the next step of FIG. 3A.
  • FIG. 3C is a cross-sectional view showing the next step of FIG. 3B.
  • FIG. 3D is a cross-sectional view showing the next step of FIG. 3C.
  • FIG. 3E is a cross-sectional view showing the next step of FIG. 3D.
  • FIG. 3F is a cross-sectional view showing the next step of FIG. 3E.
  • FIG. 3G is a cross-sectional view showing the next step of FIG. 3F.
  • FIG. 3H is a cross-sectional view showing the next step of FIG. 3G.
  • FIG. 3I is a cross-sectional view showing the next step of FIG. 3H.
  • FIG. 3J is a cross-sectional view showing the next step of FIG. 3I.
  • FIG. 3K is a cross-sectional view showing the next step of FIG. 3J.
  • FIG. 3L is a cross-sectional view showing the next step of FIG. 3K.
  • FIG. 3M is a cross-sectional view showing the next step of FIG. 3L.
  • FIG. 3N is a cross-sectional view showing the next step of FIG. 3M.
  • FIG. 3O is a cross-sectional view showing the next step of FIG. 3N.
  • FIG. 3P is a cross-sectional view showing the next step of FIG. 3O.
  • FIG. 3Q is a cross-sectional view showing the next step of FIG. 3P.
  • FIG. 3R is a cross-sectional view showing the next step of FIG. 3Q.
  • FIG. 3S is a cross-sectional view showing the next step of FIG. 3R.
  • FIG. 4 is a cross-sectional view for explaining a modified example of the manufacturing process of the nitride semiconductor device of FIG.
  • FIG. 5 is a cross-sectional view for explaining the configuration of the nitride semiconductor device according to the second embodiment of the present invention.
  • FIG. 6 is an enlarged cross-sectional view taken along the line VI-VI of FIG.
  • FIG. 1 is a plan view for explaining the configuration of the nitride semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is an enlarged cross-sectional view taken along the line II-II of FIG.
  • the passivation film 15 (see FIG. 2) is omitted for convenience of explanation.
  • the source electrode 3 only the source main electrode portion 3A is shown, and the extension portion 3B is omitted.
  • the width of the ridge portion 21A of the third nitride semiconductor layer 21 is larger than the width of the gate main electrode portion 22A of the gate electrode 22, but in FIG. 1, the width of the ridge portion 21A is the gate. It is shown as being equal to the width of the main electrode portion 22A.
  • the horizontal direction of the paper surface of FIG. 1 may be referred to as the horizontal direction
  • the vertical direction of the paper surface of FIG. 1 may be referred to as the vertical direction
  • the nitride semiconductor device 1 has a quadrangular shape having two sides parallel to each other in the horizontal direction and two sides parallel to each other in the vertical direction in a plan view.
  • the nitride semiconductor device 1 includes a semiconductor laminated structure 2 (see FIG. 2) and an electrode metal structure arranged on the semiconductor laminated structure 2.
  • the electrode metal structure includes a plurality of source electrodes 3, a gate electrode 22, and a plurality of drain electrodes 4.
  • the source electrode 3 and the drain electrode 4 extend in the vertical direction.
  • the gate electrode 22 includes a plurality of gate main electrode portions 22A extending in the vertical direction parallel to each other, and two base portions 22B connecting the corresponding ends of the gate main electrode portions 22A.
  • One source electrode 3 includes a source main electrode portion 3A arranged between two adjacent gate main electrode portions 22A and an extension portion 3B (see FIG. 2) around the source main electrode portion 3A in a plan view. Consists of.
  • the source main electrode portion 3A refers to a region including a region surrounded by the contour of the source contact hole 5 and a peripheral region thereof in the entire region of the source electrode 3 in a plan view.
  • the extension portion 3B refers to a portion of the entire region of the source electrode 3 other than the source main electrode portion 3A in a plan view. As shown in FIG. 2, the extension portion 3B covers a pair of gate main electrode portions 22A arranged on both sides of the source main electrode portion 3A.
  • Drain electrodes 4 are arranged on both sides of one source electrode 3.
  • the adjacent drain electrode 4 and the source main electrode portion 3A face each other with the gate main electrode portion 22A in between in a plan view.
  • the length of the drain electrode 4 and the length of the source main electrode portion 3A are substantially equal to each other, and the vertical positions of both ends of the drain electrode 4 and the vertical positions of the corresponding ends of the source main electrode portion 3A are substantially equal to each other. Match.
  • the source main electrode portion 3A (S), the gate main electrode portion 22A (G), and the drain electrode 4 (D) are periodically arranged in the order of DGSGDGS in the lateral direction.
  • the element structure is formed by sandwiching the gate main electrode portion 22A (G) between the source main electrode portion 3A (S) and the drain electrode 4 (D).
  • the surface region on the semiconductor laminated structure 2 is composed of an active region 31 that contributes to the transistor operation and a non-active region 32 that does not contribute to the transistor operation.
  • the alternate long and short dash line 33 indicates the boundary line between the active region 31 and the inactive region 32.
  • the active region 31 refers to a region in which a current flows between the source and drain when an on-voltage is applied to the gate electrode 22.
  • the semiconductor laminated structure 2 includes a substrate 11, a buffer layer 12 formed on the surface of the substrate 11, a first nitride semiconductor layer 13 epitaxially grown on the buffer layer 12, and first nitride. It includes a second nitride semiconductor layer 14 epitaxially grown on the material semiconductor layer 13.
  • the substrate 11 may be, for example, a low resistance silicon substrate.
  • the low resistance silicon substrate may be, for example, a p-type substrate having an electrical resistivity of 0.001 ⁇ mm to 0.5 ⁇ mm (more specifically, about 0.01 ⁇ mm to 0.1 ⁇ mm).
  • the substrate 11 may be a low resistance silicon substrate, a low resistance SiC substrate, a low resistance GaN substrate, or the like.
  • the substrate 11 may be an insulating substrate such as a sapphire substrate.
  • the thickness of the substrate 11 is, for example, about 650 ⁇ m in the semiconductor process, and is ground to about 300 ⁇ m or less in the stage before chipping.
  • the substrate 11 is electrically connected to the source electrode 3.
  • the buffer layer 12 is composed of a multilayer buffer layer in which a plurality of nitride semiconductor films are laminated.
  • the buffer layer 12 is laminated on a first buffer layer (not shown) made of an AlN film in contact with the surface of the substrate 11 and a surface of the first buffer layer (a surface opposite to the substrate 11). It is composed of a second buffer layer (not shown) composed of an AlN / AlGaN superlattice layer.
  • the film thickness of the first buffer layer is about 100 nm to 500 nm.
  • the film thickness of the second buffer layer is about 500 nm to 2 ⁇ m.
  • the buffer layer 12 may be composed of, for example, a single film or a composite film of AlGaN.
  • Impurities may be introduced to make the buffer layer 12 semi-insulating.
  • the concentration of impurities is preferably 4 ⁇ 10 16 cm -3 or more.
  • the impurity is, for example, Fe (iron).
  • the first nitride semiconductor layer 13 constitutes an electron traveling layer.
  • the first nitride semiconductor layer 13 is made of a GaN layer and has a thickness of about 0.5 ⁇ m to 2 ⁇ m. Further, for the purpose of suppressing the leakage current flowing through the first nitride semiconductor layer 13, even if impurities for semi-insulating are introduced in the region other than the surface layer portion of the first nitride semiconductor layer 13. good.
  • the concentration of impurities is preferably 1 ⁇ 10 17 cm -3 or more.
  • the impurity is, for example, C (carbon).
  • the second nitride semiconductor layer 14 constitutes an electron supply layer.
  • the second nitride semiconductor layer 14 is made of a nitride semiconductor having a bandgap larger than that of the first nitride semiconductor layer 13.
  • the second nitride semiconductor layer 14 is made of a nitride semiconductor having a higher Al composition than the first nitride semiconductor layer 13. In a nitride semiconductor, the higher the Al composition, the larger the band gap.
  • the second nitride semiconductor layer 14 is composed of an Al x1 Ga 1-x1 N layer (0 ⁇ x1 ⁇ 1), and its thickness is about 5 nm to 25 nm.
  • the first nitride semiconductor layer (electron traveling layer) 13 and the second nitride semiconductor layer (electron supply layer) 14 are made of nitride semiconductors having different band gaps (Al composition), and are between them. Has a grid mismatch. Then, due to the spontaneous polarization of the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 and the piezo polarization due to the lattice mismatch between them, the first nitride semiconductor layer 13 and the second nitride semiconductor are formed. The energy level of the conduction band of the first nitride semiconductor layer 13 at the interface with the layer 14 is lower than the Fermi level.
  • a third nitride semiconductor layer (semiconductor gate layer) 21 is interposed between the second nitride semiconductor layer 14 and the gate electrode 22.
  • the third nitride semiconductor layer 21 is formed on the surface of the second nitride semiconductor layer 14 by epitaxial growth.
  • the third nitride semiconductor layer 21 has substantially the same shape as the gate electrode 22 in a plan view.
  • the third nitride semiconductor layer 21 has a plurality of ridge portions 21A extending in the longitudinal direction parallel to each other and two connecting portions 21B (2 connecting portions 21B) for connecting the corresponding ends of the ridge portions 21A. (See FIG. 1).
  • the gate electrode 22 is formed on the third nitride semiconductor layer 21. More specifically, the gate main electrode portion 22A of the gate electrode 22 is formed on each of the ridge portions 21A of the third nitride semiconductor layer 21. A base portion 22B of the gate electrode 22 is formed on each of the two connecting portions 21B of the third nitride semiconductor layer 21.
  • the ridge-shaped gate portion 20 is formed by the ridge portion 21A of the third nitride semiconductor layer 21 and the gate main electrode portion 22A formed on the ridge portion 21A.
  • the gate portion 20 including the leftmost ridge portion 21A in FIG. 2 and the gate main electrode portion 22A above the ridge portion 21A functions as a guard link and does not contribute to the operation of the transistor.
  • the gate portion 20 including the rightmost ridge portion 21A in FIG. 1 and the gate main electrode portion 22A above the ridge portion 21A also functions as a guard link and does not contribute to the operation of the transistor.
  • the cross section of the ridge portion 21A and the gate main electrode portion 22A is rectangular.
  • the width of the gate main electrode portion 22A is narrower than the width of the ridge portion 21A.
  • the gate main electrode portion 22A is formed on the width intermediate portion of the upper surface of the ridge portion 21A. Therefore, a step is formed between the upper surface of the gate main electrode portion 22A and the upper surface of one side portion of the ridge portion 21A, and the upper surface of the gate main electrode portion 22A and the upper surface of the other side portion of the ridge portion 21A. A step is formed between the and. Further, in a plan view, both side edges of the gate main electrode portion 22A are retracted inward from the corresponding side edges of the ridge portion 21A.
  • the gate electrode 22 is in Schottky contact with the upper surface of the third nitride semiconductor layer 21.
  • the gate electrode 22 is made of TiN.
  • the film thickness of the gate electrode 22 is about 50 nm to 150 nm.
  • the gate electrode 22 may be composed of a single film of any one of a Ti film, a TiN film, a TiW film and W, or a composite film composed of any combination of two or more thereof.
  • the third nitride semiconductor layer 21 is made of a nitride semiconductor doped with acceptor-type impurities.
  • the third nitride semiconductor layer 21 is composed of a GaN layer (p-type GaN layer) doped with acceptor-type impurities.
  • the acceptor-type impurity is Mg (magnesium).
  • the acceptor-type impurity may be an acceptor-type impurity other than Mg such as Zn (zinc). Further, the acceptor type impurity may be a codope of Mg and Zn.
  • the film thickness of the third nitride semiconductor layer 21 is preferably larger than 100 nm, more preferably 110 nm or more.
  • the film thickness of the third nitride semiconductor layer 21 is more preferably 110 nm or more and 150 nm or less. This is because when the film thickness of the third nitride semiconductor layer 21 is 110 nm or more and 150 nm or less, the maximum rated voltage of the gate in the positive direction can be increased.
  • the film thickness of the third nitride semiconductor layer 21 is about 120 nm.
  • the third nitride semiconductor layer 21 changes the energy level of the conduction band at the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 in the region directly below the gate portion 20, and the gate voltage. Is provided so that the two-dimensional electron gas 9 is not generated in the region directly below the gate portion 20 in a state where the above is not applied.
  • a passivation film 15 is formed on the second nitride semiconductor layer 14 to cover the exposed surfaces of the second nitride semiconductor layer 14, the third nitride semiconductor layer 21, and the gate electrode 22. .. Therefore, the side surface and the surface of the gate portion 20 are covered with the passivation film 15.
  • the passivation film 15 is made of a SiN film and has a thickness of about 50 nm to 200 nm.
  • the passivation film 15 may be composed of a single film of SiN, SiO 2 and SiON, or a composite film composed of any combination of two or more thereof.
  • a source contact hole 5 and a drain contact hole 6 are formed in the passivation film 15.
  • the source contact hole 5 and the drain contact hole 6 are formed so as to sandwich the gate portion 20.
  • the source main electrode portion 3A of the source electrode 3 penetrates the source contact hole 5 and is in contact with the second nitride semiconductor layer 14. As shown in FIG. 2, the extension portion 3B of the source electrode 3 covers the gate portion 20. A recess (source electrode recess) extending in the length direction of the source main electrode portion 3A is formed in the width intermediate portion of the surface of the source main electrode portion 3A.
  • the drain electrode 4 penetrates the drain contact hole 6 and is in contact with the second nitride semiconductor layer 14.
  • a recess (drain electrode recess) extending in the length direction of the drain electrode 4 is formed in the intermediate width of the surface of the drain electrode 4.
  • the source electrode 3 and the drain electrode 4 are, for example, a first metal layer (ohmic metal layer) in contact with the second nitride semiconductor layer 14 and a second metal layer (main electrode metal layer) laminated on the first metal layer. It is composed of a third metal layer (adhesion layer) laminated on the second metal layer and a fourth metal layer (barrier metal layer) laminated on the third metal layer.
  • the first metal layer is, for example, a Ti layer having a thickness of about 10 nm to 20 nm.
  • the second metal layer is, for example, an AlCu layer having a thickness of about 100 nm to 300 nm.
  • the third metal layer is, for example, a Ti layer having a thickness of about 10 nm to 20 nm.
  • the fourth metal layer is, for example, a TiN layer having a thickness of about 10 nm to 50 nm.
  • the peripheral portion of the nitride semiconductor device 1 penetrates the passivation film 15 and the second nitride semiconductor layer 14 to reach the first nitride semiconductor layer 13, and has an upper surface and an outer surface (outer peripheral surface).
  • the first recess 16 is formed.
  • the second recess 17 penetrates the first nitride semiconductor layer 13 and the buffer layer 12 and reaches the substrate 11, and the upper surface and the outer surface (outer peripheral surface) are opened. Is formed.
  • a substrate contact metal (not shown) for electrically connecting the substrate 11 to the source electrode 3 is embedded in the first recess 16 and the second recess 17.
  • the non-active region 32 includes a first region 32a for directly measuring the film thickness of the second nitride semiconductor layer 14 in the manufacturing process of the nitride semiconductor device 1.
  • the first region 32a in a plan view, is formed in the region between the peripheral edge of the nitride semiconductor device 1 and the active region 31. More specifically, the first region 32a is a region between the outer peripheral edge of the third nitride semiconductor layer 21 of FIGS. 1 and 2 and the first recess 16 in a plan view. Therefore, the first region 32a is adjacent to the outer peripheral edge of the third nitride semiconductor layer 21. In FIG. 1, the first region 32a is shown as a dot region.
  • the film thickness of the second nitride semiconductor layer 14 in the first region 32a and the region of the active region 31 in which the ridge portion 21A, the source contact hole 5 and the drain contact hole 6 are not formed (hereinafter, “access region 34””. It is different from the film thickness of the second nitride semiconductor layer 14 in).
  • the film thickness of the second nitride semiconductor layer 14 in the first region 32a is larger than the film thickness of the access region 34.
  • the film thickness of the second nitride semiconductor layer 14 in the first region 32a may be smaller than the film thickness of the access region 34.
  • a second nitride semiconductor layer (electron supply layer) 14 having a different band gap (Al composition) is formed on the first nitride semiconductor layer (electron traveling layer) 13 to form a heterojunction.
  • a two-dimensional electron gas 9 is formed in the first nitride semiconductor layer 13 near the interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14, and the two-dimensional electron gas 9 is used as a channel.
  • the used HEMT is formed.
  • the gate main electrode portion 22A of the gate electrode 22 faces the second nitride semiconductor layer 14 with the ridge portion 21A of the third nitride semiconductor layer 21 interposed therebetween.
  • the energy levels of the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 are raised by the ionization acceptor contained in the ridge portion 21A composed of the p-type GaN layer. Therefore, the energy level of the conduction band at the heterojunction interface between the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 is higher than the Fermi level. Therefore, immediately below the gate main electrode portion 22A (gate portion 20), a two-dimensional electron gas caused by spontaneous polarization of the first nitride semiconductor layer 13 and the second nitride semiconductor layer 14 and piezo polarization due to lattice mismatch thereof. 9 is not formed.
  • a predetermined voltage for example, 50V to 100V
  • an off voltage (0V) or an on voltage (5V) is applied to the gate electrode 22 with the source electrode 3 as a reference potential (0V).
  • 3A to 3S are cross-sectional views for explaining an example of the manufacturing process of the above-mentioned nitride semiconductor device 1, and show cross-sectional structures at a plurality of stages in the manufacturing process.
  • the buffer layer 12, the first nitride semiconductor layer (electron traveling layer) 13, and the second nitride semiconductor layer (electrons) are placed on the substrate 11 by the MOCVD (Metalorganic Chemical Vapor Deposition) method.
  • the supply layer) 14 is epitaxially grown.
  • the semiconductor laminated structure 2 is obtained.
  • the third semiconductor material film 41 which is the material film of the third nitride semiconductor layer 21, is epitaxially grown on the second nitride semiconductor layer 14 by the MOCVD method.
  • the third semiconductor material film 41 is a p-type GaN film.
  • a gate electrode film 42 which is a material film of the gate electrode 22, is formed on the third semiconductor material film 41 by, for example, a sputtering method.
  • the resist 43 is formed on the region excluding the peripheral edge of the gate electrode film 42.
  • the peripheral edge portion of the gate electrode film 42 refers to a region corresponding to the outer periphery of the outer peripheral edge of the third nitride semiconductor layer 21 of FIGS. 1 and 2.
  • the gate electrode film 42 is dry-etched using the resist 43 as a mask.
  • the third semiconductor material film 41 is dry-etched using the first resist 43 and the gate electrode film 42 as masks. As a result, an opening region 44 penetrating the gate electrode film 42 and the third semiconductor material film 41 is formed in a region corresponding to the outer periphery of the outer peripheral edge of the third nitride semiconductor layer 21 of FIGS. 1 and 2.
  • the gate electrode film 42 is isotropically etched.
  • the side edge of the gate electrode film 42 on the opening region 44 side recedes toward the outside of the opening region 44 from the side edge of the third semiconductor material film 41 on the opening region 44 side.
  • the etching steps of FIGS. 3D to 3F (when the etching of FIG. 3F is not performed as described later, the etching steps of FIGS. 3D to 3E) will be referred to as a first etching step.
  • the step of etching the TiN (gate electrode film 42) of the first region 32a as shown in FIG. 3D is referred to as a third etching step, and as shown in FIG. 3E, the p-type GaN (third semiconductor) of the first region 32a.
  • the step of etching the material film 41) is called a fourth etching step.
  • the etching conditions of the third etching step and the fourth etching step are different.
  • the third etching step for example, CF 4 / Cl 2 / N 2 is used as the etching gas.
  • the fourth etching step for example, Cl 2 / O 2 / Ar is used as the etching gas.
  • the first etching step also serves as an alignment forming step. That is, in this embodiment, the alignment mark is formed by the first etching step.
  • the first resist 43 is removed.
  • the film thickness of the third semiconductor material film 41 is directly measured by an AFM (Atomic Force Microscope).
  • reference numeral 45 indicates an AFM probe.
  • the film thickness of the third semiconductor material film 41 is directly measured when the film thickness of the third semiconductor material film 41 is larger than 100 nm by a normal indirect measurement method. This is because it is difficult to measure the film thickness of 41 with high accuracy.
  • Normal indirect measurement methods include a method of irradiating a wafer with a laser during crystal growth and identifying the film thickness from the intensity cycle of the reflected light, an XRR (X-Ray Reflectivity) for observing a thin film, and the like.
  • a SiN film (insulating film) 46 is formed on the entire exposed surface.
  • the resist film 47 is selected on the SiN film 46 so as to cover the region where the gate electrode is planned to be created and the region outside the outer peripheral edge of the region where the gate electrode is planned to be created in a plan view. Is formed.
  • the SiN film 46 and the gate electrode film 42 are patterned by dry etching using the resist film 47 as a mask. As a result, the gate electrode 22 is formed. After this, the resist film 47 is removed.
  • the SiO 2 film 48 is formed so as to cover the entire exposed surface by, for example, a plasma chemical vapor deposition method (PECVD method).
  • PECVD method plasma chemical vapor deposition method
  • SiO 2 film 48 by being etched back, SiO 2 film 48 covering the side surfaces of the gate electrode 22 and SiN film 46 is formed thereon.
  • the third semiconductor material film 41 is patterned by dry etching using the SiN film 46 and the SiO 2 film 48 as masks. As a result, the third nitride semiconductor layer 21 is obtained.
  • the etching steps of FIGS. 3J and 3M will be referred to as a second etching step.
  • the step of etching the TiN (gate electrode film 42) of the active region 31 as shown in FIG. 3J is referred to as a fifth etching step, and as shown in FIG. 3M, the p-type GaN (third semiconductor material film) of the active region 31 is used.
  • the step of etching 41) is referred to as a sixth etching step.
  • the etching conditions of the second etching step are determined based on the film thickness of the third semiconductor material film 41 directly measured by the step of FIG. 3G.
  • the etching conditions of the fifth etching step and the sixth etching step are different.
  • the fifth etching step for example, CF 4 / Cl 2 / N 2 is used as the etching gas.
  • the sixth etching step for example, Cl 2 / O 2 / Ar is used as the etching gas.
  • the etching conditions of the third etching step (see FIG. 3D) and the fifth etching step (see FIG. 3J) may be the same.
  • the etching conditions of the fourth etching step (see FIG. 3E) and the sixth etching step (see FIG. 3M) are different.
  • the oxygen flow rate in the fourth etching step is higher than the oxygen flow rate in the sixth etching step.
  • the larger the oxygen flow rate the easier it is for the third semiconductor material film 41 and the second nitride semiconductor layer 14 to oxidize, so that the etching rate becomes slower. Therefore, the etching time of the fourth etching step (see FIG. 3E) is set longer than the etching time of the sixth etching step (see FIG. 3M).
  • the etching rate of the second nitride semiconductor layer 14 is slower than that of the third semiconductor material film 41, but the larger the oxygen flow rate, the larger the difference in etching rate between the two. Therefore, the larger the oxygen flow rate, the easier it is to etch the third semiconductor material film 41 to the depth of the surface of the second nitride semiconductor layer 14 with higher accuracy. Therefore, the fourth etching step (see FIG. 3E) makes it easier to etch the third semiconductor material film 41 with higher accuracy than the sixth etching step (see FIG. 3M). However, as the oxygen flow rate increases, the etched surface becomes more likely to become rough. Therefore, in the sixth etching step for creating the device structure, the oxygen flow rate is reduced as compared with the fourth etching step for creating the first region 32a.
  • the film thickness of the second nitride semiconductor layer 14 in the first region 32a and the access region 34 is different from the film thickness of the second nitride semiconductor layer 14.
  • the amount of etching on the surface layer of the second nitride semiconductor layer 14 in the sixth etching step is larger than the amount of etching on the surface layer of the second nitride semiconductor layer 14 in the fourth etching step.
  • the film thickness of the second nitride semiconductor layer 14 in the access region 34 is thinner than the film thickness of the second nitride semiconductor layer 14 in the first region 32a.
  • the film thickness of the second nitride semiconductor layer 14 in the first region 32a may be the film of the second nitride semiconductor layer 14 in the access region 34. It may be thinner than it is thick.
  • the SiN film 46 and the SiO 2 film 48 are removed by wet etching.
  • the gate portion 20 including the ridge portion 21A of the third nitride semiconductor layer 21 and the gate main electrode portion 22A formed on the width intermediate portion of the upper surface of the third nitride semiconductor layer 21 is obtained.
  • the passivation film 15 is formed so as to cover the entire exposed surface.
  • the passivation film 15 is made of, for example, SiN.
  • a source contact hole 5 and a drain contact hole 6 reaching the second nitride semiconductor layer 14 are formed on the passivation film 15.
  • the source / drain electrode film 49 is formed so as to cover the entire exposed surface.
  • the source / drain electrode film 49 is patterned by photolithography and etching to form the source electrode 3 and the drain electrode 4 in contact with the second nitride semiconductor layer 14.
  • the first recess 16 reaching the first nitride semiconductor layer 13 is formed in the second nitride semiconductor layer 14 and the passivation film 15.
  • a second recess 17 reaching the substrate 11 is formed on the outer peripheral edge of the bottom surface of the first recess 16. In this way, the nitride semiconductor device 1 having the structure shown in FIGS. 1 and 2 is obtained.
  • the side edge of the gate electrode film 42 on the opening region 44 side is set to be larger than the side edge of the third semiconductor material film 41 on the opening region 44 side by the etching step of FIG. 3F. It is retracted toward the outside of the opening region 44.
  • the film thickness of the third semiconductor material film 41 may be measured after removing the resist 43 on the gate electrode film 42. Specifically, for example, the sum d3 of the film thickness d1 of the gate electrode film 42 and the film thickness d2 of the third semiconductor material film 41 is directly measured by an AFM. Further, the film thickness d1 of the gate electrode film 42 is measured by a normal indirect measuring method. Then, by calculating (d3-d1), the film thickness d2 of the third semiconductor material film 41 is obtained.
  • the film thickness of the material film (third semiconductor material film 41) of the third nitride semiconductor layer 21 is directly measured before forming the ridge portion 21A of the third nitride semiconductor layer 21. It becomes possible. As a result, the etching conditions for forming the ridge portion 21A of the third nitride semiconductor layer 21 can be appropriately determined.
  • this embodiment is particularly effective when the film thickness of the third nitride semiconductor layer 21 is made thicker than 100 nm in order to increase the maximum rated voltage of the gate in the positive direction.
  • FIG. 5 is a plan view for explaining the configuration of the nitride semiconductor device according to the second embodiment of the present invention.
  • FIG. 6 is an enlarged cross-sectional view taken along the line VI-VI of FIG.
  • the parts corresponding to the respective parts of FIG. 1 described above are designated by the same reference numerals as those in FIG.
  • the portions corresponding to the respective parts of FIG. 2 described above are designated by the same reference numerals as those in FIG.
  • the passivation film 15 (see FIG. 6) is omitted for convenience of explanation.
  • the source electrode 3 only the source main electrode portion 3A is shown, and the extension portion 3B is omitted.
  • the width of the ridge portion 21A of the third nitride semiconductor layer 21 is larger than the width of the gate main electrode portion 22A of the gate electrode 22, but in FIG. 5, the ridge portion 21A The width is shown as being equal to the width of the gate main electrode portion 22A.
  • the nitride semiconductor device 1A according to the second embodiment is different from the nitride semiconductor device 1 according to the first embodiment in the first region 32a formed in the non-active region 32.
  • the first region 32a is formed in the connecting portion 21B of the third nitride semiconductor layer 21. More specifically, as shown in FIG. 5, in the connecting portion 21B of the third nitride semiconductor layer 21, a first region having a rectangular shape in a plan view is located near the upper left corner of the third nitride semiconductor layer 21. 32a is formed.
  • the connecting portion 21B of the third nitride semiconductor layer 21 is an example of the “extended region extending from the end of the ridge portion” in the present invention.
  • the first region 32a has a planar quadrangular shape that penetrates the base portion 22B of the gate electrode 22 and the connecting portion 21B of the third nitride semiconductor layer 21 and reaches the second nitride semiconductor layer 14.
  • the opening 51 is formed.
  • the opening 51 communicates with the first opening 51a having a rectangular shape in a plan view penetrating the base portion 22B of the gate electrode 22 and the first opening 51a, and penetrates the connecting portion 21B of the third nitride semiconductor layer 21. It is composed of a second opening 51b having a rectangular shape in a plan view. Therefore, the first region 32a is adjacent to the third nitride semiconductor layer 21.
  • the first opening 51a is larger than the second opening 51b, and the four sides of the first opening 51a are parallel to the four sides of the second opening 51b, respectively.
  • the second opening 51b is located at the center of the first opening 51a. Therefore, the peripheral edge of the opening 51 (first opening 51a) of the gate electrode 22 is outside the opening 51 with respect to the peripheral edge of the opening 51 (second opening 51b) of the third nitride semiconductor layer 21. Retreating towards.
  • the manufacturing method of the nitride semiconductor device 1A will be briefly described.
  • the steps of FIG. 3A and the steps of FIG. 3B described above are the same.
  • the opening 51 penetrating the gate electrode film 42 and the third semiconductor material film 41 is formed by photolithography and etching.
  • the film thickness of the third semiconductor material film 41 is directly measured by AFM.
  • the same steps as those in FIGS. 3H to 3S described above are performed.
  • the region of the SiN film 46 surface corresponding to the region to be formed of the gate electrode is covered with the resist film 47, but the region to be formed of the gate electrode is planned.
  • the region outside the outer peripheral edge of the is not covered by the resist film 47. Therefore, the gate electrode film 42 in the region outside the outer peripheral edge of the region where the gate electrode is planned to be formed and the third semiconductor material film 41 in the region outside the outer peripheral edge of the region where the third nitride semiconductor layer is planned to be formed are shown in FIG. 3I. -Etched (removed) by the process shown in FIG. 3N.
  • Si may be contained in the second nitride semiconductor layer 14 directly below the source electrode 3 and the drain electrode 4.
  • silicon is exemplified as a material example of the substrate 11, but other substrate materials such as a sapphire substrate and a QST substrate can be applied.
  • Nitride semiconductor device Semiconductor laminated structure 3 Source electrode 3A Source main electrode part 3B Extension part 4 Drain electrode 5 Source contact hole 6 Drain contact hole 9 Two-dimensional electron gas) 11 Substrate 12 Buffer layer 13 First nitride semiconductor layer (electron traveling layer) 14 Second nitride semiconductor layer (electron supply layer) 15 Passivation film 16 1st recess 17 2nd recess 20 Gate 21 3rd nitride semiconductor layer (semiconductor gate layer) 21A Ridge part 21B Connecting part 22 Gate electrode 22A Gate main electrode part 22B Base part 31 Active area 32 Non-active area 32a First area 33 Boundary 41 Third semiconductor material film 42 Gate electrode film 43 Resist 44 Open area 45 AFC probe 46 SiN film 47 Resist film 48 SiO 2 film 49 Source / drain electrode film 51 Opening 51a First opening 51b Second opening

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11424247B1 (en) * 2021-05-07 2022-08-23 Fujian Jinhua Integrated Circuit Co., Ltd. Semiconductor memory device having a second active region disposed at an outer side of a first active region
WO2023042617A1 (ja) * 2021-09-14 2023-03-23 ローム株式会社 半導体装置
WO2023219046A1 (ja) * 2022-05-12 2023-11-16 ローム株式会社 窒化物半導体装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012523697A (ja) * 2009-04-08 2012-10-04 エフィシエント パワー コンヴァーション コーポレーション エンハンスメントモードＧａＮＨＥＭＴデバイス、及びその製造方法
JP2012523700A (ja) * 2009-04-08 2012-10-04 エフィシエント パワー コンヴァーション コーポレーション 逆拡散抑制構造
JP2015204304A (ja) * 2014-04-10 2015-11-16 トヨタ自動車株式会社 スイッチング素子
JP2018163928A (ja) * 2017-03-24 2018-10-18 住友電気工業株式会社 半導体装置の製造方法
JP2018195845A (ja) * 2018-08-06 2018-12-06 ルネサスエレクトロニクス株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012523697A (ja) * 2009-04-08 2012-10-04 エフィシエント パワー コンヴァーション コーポレーション エンハンスメントモードＧａＮＨＥＭＴデバイス、及びその製造方法
JP2012523700A (ja) * 2009-04-08 2012-10-04 エフィシエント パワー コンヴァーション コーポレーション 逆拡散抑制構造
JP2015204304A (ja) * 2014-04-10 2015-11-16 トヨタ自動車株式会社 スイッチング素子
JP2018163928A (ja) * 2017-03-24 2018-10-18 住友電気工業株式会社 半導体装置の製造方法
JP2018195845A (ja) * 2018-08-06 2018-12-06 ルネサスエレクトロニクス株式会社 半導体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11424247B1 (en) * 2021-05-07 2022-08-23 Fujian Jinhua Integrated Circuit Co., Ltd. Semiconductor memory device having a second active region disposed at an outer side of a first active region
US11706911B2 (en) 2021-05-07 2023-07-18 Fujian Jinhua Integrated Circuit Co., Ltd. Method of fabricating semiconductor memory having a second active region disposed at an outer side of a first active region
WO2023042617A1 (ja) * 2021-09-14 2023-03-23 ローム株式会社 半導体装置
WO2023219046A1 (ja) * 2022-05-12 2023-11-16 ローム株式会社 窒化物半導体装置

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