WO2022201841A1 - 窒化物半導体装置 - Google Patents
窒化物半導体装置 Download PDFInfo
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- WO2022201841A1 WO2022201841A1 PCT/JP2022/003094 JP2022003094W WO2022201841A1 WO 2022201841 A1 WO2022201841 A1 WO 2022201841A1 JP 2022003094 W JP2022003094 W JP 2022003094W WO 2022201841 A1 WO2022201841 A1 WO 2022201841A1
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 227
- 239000004065 semiconductor Substances 0.000 title claims abstract description 175
- 229910052751 metal Inorganic materials 0.000 claims abstract description 121
- 239000002184 metal Substances 0.000 claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 230000005533 two-dimensional electron gas Effects 0.000 claims abstract description 20
- 229910002704 AlGaN Inorganic materials 0.000 claims description 20
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 7
- 238000000605 extraction Methods 0.000 claims description 6
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- 230000017525 heat dissipation Effects 0.000 description 54
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- 238000005530 etching Methods 0.000 description 17
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- 229910002601 GaN Inorganic materials 0.000 description 14
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- 238000004519 manufacturing process Methods 0.000 description 13
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- 229910052737 gold Inorganic materials 0.000 description 10
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 9
- 239000000463 material Substances 0.000 description 8
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- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H01L29/107—Substrate region of field-effect devices
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/2003—Nitride compounds
Definitions
- the present disclosure relates to a nitride semiconductor device made of a Group III nitride semiconductor (hereinafter sometimes simply referred to as "nitride semiconductor").
- a group III nitride semiconductor is a semiconductor in which nitrogen is used as a group V element in a group III-V semiconductor.
- Aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN) are representative examples. In general, it can be expressed as AlxInyGa1 -x-yN ( 0 ⁇ x ⁇ 1 , 0 ⁇ y ⁇ 1, 0 ⁇ x+y ⁇ 1).
- Patent Document 1 discloses a HEMT (High Electron Mobility Transistor) using a nitride semiconductor.
- the HEMT of Patent Document 1 includes a p-type Si substrate, a buffer layer formed on the p-type Si substrate, an electron transit layer made of GaN formed on the buffer layer, and an AlGaN electron transit layer formed on the electron transit layer. and an electron supply layer consisting of A drain electrode and a gate electrode are formed in contact with the electron supply layer.
- a source electrode is formed so as to penetrate through the electron supply layer, the electron transit layer and the buffer layer and come into contact with the p-type Si substrate.
- a back surface electrode electrically connected to the source electrode via the p-type Si substrate is formed on the back surface of the p-type Si substrate.
- a two-dimensional electron gas is formed in the electron transit layer at a position several angstroms inward from the interface between the electron transit layer and the electron supply layer. .
- this two-dimensional electron gas is connected.
- the gate electrode By applying a control voltage to the gate electrode to cut off the two-dimensional electron gas, the connection between the source and the drain is cut off.
- An object of the present disclosure is to provide a nitride semiconductor device with high heat dissipation.
- One embodiment of the present disclosure is a nitride semiconductor device including a substrate having a first main surface and a second main surface opposite thereto, and a nitride epitaxial layer formed on the first main surface.
- the nitride semiconductor device has, in plan view, an active region in which a two-dimensional electron gas can be formed in the nitride epitaxial layer and an inactive region in which a two-dimensional electron gas is not formed in the nitride epitaxial layer.
- a nitride semiconductor device is provided, including a buried metal formed therein.
- FIG. 1 is a plan view for explaining the configuration of a nitride semiconductor device according to a first embodiment of the present disclosure
- FIG. FIG. 2 is a cross-sectional view taken along line II--II of FIG.
- FIG. 3 is a cross-sectional view taken along line III--III in FIG.
- FIG. 4A is a cross-sectional view showing an example of the manufacturing process of the nitride semiconductor device.
- FIG. 4B is a cross-sectional view showing the next step of FIG. 4A.
- FIG. 4C is a cross-sectional view showing the next step of FIG. 4B.
- FIG. 4D is a cross-sectional view showing the next step of FIG. 4C.
- FIG. 4E is a cross-sectional view showing the next step of FIG.
- FIG. 4F is a cross-sectional view showing the next step of FIG. 4E.
- FIG. 4G is a cross-sectional view showing the next step of FIG. 4F.
- FIG. 4H is a cross-sectional view showing the next step of FIG. 4G.
- FIG. 4I is a cross-sectional view showing the next step of FIG. 4H.
- FIG. 5 is a plan view for explaining the configuration of the nitride semiconductor device according to the second embodiment of the present disclosure.
- FIG. 6 is a cross-sectional view taken along line VI-VI of FIG.
- FIG. 7 is a cross-sectional view along line VII-VII of FIG.
- FIG. 8A is a cross-sectional view showing an example of the manufacturing process of the nitride semiconductor device.
- FIG. 8B is a cross-sectional view showing the next step of FIG. 8A.
- FIG. 8C is a cross-sectional view showing the next step of FIG. 8B.
- FIG. 8D is a cross-sectional view showing the next step of FIG. 8C.
- FIG. 9 is a plan view for explaining the configuration of the nitride semiconductor device according to the third embodiment of the present disclosure.
- 10 is a cross-sectional view taken along line XX of FIG. 9.
- FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 10.
- FIG. FIG. 12A is a cross-sectional view showing an example of the manufacturing process of the nitride semiconductor device.
- FIG. 12B is a cross-sectional view showing the next step of FIG.
- FIG. 12A is a cross-sectional view showing the next step of FIG. 12B.
- FIG. 12D is a cross-sectional view showing the next step of FIG. 12C.
- FIG. 12E is a cross-sectional view showing the next step of FIG. 12D.
- FIG. 12F is a cross-sectional view showing the next step of FIG. 12E.
- FIG. 12G is a cross-sectional view showing the next step of FIG. 12F.
- FIG. 12H is a cross-sectional view showing the next step of FIG. 12G.
- 13 is a cross-sectional view showing a modification of the nitride semiconductor device of FIG. 2.
- FIG. 14 is a cross-sectional view showing a modification of the nitride semiconductor device of FIG. 6.
- FIG. 15 is a cross-sectional view showing a modification of the nitride semiconductor device of FIG. 10.
- One embodiment of the present disclosure is a nitride semiconductor device including a substrate having a first main surface and a second main surface opposite thereto, and a nitride epitaxial layer formed on the first main surface.
- the nitride semiconductor device has, in plan view, an active region in which a two-dimensional electron gas can be formed in the nitride epitaxial layer and an inactive region in which a two-dimensional electron gas is not formed in the nitride epitaxial layer.
- a nitride semiconductor device is provided, including a buried metal formed therein.
- the trench is formed only in the inactive region of the active region and the inactive region.
- the trench is formed in both the active area and the inactive area.
- the total volume of trenches present in the inactive region is 1 ⁇ 3 or more of the volume of the substrate in the inactive region.
- An embodiment of the present disclosure includes a lead metal formed on the second main surface and thermally connected to the embedded metal.
- the trench is dug halfway through the substrate from the second main surface toward the first main surface.
- the trench extends through the substrate to the nitride epitaxial layer.
- a source electrode, a drain electrode, and a gate electrode arranged on the nitride epitaxial layer and electrically connecting the source electrode and the embedded metal through the nitride epitaxial layer Including contact metal to be connected.
- the nitride epitaxial layer is formed on a first nitride semiconductor layer forming an electron transit layer, and on the first nitride semiconductor layer to form an electron supply layer. and a second nitride semiconductor layer having a bandgap higher than that of the first nitride semiconductor layer.
- An embodiment of the present disclosure includes a semi-insulating nitride layer disposed between the substrate and the first nitride semiconductor layer and having an acceptor concentration higher than a donor concentration.
- a buffer layer made of a nitride semiconductor is included between the substrate and the semi-insulating nitride layer.
- the first nitride semiconductor layer is a GaN layer
- the second nitride semiconductor layer is an AlGaN layer.
- the first nitride semiconductor layer is a GaN layer
- the second nitride semiconductor layer is an AlGaN layer
- the semi-insulating nitride layer is a GaN layer containing carbon
- the first nitride semiconductor layer is a GaN layer
- the second nitride semiconductor layer is an AlGaN layer
- the semi-insulating nitride layer is a GaN layer containing carbon
- the buffer layer is composed of a laminated film of an AlN layer formed on the first main surface and an AlGaN layer laminated on the AlN layer.
- the first nitride semiconductor layer is a GaN layer
- the second nitride semiconductor layer is an AlGaN layer
- the semi-insulating nitride layer is a GaN layer containing carbon
- the buffer layer is composed of an AlN layer or an AlGaN layer.
- FIG. 1 is a plan view for explaining the configuration of the nitride semiconductor device according to the first embodiment of the present disclosure.
- FIG. 2 is a cross-sectional view taken along line II--II of FIG.
- FIG. 3 is a cross-sectional view taken along line III--III in FIG.
- the horizontal direction of the paper surface of FIG. 1 may be referred to as the horizontal direction
- the vertical direction of the paper surface of FIG. 1 may be referred to as the vertical direction
- the nitride semiconductor device 1 has, for example, a laterally elongated rectangular parallelepiped shape.
- a nitride semiconductor device 1 includes a substrate 2 having a first main surface (front surface) 2a and a second main surface (back surface) 2b opposite thereto, and a nitride epitaxial layer formed on the first main surface 2a of the substrate 2. and layer 20 .
- Nitride epitaxial layer 20 includes buffer layer 3 formed on first main surface 2a of substrate 2, semi-insulating nitride layer 4 formed on buffer layer 3, and semi-insulating nitride layer 4. and a second nitride semiconductor layer 6 formed on the first nitride semiconductor layer 5 .
- this nitride semiconductor device 1 includes an insulating film 7 formed on the second nitride semiconductor layer 6 .
- Nitride semiconductor device 1 further includes source electrode 10 and drain electrode 11 penetrating through source contact hole 8 and drain contact hole 9 formed in insulating film 7 and making ohmic contact with second nitride semiconductor layer 6 . .
- the source electrode 10 and the drain electrode 11 are spaced apart.
- this nitride semiconductor device 1 includes a gate electrode 13 that penetrates through a gate contact hole 12 formed in the insulating film 7 and contacts the second nitride semiconductor layer 6 .
- the gate electrode 13 is arranged between the source electrode 10 and the drain electrode 11 .
- this nitride semiconductor device 1 has a heat dissipation structure 15 .
- the substrate 2 is made of a low resistance Si (silicon) substrate in this embodiment.
- the substrate 2 may contain p-type impurities, for example.
- the p-type impurity concentration may be, for example, 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 20 cm ⁇ 3 .
- the thickness of the substrate 2 is, for example, about 100 ⁇ m to 700 ⁇ m. In this embodiment, the thickness of the substrate 2 is of the order of 200 ⁇ m.
- the buffer layer 3 is a buffer layer for relaxing strain caused by a difference between the lattice constant of the semi-insulating nitride layer 4 formed on the buffer layer 3 and the lattice constant of the substrate 2 .
- the buffer layer 3 is composed of a multi-layered buffer layer in which a plurality of nitride semiconductor films are laminated.
- the buffer layer 3 is composed of a laminated film of an AlN film in contact with the surface of the substrate 2 and an AlGaN film laminated on the surface of this AlN film (the surface opposite to the substrate 2).
- the buffer layer 3 may be composed of a single AlN film or a single AlGaN film.
- the thickness of the buffer layer 3 is, for example, about 0.1 ⁇ m to 5 ⁇ m. In this embodiment, the thickness of the buffer layer 3 is approximately 0.5 ⁇ m.
- the semi-insulating nitride layer 4 is provided to suppress leakage current.
- the semi-insulating nitride layer 4 is composed of an impurity-doped GaN layer and has a thickness of about 1 ⁇ m to 10 ⁇ m. In this embodiment, the thickness of the semi-insulating nitride layer 4 is of the order of 2 ⁇ m.
- the impurity is C (carbon), for example, and is doped so that the difference (Na ⁇ Nd) between the acceptor concentration Na and the donor concentration Nd is approximately 1 ⁇ 10 17 cm ⁇ 3 .
- the first nitride semiconductor layer 5 constitutes an electron transit layer.
- the first nitride semiconductor layer 5 is an n-type GaN layer doped with donor-type impurities, and has a thickness of, for example, about 0.05 ⁇ m to 1 ⁇ m. In this embodiment, the thickness of the first nitride semiconductor layer 5 is approximately 0.2 ⁇ m.
- the first nitride semiconductor layer 5 may be composed of an undoped GaN layer.
- the lower surface on the semi-insulating nitride layer 4 side is called the back surface, and the upper surface on the opposite side is called the front surface.
- a laterally long rectangular center portion 5A on the surface of the first nitride semiconductor layer 5 in plan view protrudes from a rectangular annular peripheral portion 5B in plan view on the surface. Thereby, a step is formed between the central portion 5A and the peripheral edge portion 5B of the surface of the first nitride semiconductor layer 5 . Therefore, the surface (upper surface) of the first nitride semiconductor layer 5 is composed of a central portion 5A of a high step portion, a peripheral edge portion 5B of a low step portion, and a connecting portion 5C connecting them.
- the second nitride semiconductor layer 6 is formed on the central portion 5A of the surface of the first nitride semiconductor layer 5 .
- the second nitride semiconductor layer 6 constitutes an electron supply layer.
- the second nitride semiconductor layer 6 is made of a nitride semiconductor having a bandgap larger than that of the first nitride semiconductor layer 5 .
- the second nitride semiconductor layer 6 is made of a nitride semiconductor having a higher Al composition than the first nitride semiconductor layer 5 . In nitride semiconductors, the higher the Al composition, the larger the bad gap.
- the first nitride semiconductor layer 5 (electron transit layer) and the second nitride semiconductor layer 6 (electron supply layer) are made of nitride semiconductors having different band gaps (Al compositions). has lattice mismatch. Then, the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6 are polarized by spontaneous polarization of the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6 and piezoelectric polarization caused by lattice mismatch therebetween. The energy level of the conduction band of the first nitride semiconductor layer 5 at the interface with is lower than the Fermi level.
- a two-dimensional electron gas (2DEG) 19 spreads in the first nitride semiconductor layer 5 at a position close to the interface with the second nitride semiconductor layer 6 (for example, a distance of several angstroms from the interface).
- a region where the two-dimensional electron gas 19 can be formed is called an active region 101, and a region where the two-dimensional electron gas (2DEG) 19 is not formed is called an inactive region 102.
- the region where the central portion 5A of the surface of the first nitride semiconductor layer 5 exists in plan view is the active region 101, and the peripheral portion 5B of the surface of the first nitride semiconductor layer 5 exists in plan view.
- the area to be covered is the inactive area 102 .
- the insulating film 7 is formed over substantially the entire surface of the second nitride semiconductor layer 6 .
- the insulating film 7 is made of SiN in this embodiment.
- the thickness of the insulating film 7 is, for example, about 10 nm to 200 nm. In this embodiment, the thickness of the insulating film 7 is approximately 100 nm.
- the insulating film 7 may be composed of SiN, SiO 2 , SiN, SiON, Al 2 O 3 , AlN, AlON, HfO, HfN, HfON, HfSiON, AlON, or the like.
- the source electrode 10 covers the source contact hole 8 and the peripheral portion of the source contact hole 8 on the surface of the insulating film 7 . A portion of the source electrode 10 enters the source contact hole 8 and contacts the surface of the second nitride semiconductor layer 6 within the source contact hole 8 .
- the drain electrode 11 covers the drain contact hole 9 and the periphery of the drain contact hole 9 on the surface of the insulating film 7 . A portion of the drain electrode 11 enters the drain contact hole 9 and contacts the surface of the second nitride semiconductor layer 6 within the drain contact hole 9 .
- the source electrode 10 and the drain electrode 11 are composed of, for example, a Ti/Al laminated film in which a Ti film and an Al film are laminated in that order from the lower layer.
- the thickness of the Ti film on the lower layer side is, for example, about 20 nm
- the thickness of the Al film on the upper layer side is, for example, about 300 nm.
- the source electrode 10 and the drain electrode 11 need only be made of a material that can make ohmic contact with the second nitride semiconductor layer 6 (AlGaN layer).
- the source electrode 10 and the drain electrode 11 may be composed of a Ti/Al/Ni/Au laminated film in which a Ti film, an Al film, a Ni film and an Au film are laminated in that order from the bottom.
- the gate electrode 13 covers the gate contact hole 12 and the peripheral portion of the gate contact hole 12 on the surface of the insulating film 7 . A portion of gate electrode 13 enters gate contact hole 12 and contacts the surface of second nitride semiconductor layer 6 within gate contact hole 12 .
- the gate electrode 13 is composed of, for example, a Ni/Au laminated film in which a Ni film and an Au film are laminated in that order from the lower layer.
- the thickness of the Ni film on the lower layer side is, for example, about 10 nm
- the thickness of the Au film on the upper layer side is, for example, about 600 nm.
- the gate electrode 13 may be made of a material capable of forming a Schottky barrier against the second nitride semiconductor layer 6 (AlGaN layer).
- the substrate 2 in the inactive region 102, is formed with a plurality of trenches 14 dug down from the second main surface 2b toward the first main surface 2a.
- the trench 14 is dug halfway through the thickness of the substrate 2 from the second major surface 2b toward the first major surface 2a.
- the cross-sectional shape of trench 14 is elliptical in this embodiment.
- the plurality of trenches 14 are arranged in a grid pattern in plan view.
- the plurality of trenches 14 are arranged in a matrix in plan view.
- the plurality of trenches 14 may be arranged in a zigzag pattern in plan view.
- the shape of the cross section of the trench 14 is arbitrary, and may be circular or polygonal (triangular, quadrangular, hexagonal, etc.). Moreover, the size of the cross section of the trench 14 (the area of the cross section) and the interval between two adjacent trenches 14 can be set arbitrarily.
- the depth of the trench 14 is preferably 1/2 or more of the thickness of the substrate 2, more preferably 2/3 or more of the thickness of the substrate 2, and even more preferably 3/4 or more of the thickness of the substrate 2.
- the total volume (total volume) of the plurality of trenches 14 existing in the inactive region 102 is preferably 1 ⁇ 3 or more of the volume of the substrate 2 in the inactive region 102 .
- a barrier metal film 16 is formed over the entire inner surface (side and bottom surfaces) of each trench 14 and the entire second main surface 2 b of the substrate 2 .
- the barrier metal film 16 is made of TiN, for example.
- a heat dissipation metal 17 is embedded in each trench 14 while being surrounded by a barrier metal film 16 .
- the heat dissipation metal 17 is made of metal with high thermal conductivity such as gold (Au) or copper (Cu). In this embodiment, the heat dissipation metal 17 is made of gold (Au).
- the heat dissipation metal 17 includes an embedded portion 17A inside the trench 14 and an extraction portion 17B extracted along the second main surface 2b of the substrate 2 from the opening end of the trench 14 outside the trench 14 .
- the lead portions 17B are uniformly led out from each trench 14 and cover the entire second main surface 2b of the substrate 2 .
- the rear surface of the heat dissipation metal 17 (the rear surface of the lead portion 22B) is formed flat throughout.
- the barrier metal film 16 in the trench 14 and the buried portion 17A surrounded by the barrier metal film 16 constitute the buried metal 15A in the present disclosure.
- the barrier metal film 16 formed on the second main surface 2b of the substrate 2 and the lead portion 17B constitute the lead metal 15B in the present disclosure.
- a heat dissipation structure 15 is composed of all the embedded metals 15A in the trenches 14 and the extraction metals 15B. In other words, the barrier metal film 16 and the heat dissipation metal 17 constitute the heat dissipation structure 15 .
- the heat dissipation metal 17 does not have to be completely embedded in the trench 14 . In that case, the back surface of the heat dissipation metal 17 does not have to be flat. Moreover, the barrier metal film 16 and the heat dissipation metal 17 may not be formed on the second main surface 2 b of the substrate 2 .
- a second nitride semiconductor layer 6 (electron supply layer) having a different bandgap (Al composition) is formed on a first nitride semiconductor layer 5 (electron transit layer) to form a heterojunction. It is As a result, a two-dimensional electron gas 19 is formed in the first nitride semiconductor layer 5 near the interface between the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6, and the two-dimensional electron gas 19 is used as a channel. A utilized HEMT is formed.
- this HEMT is a normally-on type.
- a control voltage is applied to the gate electrode 13 such that the potential of the gate electrode 13 becomes negative with respect to the source electrode 10
- the two-dimensional electron gas 19 is shut off and the HEMT is turned off.
- 4A to 4I are cross-sectional views for explaining an example of the manufacturing process of the nitride semiconductor device 1 described above, showing cross-sectional structures at a plurality of stages in the manufacturing process.
- a buffer layer 3 and a semi-insulating nitride layer 4 are epitaxially grown in order on the first main surface 2a of the substrate 2 by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). Further, a first nitride semiconductor layer (electron transit layer) 5 and a second nitride semiconductor layer (electron supply layer) 6 are epitaxially grown in this order on the semi-insulating nitride layer 4 by MOCVD.
- MOCVD Metal Organic Chemical Vapor Deposition
- a nitride epitaxial layer 20 composed of the buffer layer 3 , the semi-insulating nitride layer 4 , the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6 is formed on the first main surface 2 a of the substrate 2 . be done.
- a resist film (not shown) is formed on the second nitride semiconductor layer 6 so as to cover a region immediately above the planned formation region of the central portion 5A of the surface of the first nitride semiconductor layer 5 .
- a resist film By dry etching using this resist film as a mask, as shown in FIG. 4B, the peripheral portion of the second nitride semiconductor layer 6 is removed, and the peripheral portion of the first nitride semiconductor layer 5 is removed halfway through the thickness. be done.
- the surface of the first nitride semiconductor layer 5 is composed of a high-level central portion 5A, a low-level peripheral edge portion 5B, and a connecting portion 5C connecting them.
- an etching gas for example, a chlorine-based gas such as Cl 2 or BCl 3 is used.
- an inactive region 102 is formed in which the two-dimensional electron gas 19 is not formed.
- a region corresponding to the central portion 5A of the surface of the first nitride semiconductor layer 5 in plan view is the active region 101, and a region corresponding to the peripheral portion 5B of the surface of the first nitride semiconductor layer 5 in plan view is inactive. area 102;
- This etching may be performed until the bottom of the etching reaches the upper surface of the semi-insulating nitride layer 4, or may be performed until the thickness of the semi-insulating nitride layer 4 reaches halfway. This etching may be performed until the etching bottom surface reaches the upper surface of the buffer layer 3 or may be performed until the thickness of the buffer layer 3 reaches halfway.
- the peripheral edge portion 5B and the connecting portion 5C and the second contact portion 5C on the surface of the first nitride semiconductor layer 5 are subjected to a plasma CVD method, a low pressure CVD (LPCVD) method, an MOCVD method, a sputtering method, or the like.
- An insulating material film 31 which is a material film for insulating film 7 , is formed to cover the exposed surface of nitride semiconductor layer 6 .
- a resist film (not shown) is formed on the insulating material film 31 except for the regions where the source contact holes 8 and the drain contact holes 9 are to be formed.
- a resist film By dry etching the insulating material film 31 through the resist film, the source contact hole 8 and the drain contact hole 9 are formed in the insulating material film 31 as shown in FIG. 4D.
- Source contact hole 8 and drain contact hole 9 penetrate insulating material film 31 and reach second nitride semiconductor layer 6 .
- the widths of the source contact hole 8 and the drain contact hole 9 are approximately 3 to 5 ⁇ m.
- CF 4 gas for example, is used as the etching gas. After that, the resist film is removed.
- an electrode film which is a material film for the source electrode 10 and the drain electrode 11, is formed on the insulating material film 31 by, for example, a vapor deposition method, a sputtering method, or the like. Thereafter, a resist film is formed to cover the source electrode formation scheduled region and the drain electrode formation scheduled region on the surface of the electrode film. Using this resist film as a mask, the electrode film is selectively etched to obtain the source electrode 10 and the drain electrode 11 as shown in FIG. 4E. After that, the resist film is removed.
- a plurality of trenches 14 extending halfway through the thickness of the substrate 2 from the second main surface 2b toward the first main surface 2a are formed in the inactive region 102 by photolithography and etching. It is formed on the substrate 2 .
- a Bosch process may be used for this etching.
- the plurality of trenches 14 are arranged in a matrix in plan view.
- a barrier metal film 16 made of, for example, a TiN layer is formed on the inner surfaces (side and bottom surfaces) of the trenches 14 and the second main surface 2b of the substrate 2 by, for example, sputtering.
- the heat dissipation structure 15 is formed of the embedded metal 15A embedded in each trench 14 and the lead metal 15B formed on the second main surface 2b.
- a resist film (not shown) is formed on the insulating material film 31, the source electrode 10 and the drain electrode 11 except for the region where the gate contact hole 12 is to be formed.
- a gate contact hole 12 is formed in the insulating material film 31 as shown in FIG. 4I.
- the insulating material film 31 is patterned and the insulating film 7 is obtained.
- Gate contact hole 12 penetrates insulating film 7 and reaches second nitride semiconductor layer 6 .
- CF 4 gas for example, is used as the etching gas.
- the gate electrode 13 is formed to obtain the nitride semiconductor device 1 as shown in FIGS. 1 to 3.
- FIG. The gate electrode 13 is made of, for example, a Ni/Au laminated film in which a Ni film and an Au film are laminated in that order from the bottom.
- FIG. 5 is a plan view for explaining the configuration of the nitride semiconductor device according to the second embodiment of the present disclosure.
- FIG. 6 is a cross-sectional view along line VI-VI of FIG.
- FIG. 7 is a cross-sectional view along line VII-VII of FIG.
- FIGS. 5, 6 and 7 the same reference numerals as in FIGS. 1, 2 and 3 are used for the parts corresponding to the parts in FIGS. 1, 2 and 3 described above.
- trenches 14 are formed in the substrate 2 not only in the inactive region 102 but also in the active region 101, which is different from that of the nitride semiconductor device 1A according to the first embodiment. is different from
- a plurality of trenches 14 are formed in the active region 101 and the inactive region 102 .
- the plurality of trenches 14 are arranged in a matrix in plan view.
- the plurality of trenches 14 may be arranged in a zigzag pattern in plan view.
- a barrier metal film 16 is formed on the inner surfaces of the plurality of trenches 14 .
- a heat dissipation metal 17 is embedded in these trenches 14 while being surrounded by a barrier metal film 16 .
- the barrier metal film 16 in the trench 14 and the buried portion 17A surrounded by the barrier metal film 16 constitute the buried metal 15A in the present disclosure.
- the barrier metal film 16 formed on the second main surface 2b of the substrate 2 and the lead portion 17B constitute the lead metal 15B in the present disclosure.
- a heat dissipation structure 15 is composed of all the embedded metals 15A in the trenches 14 and the extraction metals 15B. In other words, the heat dissipation structure 15 is formed by the barrier metal film 51 and the heat dissipation metal 17 formed in the active region 101 and the inactive region 102 .
- the embedded metal 15A since the embedded metal 15A is provided, heat dissipation can be improved. Moreover, since it has the lead metal 15B, heat dissipation can be further improved.
- a plurality of trenches 14 are formed not only in the inactive region 102 but also in the active region 101, and the heat dissipation metal 17 is embedded in the plurality of trenches 14 via the barrier metal film 16. Therefore, it is possible to further improve heat dissipation compared to the first embodiment.
- FIGS. 8A to 8D are cross-sectional views for explaining an example of the manufacturing process of the nitride semiconductor device 1A described above, showing cross-sectional structures at a plurality of stages in the manufacturing process.
- FIG. 8A When the process shown in FIG. 4E is completed, as shown in FIG. 8A, photolithography and etching are performed in both the active region 101 and the inactive region 102 from the second major surface 2b toward the first major surface 2a.
- a plurality of trenches 14 extending halfway through the thickness of the substrate 2 are formed in the substrate 2 .
- a Bosch process may be used for this etching.
- the plurality of trenches 14 are arranged in a matrix in plan view.
- a barrier metal film 16 made of, for example, a TiN layer is formed on the inner surfaces (side and bottom surfaces) of the trenches 14 and the second main surface 2b of the substrate 2 by, for example, sputtering.
- the heat dissipation structure 15 composed of the barrier metal film 16 and the heat dissipation metal 17 is obtained.
- the heat dissipation structure 15 is obtained which is composed of the embedded metal 15A embedded in each trench 14 and the lead metal 15B formed on the second main surface 2b.
- a resist film (not shown) is formed on the insulating material film 31, the source electrode 10 and the drain electrode 11 except for the region where the gate contact hole 12 is to be formed.
- a gate contact hole 12 is formed in the insulating material film 31 as shown in FIG. 8D.
- the insulating material film 31 is patterned and the insulating film 7 is obtained.
- Gate contact hole 12 penetrates insulating film 7 and reaches second nitride semiconductor layer 6 .
- CF 4 gas for example, is used as the etching gas.
- the gate electrode 13 is formed to obtain the nitride semiconductor device 1A as shown in FIGS.
- the gate electrode 13 is made of, for example, a Ni/Au laminated film in which a Ni film and an Au film are laminated in that order from the bottom.
- FIG. 9 is a plan view for explaining the configuration of the nitride semiconductor device according to the third embodiment of the present disclosure.
- 10 is a cross-sectional view taken along line XX of FIG. 9.
- FIG. 11 is a cross-sectional view taken along line XI-XI of FIG. 10.
- FIG. 10 is a cross-sectional view taken along line XX of FIG. 9.
- FIGS. 9, 10 and 11 the same reference numerals as in FIGS. 1, 2 and 3 are used for the parts corresponding to the parts in FIGS. 1, 2 and 3 described above.
- the horizontal direction of the paper surface of FIG. 9 may be referred to as the horizontal direction
- the vertical direction of the paper surface of FIG. 9 may be referred to as the vertical direction
- the structure of the source electrode 10 and the drain electrode 11 and the fact that the trenches 14 are formed in the substrate 2 not only in the inactive region 102 but also in the active region 101 are It differs from the nitride semiconductor device 1 according to the first embodiment.
- the nitride epitaxial layer 20 and the insulating film 7 , the insulating film 7 and the nitride epitaxial layer 20 are continuously formed from the surface of the insulating film 7 on the opposite side of the source contact hole 8 from the gate contact hole 12 .
- a back contact hole 18 is formed that penetrates through the substrate 2 and extends halfway through the thickness of the substrate 2 .
- the source electrode 10 includes a main electrode portion 10A and an extension portion 10B.
- the main electrode portion 10A covers the source contact hole 8 and the peripheral portion of the source contact hole 8 on the surface of the insulating film 7 .
- a portion of the main electrode portion 10A enters the source contact hole 8 and contacts the surface of the second nitride semiconductor layer 6 within the source contact hole 8 .
- the extension part 10B covers the back contact hole 18 and the peripheral edge of the back contact hole 18 on the surface of the insulating film 7 .
- the side edge of the extension portion 10B on the side of the main electrode portion 10A and the side edge of the main electrode portion 10A on the side of the extension portion 10B are connected.
- a part of the extension 10B enters the back contact hole 18 and contacts the substrate 2 inside the back contact hole 18 .
- the extension 10B is an example of "a conductive member that electrically connects the source electrode and the embedded metal" in the present disclosure.
- the source electrode 10 is composed of a barrier metal film 41 and an electrode metal 42 formed on the barrier metal film 41 .
- the barrier metal film 41 is formed on the inner surface (side and bottom surfaces) of the source contact hole 8, the peripheral edge of the source contact hole 8 on the surface of the insulating film 7, the inner surface of the back contact hole 18, and the peripheral edge of the back contact hole 18 on the surface of the insulating film 7. covering the The barrier metal film 41 is made of, for example, a TiN film.
- the electrode metal 42 is made of Au, for example.
- the electrode metal 42 may be made of Cu.
- the drain electrode 11 covers the drain contact hole 9 and the periphery of the drain contact hole 9 on the surface of the insulating film 7 . A portion of the drain electrode 11 enters the drain contact hole 9 and contacts the surface of the second nitride semiconductor layer 6 within the drain contact hole 9 .
- the drain electrode 11 is composed of a barrier metal film 43 covering the drain contact hole 9 and the peripheral portion of the drain contact hole 9 on the surface of the insulating film 7 and an electrode metal 44 formed on the barrier metal film 43 .
- the barrier metal film 51 is made of, for example, a TiN film.
- the electrode metal 44 is made of Au, for example.
- the electrode metal 44 may be made of Cu.
- a plurality of trenches 14 are formed in the substrate 2 in the active region 101 and the inactive region 102 .
- the multiple trenches 14 include contact trenches 14A reaching the barrier metal film 41 formed on the bottom surface of the back contact hole 18 .
- a plurality of trenches 14 other than the contact trenches 14A are arranged in a matrix in plan view. These multiple trenches 14 may be arranged in a zigzag pattern in plan view.
- a barrier metal film 16 is formed on the inner surfaces of the plurality of trenches 14 including the contact trenches 14A.
- a heat dissipation metal 17 is embedded in these trenches 14 while being surrounded by a barrier metal film 16 .
- the heat dissipation metal 17 is made of metal with high thermal conductivity and electrical conductivity, such as gold (Au) and copper (Cu). In this embodiment, the heat dissipation metal 17 is made of gold (Au).
- the heat dissipation metal 17 includes an embedded portion 17A inside the trench 14 and an extraction portion 17B extracted along the second main surface 2b of the substrate 2 from the opening end of the trench 14 outside the trench 14 .
- the lead portions 17B are uniformly led out from each trench 14 and cover the entire second main surface 2b of the substrate 2 .
- the rear surface of the heat dissipation metal 17 (the rear surface of the lead portion 22B) is formed flat throughout.
- the barrier metal film 16 in the trench 14 (including the contact trench 14A) and the buried portion 17A surrounded by the barrier metal film 16 constitute the buried metal 15A in the present disclosure.
- the barrier metal film 16 formed on the second main surface 2b of the substrate 2 and the lead portion 17B constitute the lead metal 15B in the present disclosure.
- a heat dissipation structure 15 is composed of all the embedded metals 15A in the trenches 14 and the extraction metals 15B. In other words, the barrier metal film 16 and the heat dissipation metal 17 formed in the active region 101 and the inactive region 102 constitute the heat dissipation structure 15 .
- the embedded metal 15A since the embedded metal 15A is provided, heat dissipation can be improved. Moreover, since it has the lead metal 15B, heat dissipation can be further improved.
- a plurality of trenches 14 are formed not only in the inactive region 102 but also in the active region 101, and the heat dissipation metal 17 is embedded in the plurality of trenches 14 via the barrier metal film 16. Therefore, it is possible to further improve heat dissipation compared to the first embodiment.
- the main electrode portion 10A of the source electrode 10 is electrically connected to the lead metal 15B via the extension portion 10B and the embedded metal 15A in the contact trench 14A. Therefore, the lead metal 15B can be used as the back electrode of the source electrode 10.
- 12A to 12H are cross-sectional views for explaining an example of the manufacturing process of the nitride semiconductor device 1B described above, showing cross-sectional structures at a plurality of stages in the manufacturing process.
- a resist film (not shown) is formed on regions other than regions where the back contact hole 18, the source contact hole 8 and the drain contact hole 9 are to be formed.
- a resist film By dry-etching the insulating material film 31 through the resist film, a portion 18A of the back contact hole 18, the source contact hole 8 and the drain contact hole 9 are formed in the insulating material film 31 as shown in FIG. 12A. be.
- CF 4 gas for example, is used as the etching gas. After that, the resist film is removed.
- a resist film (not shown) is formed on the insulating material film 31 except for the region where the back contact hole 18 is to be formed.
- Part of nitride epitaxial layer 20 and substrate 2 is etched through this resist film.
- a hole 18B penetrating the nitride epitaxial layer 20 and reaching the inside of the substrate 2, that is, the remaining portion 18B of the back contact hole 18 is formed.
- a back contact hole 18 consisting of a portion 18A and a remaining portion 18B is obtained.
- the resist film is removed.
- the material of the barrier metal films 41 and 43 is applied to the surface of the insulating material film 31, the inner surfaces (side and bottom surfaces) of the back contact holes 18, the inner surfaces of the source contact holes 8, and the inner surfaces of the drain contact holes 9 by, for example, a sputtering method.
- a barrier metal material film (for example, a TiN film), which is a film, is formed. By patterning the barrier metal material film, barrier metal films 41 and 43 are formed as shown in FIG. 12C.
- Source electrode 10 composed of the barrier metal film 41 and the electrode metal 42 and the drain electrode 11 composed of the barrier metal film 43 and the electrode metal 45 are obtained.
- Source electrode 10 includes main electrode portion 10A and extension portion 10B.
- both the active region 101 and the inactive region 102 are formed in the middle of the thickness of the substrate 2 from the second main surface 2b toward the first main surface 2a.
- a plurality of trenches 14 extending to the substrate 2 are formed.
- the plurality of trenches 14 include contact trenches 14 ⁇ /b>A extending from the second main surface 2 b of the substrate 2 to the bottom surface of the barrier metal film 41 formed on the bottom surface of the back contact hole 18 .
- a Bosch process may be used as the etching.
- the plurality of trenches 14 other than the contact trenches 14A are arranged in a matrix in plan view.
- a barrier metal film 16 made of, for example, a TiN layer is formed on the inner surfaces (side and bottom surfaces) of the trenches 14 and the second main surface 2b of the substrate 2 by, for example, sputtering.
- the barrier metal film 16 is deposited on the barrier metal film 16 by, for example, plating.
- the trench 14 is filled with gold (Au), which is the material of the heat dissipation metal 17 .
- Au is the material of the heat dissipation metal 17 .
- the heat dissipation metal 17 including the buried portion 17A and the lead portion 17B is formed.
- the heat dissipation structure 15 composed of the barrier metal film 16 and the heat dissipation metal 17 is obtained.
- a heat dissipation structure 15 consisting of embedded metal 15A embedded in each trench 14 and lead metal 15B formed on the second main surface 2b is obtained. Also, the source electrode 10 is electrically connected to the lead metal 15B via the extension 10B and the buried metal 15A in the contact trench 14A.
- a resist film (not shown) is formed on the insulating material film 31, the source electrode 10 and the drain electrode 11 except for the region where the gate contact hole 12 is to be formed.
- a gate contact hole 12 is formed in the insulating material film 31 as shown in FIG. 12H.
- the insulating material film 31 is patterned and the insulating film 7 is obtained.
- Gate contact hole 12 penetrates insulating film 7 and reaches second nitride semiconductor layer 6 .
- CF 4 gas for example, is used as the etching gas.
- the gate electrode 13 is formed to obtain the nitride semiconductor device 1B as shown in FIGS. 9 to 11.
- FIG. The gate electrode 13 is made of, for example, a Ni/Au laminated film in which a Ni film and an Au film are laminated in that order from the bottom.
- FIGS. 13, 14 and 15 are cross-sectional views showing modifications of the first, second and third embodiments, respectively, and are cross-sectional views corresponding to the cross-sectional planes of FIGS. 2, 6 and 10.
- the trench 14 extends halfway through the thickness of the substrate 2 from the second main surface 2b toward the first main surface 2a. However, as shown in FIGS. 13, 14 and 15, the trench 14 penetrates the substrate 2 from the second main surface 2b toward the first main surface 2a and extends into the buffer layer 3 (nitride epitaxial layer 20). ).
- the semi-insulating nitride layer 4 is formed on the buffer layer 3 in the first to third embodiments described above, the semi-insulating nitride layer 4 may not be formed.
- the first nitride semiconductor layer (electron transit layer) 5 is made of a GaN layer
- the second nitride semiconductor layer (electron supply layer) 6 is made of an AlGaN layer.
- the first nitride semiconductor layer 5 and the second nitride semiconductor layer 6 have different bandgaps (for example, Al composition), and other combinations are also possible.
- the combination of the first nitride semiconductor layer 5/second nitride semiconductor layer 6 can be GaN/AlN, AlGaN/AlN, or the like.
- Reference Signs List 1 1A, 1B nitride semiconductor device 2 substrate 3 buffer layer 4 semi-insulating nitride layer 5 first nitride semiconductor layer 6 second nitride semiconductor layer 7 insulating film 8 source contact hole 9 drain contact hole 10 source electrode 10A Main electrode portion 10B Extension portion 11 Drain electrode 12 Gate contact hole 13 Gate electrode 14 Trench 14A Contact trench 15 Heat dissipation structure 15A Embedded metal 15B Lead metal 16 Barrier metal film 17 Heat dissipation metal 17A Embedded portion 17B Lead portion 18 Back contact hole 19 Two Dimensional electron gas 20 nitride epitaxial layer 31 insulating material film 41, 43 barrier metal film 42, 44 electrode metal
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Abstract
Description
本開示の一実施形態は、第1主面とその反対側の第2主面とを有する基板と、前記第1主面上に形成された窒化物エピタキシャル層とを含む窒化物半導体装置であって、前記窒化物半導体装置は、平面視において、前記窒化物エピタキシャル層内に二次元電子ガスが形成され得る活性領域と、前記窒化物エピタキシャル層内に二次元電子ガスが形成されない不活性領域とを有しており、前記活性領域および前記不活性領域のうちの少なくとも前記不活性領域において、前記基板の第2主面から前記基板の第1主面に向かって掘り下げられたトレンチと、前記トレンチ内に形成された埋め込みメタルとを含む、窒化物半導体装置を提供する。
以下では、本開示の実施形態を、添付図面を参照して詳細に説明する。
2 基板
3 バッファ層
4 半絶縁性窒化物層
5 第1窒化物半導体層
6 第2窒化物半導体層
7 絶縁膜
8 ソースコンタクトホール
9 ドレインコンタクトホール
10 ソース電
10A 主電極部
10B 延長部
11 ドレイン電極
12 ゲートコンタクトホール
13 ゲート電極
14 トレンチ
14A コンタクト用トレンチ
15 放熱構造
15A 埋め込みメタル
15B 引出しメタル
16 バリアメタル膜
17 放熱メタル
17A 埋め込み部
17B 引出し部
18 バックコンタクトホール
19 二次元電子ガス
20 窒化物エピタキシャル層
31 絶縁材料膜
41,43 バリアメタル膜
42,44 電極メタル
Claims (15)
- 第1主面とその反対側の第2主面とを有する基板と、前記第1主面上に形成された窒化物エピタキシャル層とを含む窒化物半導体装置であって、
前記窒化物半導体装置は、平面視において、前記窒化物エピタキシャル層内に二次元電子ガスが形成され得る活性領域と、前記窒化物エピタキシャル層内に二次元電子ガスが形成されない不活性領域とを有しており、
前記活性領域および前記不活性領域のうちの少なくとも前記不活性領域において、前記基板の第2主面から前記基板の第1主面に向かって掘り下げられたトレンチと、
前記トレンチ内に形成された埋め込みメタルとを含む、窒化物半導体装置。 - 前記トレンチが、前記活性領域および前記不活性領域のうちの前記不活性領域のみに形成されている、請求項1に記載の窒化物半導体装置。
- 前記トレンチが、前記活性領域および前記不活性領域の両方に形成されている、請求項1に記載の窒化物半導体装置。
- 前記不活性領域内に存在するトレンチの総体積が、前記不活性領域内の前記基板の体積の1/3以上である、請求項1~3のいずれか一項に記載の窒化物半導体装置。
- 前記第2主面上に形成され、前記埋め込みメタルと熱的に接続された引出しメタルを含む、請求項1~4のいずれか一項に記載の窒化物半導体装置。
- 前記トレンチが、前記第2主面から前記第1主面に向かって、前記基板の途中まで掘り下げられている、請求項1~5のいずれか一項に記載の窒化物半導体装置。
- 前記トレンチが、前記基板を貫通して、前記窒化物エピタキシャル層に達している、請求項1~5のいずれか一項に記載の窒化物半導体装置。
- 前記窒化物エピタキシャル層上に配置された、ソース電極、ドレイン電極およびゲート電極と、
前記窒化物エピタキシャル層を貫通し、前記ソース電極と前記埋め込みメタルとを電気的に接続するコンタクトメタルと含む、請求項1~7のいずれか一項に記載の窒化物半導体装置。 - 前記窒化物エピタキシャル層は、
電子走行層を構成する第1窒化物半導体層と、
前記第1窒化物半導体層上に形成され、電子供給層を構成し、前記第1窒化物半導体層よりもバンドギャップの高い第2窒化物半導体層とを含む、請求項1~8のいずれか一項に記載の窒化物半導体装置。 - 前記基板と前記第1窒化物半導体層との間に配置され、アクセプタ濃度がドナー濃度よりも高い半絶縁性窒化物層を含む、請求項9に記載の窒化物半導体装置。
- 前記基板と前記半絶縁性窒化物層との間に配置され、窒化物半導体からなるバッファ層を含む、請求項10に記載の窒化物半導体装置。
- 前記第1窒化物半導体層がGaN層からなり、前記第2窒化物半導体層がAlGaN層からなる、請求項9~11のいずれか一項に記載の窒化物半導体装置。
- 前記第1窒化物半導体層がGaN層からなり、前記第2窒化物半導体層がAlGaN層からなり、前記半絶縁性窒化物層が炭素を含むGaN層からなる、請求項10に記載の窒化物半導体装置。
- 前記第1窒化物半導体層がGaN層からなり、前記第2窒化物半導体層がAlGaN層からなり、前記半絶縁性窒化物層が炭素を含むGaN層からなり、前記バッファ層が、前記第1主面上に形成されたAlN層と前記AlN層上に積層されAlGaN層との積層膜からなる、請求項11に記載の窒化物半導体装置。
- 前記第1窒化物半導体層がGaN層からなり、前記第2窒化物半導体層がAlGaN層からなり、前記半絶縁性窒化物層が炭素を含むGaN層からなり、前記バッファ層が、AlN層またはAlGaN層からなる、請求項11に記載の窒化物半導体装置。
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