WO2021147054A1 - 一种集成电路 - Google Patents

一种集成电路 Download PDF

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Publication number
WO2021147054A1
WO2021147054A1 PCT/CN2020/073930 CN2020073930W WO2021147054A1 WO 2021147054 A1 WO2021147054 A1 WO 2021147054A1 CN 2020073930 W CN2020073930 W CN 2020073930W WO 2021147054 A1 WO2021147054 A1 WO 2021147054A1
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WIPO (PCT)
Prior art keywords
coil
phase differential
port
positive
negative
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PCT/CN2020/073930
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English (en)
French (fr)
Inventor
胡俊伟
彭嵘
Original Assignee
华为技术有限公司
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Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202080094396.4A priority Critical patent/CN114982206B/zh
Priority to PCT/CN2020/073930 priority patent/WO2021147054A1/zh
Publication of WO2021147054A1 publication Critical patent/WO2021147054A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems

Definitions

  • This application relates to the field of electronic technology, in particular to an integrated circuit.
  • Microwave usually refers to electromagnetic waves with a wavelength of 1 m to 1 mm and a corresponding frequency range of 300 MHz to 300 GHz.
  • Microwave communication refers to a wireless communication method that uses microwaves as a carrier to carry information and transmit it through space waves. In microwave communication, it is usually necessary to divide a signal into multiple signals.
  • a directional coupler is a microwave branch circuit with branching function commonly used in microwave communication. As a typical microwave branch circuit in the directional coupler, the quadrature coupler is widely used in microwave communication.
  • the quadrature coupler includes a through path and a coupling path. The input signal can be divided into a through path signal and a coupled path signal through the quadrature coupler. The power of the two signals is equal and the phase difference is 90°.
  • the quadrature coupler includes two microstrip transmission lines.
  • the two microstrip transmission lines are a through-path transmission line and a coupled-path transmission line.
  • IN represents a straight-through input port
  • OUT represents a straight-through output port
  • COP represents a coupled port
  • ISO represents an isolated port.
  • the orthogonal coupler based on the principle of the microstrip transmission line is a single-port orthogonal coupler.
  • Two microstrip transmission lines are routed on a shared ground plane. In an integrated circuit, two microstrip transmission lines and a shared ground plane need to be implemented at the same time.
  • the quadrature coupler in this way also realizes a specific port impedance.
  • the line width of the microstrip transmission line and the distance between the microstrip transmission line and the ground plane both There are certain restrictions, so the occupied integrated circuit area is relatively large.
  • This application provides an integrated circuit for reducing the area in the integrated circuit occupied by the quadrature coupler.
  • an integrated circuit is provided.
  • the integrated circuit is provided with a quadrature coupler; the quadrature coupler is provided with a positive-phase differential input port, a negative-phase differential input port, a positive-phase differential through port, and a negative-phase differential through port.
  • the mutual coupling of the first coil and the second coil can be used as the direct path of the orthogonal coupler
  • the mutual coupling of the third coil and the fourth coil can be used as the coupling path of the orthogonal coupler
  • the first coil and the second coil The mutual coupling of the second coil, the third coil and the fourth coil can realize the coupling of the straight path and the coupling path, so that the design of an eight-port differential quadrature coupler is realized by the four coils coupled to each other.
  • the first coil and the second coil, the third coil and the fourth coil are respectively implemented as two sets of two-wire transmission lines, without the need to set a ground plane, which eliminates the limitation of the ground plane on the integrated circuit, thereby reducing the orthogonal coupling The area of the device in the integrated circuit.
  • the first coil and the second coil are nested with each other and have the same number of turns.
  • the performance of the two-wire transmission line composed of the first coil and the second coil can be optimized.
  • the coupling gap between the first coil and the second coil is kept constant. In the foregoing possible implementation manners, it can be ensured that the electrical coupling amount at any position when the first coil and the second coil are coupled to each other is the same, thereby ensuring the continuity of the port impedance.
  • the line width of the third coil and the fourth coil are the same. In the foregoing possible implementation manners, the coupling performance of the third coil and the fourth coil can be improved.
  • the first coil and the second coil respectively have a via hole, and the first coil and the second coil are coupled to each other through the via hole on the same metal layer.
  • the area of the integrated circuit occupied when the first coil and the second coil are wired can be reduced.
  • the third coil and the fourth coil respectively have a via hole, and the third coil and the fourth coil are coupled to each other through the via hole on the same metal layer.
  • the area of the integrated circuit occupied when the third coil and the fourth coil are wired can be reduced.
  • the number of turns of the first coil, the second coil, the third coil, and the fourth coil is the same.
  • the lengths of the four coils coupled to each other are all equal, which can improve the symmetry of the two sets of two-wire transmission lines, thereby optimizing the coupling performance of the two sets of two-wire transmission lines.
  • the positive-phase differential input port and the positive-phase differential coupling port are coupled through a first capacitor, and the negative-phase differential input port and the negative-phase differential coupling port are coupled through a second capacitor, and the positive-phase differential input port is coupled through a second capacitor.
  • the through port and the positive phase differential isolation port are coupled through a third capacitor, and the negative phase differential through port and the negative phase differential isolation port are coupled through a fourth capacitor.
  • the electric field coupling amount of the orthogonal coupler can be adjusted, so that the orthogonal coupler It has better broadband characteristics, and at the same time has a relatively small phase error and transmission error.
  • the integrated circuit is further provided with four adjustable resistance devices; the four adjustable resistance devices are respectively connected to the positive phase differential coupling port, the negative phase differential coupling port, and the positive phase difference Between the through port, the negative-phase differential through port and the ground terminal.
  • a reflective attenuator RTA is provided.
  • the RTA has the advantages of small phase error and small amplitude error, and at the same time occupies a small integrated circuit area.
  • the integrated circuit is also provided with four adjustable reactance devices; the four adjustable reactance devices are respectively connected to the positive phase differential coupling port, the negative phase differential coupling port, and the positive phase difference Between the through port, the negative-phase differential through port and the ground terminal.
  • a reflective phase shifter RTPS is provided, which has the advantages of small phase error and small amplitude error, and at the same time occupies a small area of the integrated circuit.
  • the integrated circuit is provided with two quadrature couplers, a splitter and a two-way mixer; the two differential output ports of the splitter are respectively connected with The differential input ports of the two mixers are coupled, and the differential output ports of the two mixers are respectively connected to the positive phase differential input port and the negative phase differential input port of the first quadrature coupler, as well as the positive phase differential coupling port and the negative phase.
  • Phase differential coupling port coupling, the second quadrature coupler is used to provide differential local oscillators for the two mixers through the positive phase differential input port and the negative phase differential input port, as well as the positive phase differential coupling port and the negative phase differential coupling port. Signal.
  • an image rejection mixer IRM is provided.
  • the IRM has broadband image rejection characteristics and at the same time occupies a small area of an integrated circuit.
  • a communication device in a second aspect, includes an integrated circuit in which a quadrature coupler is provided; the quadrature coupler is provided with a positive phase differential input port, a negative phase differential input port, and a positive phase differential input port.
  • the quadrature coupler is provided with a first coil and a second coil coupled to each other , The third coil and the fourth coil; the positive phase differential input port and the positive phase differential through port are set at both ends of the first coil; the negative phase differential input port and the negative phase differential through port are set at both ends of the second coil; the positive phase difference The sub-coupling port and the positive-phase differential isolation port are arranged at both ends of the third coil; the negative-phase differential coupling port and the negative-phase differential isolation port are arranged at both ends of the fourth coil.
  • the third coil and the fourth coil are nested with each other and have the same number of turns.
  • the line widths of the third coil and the fourth coil are the same.
  • the coupling gap between the third coil and the fourth coil is kept constant.
  • the third coil and the fourth coil respectively have a via hole, and the third coil and the fourth coil are coupled to each other through the via hole on the same metal layer.
  • the first coil and the second coil are coupled to each other and disposed on the first metal layer, and the third coil and the fourth coil are coupled to each other and disposed on the second metal layer.
  • the number of turns of the first coil, the second coil, the third coil, and the fourth coil is the same.
  • the positive-phase differential input port is located directly below the positive-phase differential coupling port
  • the negative-phase differential input port is located directly below the negative-phase differential coupling port
  • the positive-phase differential through port is located at the positive Directly below the phase differential isolation port
  • the negative phase differential through port is located directly below the negative phase differential isolation port.
  • the positive-phase differential input port and the positive-phase differential coupling port are coupled through a first capacitor, and the negative-phase differential input port and the negative-phase differential coupling port are coupled through a second capacitor, and the positive-phase differential input port is coupled through a second capacitor.
  • the through port and the positive phase differential isolation port are coupled through a third capacitor, and the negative phase differential through port and the negative phase differential isolation port are coupled through a fourth capacitor.
  • the integrated circuit is also provided with four adjustable resistance devices; the four adjustable resistance devices are respectively connected to the positive phase differential coupling port, the negative phase differential coupling port, and the positive phase difference Between the through port, the negative-phase differential through port and the ground terminal.
  • the integrated circuit is also provided with four adjustable reactance devices; the four adjustable reactance devices are respectively connected to the positive phase differential coupling port, the negative phase differential coupling port, and the positive phase difference Between the through port, the negative-phase differential through port and the ground terminal.
  • the integrated circuit is also provided with two amplitude adjustment circuits and a combiner; in the two amplitude adjustment circuits, one of the amplitude adjustment circuits has a differential input port and a positive-phase differential through port Coupled with the negative-phase differential through port, the differential input port of the other amplitude adjustment circuit is coupled with the positive-phase differential coupling port and the negative-phase differential coupling port, the differential output port of the two amplitude adjustment circuits and the two differential input ports of the combiner coupling.
  • the integrated circuit is provided with two quadrature couplers, a splitter and a two-way mixer; the two differential output ports of the splitter are respectively connected with The differential input ports of the two mixers are coupled, and the differential output ports of the two mixers are respectively connected to the positive phase differential input port and the negative phase differential input port of the first quadrature coupler, as well as the positive phase differential coupling port and the negative phase.
  • Phase differential coupling port coupling, the second quadrature coupler is used to provide differential local oscillators for the two mixers through the positive phase differential input port and the negative phase differential input port, as well as the positive phase differential coupling port and the negative phase differential coupling port. Signal.
  • two quadrature couplers are provided in the integrated circuit, and two amplifiers are also provided; the positive-phase differential through port and the negative-phase differential of the first quadrature coupler
  • the through port, the positive-phase differential coupling port and the negative-phase differential coupling port are respectively coupled to the differential input ends of the two amplifiers, and the differential output ends of the two amplifiers are respectively coupled to the positive phase differential input port and the negative phase of the second quadrature coupler.
  • the phase differential input port, and the positive phase differential coupling port and the negative phase differential coupling port are coupled.
  • a non-transitory computer-readable medium for use with a computer has software for creating integrated circuits, and the computer-readable medium stores one or more computer-readable data structures, one or more Each computer-readable data structure has photomask data used to manufacture the above-mentioned first aspect or the integrated circuit provided by any possible implementation of the first aspect.
  • Figure 1 is a schematic diagram of the structure of a quadrature coupler
  • FIG. 2 is a schematic diagram of a two-wire transmission line provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of an integrated circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of another integrated circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of yet another integrated circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic circuit diagram of a quadrature coupler provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of an RTA provided by an embodiment of this application.
  • FIG. 9 is a schematic structural diagram of an RTPS provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a VMPS provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of an IRM provided by an embodiment of this application.
  • FIG. 12 is a schematic structural diagram of a BA provided by an embodiment of the present application.
  • circuits/components used with the term “for” include hardware, such as circuits that perform operations, and the like.
  • At least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be It can be single or multiple.
  • words such as “first” and “second” do not limit the number and order.
  • FIG. 2 is a schematic structural diagram of a two-wire transmission line provided by an embodiment of the application.
  • the two-wire transmission line includes a positive-phase transmission line and a negative-phase transmission line coupled with each other. Both ends of the positive-phase transmission line are provided with a positive-phase differential input port INP and a positive-phase differential output port OUTP. Both ends of the negative-phase transmission line are provided with a negative-phase differential input port INN and a negative-phase differential output port OUTN.
  • the signal transmitted in the positive-phase transmission line and the signal transmitted in the negative-phase transmission line have the same amplitude, phase difference of 180 degrees, and opposite polarity, and are used to transmit one signal, which is the same as the signal transmitted in the microstrip transmission line.
  • the ground plane is not required as a reference.
  • the positive-phase transmission line and the negative-phase transmission line in the two-wire transmission line can be nested and coupled with each other.
  • different characteristic impedances and different characteristic impedances can be realized by setting the length, line width and line distance of the positive-phase transmission line and the negative-phase transmission line.
  • the electrical length of the two-wire transmission line Figure 2 (b) is a schematic diagram of the layout of a two-wire transmission line in an integrated circuit.
  • (C) in FIG. 2 is an equivalent schematic diagram of the two-wire transmission line.
  • the positive-phase transmission line and the negative-phase transmission line can be respectively equivalent to the inductance L, and the parasitic capacitance between the positive-phase transmission line and the negative-phase transmission line can be expressed as C.
  • an embodiment of the present application provides a quadrature coupler based on a two-wire transmission line, which is used to reduce the area of an integrated circuit occupied by the quadrature coupler.
  • FIG. 3 is a schematic structural diagram of an integrated circuit provided by an embodiment of the application, and a quadrature coupler is provided in the integrated circuit.
  • the quadrature coupler is provided with a positive-phase differential input port INP, a negative-phase differential input port INN, a positive-phase differential through port TP, a negative-phase differential through port TN, a positive-phase differential coupling port CP, and a negative-phase differential coupling port.
  • CN positive phase differential isolation port ISOP and negative phase differential isolation port ISON.
  • the quadrature coupler is also provided with a first coil L1, a second coil L2, a third coil L3, and a fourth coil L4 coupled to each other.
  • the mutual coupling of the first coil L1 and the second coil L2 can be used as the through path of the orthogonal coupler, and the third coil L3 and the fourth coil L4 can be coupled with each other as the coupling path of the orthogonal coupler.
  • the mutual coupling of the first coil L1 and the second coil L2 with the third coil L3 and the fourth coil L4 can realize the coupling of the through path and the coupling path, so that the eight-port differential quadrature coupling is realized through the four coils coupled to each other.
  • the first coil L1 and the second coil L2, the third coil L3 and the fourth coil L4 are respectively implemented as two sets of two-wire transmission lines. There is no need to set a ground plane, which eliminates the limitation of the ground plane on the integrated circuit, thereby reducing The area of the quadrature coupler in the integrated circuit is calculated.
  • the third coil L3 and the fourth coil L4 respectively have via holes, and the third coil L3 and the fourth coil L4 are coupled to each other through the via holes on the same metal layer.
  • the third coil L3 and the fourth coil L4 are nested and coupled with each other on the same metal layer, the two coils will cross.
  • the two coils can be crossed by layer jump. Segment wiring to achieve mutual coupling of two coils on the same metal layer.
  • the third coil L3 and the fourth coil L4 are nested and coupled with each other on the top metal layer or the sub-top metal layer.
  • the cross section of the coils can be located on the top metal layer or the second Metal layers other than the top metal layer.
  • the coupling gap between the third coil L3 and the fourth coil L4 remains constant.
  • the coupling gap between the third coil L3 and the fourth coil L4 is kept constant, which can ensure that the amount of electrical coupling at any position when the third coil L3 and the fourth coil L4 are coupled to each other is the same, thereby ensuring the positive phase differential coupling port CP
  • the coupling can be performed by coupling between different metal layers, that is, The first coil L1 and the second coil L2 are coupled to each other and disposed on the first metal layer, and the third coil L3 and the fourth coil L4 are coupled to each other and disposed on the second metal layer.
  • the first metal layer is different from the second metal layer.
  • the metal layer where the first coil L1 and the second coil L2 are coupled to each other may be the top metal layer, and the metal layer where the third coil L3 and the fourth coil L4 are coupled to each other may be the second top metal layer.
  • the projections of the first coil L1 and the second coil L2 and the third coil L3 and the fourth coil L4 on the same metal layer overlap, and different mutual inductances between the four coils can be achieved by setting different overlap ratios. value.
  • INP, INN, TP, and TN are located on the top metal layer
  • CP, CN, ISOP, and ISON are located on the second top metal layer
  • the projections of INP and CP on the same metal layer overlap
  • the projections of INN and CN on the same metal layer overlap
  • the projections of TP and ISOP on the same metal layer overlap
  • the projections of TN and ISON on the same metal layer overlap.
  • Figure 6 is a schematic circuit diagram of the quadrature coupler, positive phase differential input port INP, negative phase differential input port INN, positive phase differential through port TP, negative phase differential through port TN, positive phase differential coupled port CP, negative phase differential Coupling port CN, positive phase differential isolation port ISOP, negative phase differential isolation port ISON, first coil L1, second coil L2, third coil L3, fourth coil L4, first capacitor C1, second capacitor C2, third The relationship between the capacitor C3 and the fourth capacitor C4 may be specifically as shown in FIG. 6.
  • the magnetic field coupling between the through channel and the coupling channel of the orthogonal coupler can pass through the first coil L1 and the second coil L2, and the third coil L3 and the fourth coil L4.
  • the mutual inductance between the two can be adjusted, and the amount of electric field coupling can be adjusted by the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, so that the quadrature coupler has better broadband characteristics, and at the same time It has phase error and small transmission error.
  • the first coil L1 and the second coil L2, the third coil L3 and the fourth coil L4 are respectively wired as two sets of two-wire transmission lines. There is no need to set a ground plane, which eliminates the limitation of the ground plane on the integrated circuit, thereby reducing The area of the quadrature coupler in the integrated circuit is calculated.
  • the integrated circuit provided by the embodiments of the present application may also include other devices, and the other devices and the quadrature coupler together form a variety of different electronic circuits, that is, the quadrature coupler can be applied to a variety of different electronic circuits, For example, reflection type attenuator (RTA), reflection type phase shifter (RTPS), vector composite phase shifter (VMPS), image rejection mixer (image rejection) mixer, IRM) and balanced amplifier (BA), etc.
  • RTA reflection type attenuator
  • RTPS reflection type phase shifter
  • VMPS vector composite phase shifter
  • IRM image rejection mixer
  • BA balanced amplifier
  • the positive phase differential input port INP and the negative phase differential input port INN of the quadrature coupler are used as the differential input port of the RTA, and the positive phase differential isolation port ISOP and the negative phase differential isolation port ISON of the quadrature coupler are used as the differential of the RTA
  • the output ports are represented as OUTP and OUTN in Figure 8.
  • the resistance adjustable device refers to a device whose resistance can be adjusted.
  • the resistance adjustable device may be a diode, a transistor, an adjustable resistor, etc.
  • the transistor may be a PMOS tube or an NMOS tube.
  • four resistance adjustable devices are transistors M1 to M4, and M1 is connected between CP and ground through source and drain, M2 is connected between CN and ground through source and drain, M3 Take the source and drain connected between TP and ground, and M4 through the source and drain connected between TN and ground as an example.
  • the gates of the transistors M1 to M4 can be used to receive control signals.
  • the gate of M1 is used to receive the control signal Va
  • the gate of M2 is used to receive the control signal Vb
  • the gate of M3 is used to receive the control signals Vc, M4.
  • the gate is used to receive the control signal Vd
  • the control signals Va, Vb, Vc, and Vd can be used to control the on or off of the transistors M1, M2, M3, and M4, respectively.
  • the input signal is injected from the positive phase differential input port INP and the negative phase differential input port INN of the quadrature coupler; when the control signals Va, Vb, Vc, and Vd control the transistors M1, M2, and When M3 and M4 are turned on or off, the equivalent impedance of the transistors M1 to M4 connected to the RTA can be adjusted.
  • the equivalent impedance matches the characteristic impedance of the RTA, the power or energy flowing to the positive-phase differential through port TP and the reverse-phase differential through port, and the power or energy flowing to the positive-phase differential coupling port CP and the reverse-phase differential coupling port in the input signal The power or energy of the CN is absorbed.
  • the quadrature coupler is applied to the RTA, which can make the RTA have the advantages of small phase error and small amplitude error, and at the same time, the layout of the above-mentioned quadrature coupler is adopted in the integrated circuit including the RTA.
  • the design can make the area of the integrated circuit occupied by the RTA smaller.
  • FIG. 9 is a schematic structural diagram of a reflective phase shifter RTPS provided by an embodiment of the application.
  • the RTPS includes four reactance adjustable devices and a quadrature coupler. Among them, the first reactance adjustable device is connected between the positive phase differential coupling port CP of the quadrature coupler and the ground terminal, the second reactance adjustable device is connected between the negative phase differential coupling port CN and the ground terminal, and the third One reactance adjustable device is connected between the positive-phase differential through port TP and the ground terminal, and the fourth reactance adjustable device is connected between the negative-phase differential through port TN and the ground terminal.
  • the positive phase differential input port INP and the negative phase differential input port INN of the quadrature coupler are used as the differential input terminals of the RTPS
  • the positive phase differential isolation port ISOP and the negative phase differential isolation port ISON of the quadrature coupler are used as the RTPS Differential output terminals, shown in Figure 9 as OUTP and OUTN.
  • the adjustable reactance device may refer to a device whose inductive reactance or capacitive reactance can be adjusted.
  • the adjustable reactance device may be an adjustable inductor or an adjustable capacitor.
  • four adjustable reactance devices are used as adjustable capacitors C11 to C14, and C11 is connected between CP and ground, C12 is connected between CN and ground, and C13 is connected between TP and ground. In between, C14 is connected between TN and ground as an example for description.
  • the quadrature coupler is applied to the RTPS, which can make the RTPS have the advantages of small phase error and small amplitude error.
  • the layout of the above-mentioned quadrature coupler is adopted in the integrated circuit including the RTPS. The design can make the area of the integrated circuit occupied by the RTPS smaller.
  • FIG. 10 is a schematic structural diagram of a vector synthesis phase shifter VMPS provided by an embodiment of the application.
  • the VMPS includes a quadrature coupler, a two-channel amplitude adjuster, and a combiner.
  • the differential input port of one of the two amplitude adjustment circuits is coupled with the positive-phase differential through port TP and the negative-phase differential through port TN
  • the differential input port of the other amplitude adjusting circuit is coupled with the positive-phase differential coupling port CP
  • the negative phase differential coupling port CN is coupled
  • the differential output ports of the two-channel amplitude adjustment circuit are coupled with the two differential input ports of the combiner.
  • the amplitude adjuster refers to a device that can adjust the signal amplitude.
  • the amplitude adjuster can be a digital stepper appliance (DSA) or a variable gain amplifier (VGA), etc.
  • DSA digital stepper appliance
  • VGA variable gain amplifier
  • the amplitude adjuster is VGA as an example for description.
  • the positive-phase differential through port TP and the negative-phase differential through port of the quadrature coupler output the first signal
  • the positive-phase differential coupling port CP and the negative-phase differential coupling port and CN output the second signal.
  • the phase difference between the first signal and the second signal is 90°; the two amplitude adjusters adjust the amplitude of the first signal and the second signal respectively, and the adjusted two signals are input to the two signals of the combiner.
  • the exchange processing of the N signal in the first signal and the P signal in the second signal can be implemented by a combiner or The two-channel signals after adjustment are exchanged before they are input to the combiner, which is not specifically limited in the embodiment of the present application.
  • the quadrature coupler is applied to the VMPS, which can make the RTPS have better broadband characteristics, and the advantages of small phase error and small amplitude error. At the same time, it can be used in an integrated circuit including the VMPS.
  • the layout design of the above quadrature coupler can make the area of the integrated circuit occupied by the VMPS smaller.
  • FIG. 11 is a schematic structural diagram of an image rejection mixer IRM provided by an embodiment of the application.
  • the IRM includes a splitter, two quadrature couplers, and two mixers.
  • the two mixers are represented as the first A mixer MIX1 and a second mixer MIX2, and the two quadrature couplers are respectively denoted as a first quadrature coupler COP1 and a second quadrature coupler COP2.
  • the two differential output ports of the splitter are respectively connected to the differential input ports of the two mixers MIX1 and MIX2; the differential output ports of the two mixers MIX1 and MIX2 are respectively connected to the positive of the first quadrature coupler COP1.
  • Phase differential input port INP1 and negative phase differential input port INN1, and positive phase differential coupling port CP1 and negative phase differential coupling port CN1 are coupled;
  • the second quadrature coupler COP2 is used for positive phase differential input port INP2 and negative phase differential input
  • the port INN2, the positive phase differential coupling port CP2 and the negative phase differential coupling port CN2 are coupled to provide differential local oscillator signals for the two mixers MIX1 and MIX2, respectively.
  • the differential input end of the splitter is used as the differential input port of the IRM, and the positive-phase differential through port TP1 and the negative-phase differential through port TN1 of the first quadrature coupler COP1 are used as the differential output port of the IRM.
  • the differential local oscillator signals corresponding to the two mixers MIX1 and MIX2 are represented as LO1 and LO2.
  • the image frequency is the signal frequency generated by the frequency conversion processing of the useful signal frequency.
  • the image frequency is very close to the useful signal frequency, or the image frequency even falls within the signal bandwidth of the useful signal.
  • the time filter is difficult to filter out the image frequency, and the image rejection mixer can solve this problem well.
  • the image rejection mixer in addition to the phase conversion of the two I/Q signals at the differential output port of the mixer, it is also necessary to provide quadrature local oscillator signals with a phase difference of 90° for the two mixers.
  • the two-channel I/Q signals output by the differential output port of the two-channel mixer through a quadrature coupler are used for phase conversion, and the other quadrature coupler is used to provide a phase difference of 90 for the two-channel mixers.
  • ° Quadrature local oscillator signal ° Quadrature local oscillator signal.
  • applying the quadrature coupler to the IRM can make the IRM have broadband image rejection characteristics.
  • the layout design of the quadrature coupler can be used in the integrated circuit including the IRM.
  • the area of the integrated circuit occupied by the IRM is relatively small.
  • the positive phase differential through port TP1 and the negative phase differential through port TN1 of the first quadrature coupler, as well as the positive phase differential coupling port CP1 and the negative phase differential coupling port CN1 are respectively coupled to the differential input ports of the two amplifiers AMP1 and AMP2 .
  • the differential output ports of the two amplifiers AMP1 and AMP2 are respectively coupled with the positive phase differential input port INP2 and the negative phase differential input port INN2 of the second quadrature coupler, as well as the positive phase differential coupling port CP2 and the negative phase differential coupling port CN2. .
  • the positive phase differential input port INP1 and the negative phase differential input port INN1 of the first differential quadrature coupler are used as the input ports of the BA, and the positive phase differential through port TP2 and the negative phase differential through port TN2 of the second differential quadrature coupler are used as The output ports of this BA are OUTP and OUTN.
  • the differential input ports and differential output ports of the two amplifiers are both isolated by the first quadrature coupler and the second differential quadrature coupler, so that the impedance matching in the BA is not affected by the internal
  • the interference of the input and output impedances of the two amplifiers AMP1 and AMP2 improves the stability of the BA. Since the bandwidth of the coupler determines the bandwidth of the balanced amplifier BA, applying the quadrature coupler provided in this article to the BA can make the bandwidth of the BA specific, and at the same time use the above-mentioned quadrature coupler layout in the integrated circuit including the BA The design can make the area of the integrated circuit occupied by the BA smaller.
  • the communication device may include any of the orthogonal couplers shown in FIGS. 3 to 6 above, or the orthogonal coupler provided in any of the diagrams in FIGS. 8-12 Other circuits, etc.
  • the quadrature coupler and other circuits including the quadrature coupler reference may be made to the corresponding description above, and details are not repeated here in the embodiments of the present application.
  • a non-transitory computer-readable medium for use with a computer, the computer has software for creating integrated circuits, and one or more computer-readable media are stored on the computer-readable medium. Read the data structure.
  • One or more computer-readable data structures have photomask data for manufacturing the circuit provided in any of the above figures 3-6 and 8-12.
  • each MOS tube in any embodiment or drawing can be a single MOS tube that meets the required start-up gain or the required conduction current.
  • It can also be a combination of multiple MOS transistors in parallel that needs to meet the required start-up gain or the required conduction current, that is, the sum of the corresponding start-up gains of each of the multiple MOS transistors is greater than or equal to The required startup gain;
  • each capacitor in the embodiment of the present application can be a capacitor that meets the required capacitance value, or it can be a combination of capacitors that meet the required capacitance value formed by multiple capacitors in parallel or in series, that is, the After multiple capacitors are connected in series or in parallel, the corresponding capacitance value is equal to the required capacitance value;
  • each inductor in the embodiment of the present application can be an inductor that meets the required inductance value, or multiple inductors can be connected in series or in parallel.
  • each resistor in the embodiment of the present application can be a resistor that meets the required resistance value, or it can be composed of multiple resistors that meet the required resistance value in parallel or in series.
  • the resistance combination that is, the corresponding resistance value after the multiple resistances are connected in series or in parallel is equal to the required resistance value.

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Abstract

提供一种集成电路，涉及电子技术领域，用于减小正交耦合器占用的集成电路中的面积。该集成电路中的正交耦合器上设置有正相差分输入端口（INP）、负相差分输入端口（INN），正相差分直通端口（TP）、负相差分直通端口（TN）、正相差分耦合端口（CP）、负相差分耦合端口（CN）、正相差分隔离端口（ISOP）和负相差分隔离端口（ISON）；正交耦合器上设置有相互耦合的第一线圈（L1）、第二线圈（L2）、第三线圈（L3）和第四线圈（L4）；正相差分输入端口（INP）和正相差分直通端口（TP）设置在第一线圈（L1）的两端；负相差分输入端口（INN）和负相差分直通端口（TN）设置在第二线圈（L2）的两端；正相差分耦合端口（CP）和正相差分隔离端口（ISOP）设置在第三线圈（L3）的两端；负相差分耦合端口（CN）和负相差分隔离端口（ISON）设置在第四线圈（L4）的两端。

Description

一种集成电路 技术领域
本申请涉及电子技术领域，尤其涉及一种集成电路。
背景技术
微波通常是指波长为1m～1mm、对应频率范围为300MHz～300GHz的电磁波。微波通信是指利用微波作为载体来携带信息并通过空间电波进行传输的一种无线通信方式。微波通信中通常需要将一路信号分成多路信号，定向耦合器是微波通信中常用的具有分路功能的微波分支电路。正交耦合器作为定向耦合器中一种典型的微波分支电路，在微波通信中应用十分广泛。正交耦合器包括直通通路和耦合通路，通过正交耦合器可以将输入信号分成直通通路信号和耦合通路信号，两路信号的功率相等、相位相差90°。
现有技术中，通常采用微带传输线原理来设计正交耦合器。如图1所示，该正交耦合器包括两路微带传输线，这两路微带传输线分别为直通通路传输线和耦合通路传输线，当这两路微带传输线靠的足够近时能量就能从一路传输线上耦合到另一路传输线上。图1中IN表示直通输入端口，OUT表示直通输出端口，COP表示耦合端口，ISO表示隔离端口。基于微带传输线原理的正交耦合器为单端口正交耦合器，两路微带传输线在共用的地平面上走线，在集成电路中需要同时实现两路微带传输线和共用的地平面。
这种方式的正交耦合器为了传输准横电磁(transverse electric and magnetic，TEM)波，同时实现特定的端口阻抗，对于微带传输线的线宽、以及微带传输线与地平面之间的距离都有一定的限制，因此占用的集成电路的面积较大。
发明内容
本申请提供一种集成电路，用于减小正交耦合器占用的集成电路中的面积。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种集成电路，该集成电路中设置有正交耦合器；正交耦合器上设置有正相差分输入端口、负相差分输入端口，正相差分直通端口、负相差分直通端口、正相差分耦合端口、负相差分耦合端口、正相差分隔离端口和负相差分隔离端口；正交耦合器上设置有相互耦合的第一线圈、第二线圈、第三线圈和第四线圈；正相差分输入端口和正相差分直通端口设置在第一线圈的两端；负相差分输入端口和负相差分直通端口设置在第二线圈的两端；正相差分耦合端口和正相差分隔离端口设置在第三线圈的两端；负相差分耦合端口和负相差分隔离端口设置在第四线圈的两端。
上述技术方案中，第一线圈和第二线圈相互耦合可以作为该正交耦合器的直通通路，第三线圈和第四线圈相互耦合可以作为该正交耦合器的耦合通路，第一线圈和第二线圈与第三线圈和第四线圈的相互耦合可以实现直通通路与耦合通路的耦合，从而通过相互耦合的四个线圈实现了八端口的差分正交耦合器的设计。同时，第一线圈与第二线圈、第三线圈与第四线圈分别作为两组双线传输线的方式来实现，无需设置地 平面，摆脱了地平面对于集成电路的限制，从而降低了正交耦合器在集成电路中的面积。
在第一方面的一种可能的实现方式中，第一线圈和第二线圈相互嵌套且匝数相同。上述可能的实现方式中，可以优化第一线圈和第二线圈构成的双线传输线的性能。
在第一方面的一种可能的实现方式中，第一线圈与第二线圈的线宽相同。上述可能的实现方式中，可以提高第一线圈与第二线圈耦合的性能。
在第一方面的一种可能的实现方式中，第一线圈与第二线圈之间的耦合缝隙保持恒定。上述可能的实现方式中，可以保证第一线圈与第二线圈相互耦合时任一位置的电耦合量相同，从而保证端口阻抗的连续性。
在第一方面的一种可能的实现方式中，第三线圈和第四线圈相互嵌套且匝数相同。上述可能的实现方式中，可以优化第三线圈和第四线圈构成的双线传输线的性能。
在第一方面的一种可能的实现方式中，第三线圈与第四线圈的线宽相同。上述可能的实现方式中，可以提高第三线圈与第四线圈耦合的性能。
在第一方面的一种可能的实现方式中，第三线圈与第四线圈之间的耦合缝隙保持恒定。上述可能的实现方式中，可以保证第三线圈与第四线圈相互耦合时任一位置的电耦合量相同，从而保证端口阻抗的连续性。
在第一方面的一种可能的实现方式中，第一线圈与第二线圈分别具有过孔，第一线圈和第二线圈在同一金属层通过该过孔相互耦合。上述可能的实现方式中，可以减小第一线圈与第二线圈布线时占用的集成电路的面积。
在第一方面的一种可能的实现方式中，第三线圈与第四线圈分别具有过孔，第三线圈和第四线圈在同一金属层通过该过孔相互耦合。上述可能的实现方式中，可以减小第三线圈与第四线圈布线时占用的集成电路的面积。
在第一方面的一种可能的实现方式中，第一线圈和第二线圈相互耦合设置于第一金属层、第三线圈和第四线圈相互耦合设置于第二金属层。上述可能的实现方式中，可以通过设置上述两个金属层的重叠比例实现四个线圈之间的不同互感，同时可以减小第一线圈和第二线圈、与第三线圈与第四线圈布线时占用的集成电路的面积。
在第一方面的一种可能的实现方式中，第一线圈、第二线圈、第三线圈和第四线圈的匝数相同。上述可能的实现方式中，相互耦合的四个线圈的长度均相等，这样可以提高两组双线传输线的对称性，从而优化两组双线传输线耦合的性能。
在第一方面的一种可能的实现方式中，正相差分输入端口位于正相差分耦合端口的正下方，负相差分输入端口位于负相差分耦合端口的正下方，正相差分直通端口位于正相差分隔离端口的正下方，负相差分直通端口位于负相差分隔离端口的正下方。上述可能的实现方式中，可以减小第一线圈和第二线圈、与第三线圈与第四线圈布线时占用的集成电路的面积。
在第一方面的一种可能的实现方式中，正相差分输入端口与正相差分耦合端口通过第一电容耦合，负相差分输入端口与负相差分耦合端口通过第二电容耦合，正相差分直通端口与正相差分隔离端口通过第三电容耦合，负相差分直通端口与负相差分隔离端口通过第四电容耦合。上述可能的实现方式中，可以通过调节第一电容、第二电容、第三电容和第四电容的大小，可以实现对该正交耦合器的电场耦合量的调节，从 而使得该正交耦合器具有较好的宽带特性，同时具有相位误差和传输误差较小。
在第一方面的一种可能的实现方式中，该集成电路中还设置有四个电阻可调器件；四个电阻可调器件分别连接在正相差分耦合端口、负相差分耦合端口、正相差分直通端口、负相差分直通端口与接地端之间。上述可能的实现方式中，提供了一种反射型衰减器RTA，该RTA具有相位误差小和幅度误差小的优点，同时占用的集成电路的面积较小。
在第一方面的一种可能的实现方式中，该集成电路中还设置有四个可调电抗器件；四个可调电抗器件分别连接在正相差分耦合端口、负相差分耦合端口、正相差分直通端口、负相差分直通端口与接地端之间。上述可能的实现方式中，提供了一种反射型移相器RTPS，该RTPS具有相位误差小和幅度误差小的优点，同时占用的集成电路的面积较小。
在第一方面的一种可能的实现方式中，该集成电路中还设置有两路幅度调节电路和合路器；两路幅度调节电路中的一路幅度调节电路的差分输入端口与正相差分直通端口和负相差分直通端口耦合，另一路幅度调节电路的差分输入端口与正相差分耦合端口和负相差分耦合端口耦合，两路幅度调节电路的差分输出端口与合路器的两个差分输入端口耦合。上述可能的实现方式中，提供了一种矢量合成移相器VMPS，该VMPS具有较好的宽带特性、以及相位误差小和幅度误差小的优点，同时占用的集成电路的面积较小。
在第一方面的一种可能的实现方式中，该集成电路中设置有两个正交耦合器，还设置有分路器和两路混频器；分路器的两路差分输出端口分别与两路混频器的差分输入端口耦合，两路混频器的差分输出端口分别与第一个正交耦合器的正相差分输入端口和负相差分输入端口、以及正相差分耦合端口和负相差分耦合端口耦合，第二个正交耦合器用于通过正相差分输入端口和负相差分输入端口、以及正相差分耦合端口和负相差分耦合端口分别为两路混频器提供差分本振信号。上述可能的实现方式中，提供了一种镜像抑制混频器IRM，该IRM具有宽带镜像抑制特性，同时占用的集成电路的面积较小。
在第一方面的一种可能的实现方式中，该集成电路中设置有两个正交耦合器，还设置有两路放大器；第一个正交耦合器的正相差分直通端口和负相差分直通端口、以及正相差分耦合端口和负相差分耦合端口分别与两路放大器的差分输入端耦合，两路放大器的差分输出端分别与第二个正交耦合器的正相差分输入端口和负相差分输入端口、以及正相差分耦合端口和负相差分耦合端口耦合。上述可能的实现方式中，正交耦合器带宽决定了平衡放大器BA的带宽，同时占用的集成电路的面积较小。
第二方面，提供一种通信设备，该通信设备包括集成电路，该集成电路中设置有正交耦合器；正交耦合器上设置有正相差分输入端口、负相差分输入端口，正相差分直通端口、负相差分直通端口、正相差分耦合端口、负相差分耦合端口、正相差分隔离端口和负相差分隔离端口；正交耦合器上设置有相互耦合的第一线圈、第二线圈、第三线圈和第四线圈；正相差分输入端口和正相差分直通端口设置在第一线圈的两端；负相差分输入端口和负相差分直通端口设置在第二线圈的两端；正相差分耦合端口和正相差分隔离端口设置在第三线圈的两端；负相差分耦合端口和负相差分隔离端口设 置在第四线圈的两端。
在第二方面的一种可能的实现方式中，第一线圈和第二线圈相互嵌套且匝数相同。在第二方面的一种可能的实现方式中，第一线圈与第二线圈的线宽相同。在第二方面的一种可能的实现方式中，第一线圈与第二线圈之间的耦合缝隙保持恒定。
在第二方面的一种可能的实现方式中，第三线圈和第四线圈相互嵌套且匝数相同。在第二方面的一种可能的实现方式中，第三线圈与第四线圈的线宽相同。在第二方面的一种可能的实现方式中，第三线圈与第四线圈之间的耦合缝隙保持恒定。
在第二方面的一种可能的实现方式中，第一线圈与第二线圈分别具有过孔，第一线圈和第二线圈在同一金属层通过该过孔相互耦合。
在第二方面的一种可能的实现方式中，第三线圈与第四线圈分别具有过孔，第三线圈和第四线圈在同一金属层通过该过孔相互耦合。
在第二方面的一种可能的实现方式中，第一线圈和第二线圈相互耦合设置于第一金属层、第三线圈和第四线圈相互耦合设置于第二金属层。
在第二方面的一种可能的实现方式中，第一线圈、第二线圈、第三线圈和第四线圈的匝数相同。
在第二方面的一种可能的实现方式中，正相差分输入端口位于正相差分耦合端口的正下方，负相差分输入端口位于负相差分耦合端口的正下方，正相差分直通端口位于正相差分隔离端口的正下方，负相差分直通端口位于负相差分隔离端口位于的正下方。
在第二方面的一种可能的实现方式中，正相差分输入端口与正相差分耦合端口通过第一电容耦合，负相差分输入端口与负相差分耦合端口通过第二电容耦合，正相差分直通端口与正相差分隔离端口通过第三电容耦合，负相差分直通端口与负相差分隔离端口通过第四电容耦合。
在第二方面的一种可能的实现方式中，该集成电路中还设置有四个电阻可调器件；四个电阻可调器件分别连接在正相差分耦合端口、负相差分耦合端口、正相差分直通端口、负相差分直通端口与接地端之间。
在第二方面的一种可能的实现方式中，该集成电路中还设置有四个可调电抗器件；四个可调电抗器件分别连接在正相差分耦合端口、负相差分耦合端口、正相差分直通端口、负相差分直通端口与接地端之间。
在第二方面的一种可能的实现方式中，该集成电路中还设置有两路幅度调节电路和合路器；两路幅度调节电路中的一路幅度调节电路的差分输入端口与正相差分直通端口和负相差分直通端口耦合，另一路幅度调节电路的差分输入端口与正相差分耦合端口和负相差分耦合端口耦合，两路幅度调节电路的差分输出端口与合路器的两个差分输入端口耦合。
在第二方面的一种可能的实现方式中，该集成电路中设置有两个正交耦合器，还设置有分路器和两路混频器；分路器的两路差分输出端口分别与两路混频器的差分输入端口耦合，两路混频器的差分输出端口分别与第一个正交耦合器的正相差分输入端口和负相差分输入端口、以及正相差分耦合端口和负相差分耦合端口耦合，第二个正交耦合器用于通过正相差分输入端口和负相差分输入端口、以及正相差分耦合端口和 负相差分耦合端口分别为两路混频器提供差分本振信号。
在第二方面的一种可能的实现方式中，该集成电路中设置有两个正交耦合器，还设置有两路放大器；第一个正交耦合器的正相差分直通端口和负相差分直通端口、以及正相差分耦合端口和负相差分耦合端口分别与两路放大器的差分输入端耦合，两路放大器的差分输出端分别与第二个正交耦合器的正相差分输入端口和负相差分输入端口、以及正相差分耦合端口和负相差分耦合端口耦合。
第三方面，提供一种与计算机一起使用的非瞬时性计算机可读介质，计算机具有用于创建集成电路的软件，计算机可读介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构具有用于制造上述第一方面或者第一方面的任一种可能的实现方式所提供的集成电路的光掩膜数据。
可以理解地是，上述提供的任一种通信设备和与计算机一起使用的非瞬时性计算机可读介质等包含了上文所提供的集成电路，因此，其所能达到的有益效果可参考上文所提供的对应的集成电路中的有益效果，此处不再赘述。
附图说明
图1为一种正交耦合器的结构示意图；
图2为本申请实施例提供的一种双线传输线的示意图；
图3为本申请实施例提供的一种集成电路的结构示意图；
图4为本申请实施例提供的另一种集成电路的结构示意图；
图5为本申请实施例提供的又一种集成电路的结构示意图；
图6为本申请实施例提供的一种正交耦合器的电路示意图；
图7为本申请实施例提供的一种正交耦合器的仿真结果示意图；
图8为本申请实施例提供的一种RTA的结构示意图；
图9为本申请实施例提供的一种RTPS的结构示意图；
图10为本申请实施例提供的一种VMPS的结构示意图；
图11为本申请实施例提供的一种IRM的结构示意图；
图12为本本申请实施例提供的一种BA的结构示意图。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。
各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路系统)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/ 或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
图2为本申请实施例提供的一种双线传输线的结构示意图。如图2中的(a)所示，该双线传输线包括相互耦合的正相传输线和负相传输线，该正相传输线的两端设置有正相差分输入端口INP和正相差分输出端口OUTP，该负相传输线的两端设置有负相差分输入端口INN和负相差分输出端口OUTN。在该双线传输线中，正相传输线中传输的信号与负相传输线中传输的信号的振幅相等、相位相差180度、极性相反，用于传输一路信号，这与微带传输线中传输的信号相比，不需要地平面作为参考。
在集成电路中，该双线传输线中的正相传输线和负相传输线可以相互嵌套耦合，同时通过设置正相传输线和负相传输线的长度、线宽和线距等可以实现不同特征阻抗和不同电长度的双线传输线，图2中的(b)为一种双线传输线在集成电路中的版图示意。图2中的(c)为该双线传输线的等效示意图，正相传输线和负相传输线可以分别等效于电感L，正相传输线与负相传输线之间的寄生电容可以表示为C。
通过集成电路的高精度工艺，可以解决双线传输线无法在高频领域应用的技术问题。同时，双线传输线与微波传输线在集成电路中的应用相比，双线传输线无需设置地平面，从而摆脱了地平面对于集成电路的限制。基于此，本申请实施例提供一种基于双线传输线的正交耦合器，用于减小正交耦合器占用的集成电路的面积。
图3为本申请实施例提供的一种集成电路的结构示意图，该集成电路中设置有正交耦合器。
其中，该正交耦合器上设置有正相差分输入端口INP、负相差分输入端口INN，正相差分直通端口TP、负相差分直通端口TN、正相差分耦合端口CP、负相差分耦合端口CN、正相差分隔离端口ISOP和负相差分隔离端口ISON。该正交耦合器上还设置有相互耦合的第一线圈L1、第二线圈L2、第三线圈L3和第四线圈L4。正相差分输入端口INP和正相差分直通端口TP设置在第一线圈L1的两端；负相差分输入端口INN和负相差分直通端口TN设置在第二线圈L2的两端；正相差分耦合端口CP和正相差分隔离端口ISOP设置在第三线圈L3的两端；负相差分耦合端口CN和负相差分隔离端口ISON设置在第四线圈L4的两端。
在本申请实施例中，第一线圈L1和第二线圈L2相互耦合可以作为该正交耦合器的直通通路，第三线圈L3和第四线圈L4相互耦合可以作为该正交耦合器的耦合通路，第一线圈L1和第二线圈L2与第三线圈L3和第四线圈L4的相互耦合可以实现直通通 路与耦合通路的耦合，从而通过相互耦合的四个线圈实现了八端口的差分正交耦合器的设计。同时，第一线圈L1与第二线圈L2、第三线圈L3与第四线圈L4分别作为两组双线传输线的方式来实现，无需设置地平面，摆脱了地平面对于集成电路的限制，从而降低了正交耦合器在集成电路中的面积。
在一种可能的实施例中，第一线圈L1与第二线圈L2相互耦合时，第一线圈L1与第二线圈L2相互嵌套且匝数相同。其中，第一线圈L1与第二线圈L2的匝数相同可以是指第一线圈L1与第二线圈L2的长度相同，将长度相同的两个线圈以相互嵌套的方式布线于集成电路中，可以优化第一线圈L1和第二线圈L2构成的双线传输线的性能。另外，第一线圈L1与第二线圈L2的线宽可以相同，这样可以提高第一线圈L1和第二线圈的对称性，从而优化第一线圈L1和第二线圈L2耦合的性能。
进一步的，如图4所示，第一线圈L1与第二线圈L2分别具有过孔，第一线圈L1和第二线圈L2在同一金属层通过该过孔相互耦合。当第一线圈L1与第二线圈L2在同一金属层相互嵌套耦合时，两个线圈会存在交叉，通过在该金属层中设置过孔，以使两个线圈通过跳层的方式实现线圈交叉段的布线，以此来实现两个线圈在同一金属层相互耦合。比如，第一线圈L1和第二线圈L2在顶层金属层或者次顶层金属层相互嵌套耦合，第一线圈L1和第二线圈L2相互嵌套时的线圈交叉段可以分别位于顶层金属层和次顶层金属层之外其他金属层。
可选的，第一线圈L1与第二线圈L2之间的耦合缝隙保持恒定。其中，第一线圈L1与第二线圈L2之间的耦合缝隙保持恒定，可以保证第一线圈L1与第二线圈L2相互耦合时任一位置的电耦合量相同，从而保证正相差分输入端口INP与负相差分输入端口INN构成的输入端口、以及正相差分直通端口TP与负相差分直通端口TN构成的直通端口的阻抗的连续性。
在另一种可能的实施例中，第三线圈L3与第四线圈L4相互耦合时，第三线圈L3与第四线圈L4相互嵌套且匝数相同。其中，第三线圈L3与第四线圈L4的匝数相同可以是指第三线圈L3与第四线圈L4的长度相同，将长度相同的两个线圈以相互嵌套的方式布线于集成电路中，这样可以优化第三线圈L3和第四线圈L4构成的双线传输线的性能。另外，第三线圈L3与第四线圈L4的线宽可以相同，这样可以提高第三线圈L3与第四线圈L4耦合的性能。
进一步的，如图5所示，第三线圈L3与第四线圈L4分别具有过孔，第三线圈L3与第四线圈L4在同一金属层通过该过孔相互耦合。当第三线圈L3与第四线圈L4在同一金属层相互嵌套耦合时，两个线圈会存在交叉，通过在该金属层中设置过孔，以使两个线圈通过跳层的方式实现线圈交叉段的布线，以此来实现两个线圈在同一金属层相互耦合。比如，第三线圈L3和第四线圈L4在顶层金属层或者次顶层金属层相互嵌套耦合，第三线圈L3和第四线圈L4相互嵌套时的线圈交叉段可以分别位于顶层金属层或次顶层金属层之外的其他金属层。
可选的，第三线圈L3与第四线圈L4之间的耦合缝隙保持恒定。其中，第三线圈L3与第四线圈L4之间的耦合缝隙保持恒定，可以保证第三线圈L3与第四线圈L4相互耦合时任一位置的电耦合量相同，从而保证正相差分耦合端口CP与负相差分耦合端口CN构成的耦合端口、以及正相差分隔离端口ISOP与负相差分隔离端口ISON构 成的隔离端口的阻抗的连续性。
在另一种可能的实施例中，第一线圈L1和第二线圈L2、与第三线圈L3和第四线圈L4相互耦合时可以通过不同金属层之间的耦合方式进行耦合，也即是，第一线圈L1和第二线圈L2相互耦合设置于第一金属层、第三线圈L3和第四线圈L4相互耦合设置于第二金属层，第一金属层与第二金属层不同。比如，第一线圈L1和第二线圈L2相互耦合的金属层可以为顶层金属层，第三线圈L3和第四线圈L4相互耦合的金属层可以为次顶层金属层。可选的，第一线圈L1和第二线圈L2、与第三线圈L3和第四线圈L4在同一金属层中的投影存在重叠，通过设置不同的重叠比例可以实现四个线圈之间的不同互感值。
在实际应用中，第一线圈L1和第二线圈L2、与第三线圈L3和第四线圈L4相互耦合时也可以通过同一金属层相互嵌套的方式进行耦合，也即是，第一线圈L1和第二线圈L2的金属层相互耦合的金属层、与第三线圈L3和第四线圈L4相互耦合的金属层相同。本申请实施例对此不作具体限制。
可选的，第一线圈L1和第二线圈L2、与第三线圈L3和第四线圈L4相互耦合时，第一线圈L1、第二线圈L2、第三线圈L3和第四线圈L4的匝数相同。也即是，相互耦合的四个线圈的长度均相等，这样可以提高两组双线传输线的对称性，从而优化两组双线传输线耦合的性能。
在另一种可能的实施例中，正相差分输入端口INP位于正相差分耦合端口CP的正下方，负相差分输入端口INN位于负相差分耦合端口CN的正下方，正相差分直通端口TP位于正相差分隔离端口ISOP的正下方，负相差分直通端口TN位于负相差分隔离端口ISON的正下方。其中，这里的一个端口位于另一个端口的正下方是指这两个端口全部或部分地在俯视图角度上重合。比如，INP、INN、TP和TN位于顶层金属层，CP、CN、ISOP和ISON位于次顶层金属层，且INP和CP在同一金属层的投影重叠，INN和CN在同一金属层的投影重叠，TP和ISOP在同一金属层的投影重叠，TN和ISON在同一金属层的投影重叠。
进一步的，如图3所示，正相差分输入端口INP与正相差分耦合端口CP通过第一电容C1耦合，负相差分输入端口INN与负相差分耦合端口CN通过第二电容C2耦合，正相差分直通端口TP与正相差分隔离端口ISOP通过第三电容C3耦合，负相差分直通端口TN与负相差分隔离端口ISON通过第四电容C4耦合。
图6为该正交耦合器的电路示意图，正相差分输入端口INP、负相差分输入端口INN，正相差分直通端口TP、负相差分直通端口TN、正相差分耦合端口CP、负相差分耦合端口CN、正相差分隔离端口ISOP、负相差分隔离端口ISON、第一线圈L1、第二线圈L2、第三线圈L3、第四线圈L4、第一电容C1、第二电容C2、第三电容C3和第四电容C4的关系具体可以如图6所示。
本申请实施例提供的正交耦合器通过仿真测试，可以得到图7所示的相位误差和增益误差，该相位误差和增益误差分别为该正交耦合器的正相差分直通端口TP和负相差分直通端口TN与正相差分耦合端口CP和负相差耦合端口CN之间的相位误差和增益误差，图7中的S21 dB20表示正相差分直通端口TP和负相差分直通端口TN的增益误差，S31 dB20表示正相差分耦合端口CP和负相差耦合端口CN的增益误差。 由图7可知，在17～25GHz频段内的增益误差小于0.2dB。该正交耦合器占用的集成电路的面积为180×160um 2。
在本申请实施例提供的集成电路中，该正交耦合器的直通通道与耦合通道之间的磁场耦合量可以通过第一线圈L1和第二线圈L2、与第三线圈L3和第四线圈L4之间的互感值来调节，电场耦合量可以通过第一电容C1、第二电容C2、第三电容C3和第四电容C4来调节，从而使得该正交耦合器具有较好的宽带特性，同时具有相位误差和传输误差较小。此外，第一线圈L1与第二线圈L2、第三线圈L3与第四线圈L4分别作为两组双线传输线的方式来布线，无需设置地平面，摆脱了地平面对于集成电路的限制，从而降低了正交耦合器在集成电路中的面积。
本申请实施例提供的集成电路中还可以包括其他器件，该其他器件与该正交耦合器一起形成多种不同的电子电路，即该正交耦合器可应用于多种不同的电子电路中，比如，反射型衰减器(reflection type attenuator，RTA)、反射型移相器(reflection type phase shifter，RTPS)、矢量合成移相器(vector composite phase shifter，VMPS)、镜像抑制混频器(image rejection mixer，IRM)和平衡放大器(balanced amplifier，BA)等。
图8为本申请实施例提供的一种反射型衰减器RTA结构示意图，该RTA包括四个电阻可调器件和正交耦合器。其中，第一电阻可调器件连接在正交耦合器的正相差分耦合端口CP与接地端之间，第二个电阻可调器件连接在负相差分耦合端口CN与接地端之间，第三个电阻可调器件连接在正相差分直通端口TP与接地端之间，第四个电阻可调器件连接在负相差分直通端口TN与接地端之间。该正交耦合器的正相差分输入端口INP和负相差分输入端口INN作为该RTA的差分输入端口，正交耦合器的正相差分隔离端口ISOP和负相差分隔离端口ISON作为该RTA的差分输出端口，图8中表示为OUTP和OUTN。
其中，电阻可调器件是指电阻的大小可以调节的器件，比如，该电阻可调器件可以为二极管、晶体管和可调电阻器等，晶体管可以为PMOS管或者NMOS管等。图8中以四个电阻可调器件为晶体管M1至M4，且M1通过源极和漏极连接在CP与接地端之间，M2通过源极和漏极连接在CN与接地端之间，M3通过源极和漏极连接在TP与接地端之间，M4通过源极和漏极连接在TN与接地端之间为例进行说明。晶体管M1至M4的栅极可用于接收控制信号，比如，M1的栅极用于接收控制信号Va、M2的栅极用于接收控制信号Vb、M3的栅极用于接收控制信号Vc、M4的栅极用于接收控制信号Vd，控制信号Va、Vb、Vc和Vd可以分别用于控制晶体管M1、M2、M3和M4的导通或截止。
具体的，在该RTA中，输入信号从正交耦合器的正相差分输入端口INP和负相差分输入端口INN灌入；当通过控制信号Va、Vb、Vc和Vd分别控制晶体管M1、M2、M3和M4导通或截止时，可以调节晶体管M1至M4接入该RTA中的等效阻抗。当该等效阻抗与该RTA的特征阻抗相匹配时，输入信号中流向正相差分直通端口TP和反相差分直通端口的功率或能量、以及流向正相差分耦合端口CP和反相差分耦合端口CN的功率或能量被吸收，此时输入信号传导至正相差分隔离端口ISOP和负相差分 隔离端口ISON的功率或能量最少。当该阻抗与该RTA的特征阻抗不匹配时，输入信号中流向正相差分直通端口TP和反相差分直通端口的功率或能量、以及流向正相差分耦合端口CP和反相差分耦合端口CN的功率或能量部分被吸收、部分被反射，此时输入信号传导至正相差分隔离端口ISOP和负相差分隔离端口ISON的功率或能量从该RTA的差分输出端口OUTP和OUTN输出，且输出信号的功率或能量随着该等效阻抗与特征阻抗的差值变大而增大。
需要说明的是，该RTA中的正交耦合器在集成电路中的版图设计具体可以如上述图3-图5所示。另外，关于该RTA的详细工作原理可以参考相关技术中的阐述，本申请实施例对此不作详细阐述。
在本申请实施例中，将该正交耦合器应用于RTA中，可以使得该RTA具有相位误差小和幅度误差小的优点，同时在包括该RTA的集成电路中采用上述正交耦合器的版图设计，可以使得该RTA占用的集成电路的面积较小。
图9为本申请实施例提供的一种反射型移相器RTPS的结构示意图，该RTPS包括四个电抗可调器件和正交耦合器。其中，第一电抗可调器件连接在正交耦合器的正相差分耦合端口CP与接地端之间，第二个电抗可调器件连接在负相差分耦合端口CN与接地端之间，第三个电抗可调器件连接在正相差分直通端口TP与接地端之间，第四个电抗可调器件连接在负相差分直通端口TN与接地端之间。其中，该正交耦合器的正相差分输入端口INP和负相差分输入端口INN作为该RTPS的差分输入端，正交耦合器的正相差分隔离端口ISOP和负相差分隔离端口ISON作为该RTPS的差分输出端，图9中表示为OUTP和OUTN。
其中，电抗可调器件可以是指感抗或容抗的大小可以调节的器件，比如，该电抗可调器件可以为可调电感或者可调电容等。为便于说明，图9中以四个电抗可调器件为可调电容C11至C14，且C11连接在CP与接地端之间，C12连接在CN与接地端之间，C13连接在TP与接地端之间，C14连接在TN与接地端之间为例进行说明。
具体的，在该RTPS中，输入信号从正交耦合器的正相差分输入端口INP和负相差分输入端口INN灌入；通过调节可调电容C11至C14，可以改变正相差分隔离端口ISOP和负相差分隔离端口ISON的输出阻抗，从而改变输入信号传导至正相差分隔离端口ISOP和负相差分隔离端口ISON的信号的相位，从而实现对于输入信号的相位调节。进一步的，该RTPS还可以作为移相器应用在相控阵链路中，本申请实施例对此不作详细阐述。
需要说明的是，该RTPS中的正交耦合器在集成电路中的版图设计具体可以如上述图3-图5所示。另外，关于该RTPS的详细工作原理可以参考相关技术中的阐述，本申请实施例对此不作详细阐述。
在本申请实施例中，将该正交耦合器应用于RTPS中，可以使得该RTPS具有相位误差小和幅度误差小的优点，同时在包括该RTPS的集成电路中采用上述正交耦合器的版图设计，可以使得该RTPS占用的集成电路的面积较小。
图10为本申请实施例提供的一种矢量合成移相器VMPS的结构示意图，该VMPS包括正交耦合器、两路幅度调节器和合路器。其中，两路幅度调节电路中的一路幅度调节电路的差分输入端口与正相差分直通端口TP和负相差分直通端口TN耦合，另一 路幅度调节电路的差分输入端口与正相差分耦合端口CP和负相差分耦合端口CN耦合，两路幅度调节电路的差分输出端口与合路器的两个差分输入端口耦合。
其中，该幅度调节器是指可以调节信号幅度的器件。在实际应用中，该幅度调节器可以为数字步进测电器(digital stepper apparatus，DSA)或可变增益放大器(variable gain amplifier，VGA)等。图10中以幅度调节器为VGA为例进行说明。
具体的，在该VMPS中，正交耦合器的正相差分直通端口TP和负相差分直通端口输出第一路信号，正相差分耦合端口CP和负相差分耦合端口和CN输出第二路信号，第一路信号和第二路信号的相位相差90°；两路幅度调节器分别对第一路信号和第二路信号的幅度进行调整，调整后的两路信号输入到合路器的两个差分输入端，由合路器对调整后的两路信号作矢量相加后从差分输出端(即OUTP和PUTN)中输出。
需要说明的是，在对调整后的两路信号作矢量相加时，对第一路信号中的N信号和第二路信号中的P信号的交换处理可以由合路器来实现，也可以在将调整后的两路信号输入合路器之前进行交换，本申请实施例对此不作具体限制。
需要说明的是，该VMPS中的正交耦合器在集成电路中的版图设计具体可以如上述图3-图5所示。另外，关于该VMPS的详细工作原理可以参考相关技术中的阐述，本申请实施例对此不作详细阐述。
在本申请实施例中，将该正交耦合器应用于VMPS中，可以使得该RTPS具有较好的宽带特性、以及相位误差小和幅度误差小的优点，同时在包括该VMPS的集成电路中采用上述正交耦合器的版图设计，可以使得该VMPS占用的集成电路的面积较小。
图11为本申请实施例提供的一种镜像抑制混频器IRM的结构示意图，该IRM包括分路器、两个正交耦合器和两路混频器，两路混频器分别表示为第一混频器MIX1和第二混频器MIX2，两个正交耦合器分别表示为第一正交耦合器COP1和第二正交耦合器COP2。
其中，分路器的两个差分输出端口分别与两路混频器MIX1和MIX2的差分输入端口连接；两路混频器MIX1和MIX2的差分输出端口分别与第一正交耦合器COP1的正相差分输入端口INP1和负相差分输入端口INN1、以及正相差分耦合端口CP1和负相差分耦合端口CN1耦合；第二正交耦合器COP2用于通过正相差分输入端口INP2和负相差分输入端口INN2、以及正相差分耦合端口CP2和负相差分耦合端口CN2耦合分别为两路混频器MIX1和MIX2提供差分本振信号。分路器的差分输入端作为该IRM的差分输入端口，第一正交耦合器COP1的正相差分直通端口TP1和负相差分直通端口TN1作为该IRM的差分输出端口。图11中将两路混频器MIX1和MIX2对应的差分本振信号表示为LO1和LO2。
其中，镜像频率是经过对有用信号频率进行变频处理生成的信号频率，在低中频或零中频系统中，镜像频率和有用信号频率很接近，或者镜像频率甚至落在有用信号的信号带宽内，此时滤波器很难滤除镜像频率，而镜像抑制混频器可以很好地解决这个问题。在镜像抑制混频器中，除了需要在混频器的差分输出端口对I/Q两路信号进行相位变换，还需要为两路混频器提供相位相差90°的正交本振信号。本申请实施例中通过一个正交耦合器在两路混频器的差分输出端口输出的I/Q两路信号进行相位变换，通过另一个正交耦合器为两路混频器提供相位相差90°的正交本振信号。
需要说明的是，该IRM中的正交耦合器在集成电路中的版图设计具体可以如上述图3-图5所示。另外，关于该IRM的详细工作原理可以参考相关技术中的阐述，本申请实施例对此不作详细阐述。
在本申请实施例中，将该正交耦合器应用于IRM中，可以使得该IRM具有宽带镜像抑制特性，同时在包括该IRM的集成电路中采用上述正交耦合器的版图设计，可以使得该IRM占用的集成电路的面积较小。
图12为本本申请实施例提供的一种平衡放大器BA的结构示意图，该BA包括两个正交耦合器和两路放大器(amplifier，AMP)，两个正交耦合器分别表示为第一正交耦合器和第二正交耦合器，两路放大器分别表示为AMP1和AMP2。
其中，第一正交耦合器的正相差分直通端口TP1和负相差分直通端口TN1、以及正相差分耦合端口CP1和负相差分耦合端口CN1分别与两路放大器AMP1和AMP2的差分输入端口耦合，两路放大器AMP1和AMP2的差分输出端口分别与第二个正交耦合器的正相差分输入端口INP2和负相差分输入端口INN2、以及正相差分耦合端口CP2和负相差分耦合端口CN2耦合。第一差分正交耦合器的正相差分输入端口INP1和负相差分输入端口INN1作为该BA的输入端口，第二差分正交耦合器的正相差分直通端口TP2和负相差分直通端口TN2作为该BA的输出端口OUTP和OUTN。
需要说明的是，该BA中的正交耦合器在集成电路中的版图设计具体可以如上述图3-图5所示。另外，关于该BA的详细工作原理可以参考相关技术中的阐述，本申请实施例对此不作详细阐述。
本申请实施例提供的BA中，两路放大器的差分输入端口和差分输出端口均被第一正交耦合器和第二差分正交耦合器隔离，这样可以使得该BA中的阻抗匹配不受内部两路放大器AMP1和AMP2的输入输出阻抗的干扰，提高了该BA的稳定性。由于耦合器带宽决定了平衡放大器BA的带宽，将本文提供的正交耦合器应用于BA中，可以使得该BA的宽带特定，同时在包括该BA的集成电路中采用上述正交耦合器的版图设计，可以使得该BA占用的集成电路的面积较小。
基于此，本申请实施例还提供一种通信设备，该通信设备可以为终端或者基站等。在本申请实施例中，该通信设备中包括集成电路，该集成电路中设置有正交耦合器；该正交耦合器上设置有正相差分输入端口、负相差分输入端口，正相差分直通端口、负相差分直通端口、正相差分耦合端口、负相差分耦合端口、正相差分隔离端口和负相差分隔离端口；正交耦合器上设置有相互耦合的第一线圈、第二线圈、第三线圈和第四线圈；正相差分输入端口和正相差分直通端口设置在第一线圈的两端；负相差分输入端口和负相差分直通端口设置在第二线圈的两端；正相差分耦合端口和正相差分隔离端口设置在第三线圈的两端；负相差分耦合端口和负相差分隔离端口设置在第四线圈的两端。
在一种可能的实现方式中，该通信设备可以包括上述图3-图6所示的任一正交耦合器，或者图8-图12中任一图示所提供的包括正交耦合器的其他电路等。具体关于正交耦合器、以及包括正交耦合器的其他电路的相关描述可以参考上文中的相应描述，本申请实施例在此不再赘述。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读介质， 该计算机具有用于创建集成电路的软件，该计算机可读介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构具有用于制造如上文图3-图6、图8-图12中任一图示所提供的电路的光掩膜数据。
需要说明的是，本申请实施例和附图仅仅是一种示例，任一实施例或附图中的每个MOS管可以为一个单独的满足所需要启动增益或者所需要导通电流的MOS管，也可以为通过多个MOS管并联组合成的需要满足所需要启动增益或者所需要导通电流的MOS管组合，也即该多个MOS管中每个MOS管对应的启动增益之和大于等于所需要启动增益；本申请实施例中的每个电容可以为满足所需电容值的一个电容，也可以是由多个电容通过并联或者串联组成的满足所需电容值的电容组合，也即该多个电容串联或并联后对应的电容值等于所需要的电容值；本申请实施例中的每个电感可以为满足所需要电感值的一个电感，也可以是由多个电感通过串联或者并联方式组成的满足所需要电感值的电感组合；本申请实施例中的每个电阻可以为满足所需电阻值的一个电阻，也可以是由多个电阻通过并联或者串联组成的满足所需电阻值的电阻组合，也即，该多个电阻串联或并联后对应的电阻值等于所需要的电阻值。
应理解，在本申请中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。本申请提到的“耦合”一词，用于表达不同组件之间的互通或互相作用，可以包括直接相连或通过其他组件间接相连。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (18)

  1. 一种集成电路，其特征在于，
    所述集成电路中设置有正交耦合器；
    所述正交耦合器上设置有正相差分输入端口、负相差分输入端口，正相差分直通端口、负相差分直通端口、正相差分耦合端口、负相差分耦合端口、正相差分隔离端口和负相差分隔离端口；
    所述正交耦合器上设置有相互耦合的第一线圈、第二线圈、第三线圈和第四线圈；
    所述正相差分输入端口和所述正相差分直通端口设置在所述第一线圈的两端；所述负相差分输入端口和所述负相差分直通端口设置在所述第二线圈的两端；所述正相差分耦合端口和所述正相差分隔离端口设置在所述第三线圈的两端；所述负相差分耦合端口和所述负相差分隔离端口设置在所述第四线圈的两端。
  2. 根据权利要求1所述的集成电路，其特征在于，所述第一线圈和所述第二线圈相互嵌套且匝数相同。
  3. 根据权利要求1或2所述的集成电路，其特征在于，所述第一线圈与所述第二线圈的线宽相同。
  4. 根据权利要求1-3任一项所述的集成电路，其特征在于，所述第一线圈与所述第二线圈之间的耦合缝隙保持恒定。
  5. 根据权利要求1-4任一项所述的集成电路，其特征在于，所述第三线圈和所述第四线圈相互嵌套且匝数相同。
  6. 根据权利要求1-5任一项所述的集成电路，其特征在于，所述第三线圈与所述第四线圈的线宽相同。
  7. 根据权利要求1-6任一项所述的集成电路，其特征在于，所述第三线圈与所述第四线圈之间的耦合缝隙保持恒定。
  8. 根据权利要求1-7任一项所述的集成电路，其特征在于，所述第一线圈与所述第二线圈分别具有过孔，所述第一线圈和所述第二线圈在同一金属层通过所述过孔相互耦合。
  9. 根据权利要求1-8任一项所述的集成电路，其特征在于，所述第三线圈与所述第四线圈分别具有过孔，所述第三线圈和所述第四线圈在同一金属层通过所述过孔相互耦合。
  10. 根据权利要求1-9任一项所述的集成电路，其特征在于，所述第一线圈和所述第二线圈相互耦合设置于第一金属层、所述第三线圈和所述第四线圈相互耦合设置于第二金属层。
  11. 根据权利要求10所述的集成电路，其特征在于，所述第一线圈、所述第二线圈、所述第三线圈和所述第四线圈的匝数相同。
  12. 根据权利要求10所述的集成电路，其特征在于，所述正相差分输入端口位于所述正相差分耦合端口的正下方，所述负相差分输入端口位于所述负相差分耦合端口的正下方，所述正相差分直通端口位于所述正相差分隔离端口的正下方，所述负相差分直通端口位于所述负相差分隔离端口的正下方。
  13. 根据权利要求1-12任一项所述的集成电路，其特征在于，所述正相差分输入端口与所述正相差分耦合端口通过第一电容耦合，所述负相差分输入端口与所述负相差分耦合端口通过第二电容耦合，所述正相差分直通端口与所述正相差分隔离端口通过第三电容耦合，所述负相差分直通端口与所述负相差分隔离端口通过第四电容耦合。
  14. 根据权利要求1-13任一项所述的集成电路，其特征在于，所述集成电路中还设置有四个电阻可调器件；
    所述四个电阻可调器件分别连接在所述正相差分耦合端口、所述负相差分耦合端口、所述正相差分直通端口、所述负相差分直通端口与接地端之间。
  15. 根据权利要求1-13任一项所述的集成电路，其特征在于，所述集成电路中还设置有四个可调电抗器件；
    所述四个可调电抗器件分别连接在所述正相差分耦合端口、所述负相差分耦合端口、所述正相差分直通端口、所述负相差分直通端口与接地端之间。
  16. 根据权利要求1-13任一项所述的集成电路，其特征在于，所述集成电路中还设置有两路幅度调节电路和合路器；
    所述两路幅度调节电路中的一路幅度调节电路的差分输入端口与所述正相差分直通端口和所述负相差分直通端口耦合，另一路幅度调节电路的差分输入端口与所述正相差分耦合端口和所述负相差分耦合端口耦合，所述两路幅度调节电路的差分输出端口与所述合路器的两个差分输入端口耦合。
  17. 一种通信设备，其特征在于，所述通信设备包括权利要求1-16任一项所述的集成电路。
  18. 一种与计算机一起使用的非瞬时性计算机可读介质，其特征在于，所述计算机具有用于创建集成电路的软件，所述计算机可读介质上存储有一个或多个计算机可读数据结构，所述一个或多个计算机可读数据结构具有用于制造如权利要求1-16任一项所述的集成电路的光掩膜数据。
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