WO2021139040A1 - Transistor à effet de champ à oxyde de gallium et son procédé de fabrication - Google Patents

Transistor à effet de champ à oxyde de gallium et son procédé de fabrication Download PDF

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Publication number
WO2021139040A1
WO2021139040A1 PCT/CN2020/086192 CN2020086192W WO2021139040A1 WO 2021139040 A1 WO2021139040 A1 WO 2021139040A1 CN 2020086192 W CN2020086192 W CN 2020086192W WO 2021139040 A1 WO2021139040 A1 WO 2021139040A1
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Prior art keywords
gallium oxide
dielectric layer
fluorine
effect transistor
field effect
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PCT/CN2020/086192
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English (en)
Chinese (zh)
Inventor
吕元杰
王元刚
周幸叶
刘宏宇
宋旭波
梁士雄
马春雷
付兴昌
冯志红
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中国电子科技集团公司第十三研究所
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Publication of WO2021139040A1 publication Critical patent/WO2021139040A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • This application belongs to the field of semiconductor technology, and in particular relates to a gallium oxide field effect transistor and a preparation method thereof.
  • ultra-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices in recent years, and are expected to replace traditional silicon-based power devices in certain specific fields.
  • ultra-wide bandgap gallium oxide has outstanding advantages in breakdown field strength, Baliga's merit and cost.
  • Baliga's figure of merit is usually used to characterize the suitability of materials for power devices.
  • the Balijia figure of merit for ⁇ - Ga 2 O 3 materials is 4 times that of GaN materials, 10 times that of SiC materials, and 3444 times that of Si materials.
  • ⁇ -Ga 2 O 3 power devices have the same withstand voltage as GaN and SiC devices, with lower on-resistance and lower power consumption, which can greatly reduce the power loss during device operation.
  • Ga 2 O 3 MOSFET gallium oxide metal oxide semiconductor field effect transistor
  • NICT used Al 2 O 3 as the sub-gate dielectric and combined with the gate field plate structure to produce a Ga 2 O 3 MOSFET with a breakdown voltage of 750 V.
  • the present application provides a gallium oxide field effect transistor and a preparation method thereof to further increase the breakdown voltage of the existing gallium oxide field effect transistor.
  • the first aspect of the embodiments of the present application provides a gallium oxide field effect transistor, including a substrate, a gallium oxide channel layer provided on the substrate, a source electrode provided on the gallium oxide channel layer, and The drain electrode, the gate dielectric layer provided between the source electrode and the drain electrode, the gate electrode provided on the gate dielectric layer, and the surface area between the source electrode and the drain electrode
  • a passivation dielectric layer, the passivation dielectric layer is provided with a fluorine injection area, and the fluorine injection area is located in an area where the gate electrode is biased toward the drain electrode.
  • the lower edge of the fluorine injection region does not reach the lower surface of the passivation medium layer.
  • the left edge of the fluorine injection region does not exceed The left edge of the gate electrode, and the length of the right edge of the fluorine injection region that exceeds the right edge of the gate electrode is not more than 10 micrometers.
  • the second aspect of the embodiments of the present application provides a manufacturing method of a gallium oxide field effect transistor, the manufacturing method includes:
  • Fluorine ion implantation is performed into the passivation dielectric layer to form a fluorine implantation region, wherein the fluorine implantation region is located in a region where the gate electrode is biased toward the drain electrode.
  • the performing fluorine ion implantation into the passivation medium layer to form a fluorine implantation region includes:
  • the implantation depth of the fluorine ion implantation is smaller than the thickness of the passivation dielectric layer.
  • the left edge of the fluorine injection region does not exceed The left edge of the gate electrode, and the length of the right edge of the fluorine injection region that exceeds the right edge of the gate electrode is not more than 10 micrometers.
  • the fluorine ion implantation meter of the fluorine implantation area decreases sequentially from left to right
  • the metal mask layer is a nickel mask layer or a chromium mask layer.
  • the thickness of the metal mask layer does not exceed 1000 nanometers.
  • the gallium oxide field-effect transistor provided in the present application includes a substrate, a gallium oxide channel layer provided on the substrate, a source electrode and a drain electrode provided on the gallium oxide channel layer, and a gap between the source electrode and the drain electrode.
  • the fluorine injection area is provided.
  • the fluorine injection area can reduce or even deplete the electrons in the gallium oxide channel layer, and can increase the breakdown field strength of the passivation dielectric layer, thereby effectively suppressing the possible occurrence of the gate electrode in the area on the side of the drain electrode.
  • the peak electric field makes the distribution of the electric field more uniform, and the breakdown voltage of the gallium oxide field effect transistor is greatly increased, which is beneficial to expand the application of gallium oxide field effect transistor devices in high-voltage scenarios.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of a gallium oxide field effect transistor provided by an embodiment of the present application
  • FIG. 2 is an implementation flow chart of a method for manufacturing a gallium oxide field effect transistor provided by an embodiment of the present application
  • FIG. 3 is an implementation flowchart of step 106 in the embodiment shown in FIG. 2 provided by an embodiment of the present application;
  • FIG. 4 is a schematic diagram of fluorine ion implantation provided by an embodiment of the present application.
  • FIG. 1 shows a schematic diagram of a cross-sectional structure of a gallium oxide field effect transistor provided by an embodiment of the present application, which is described in detail as follows:
  • the gallium oxide field effect transistor provided by the embodiment of the present application includes a substrate 10, a gallium oxide channel layer 11 provided on the substrate 10, and a source electrode provided on the gallium oxide channel layer 11 12 and the drain electrode 14, the gate dielectric layer 15 provided between the source electrode 12 and the drain electrode 14, the gate electrode 16 provided on the gate dielectric layer 15, and the surface area between the source electrode 12 and the drain electrode 14
  • the passivation dielectric layer 17 is provided with a fluorine injection region 18 in the passivation dielectric layer 17, and the fluorine injection region 18 is located in a region where the gate electrode 16 is biased toward the drain electrode 14.
  • Breakdown voltage is a key parameter of metal oxide semiconductor field effect transistors.
  • the gate electrode such as a right-angle gate electrode
  • the fluorine injection area can reduce or even deplete the electrons in the gallium oxide channel layer.
  • the lower edge of the fluorine injection region 18 should not exceed the lower surface of the passivation dielectric layer 17.
  • the lateral position of the fluorine injection region 18 can be set according to the following restrictions: if the side where the source electrode 12 is located is the gate The left side of the electrode 16 and the side where the drain electrode 14 is located is the right side of the gate electrode 16, the left edge of the fluorine injection region 18 does not exceed the left edge of the gate electrode 16, and the right edge of the fluorine injection region 18 exceeds the gate electrode The length of the right edge of 16 is not more than 10 microns.
  • the gallium oxide field effect transistor provided by the present application includes a substrate, a gallium oxide channel layer provided on the substrate, a source electrode and a drain electrode provided on the gallium oxide channel layer, a source electrode and a drain electrode.
  • the gate dielectric layer between the electrodes, the gate electrode provided on the gate dielectric layer, and the passivation dielectric layer covering the surface area between the source electrode and the drain electrode, are located in the passivation dielectric layer and the gate electrode is biased toward the drain electrode.
  • a fluorine injection area is provided in the area on the side of the gate electrode.
  • the fluorine injection area can reduce or even deplete the electrons in the passivation dielectric layer, and increase the breakdown field strength of the passivation dielectric layer, thereby effectively suppressing the possible occurrence of the gate electrode in the area on the side of the drain electrode.
  • the peak electric field makes the distribution of the electric field more uniform, and the breakdown voltage of the gallium oxide field effect transistor is greatly increased, which is beneficial to expand the application of gallium oxide field effect transistor devices in high-voltage scenarios.
  • FIG. 2 shows an implementation flow chart of a method for manufacturing a gallium oxide field effect transistor provided by an embodiment of the present application, which is described in detail as follows:
  • a gallium oxide channel layer is epitaxially grown on a substrate
  • the substrate may be a high-resistance gallium oxide substrate, or a semi-insulating silicon carbide substrate, a magnesium oxide substrate, or a sapphire substrate.
  • the epitaxially grown gallium oxide channel layer may be an n-type gallium oxide channel layer.
  • the n-type gallium oxide channel layer is realized by doping elements such as Si or Sn, and the doping concentration may be 1.0 ⁇ In the range of 1015 cm-3 to 1.0 ⁇ 1020 cm-3, in some application scenarios, the doping concentration may also vary in a gradient.
  • the layer thickness of the gallium oxide channel layer may be 10 nm to 1000 nm.
  • an undoped gallium oxide layer can also be grown between the gallium oxide channel layer and the substrate. That is, an undoped gallium oxide layer can be grown on the substrate, and then a gallium oxide channel layer can be epitaxially grown on the undoped gallium oxide layer.
  • step 102 a source electrode and a drain electrode are prepared on the gallium oxide channel layer
  • the n+ region can be prepared by ion implantation on the gallium oxide channel layer, and the source electrode and the drain electrode can be deposited on the n+ region.
  • the electrode is deposited by electron beam evaporation, and the metal can be deposited It is Ti/Au or Ti/Al/Ni/Au.
  • the source electrode and the drain electrode may be deposited on both ends of the upper part of the gallium oxide channel layer.
  • step 103 a gate dielectric layer is grown between the source electrode and the drain electrode;
  • an atomic layer deposition method may be used to grow a layer of aluminum oxide or hafnium oxide as the gate dielectric layer between the source electrode and the drain electrode, and the thickness of the gate dielectric layer may be 10-100 nm.
  • step 104 a gate electrode is prepared on the gate dielectric layer
  • the gate electrode can be prepared on the gate dielectric layer by the electron beam evaporation method.
  • the gate length of the prepared gate electrode can be 50 nanometers to 10 microns, and the deposition metal of the gate electrode can be Ni/Au or Pt/Au.
  • a passivation dielectric layer is prepared on the surface area between the source electrode and the drain electrode;
  • a passivation dielectric layer can be prepared on the surface area between the source electrode and the drain electrode, and the prepared passivation dielectric layer fully covers the gate electrode.
  • the passivation dielectric layer may be a silicon nitride passivation dielectric layer, specifically, PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma-enhanced chemical vapor deposition) method to grow silicon nitride passivation dielectric layer, the thickness of the silicon nitride passivation dielectric layer can be between 50 to 2000 nanometers.
  • step 106 fluorine ion implantation is performed into the passivation dielectric layer to form a fluorine implantation region, wherein the fluorine implantation region is located in a region where the gate electrode is biased toward the drain electrode.
  • the fluorine implantation area is formed by implanting fluorine ions into the passivation dielectric layer, and the fluorine implantation area is used to reduce or even deplete the electrons in the corresponding position in the gallium oxide channel layer, and can improve the passivation dielectric layer
  • the breakdown field is strong, thereby effectively suppressing the peak electric field that may appear in the area on the side of the gate electrode biased to the drain electrode. Since the peak electric field often exists in the area on the side of the gate electrode biased to the drain electrode, the fluorine injection area is correspondingly located in the area of the gate electrode on the side of the drain electrode.
  • step 106 may be specifically completed by the following steps:
  • step 1061 a metal mask layer is sputtered or evaporated on the upper surface of the passivation medium layer
  • the passivation dielectric layer may be etched during the fluorine ion implantation process
  • a metal mask layer is sputtered or evaporated on the upper surface of the passivation dielectric layer, which can be used as a mask to prevent the passivation dielectric layer It is etched during the fluorine ion implantation process.
  • the thickness of the metal mask layer may not be higher than 1000 nanometers to avoid affecting the fluoride ion implantation effect.
  • the metal mask layer may be a nickel mask layer or a chromium mask layer, which can better protect the passivation dielectric layer from being etched and has a better fluoride ion implantation effect.
  • step 1062 a photoresist mask layer is formed on the metal mask layer, and fluorine ion implantation is performed into the passivation medium layer using the photoresist mask layer as a mask to form the fluorine implantation area ;
  • photoresist can be used as a mask to perform fluorine injection treatment on the gate electrode bias and drain electrode area.
  • the gallium oxide field obtained through step 101 to step 105 The effect transistor includes the substrate 10, the gallium oxide channel layer 11, the source electrode 12, the drain electrode 14 and the gate dielectric layer 15, the gate electrode 16, covering the passivation of the surface area between the source electrode 12 and the drain electrode 14, from bottom to top. Medium layer 17.
  • a metal mask layer 19 can be grown on the upper surface of the passivation medium layer 17, a photoresist mask layer 20 is formed on the metal mask layer 19, and the photoresist mask layer 20 is used as a mask to pass the photoresist
  • the ion implantation window on the mask layer 20 implants fluorine ions into the passivation dielectric layer 17.
  • the implantation depth of the fluorine ion implantation is smaller than the thickness of the passivation dielectric layer. If the side where the source electrode is located is the left side of the gate electrode, and the side where the drain electrode is located is the right side of the gate electrode, the left edge of the fluorine injection region does not exceed the gate electrode. The left edge of the electrode, and the length of the right edge of the fluorine injection region that exceeds the right edge of the gate electrode is not more than 10 micrometers.
  • the amount of fluorine ion implantation in the fluorine implantation area decreases sequentially from left to right.
  • the electrons in the gallium oxide channel can be depleted (or reduced). Therefore, the existence of the F injection region can effectively reduce the peak electric field intensity.
  • the amount of fluoride ion implantation is large, the channel electrons will be consumed too much, which will cause the on-resistance of the device to increase, which is detrimental to the device performance. Therefore, the amount of fluoride ion implantation can be sequentially reduced from the right edge of the gate electrode to the right, so as to achieve the purpose of not only increasing the breakdown voltage, but also maintaining a low on-resistance.
  • step 1063 the photoresist mask layer and the metal mask layer are removed.
  • the photoresist and the nickel metal mask layer can be removed to complete the fabrication of the device.
  • the method for preparing a gallium oxide field effect transistor provided by the embodiment of the present application can directly use the above steps 1061 to 1063 to implant fluorine ions on the existing gallium oxide field effect transistor to form fluoride ions in the region on the side of the gate electrode and the drain electrode.
  • the injection area suppresses the peak electric field and improves the breakdown voltage of the gallium oxide field effect transistor device.
  • the gallium oxide field effect transistor provided by the present application includes a substrate, a gallium oxide channel layer provided on the substrate, a source electrode and a drain electrode provided on the gallium oxide channel layer, a source electrode and a drain electrode.
  • the gate dielectric layer between the electrodes, the gate electrode provided on the gate dielectric layer, and the passivation dielectric layer covering the surface area between the source electrode and the drain electrode, are located in the passivation dielectric layer and the gate electrode is biased toward the drain electrode.
  • a fluorine injection area is provided in the area on the side of the fluorine injection area.
  • the fluorine injection area can reduce or even deplete the electrons in the gallium oxide channel layer, and can increase the breakdown field strength of the passivation dielectric layer, thereby effectively suppressing the gate electrode from the area on the drain electrode side
  • the peak electric field that may appear inside makes the distribution of the electric field more uniform, and the breakdown voltage of the gallium oxide field effect transistor is greatly increased, which is conducive to expanding the application of gallium oxide field effect transistor devices in high-voltage scenarios.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente demande peut s'appliquer au domaine de la technologie des semi-conducteurs et concerne un transistor à effet de champ à oxyde de gallium et son procédé de fabrication. Le transistor à effet de champ à oxyde de gallium comprend un substrat, une couche de canal d'oxyde de gallium disposée sur le substrat et une électrode de source et une électrode de drain disposées sur la couche de canal d'oxyde de gallium, une couche diélectrique de grille disposée entre l'électrode de source et l'électrode de drain, une électrode de grille disposée sur la couche diélectrique de grille et une couche diélectrique de passivation recouvrant une zone de surface entre l'électrode de source et l'électrode de drain, une zone d'implantation de fluor étant disposée dans la couche diélectrique de passivation et la zone d'implantation de fluor étant située dans la zone sur un côté de l'électrode de grille à proximité de l'électrode de drain. Le transistor à effet de champ à oxyde de gallium selon la présente demande peut supprimer efficacement un champ électrique de crête qui peut se produire dans la zone sur un côté de l'électrode de grille à proximité de l'électrode de drain, de sorte que la distribution du champ électrique soit plus uniforme et la tension de claquage du transistor à effet de champ à oxyde de gallium soit considérablement améliorée, ce qui facilite l'extension de l'application d'un dispositif de transistor à effet de champ à oxyde de gallium dans des scénarios à haute tension.
PCT/CN2020/086192 2020-01-07 2020-04-22 Transistor à effet de champ à oxyde de gallium et son procédé de fabrication WO2021139040A1 (fr)

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CN202010013525.4A CN111180398B (zh) 2020-01-07 2020-01-07 一种氧化镓场效应晶体管及其制备方法
CN202010013525.4 2020-01-07

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117276352A (zh) * 2023-11-23 2023-12-22 三峡智能工程有限公司 一种晶体管结构及其制备方法、记录媒体和系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007059220A2 (fr) * 2005-11-15 2007-05-24 The Regents Of The University Of California Procedes permettant de mettre en forme le champ electrique dans des dispositifs electroniques, de passiver des dislocations et des defauts ponctuels, et d'ameliorer le rendement de la luminescence de dispositifs optiques
CN104600107A (zh) * 2013-10-31 2015-05-06 英飞凌科技奥地利有限公司 电子器件
JP2017069260A (ja) * 2015-09-28 2017-04-06 国立研究開発法人情報通信研究機構 フィールドプレートを有するＧａ２Ｏ３系トランジスタ
CN109659355A (zh) * 2018-12-06 2019-04-19 中国电子科技集团公司第十三研究所 常关型氧化镓场效应晶体管结构及制备方法
CN110112206A (zh) * 2019-05-20 2019-08-09 中山大学 一种氧化镓结型场效应晶体管

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097483B (zh) * 2010-12-31 2012-08-29 中山大学 GaN基异质结构增强型绝缘栅场效应晶体管及制备方法
CN104393040A (zh) * 2014-10-29 2015-03-04 电子科技大学 一种具有荷电介质的hemt器件
CN107464844A (zh) * 2017-07-20 2017-12-12 中国电子科技集团公司第十三研究所 氧化镓场效应晶体管的制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007059220A2 (fr) * 2005-11-15 2007-05-24 The Regents Of The University Of California Procedes permettant de mettre en forme le champ electrique dans des dispositifs electroniques, de passiver des dislocations et des defauts ponctuels, et d'ameliorer le rendement de la luminescence de dispositifs optiques
CN104600107A (zh) * 2013-10-31 2015-05-06 英飞凌科技奥地利有限公司 电子器件
JP2017069260A (ja) * 2015-09-28 2017-04-06 国立研究開発法人情報通信研究機構 フィールドプレートを有するＧａ２Ｏ３系トランジスタ
CN109659355A (zh) * 2018-12-06 2019-04-19 中国电子科技集团公司第十三研究所 常关型氧化镓场效应晶体管结构及制备方法
CN110112206A (zh) * 2019-05-20 2019-08-09 中山大学 一种氧化镓结型场效应晶体管

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117276352A (zh) * 2023-11-23 2023-12-22 三峡智能工程有限公司 一种晶体管结构及其制备方法、记录媒体和系统
CN117276352B (zh) * 2023-11-23 2024-02-06 三峡智能工程有限公司 一种晶体管结构及其制备方法、记录媒体和系统

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